Anti-fuse memory cell and method of making same

Abstract

The embodiment of the present application relates to a kind of anti-fuse memory cell and its manufacturing method, and the anti-fuse memory cell includes: substrate, the substrate has selection gate structure;First doped region and second doped region are respectively located in the substrate of the opposite sides of selection gate structure and the same doping ion type of both;The horizontal direction of first doped region towards second doped region, there is spacing between first doped region and selection gate structure, and LDD structure is not arranged between first doped region and selection gate structure;Anti-fuse gate dielectric layer located on the substrate and anti-fuse gate located on anti-fuse gate dielectric layer, first doped region, anti-fuse gate dielectric layer and anti-fuse gate constitute anti-fuse transistor;Third doped region, third doped region is located between second doped region and selection gate structure, the same doping ion type of third doped region with second doped region, and the doping ion concentration of third doped region is less than the doping ion concentration of second doped region.

Description

[0001] This application is a divisional application of the application for invention with the application number 201910745176.2 and the application name of “Anti-fuse Memory Cell and Manufacturing Method Thereof” filed in the China Patent Office on August 13, 2019. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, in particular to an anti-fuse memory cell and a manufacturing method thereof. BACKGROUND

[0003] Memory devices can generally be divided into volatile memory devices and non-volatile memory devices. Non-volatile memory devices can be further divided into read only memory (ROM), one time programmable memory (OTP memory), and rewritable memory. Among them, one time programmable memory can be classified into fuse type and anti-fuse type.

[0004] In semiconductor devices such as DRAM (Dynamic Random Access Memory), a defective cell that cannot work normally is generally replaced by using a redundant cell to repair a defective address. In the process of storing a defective address, an anti-fuse memory is usually used to store information.

[0005] The smallest unit of an anti-fuse memory is usually composed of an anti-fuse transistor and a selection transistor. The working principle of the anti-fuse memory is to store data 1 or 0 according to whether the anti-fuse gate dielectric layer is broken down, so that the anti-fuse memory can selectively electrically connect two originally electrically isolated elements. In the prior art, during the programming of the anti-fuse memory, the source / drain end of the selection transistor instantaneously bears a high voltage transmitted from the anti-fuse transistor, causing damage to the selection gate dielectric layer and affecting the reliability of the selection transistor. SUMMARY

[0006] The embodiments of the present application provide an anti-fuse memory cell and a manufacturing method thereof, which solve the problem of damage to the selection gate structure caused by the source / drain bearing a high voltage instantaneously when the anti-fuse gate dielectric layer is broken down.

[0007] To solve the above technical problems, the embodiment of the present application provides a kind of anti-fuse memory cell, comprising: substrate, substrate has selection gate structure;First doped region and second doped region, first doped region and second doped region are located in the substrate on the opposite sides of selection gate structure, and the doping ion type of first doped region and second doped region is same;Anti-fuse gate dielectric layer located on the first doped region and anti-fuse gate located on the anti-fuse gate dielectric layer;Third doped region, third doped region is located between second doped region and selection gate structure, and the doping ion type of third doped region is same with the doping ion type of second doped region, and the doping ion concentration of third doped region is less than the doping ion concentration of second doped region.

[0008] The embodiment of the present application further provides a kind of anti-fuse memory cell's manufacturing method, comprising: providing substrate, the substrate has selection gate structure, the first doped region and the second doped region are formed in the substrate on the opposite sides of selection gate structure, and the doping ion type of first doped region and second doped region is same;Form third doped region before forming the second doped region, the third doped region is located in the substrate and is in contact with the second doped region, and the doping ion type of third doped region is same with the doping ion type of second doped region, and the doping ion concentration of third doped region is less than the doping ion concentration of second doped region.

[0009] Compared with prior art, the technical scheme provided by the embodiment of the present application has the following advantages:

[0010] The embodiment of the present application provides a kind of anti-fuse memory cell, and third doped region is arranged between selection gate structure and second doped region, and the doping ion type of third doped region is same with the doping ion type of second doped region, i.e. no LDD structure is arranged between first doped region and selection gate structure.When dielectric breakdown occurs in anti-fuse gate dielectric layer, first doped region bears instantaneous high voltage.Because the existence of LDD structure can increase the overlapping area of strong electric field region between selection gate structure and first doped region, when no LDD structure is arranged between first doped region and selection gate structure, the overlapping area of strong electric field region formed by the instantaneous high voltage that first doped region bears and selection gate structure is reduced, and the direct damage of strong electric field to selection gate structure is reduced.

[0011] In addition, because no LDD structure is arranged between first doped region and selection gate structure, equivalent resistance is equivalent to being connected in series between first doped region and selection gate structure and can achieve voltage division effect, which is beneficial to reduce the electric field intensity of strong electric field region where selection gate structure is located, thereby weakening the damage of strong electric field region to selection gate structure.

[0012] In addition, the material of the anti-fuse gate dielectric layer is the same as that of the select gate dielectric layer, and the thickness of the anti-fuse gate dielectric layer is less than or equal to that of the select gate dielectric layer, which is beneficial to ensure that the select gate dielectric layer will not be broken down before the anti-fuse gate dielectric layer is broken down, thereby improving the electrical performance of the anti-fuse memory cell.

[0013] In addition, the doping ion concentration of the first doped region is less than or equal to the doping ion concentration of the second doped region, which is beneficial to further ensure that the select gate dielectric layer will not be broken down before the anti-fuse gate dielectric layer is broken down, thereby improving the electrical performance of the anti-fuse memory cell.

[0014] In addition, the fourth doped region is provided between the first doped region and the select gate structure, and the doping ion type of the fourth doped region is different from that of the first doped region, i.e., the fourth doped region is a HALO region. The provision of the fourth doped region is beneficial to inhibit ion diffusion of the first doped region, and further fix the breakdown region on the edge of the first doped region. Since the breakdown voltage perpendicular to the edge direction is higher than the breakdown voltage of the select gate dielectric layer perpendicular to the substrate direction, the provision of the fourth doped region can improve the breakdown voltage, thereby achieving the purpose of protecting the select gate structure.

[0015] In addition, the provision of the fourth doped region reduces the resistance between the first doped region and the second doped region, which is beneficial to compensate for the problem of increased channel resistance caused by the unilateral absence of the LDD structure, thereby improving the reaction speed of the anti-fuse memory cell. In addition, the provision of the fourth doped region can also reduce ion diffusion of the first doped region, which is used to inhibit the ion diffusion of the first doped region to cause the problem of leakage current and source-drain punchthrough.

[0016] In addition, the depth of the fourth doped region in the substrate is greater than the depth of the first doped region in the substrate, which can further inhibit ion diffusion of the first doped region.

[0017] In addition, the fifth doped region is provided below the third doped region, the fifth doped region is in contact with the second doped region, and the doping ion type of the fifth doped region is the same as that of the fourth doped region. The fifth doped region is provided to inhibit ion diffusion of the second doped region, which is used to inhibit the ion diffusion of the second doped region to cause the problem of leakage current and source-drain punchthrough. BRIEF DESCRIPTION OF DRAWINGS

[0018] One or more embodiments are illustrated by way of example in the figures that form a part of this patent document, these example are not intended to limit the embodiments, elements having the same reference numbers in the figures indicate like elements, unless otherwise specifically noted, the figures in the drawings are not to scale.

[0019] Figure 1 is a cross-sectional structure diagram of an anti-fuse memory cell;

[0020] Figure 2 FIG1 is a schematic cross-sectional structural diagram of an anti-fuse memory cell according to a first embodiment of the present invention;

[0021] Figure 3 1 is an equivalent working circuit of the anti-fuse memory cell according to the first embodiment of the present invention;

[0022] Figure 4 FIG2 is a schematic cross-sectional structural diagram of an anti-fuse memory cell according to a second embodiment of the present invention;

[0023] Figures 5 to 8 A schematic cross-sectional structural diagram corresponding to each step of the method for manufacturing an anti-fuse memory cell provided by the first embodiment of the present invention;

[0024] Figure 9 A schematic cross-sectional structural diagram corresponding to an intermediate step of a method for manufacturing an anti-fuse memory cell provided in a second embodiment of the present invention. DETAILED DESCRIPTION

[0025] As known from the background art, the select gate dielectric layer in the anti-fuse memory cell in the prior art is easily damaged.

[0026] refer to Figure 1 , Figure 1 This is a schematic diagram of the cross-sectional structure of an antifuse memory cell. Figure 1 The anti-fuse memory cell includes: a substrate 21 having a select gate structure 24 thereon; a first doping region 25 and a second doping region 29, the first doping region 25 and the second doping region 29 being located in the substrate 21 on opposite sides of the select gate structure 24, respectively, and having the same doping ion type; an anti-fuse gate dielectric layer 232 located on the first doping region 25, and an anti-fuse gate 233 located on the anti-fuse gate dielectric layer 232; a third doping region 27, the third doping region 27 being located between the second doping region 29 and the select gate structure 24, having the same doping ion type as the second doping region 29, and having a doping ion concentration less than that of the second doping region 29; and a fourth doping region 20, the fourth doping region 20 being located between the first doping region 25 and the select gate structure 24, having the same doping ion type as the first doping region 25, and having a doping ion concentration less than that of the first doping region 25.

[0027] The above anti-fuse memory cell has a problem that the select gate dielectric layer 242 is damaged by a strong electric field. Analysis shows that the cause of the above problem is as follows: when the voltage drop applied to both ends of the anti-fuse gate dielectric layer 232 reaches a certain value, the anti-fuse gate dielectric layer 232 will be dielectrically broken down, causing the anti-fuse gate dielectric layer 232 to conduct instantaneously, and the first doped region 25 will bear a high instantaneous voltage. Since the fourth doped region 20 is connected to the first doped region 25, and the fourth doped region 20 is in contact with the select gate dielectric layer 242, the high instantaneous voltage borne by the first doped region 25 will generate a strong electric field between the fourth doped region 20 and the select gate dielectric layer 242, and the existence of the strong electric field will cause damage to the select gate dielectric layer 242.

[0028] To solve the above problem, embodiments of the present application provide an anti-fuse memory cell, which includes an anti-fuse transistor and a select transistor. In some embodiments, the anti-fuse gate, the anti-fuse gate dielectric layer, and the first doped region form the anti-fuse transistor, which has a single-sided source / drain and functions as a capacitor. In addition, the first doped region, the second doped region, and the select gate structure form the select transistor, the select gate structure including a select gate and a select gate dielectric layer, wherein the first doped region and the second doped region respectively serve as the drain or the source of the select transistor, and a third doped region is provided as an LDD structure only between the second doped region and the select gate structure, but not between the first doped region and the select gate structure. That is, the LDD structure in the embodiments of the present application is a single-sided LDD structure. When the anti-fuse gate dielectric layer in the anti-fuse transistor is broken down, the first doped region will bear a high instantaneous voltage. Since the LDD structure is not provided between the first doped region and the select gate structure, the problem of a strong electric field caused by conduction through the LDD structure between the first doped region and the select gate structure is avoided, and thus the problem of damage to the select gate structure caused by the strong electric field is avoided. Therefore, the select gate structure in the embodiments of the present application can always maintain good performance, which is conducive to improving the electrical performance of the anti-fuse memory cell, for example, the reliability and stability of the anti-fuse memory cell are improved.

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the reader better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0030] Figure 2A cross-sectional structure diagram of the anti-fuse memory cell provided by the first embodiment of the present application is shown in the figure.

[0031] Reference Figure 2 In the embodiment, the anti-fuse memory cell comprises: a substrate 11, the substrate 11 having a select gate structure 14; a first doped region 15 and a second doped region 19, the first doped region 15 and the second doped region 19 being respectively located in the substrate 11 on opposite sides of the select gate structure 14, and the first doped region 15 and the second doped region 19 having the same type of doped ions; an anti-fuse gate dielectric layer 132 located on the first doped region 15 and an anti-fuse gate 133 located on the anti-fuse gate dielectric layer 132; and a third doped region 17, the third doped region 17 being located between the second doped region 19 and the select gate structure 14, the third doped region 17 having the same type of doped ions as the second doped region 19, and the third doped region 17 having a lower concentration of doped ions than the second doped region 19.

[0032] The anti-fuse memory cell provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0033] In the embodiment, the select gate structure 14 is located on the substrate 11, the select gate structure 14 comprises a select gate dielectric layer 142 and a select gate 143 located on the select gate dielectric layer 142, and the sidewall surfaces of the select gate structure 14 on opposite sides have a first side wall 141.

[0034] The material of the select gate 143 can be polysilicon or metal, the material of the select gate dielectric layer 142 is usually oxide, and the material of the first side wall 141 can be one of silicon oxide, silicon nitride and silicon oxynitride or a combination thereof, and the first side wall 141 serves to protect the select gate 143 and the select gate dielectric layer 142.

[0035] In the embodiment, the substrate 11 further has an isolation structure 12, and the material of the isolation structure 12 can be silicon oxide or silicon nitride. It should be noted that the depth of the isolation structure 12 in the substrate 11 can be adjusted according to actual conditions.

[0036] The substrate 11 has the first doped region 15 and the second doped region 19, the first doped region 15 and the second doped region 19 are respectively located on opposite sides of the select gate structure 14, and the first doped region 15 and the second doped region 19 have the same type of doped ions, which includes N-type ions or P-type ions. The first doped region 15, the select gate structure 14 and the second doped region 19 constitute a select transistor, the first doped region 15 serves as a source or a drain of the select transistor, and the second doped region 19 serves as a drain or a source of the select transistor.

[0037] In the embodiment, the doping ion concentration of the first doped region 15 is less than the doping ion concentration of the second doped region 19. In this way, the first doped region 15 can provide an effective voltage to the antifuse transistor, so as to ensure that the select gate dielectric layer 142 will not be broken down before the antifuse gate dielectric layer 132 is broken down, thereby improving the electrical performance of the antifuse memory cell.

[0038] When the select transistor in the antifuse memory cell is an NMOS transistor, the first doped region 15 and the second doped region 19 are N-type doped; when the select transistor in the antifuse memory cell is a PMOS transistor, the first doped region 15 and the second doped region 19 are P-type doped.

[0039] In addition, the substrate 11 further includes a well region (not shown), and the doping type of the well region is different from the doping type of the first doped region 15 and the second doped region 19.

[0040] In the annealing process, the edge 151 of the first doped region 15 towards the second doped region 19 will slightly move towards the second doped region 19.

[0041] In the embodiment, the edge 151 of the first doped region 15 towards the select gate structure 14 is aligned with the sidewall 144 of the select gate 14 towards the first doped region 15.

[0042] It should be noted that in other embodiments, in the horizontal direction of the first doped region towards the second doped region, the edge of the first doped region towards the select gate structure and the sidewall of the select gate structure towards the first doped region have a spacing greater than 0 nm and less than or equal to 800 nm. For example, the spacing can be 10 nm, 50 nm, 100 nm, 300 nm, 500 nm or 800 nm. When the spacing is within the range of 0 nm to 800 nm, it can not only ensure that the electric field between the first doped region and the select gate structure will not damage the select gate dielectric layer when the first doped region is subjected to a transient high voltage, but also ensure that the first doped region and the second doped region can normally conduct when the select gate is at a working voltage.

[0043] The substrate 11 further has an antifuse gate dielectric layer 132 and an antifuse gate 133 on the antifuse gate dielectric layer, and the antifuse gate dielectric layer 132 is on the first doped region 15 and the isolation structure 12. The first doped region 15, the antifuse gate dielectric layer 132 and the antifuse gate 133 constitute an antifuse transistor with a single-side source / drain, which functions as a capacitor. The antifuse transistor and the select transistor together constitute an antifuse memory cell.

[0044] For example, when the voltage drop across the antifuse transistor reaches 6V, the antifuse gate dielectric layer 132 will be dielectrically broken, and the data storage process of the antifuse memory cell is completed. It should be noted that in the embodiment, the antifuse gate dielectric layer 132 is partially located on the first doped region 15, so that after the dielectric breakdown of the antifuse gate dielectric layer 132, the direction of the current is unidirectional, the energy utilization rate is improved, and the electrical performance of the antifuse memory cell is enhanced.

[0045] In the embodiment, the material of the antifuse gate 133 and the material of the select gate 143 can be the same or different, and the material of the antifuse gate dielectric layer 132 and the material of the select gate dielectric layer 142 can be the same or different. In the embodiment, the material of the antifuse gate dielectric layer 132 and the material of the select gate dielectric layer 142 are taken as an example, and both are silicon oxide.

[0046] When the material of the antifuse gate dielectric layer 132 and the material of the select gate dielectric layer 142 are the same, the thickness of the antifuse gate dielectric layer 132 is less than or equal to the thickness of the select gate dielectric layer 142. In this way, it is effectively ensured that the select gate dielectric layer 142 will not be broken down before the antifuse gate dielectric layer 132 is broken down, so that the antifuse gate 133 can provide an effective voltage to the antifuse transistor, so that the antifuse transistor can be effectively broken down. If the thickness of the antifuse gate dielectric layer is greater than the thickness of the select gate dielectric layer, the select gate dielectric layer will be broken down before the antifuse gate dielectric layer is broken down, which will affect the breakdown effect of the antifuse transistor.

[0047] In addition, it should be noted that the spacing 112 between the sidewall of the antifuse gate 133 facing the select gate 143 and the sidewall of the select gate 143 facing the antifuse gate 133 is 400nm-800nm. For example, the spacing can be 400nm, 500nm, 600nm, 700nm or 800nm. The purpose of setting the spacing 112 range is to ensure that the potential difference between the antifuse gate 133 and the select gate 143 cannot break down the dielectric between them, avoid the antifuse gate 133 and the select gate 143 form an electrical connection, avoid the antifuse memory cell failure, and at the same time make the antifuse memory cell have smaller size, realize high integration.

[0048] The third doped region 17 serves as an LDD structure between the second doped region 19 and the select gate structure 14, and plays a role in reducing the electric field between the source and the drain. At the same time, since the third doped region 17 is located between the first doped region 15 and the second doped region 19, the third doped region 17 shortens the spacing between the source and the drain, thereby avoiding the hot electron effect.

[0049] Reference Figure 3 , Figure 3 is the equivalent working circuit of the antifuse memory cell of the first embodiment of the present application. In combination with the above description of the first embodiment of the present application, the working principle of the antifuse memory cell of the first embodiment of the present application is described. Figure 2and Figure 3 The anti-fuse gate 133, the anti-fuse gate dielectric layer 132 and the first doped region 15 form an anti-fuse transistor 41, which functions as a capacitor, and the first doped region 15, the second doped region 19 and the select gate structure 14 form a select transistor 43. Since no LDD structure is provided between the first doped region 15 and the select gate structure 14, an equivalent resistor 42 is connected in series between the first doped region 15 and the select gate structure 14, which can achieve a voltage dividing effect and weaken the electric field damage to the select gate dielectric layer 142, thereby improving the reliability of the select transistor 43 and the electrical performance of the anti-fuse memory cell.

[0050] In the first embodiment of the present application, no LDD structure is provided between the first doped region 15 and the select gate structure 14, and only the single-sided LDD structure between the second doped region 19 and the select gate structure 14, i.e. the third doped region 17, is reserved. Since the LDD structure increases the overlapping area of the strong electric field region between the select gate structure 14 and the first doped region 15, when no LDD structure is provided between the first doped region 15 and the select gate structure 14, the overlapping area of the strong electric field region formed by the transient high voltage on the first doped region 15 and the select gate structure 14 is reduced, thereby reducing the direct damage of the strong electric field to the anti-fuse gate dielectric layer 142. In addition, since no LDD structure is provided between the first doped region 15 and the select gate structure 14, an equivalent resistor is connected in series between the first doped region 15 and the select gate structure 14, which can achieve a voltage dividing effect and weaken the electric field damage to the select gate dielectric layer 142.

[0051] The second embodiment of the present application also provides an anti-fuse memory cell. Different from the previous embodiment, in the present embodiment, the anti-fuse memory cell further comprises a fourth doped region and a fifth doped region. The fourth doped region is located in the substrate and in contact with the first doped region, the fourth doped region is located between the first doped region and the select gate structure, and the doping ion type of the fourth doped region is different from that of the first doped region. The fifth doped region is located in the substrate and in contact with the second doped region, the fifth doped region is located below the third doped region, and the doping ion type of the fifth doped region is the same as that of the fourth doped region. The following will be described in detail with reference to the accompanying drawings. It should be noted that the same or corresponding features as the previous embodiments can refer to the corresponding description of the previous embodiments, which will not be described here.

[0052] Figure 4 A cross-sectional structure schematic diagram of the anti-fuse memory cell provided by the second embodiment of the present application.

[0053] Reference Figure 4The anti-fuse memory cell provided by the embodiment comprises: a substrate 31; a select gate structure 34; a first doped region 35 and a second doped region 39; an anti-fuse gate dielectric layer 332 and an anti-fuse gate 333; a third doped region 37; a fourth doped region, the fourth doped region 36 is located in the substrate 31 and is in contact with the first doped region 35, the fourth doped region 36 is located between the first doped region 35 and the select gate structure 34, and the doping ion type of the fourth doped region 36 is different from the doping ion type of the first doped region 35; a fifth doped region 38, the fifth doped region 38 is located in the substrate 31 and is in contact with the second doped region 39, the fifth doped region 38 is located below the third doped region 37, and the doping ion type of the fifth doped region 38 is the same as the doping ion type of the fourth doped region 36.

[0054] The third doped region 37 is an LDD structure of the anti-fuse memory cell. The fourth doped region 36 and the fifth doped region 38 are HALO (halo) regions of the anti-fuse memory cell.

[0055] The fourth doped region 36 is arranged to inhibit ion diffusion of the first doped region 35, thereby fixing a breakdown region on the edge of the first doped region 35. Since the breakdown voltage in the direction perpendicular to the edge is higher than the breakdown voltage of the select gate dielectric layer 342 in the direction perpendicular to the substrate, the arrangement of the fourth doped region 36 can improve the breakdown voltage and achieve the purpose of protecting the select gate structure 34.

[0056] In the embodiment, the depth of the fourth doped region 36 in the substrate 31 is greater than the depth of the first doped region 35 in the substrate 31. When the depth of the fourth doped region 36 in the substrate 31 is greater than the depth of the first doped region 35 in the substrate 31, the fourth doped region 36 can inhibit the diffusion of the doping ions in the first doped region 35 into the substrate 31 below the first doped region 35, thereby inhibiting the substrate leakage current caused by ion diffusion.

[0057] The fifth doped region 38 is used to inhibit the leakage current and source-drain punch-through problem caused by ion diffusion of the second doped region 39.

[0058] In the embodiment, the fourth doped region 36 inhibits ion diffusion of the first doped region 35, and the fifth doped region 38 inhibits ion diffusion of the second doped region 36. That is, the HALO region comprising the fourth doped region 36 and the fifth doped region 38 inhibits the leakage current and source-drain punch-through problem caused by ion diffusion of the first doped region 35 and the second doped region 36. In addition, the fourth doped region 36 is beneficial to solving the problem of resistance increase between the first doped region 35 and the second doped region 39 caused by the absence of the single-side LDD structure, so that the saturation current is increased and the reaction speed of the anti-fuse memory cell is increased.

[0059] In the embodiment, the LDD structure is not arranged between the first doped region 35 and the select gate structure 34, the area of the overlapping region between the strong electric field area of the first doped region 35 subjected to the instantaneous high voltage and the select gate structure 34 is reduced, and the direct damage of the strong electric field to the select gate dielectric layer 342 in the select gate structure 34 is reduced. In addition, since the LDD structure is not arranged between the first doped region 35 and the select gate structure 34, the resistance is connected in series between the first doped region 35 and the select gate structure 34, and the voltage division effect is achieved, and the damage of the electric field to the select gate dielectric layer 342 is weakened.

[0060] In addition, the anti-fuse memory cell has a fourth doped region 36 in contact with the first doped region 35 and a fifth doped region 38 in contact with the second doped region 39, and the HALO region composed of the fourth doped region 36 and the fifth doped region 38 plays a role in inhibiting the ion diffusion of the first doped region 35 and the second doped region 39, thereby inhibiting the leakage current and the source-drain punchthrough problem caused by the diffusion of the doped ions of the first doped region 35 and the second doped region 39. In addition, by arranging the fourth doped region 36 to inhibit the ion diffusion of the first doped region 35, the breakdown region can be fixed on the edge of the first doped region 35. Since the breakdown voltage in the direction perpendicular to the edge is higher than the breakdown voltage of the select gate dielectric layer in the direction perpendicular to the surface of the substrate, the arrangement of the fourth doped region can indirectly increase the breakdown voltage, thereby achieving the purpose of protecting the select gate structure.

[0061] Correspondingly, the embodiment of the present application further provides a manufacturing method of the anti-fuse memory cell, which comprises the following steps: providing a substrate, wherein the substrate has a select gate structure, and the substrate has a first doped region and a second doped region formed in the substrate on the opposite sides of the select gate structure, and the first doped region and the second doped region have the same type of doped ions; and forming a third doped region before forming the second doped region, wherein the third doped region is located in the substrate and in contact with the second doped region, the third doped region has the same type of doped ions as the second doped region, and the doped ion concentration of the third doped region is less than the doped ion concentration of the second doped region.

[0062] The manufacturing method of the anti-fuse memory cell provided by the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0063] Figures 5 to 8 The manufacturing method of the anti-fuse memory cell provided by the first embodiment of the present application is corresponding to the cross-sectional structure schematic diagram of each step. In the embodiment, the anti-fuse gate dielectric layer and the anti-fuse gate electrode are simultaneously formed in the process step of forming the select gate structure.

[0064] Referring to Figure 5 , a substrate 11 is provided, and a first doped region 15 is formed in the substrate 11 by using an ion implantation process.

[0065] The first doped region 15 serves as a source or a drain of a subsequent selected transistor, and also serves as a single-side source / drain of an antifuse transistor.

[0066] The forming process of the first doped region 15 includes: forming a patterned mask layer 102 on the surface of the substrate 11, the patterned mask layer 102 covering the surface of the substrate 11 except the surface of the substrate 11 corresponding to the first doped region 15 in the vertical direction; and performing ion implantation with the patterned mask layer 102 as a mask to form the first doped region 15.

[0067] In the embodiment, before forming the first doped region 15, a well region (not shown) and an isolation structure 12 are also formed. The doping ion type of the well region can be N-type or P-type, which is opposite to the type of the selected transistor in the antifuse memory cell. The material of the isolation structure can be oxide or nitride.

[0068] Referring to Figure 6 and Figure 7 The selected gate structure 14 is formed on the substrate 31, and the first doped region 15 is located in the substrate on one side of the selected gate structure 14; in the process step of forming the selected gate structure 14, the antifuse gate dielectric layer 132 and the antifuse gate 133 located on the antifuse gate dielectric layer 132 are simultaneously formed on the first doped region 15. The antifuse gate dielectric layer 132 is partially located on the first doped region 15.

[0069] The selected gate structure 14 includes a selected gate 143 and a selected gate dielectric layer 142. Specifically, the antifuse gate dielectric layer 132 is simultaneously formed in the process step of forming the selected gate dielectric layer 142; and the antifuse gate 133 is simultaneously formed in the process step of forming the selected gate 143.

[0070] In the embodiment, the antifuse gate dielectric layer 142 and the antifuse gate 143 are formed in the same process step as the selected gate structure 14. It should be noted that, in other embodiments, the antifuse gate dielectric layer and the antifuse gate and the selected gate structure can also be formed in different process steps.

[0071] The forming process steps of the anti-fuse gate dielectric layer 132, the anti-fuse gate 133 and the select gate structure 14 include: forming a dielectric layer 140 on the surface of the substrate 11, the dielectric layer 140 covers the first doped region 15, and the dielectric layer 140 provides a process basis for forming the anti-fuse gate dielectric layer 132 and the select gate dielectric layer 142; forming an anti-fuse gate (not shown) on the dielectric layer 140; forming a patterned mask on the anti-fuse gate; etching the anti-fuse gate and the dielectric layer 140 with the patterned mask as a mask, thereby forming adjacent and independent anti-fuse gate structures and the select gate structure 14, wherein the anti-fuse gate structure includes the anti-fuse gate 133 and the anti-fuse gate dielectric layer 132, and the select gate structure 14 includes the select gate 143 and the select gate dielectric layer 142.

[0072] The forming method of the dielectric layer 140 can be a conventional vacuum coating technology, such as furnace tube thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) process, and the like. The material of the anti-fuse gate can be polysilicon or metal, and the forming method thereof includes low-pressure chemical vapor deposition and physical vapor deposition.

[0073] In the embodiment, the first doped region 15 is formed before the anti-fuse gate dielectric layer 132 and the anti-fuse gate 133, so as to avoid damage to the anti-fuse gate 133 and the anti-fuse gate dielectric layer 132 caused by the ion implantation process for forming the first doped region 15, and ensure good performance of the anti-fuse gate 133 and the anti-fuse gate dielectric layer 132.

[0074] It should be noted that, in other embodiments, the forming process steps of the anti-fuse gate and the anti-fuse gate dielectric layer, and the forming process steps of the select gate structure, can also be formed in sequence. For example, the select gate structure and the first doped region are formed first, and then the anti-fuse gate dielectric layer and the anti-fuse gate are formed.

[0075] Reference Figure 8 The third doped region 17 is formed in the substrate 31 by using an ion implantation process.

[0076] The third doped region 17 serves as an LDD structure for connecting the second doped region to be formed subsequently.

[0077] The third doped region 17 is located on the opposite side of the select gate structure 14 away from the first doped region 15, the doping ion type of the third doped region 17 is the same as that of the first doped region 15, and the doping ion concentration of the third doped region 17 is lower than that of the first doped region 15.

[0078] The forming process of the third doped region includes: forming a patterned mask layer 103 on the surface of the substrate 11, the patterned mask layer 103 covers the surface of the substrate 11 except the surface of the substrate 11 corresponding to the third doped region 17 in the vertical direction; performing ion implantation with a certain implantation angle by taking the patterned mask layer 103 as a mask to form the third doped region 17.

[0079] It should be noted that the implantation angle mentioned in the present application refers to the angle of the deflection of the ion beam relative to the direction perpendicular to the surface of the semiconductor substrate, i.e., the angle between the ion beam and the vertical direction.

[0080] It should be noted that in other embodiments, before performing ion implantation of the third doped region, amorphization implantation can also be performed in the substrate on both sides of the select gate structure, so as to form an amorphous layer on the surface of the substrate. The amorphous layer can avoid channeling effect during ion implantation of the third doped region, and can better control the depth of ion implantation.

[0081] In the present embodiment, in order to avoid damage to the select gate structure 14 caused by the ion implantation process for forming the third doped region 17, a first side wall 141 is formed on the surface of the sidewall on the opposite side of the select gate structure 14 before the third doped region 17 is formed.

[0082] The forming process of the first side wall 141 includes: first forming a dielectric layer (not shown) on the surface of the substrate 11, the thickness of the dielectric layer is higher than the height of the select gate structure 14; performing etching back to form the first side wall 141 on both sides of the select gate structure 14.

[0083] The material of the first side wall 141 can be one of silicon oxide, silicon nitride, silicon oxynitride or a combination thereof, and the first side wall 141 plays a role of protecting the select gate structure 141. The dielectric layer can be formed by chemical vapor deposition or physical vapor deposition.

[0084] Referring to Figure 2 The second doped region 19 is formed in the substrate 11 on the side of the select gate structure 14, and the second doped region 19 and the first doped region 15 are respectively located on the opposite sides of the select gate structure 14.

[0085] The second doped region 19 is located in the substrate 11 on the opposite side of the select gate structure 14 away from the first doped region 15, the distance between the second doped region 19 and the first doped region 15 is greater than the distance between the second doped region 17 and the first doped region 15, and the type of the doping ions of the second doped region 19 is the same as that of the first doped region 15.

[0086] The process steps for forming the second doping region 19 include: first forming a patterned mask layer (not shown) on the surface of the substrate 11 ; and performing ion implantation using the patterned mask layer as a mask to form the second doping region 19 .

[0087] The first doped region 15 , the select gate structure 14 and the second doped region 19 constitute a select transistor.

[0088] The method for fabricating an antifuse memory cell provided in the first embodiment of the present invention does not provide an LDD structure between the first doped region 15 and the select gate structure 14, retaining only a single-sided LDD structure, i.e., the third doped region 17, between the second doped region 19 and the select gate structure 14. Because the presence of the LDD structure increases the overlap area of ​​the strong electric field region between the select gate structure 14 and the first doped region 15, when the LDD structure is not provided between the first doped region 15 and the select gate structure 14, the overlap area of ​​the strong electric field region formed by the transient high voltage to which the first doped region 15 is subjected and the select gate structure 14 is reduced, thereby reducing direct damage to the antifuse gate dielectric layer 142 caused by the strong electric field. Furthermore, since the LDD structure is not provided between the first doped region 15 and the select gate structure 14, an equivalent resistor is connected in series between the first doped region 15 and the select gate structure 14, achieving a voltage divider effect and reducing damage to the select gate dielectric layer 142 caused by the electric field.

[0089] Figure 9 A schematic cross-sectional structural diagram corresponding to an intermediate step of a method for manufacturing an anti-fuse memory cell provided in a second embodiment of the present invention.

[0090] It should be noted that for the same or corresponding fabrication steps as those in the first method embodiment, reference can be made to the corresponding description of the first method embodiment and will not be repeated here. The second method embodiment of the present invention differs from the first method embodiment in that the fourth doping region 36 and the fifth doping region 38 are formed before or after the third doping region 37 is formed, and then the second doping region 39 is formed.

[0091] like Figure 9 As shown, in this embodiment, before forming the third doping region 37 , a fourth doping region 36 and a fifth doping region 39 are formed in the substrate 31 .

[0092] The fourth doping region 36 is located in the substrate 31 and contacts the first doping region 35 . The fourth doping region 36 is located between the first doping region 35 and the select gate structure 14 . The doping ion type of the fourth doping region 36 is different from that of the first doping region 35 .

[0093] The fifth doped region 38 is formed at the same time as the fourth doped region 36, is located in the substrate 31 and contacts the second doped region 39, is located below the third doped region 37, and has the same type of doped ions as the fourth doped region 36.

[0094] The forming process of the fourth doped region 36 and the fifth doped region 38 includes: first forming a patterned mask layer 304 on the surface of the substrate 31, the patterned mask layer 304 covering the surface of the substrate 31 except for the surface of the substrate 31 corresponding to the fourth doped region 36 in the vertical direction; and performing ion implantation with the patterned mask layer 304 as a mask to form the fourth doped region 36 and the fifth doped region 38.

[0095] In this embodiment, the ion implantation dose of the fourth doped region 36 is 1E12 atom / cm2-5E13 atom / cm2, the implantation energy is 20 KeV-100 KeV, the implantation angle is 0°-45°, and the implantation depth is 30 nm-100 nm. It should be noted that the ion implantation process steps for forming the fourth doped region 36 and the fifth doped region 38 can be one step or multiple steps, which is determined according to the required doped ion concentration of the fourth doped region 36 and the fifth doped region 38.

[0096] In this embodiment, to avoid damage to the antifuse gate 333 and the antifuse gate dielectric layer 332 caused by the ion implantation process for forming the fourth doped region 36, a second side wall 331 is formed on the surface of the opposite sidewalls of the antifuse gate 333 and the antifuse gate dielectric layer 332 before the fourth doped region 36 is formed. The forming process of the second side wall 331 is the same as that of the first side wall 341, which will not be described here again. The material of the second side wall 331 can be the same as or different from that of the first side wall 341.

[0097] It should be noted that in the embodiment of the present application, after all the ion implantation processes are completed, annealing treatment is performed to activate the doped ions in each doped region and repair implantation damage. In the embodiment of the present application, annealing treatment can also be performed immediately after a single ion implantation process, and the doped ions in each doped region are activated and implantation damage is repaired through multiple annealing processes. The annealing treatment includes rapid thermal annealing or spike annealing process. The temperature of the annealing treatment is 950°C-1100°C, and the time is 10s-30s.

[0098] In the embodiment, the anti-fuse memory cell is further improved by forming the fourth doped region 36 and the fifth doped region 38. The formation of the fourth doped region 36 is beneficial to inhibit the ion diffusion of the first doped region 35, and thus fix the breakdown region on the edge of the first doped region 35. Since the breakdown voltage perpendicular to the edge direction is higher than the breakdown voltage of the select gate dielectric layer perpendicular to the substrate direction, the setting of the fourth doped region can increase the breakdown voltage, and thus achieve the purpose of protecting the select gate structure.

[0099] In addition, the setting of the fourth doped region 36 is beneficial to inhibit the ion diffusion of the first doped region 35, and the formation of the fifth doped region 38 is beneficial to inhibit the ion diffusion of the second doped region 36. That is, the HALO region including the fourth doped region 36 and the fifth doped region 38 can inhibit the leakage current and the source-drain punchthrough problem caused by the ion diffusion of the first doped region 35 and the second doped region 36. In addition, the fourth doped region 36 can compensate the problem of the increased resistance between the first doped region 35 and the second doped region 39 caused by the absence of the single-side LDD structure, and thus improve the reaction speed of the anti-fuse memory cell.

[0100] The embodiment of the present application provides a manufacturing method of an anti-fuse memory cell. A third doped region is arranged between the select gate structure and the second doped region, and the third doped region has the same type of doped ions as the second doped region. That is, no LDD structure is arranged between the first doped region and the select gate structure. When the dielectric breakdown of the anti-fuse gate dielectric layer occurs, the first doped region bears the transferred high voltage. Since the presence of the LDD structure can increase the overlapping area of the strong electric field region between the select gate structure and the first doped region, when no LDD structure is arranged between the first doped region and the select gate structure, the overlapping area of the strong electric field region formed by the instantaneous high voltage borne by the first doped region and the select gate structure is reduced, and thus the direct damage of the strong electric field to the select gate structure is reduced. In addition, since no LDD structure is arranged between the first doped region and the select gate structure, a resistance is connected in series between the first doped region and the select gate structure, and thus the voltage division effect can be achieved, and the electric field damage is weakened.

[0101] In addition, the fourth doped region is arranged between the first doped region and the select gate structure, and the fourth doped region has the different type of doped ions from the first doped region. That is, the fourth doped region is a HALO region. The setting of the fourth doped region is beneficial to inhibit the ion diffusion of the first doped region, and thus fix the breakdown region on the edge of the first doped region. Since the breakdown voltage perpendicular to the edge direction is higher than the breakdown voltage of the select gate dielectric layer perpendicular to the substrate direction, the setting of the fourth doped region can indirectly increase the breakdown voltage, and thus achieve the purpose of protecting the select gate structure.

[0102] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present application, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present application, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. An antifuse memory cell, characterized in that: include: a substrate having a select gate structure thereon; a first doped region and a second doped region, the first doped region and the second doped region being respectively located in the substrate on opposite sides of the select gate structure, the first doped region and the second doped region having the same doping ion type; in a horizontal direction from the first doped region toward the second doped region, a gap exists between the first doped region and the select gate structure, and no LDD structure is disposed between the first doped region and the select gate structure; an antifuse gate dielectric layer located on the substrate and an antifuse gate located on the antifuse gate dielectric layer, wherein the first doped region, the antifuse gate dielectric layer and the antifuse gate constitute an antifuse transistor; a third doping region, wherein the third doping region is located in the substrate and contacts the second doping region, the third doping region is located between the second doping region and the selection gate structure, the doping ion type of the third doping region is the same as the doping ion type of the second doping region, and the doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region.

2. The anti-fuse memory cell according to claim 1, wherein: The selection gate structure includes a selection gate dielectric layer and a selection gate located on the top surface of the selection gate dielectric layer; the material of the selection gate dielectric layer is the same as that of the anti-fuse gate dielectric layer; the thickness of the anti-fuse gate dielectric layer is less than or equal to the thickness of the gate dielectric layer.

3. The anti-fuse memory cell according to claim 1, wherein: The doping ion concentration of the first doping region is less than or equal to the doping ion concentration of the second doping region.

4. The anti-fuse memory cell according to claim 1, wherein: Also includes: A fourth doping region is located in the substrate and in contact with the first doping region, the fourth doping region is located between the first doping region and the selection gate structure, and the doping ion type of the fourth doping region is different from the doping ion type of the first doping region.

5. The anti-fuse memory cell according to claim 4, wherein: The fourth doping region is located in the substrate at a depth greater than the first doping region is located in the substrate.

6. The antifuse memory cell according to claim 4, wherein: Also includes: A fifth doping region is located in the substrate and in contact with the second doping region. The fifth doping region is located below the third doping region. The doping ion type of the fifth doping region is the same as the doping ion type of the fourth doping region.

7. The anti-fuse memory cell according to claim 1, wherein: The distance between the edge of the first doping region facing the select gate structure and the sidewall of the select gate structure facing the first doping region is greater than 0 and less than 10 nm.

8. The anti-fuse memory cell according to claim 1, wherein: The distance between the edge of the first doping region facing the selection gate structure and the sidewall of the selection gate structure facing the first doping region is 10 nm to 800 nm.

9. The anti-fuse memory cell according to claim 1, wherein: In a horizontal direction from the anti-fuse gate toward the select gate structure, a distance between the anti-fuse gate and the select gate structure is 400 nm to 800 nm.

10. The anti-fuse memory cell according to claim 1, wherein: The anti-fuse gate dielectric layer is partially located on the first doped region.

11. A method for manufacturing an anti-fuse memory cell, characterized in that: include: A substrate is provided, wherein the substrate has a select gate structure thereon, wherein a first doped region and a second doped region are respectively formed in the substrate on opposite sides of the select gate structure, wherein the first doped region and the second doped region have the same doping ion type, an anti-fuse gate dielectric layer is formed on the substrate, and an anti-fuse gate is formed on the anti-fuse gate dielectric layer, wherein the first doped region, the anti-fuse gate dielectric layer, and the anti-fuse gate constitute an anti-fuse transistor; and wherein a spacing is provided between the first doped region and the select gate structure in a horizontal direction toward the second doped region. A third doping region is formed before forming the second doping region. The third doping region is located in the substrate and contacts the second doping region. The third doping region and the second doping region have the same doping ion type, and the doping ion concentration of the third doping region is less than the doping ion concentration of the second doping region. No LDD structure is set between the first doping region and the selection gate structure.

12. The method for manufacturing an anti-fuse memory cell according to claim 11, wherein: In the process step of forming the select gate structure, the anti-fuse gate dielectric layer and the anti-fuse gate are formed simultaneously.

13. The method for manufacturing an anti-fuse memory cell according to claim 11, wherein: Before forming the selection gate structure, the first doped region is formed.

14. The method for manufacturing an anti-fuse memory cell according to claim 13, wherein: After forming the select gate structure, the second doped region is formed.

15. The method for manufacturing an anti-fuse memory cell according to claim 11, wherein: Also includes: A fourth doping region is formed, the fourth doping region is located in the substrate and contacts the first doping region, the fourth doping region is located between the first doping region and the select gate structure, and the fourth doping region and the first doping region have different doping ion types.

16. The method for manufacturing an anti-fuse memory cell according to claim 15, wherein: The ion implantation dose of the fourth doping region is 1E12atom / cm 2 ~5E13atom / cm 2 The injection energy is 20KeV~100KeV, the injection angle is 0°~45°, and the injection depth is 30nm~100nm.

17. The method for manufacturing an anti-fuse memory cell according to any one of claims 15 to 16, wherein: Also includes: A fifth doping region is formed, the fifth doping region is formed simultaneously with the fourth doping region, the fifth doping region is located in the substrate and in contact with the second doping region, the fifth doping region is located below the third doping region, and the fifth doping region and the fourth doping region have the same doping ion type.

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