Shift register and driving method thereof, gate driving circuit and display device

Abstract

The present disclosure provides a shift register and a driving method thereof, a gate drive circuit, and a display device. The shift register includes an input circuit, an output control circuit, a first output circuit, and a second output circuit. The input circuit controls the level of a first node under the control of a second clock signal. The output control circuit controls the level of a second node under the control of the level of the first node. The first output circuit controls the level of a third node under the control of the level of the second node and the first clock signal, and outputs a first output signal at a first output terminal. The second output circuit outputs a second output signal at a second output terminal that is the inverse of the level of the first output signal under the control of the level of the third node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0002] With the development of organic light-emitting display technology, LTPO (Low Temperature Polycrystalline Oxide) has gained widespread adoption due to its advantages, including high resolution, high response speed, high brightness, high aperture ratio, low production cost, and low power consumption. LTPO pixel circuits incorporate oxide transistors in addition to polysilicon transistors. This requires providing two sets of scanning signals with opposite voltage levels to the pixel circuit to enable pixel charging on and off. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a shift register and a driving method thereof, a gate driving circuit and a display device, which can simultaneously provide two groups of output signals with inverted levels, effectively reduce the number of shift register groups, and facilitate the realization of a narrow frame.

[0004] In a first aspect of the present disclosure, a shift register is provided, comprising: an input circuit electrically connected to an input terminal, a second clock terminal and a first node, configured to control the level of the first node under the control of a second clock signal provided by the second clock terminal; an output control circuit electrically connected to the first node and the second node, configured to control the level of the second node under the control of the level of the first node; a first output circuit electrically connected to the first clock terminal, the second clock terminal, the second node and a third node, configured to control the level of the third node under the control of the level of the second node and the first clock signal provided by the first clock terminal, wherein the third node is electrically connected to a first output terminal, and the first output terminal is configured to output a first output signal; a second output circuit electrically connected to the third node and the second output terminal, configured to output a second output signal at the second output terminal under the control of the level of the third node, and the second output signal is inverted in level to the first output signal.

[0005] In some embodiments, the input circuit includes: a first transistor, wherein a control electrode of the first transistor is electrically connected to the second clock terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

[0006] In some embodiments, the first transistor is an N-type transistor.

[0007] In some embodiments, the input circuit further includes: a first capacitor, one end of the first capacitor is electrically connected to the first voltage terminal, and the other end of the first capacitor is electrically connected to the first node.

[0008] In some embodiments, the output control circuit includes: a second transistor, the control electrode of the second transistor is electrically connected to the first node, the first electrode is electrically connected to the first voltage terminal, and the second electrode is electrically connected to the second node; a third transistor, the control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the second voltage terminal, and the conduction level of the third transistor is different from that of the second transistor.

[0009] In some embodiments, one of the second transistor and the third transistor is a P-type transistor, and the other is an N-type transistor.

[0010] In some embodiments, the first output circuit includes: a first control subcircuit, electrically connected to the third node and the first clock terminal, configured to control the level of the third node under the control of the first clock signal; a second control subcircuit, electrically connected to the second node, the third node and the second clock terminal, configured to control the level of the third node under the control of the level of the second node; and a storage subcircuit, electrically connected to the second node and the third node, configured to store the level of the third node.

[0011] In some embodiments, the first control subcircuit includes: a fourth transistor, the control electrode of the fourth transistor is electrically connected to the first clock terminal, the first electrode is electrically connected to the second clock terminal or the first voltage terminal, and the second electrode is electrically connected to the third node.

[0012] In some embodiments, the second control subcircuit includes: a fifth transistor, the control electrode of the fifth transistor is electrically connected to the second node, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the second clock end; the conduction level of the fifth transistor is the same as that of the fourth transistor.

[0013] In some embodiments, the storage sub-circuit includes a second capacitor, one end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the third node.

[0014] In some embodiments, the above-mentioned shift register also includes: a compensation circuit, electrically connected to the first node, the first clock end, the second clock end and the third node, configured to compensate for the level of the third node under the control of the level of the first node, the first clock signal and the second clock signal.

[0015] In some embodiments, the compensation circuit includes: an eighth transistor, the control electrode of the eighth transistor is electrically connected to the first node, and the first electrode is electrically connected to the second clock end; a ninth transistor, the control electrode of the ninth transistor is electrically connected to the second electrode of the eighth transistor, and the first electrode is electrically connected to the first clock end; a tenth transistor, the control electrode of the tenth transistor is electrically connected to the first clock end, the first electrode is electrically connected to the second electrode of the ninth transistor, and the second electrode is electrically connected to the third node; the conduction level of the tenth transistor is different from that of the eighth transistor and the ninth transistor.

[0016] In some embodiments, the second output circuit includes: an eleventh transistor, wherein the control electrode of the eleventh transistor is electrically connected to the first voltage terminal, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the fourth node; a sixth transistor, wherein the control electrode of the sixth transistor is electrically connected to the fourth node, the first electrode is electrically connected to the first voltage terminal, and the second electrode is electrically connected to the second output terminal; a seventh transistor, wherein the control electrode of the seventh transistor is electrically connected to the fourth node, the first electrode is electrically connected to the second voltage terminal, and the second electrode is electrically connected to the second output terminal; and a twelfth transistor, wherein the control electrode of the twelfth transistor is electrically connected to the second electrode of the ninth transistor, the first electrode is electrically connected to the second voltage terminal, and the second electrode is electrically connected to the second output terminal. The conduction level of the sixth transistor is different from that of the seventh transistor, the eleventh transistor, and the twelfth transistor.

[0017] In some embodiments, the sixth transistor is a P-type transistor, and the seventh transistor, the eleventh transistor, and the twelfth transistor are N-type transistors; the first voltage provided by the first voltage terminal is greater than the second voltage provided by the second voltage terminal, and the first voltage is greater than the high-level voltage of the second clock signal provided by the second clock terminal, and is less than the high-level voltage of the first clock signal provided by the first clock terminal.

[0018] In some embodiments, the second output circuit includes: a sixth transistor, the control electrode of the sixth transistor is electrically connected to the third node, the first electrode is electrically connected to the first voltage terminal, and the second electrode is electrically connected to the second output terminal; a seventh transistor, the control electrode of the seventh transistor is electrically connected to the third node, the first electrode is electrically connected to the second output terminal, and the second electrode is electrically connected to the second voltage terminal; the first voltage provided by the first voltage terminal is greater than the second voltage provided by the second voltage terminal, and the conduction levels of the sixth transistor and the seventh transistor are different.

[0019] In some embodiments, the seventh transistor is a dual-gate transistor including a top gate and a bottom gate. The top gate of the seventh transistor is electrically connected to the third node as a control electrode, and the bottom gate is electrically connected to the second voltage terminal.

[0020] In some embodiments, the third transistor is a dual-gate transistor including a top gate and a bottom gate, the top gate of the seventh transistor is electrically connected to the first node as a control electrode, and the bottom gate is electrically connected to the second voltage terminal.

[0021] In a second aspect of the present disclosure, a gate driving circuit is provided, comprising at least two cascaded shift registers as described in the first aspect of the present disclosure.

[0022] In a third aspect of the present disclosure, a display device is provided, comprising the gate drive circuit described in the second aspect of the present disclosure and a plurality of sub-pixels arranged in an array, the sub-pixels comprising pixel circuits, the first output terminal and the second output terminal of each shift register in the gate drive circuit being electrically connected to the pixel circuits of the sub-pixels in the same row, the pixel circuits comprising at least one N-type transistor and at least one P-type transistor.

[0023] In a fourth aspect of the present disclosure, a driving method for a shift register is provided, which is applied to the shift register described in the first aspect of the present disclosure, and the method includes: the input circuit charges the first node through the input signal provided by the input end under the control of the second clock signal; the output control circuit controls the level of the second node under the control of the level of the first node; the first output circuit outputs a first output signal at the first output end under the control of the level of the second node and the first clock signal provided by the first clock end; the second output circuit outputs a second output signal, which is inverted to the level of the first output signal, at the second output end under the control of the first output signal.

[0024] The shift register provided in some embodiments of the present disclosure controls the level of the first node under the control of the second clock signal through the input circuit, controls the level of the second node under the control of the level of the first node through the output control circuit, controls the level of the third node under the control of the level of the second node and the first clock signal provided by the first clock end, and outputs the first output signal at the first output end, and the second output circuit outputs the second output signal with the level inverted of the first output signal at the second output end under the control of the level of the third node, so that two groups of scanning signals with inverted levels can be provided to the LTPO pixel circuit through a group of gate drive circuits, which is beneficial to reducing the number of gate drive circuit groups and reducing the border width.

[0025] The above description is only an overview of the technical solutions of some embodiments of the present disclosure. In order to more clearly understand the technical means of the embodiments of the present disclosure, they can be implemented in accordance with the contents of the specification. In order to make the embodiments of the present disclosure more obvious and easy to understand, the specific implementation methods of some embodiments of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are intended only to illustrate exemplary embodiments and are not to be considered as limiting the embodiments of the present disclosure. The same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0027] Figure 1 A schematic structural diagram of a display device according to some embodiments of the present disclosure is shown;

[0028] Figure 2 A schematic plan view of a display panel according to some embodiments of the present disclosure is shown;

[0029] Figure 3 A circuit diagram of an exemplary LTPO pixel circuit is shown;

[0030] Figure 4 A schematic structural diagram of a gate driving circuit according to some embodiments of the present disclosure is shown;

[0031] Figure 5 A schematic structural diagram of a shift register according to some embodiments of the present disclosure is shown;

[0032] Figure 6 shows a timing diagram of a shift register according to some embodiments of the present disclosure;

[0033] Figure 7 A circuit diagram of a shift register according to some embodiments of the present disclosure is shown;

[0034] Figures 8 to 13 Shown respectively Figure 7 The shift register shown in Figure 6 Working status diagram of the t1-t6 period;

[0035] Figure 14 Schematic diagrams showing the structures of shift registers according to other embodiments of the present disclosure are shown;

[0036] Figure 15 shows a circuit diagram of a shift register according to some other embodiments of the present disclosure;

[0037] Figure 16 shows a circuit diagram of a shift register according to some further embodiments of the present disclosure;

[0038] Figure 17 Shown Figure 16 Timing diagram of the shift register in;

[0039] Figures 18 to 21 Shown respectively Figure 16 The shift register in Figure 17 Working status diagram of the t1'-t4' period. DETAILED DESCRIPTION

[0040] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "one", "an" or "the" and similar words do not indicate quantity limitations, but rather indicate the existence of at least one. "At least one" includes one or more cases. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0042] In some embodiments of the present disclosure, the transistor may be a thin film transistor (TFT), a field effect transistor (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0043] In some embodiments of the present disclosure, the control electrode of a transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor can be structurally symmetrical, their source and drain can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in some embodiments of the present disclosure can be structurally indistinguishable. For example, the first electrode of the transistor can be the source, and the second electrode can be the drain.

[0044] In some embodiments of the present disclosure, an "operating level" refers to a voltage that can turn on an operated transistor included therein, and correspondingly, a "non-operating level" refers to a level that cannot turn on the operated transistor included therein (i.e., the transistor is cut off). Typically, for a square wave pulse signal used by a shift register during operation, the operating level corresponds to the level of the square wave pulse portion of the square wave pulse signal, while the non-operating level corresponds to the level of the non-square wave pulse portion.

[0045] In some embodiments of the present disclosure, the first node, the second node, etc. do not represent actual components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes that are equivalent to the junction points of related electrical connections in the circuit diagram.

[0046] It should be noted that in some embodiments of the present disclosure, controlling the level of a node (e.g., the first node Qa) includes charging the node to increase the level of the node, or discharging the node to decrease the level of the node. For example, a capacitor electrically connected to the node may be provided. Charging the node means charging the capacitor electrically connected to the node; similarly, discharging the node means discharging the capacitor electrically connected to the node; the high or low level of the node can be maintained by the capacitor.

[0047] Figure 1 Schematic diagram of the structure of the display device of some embodiments of the present disclosure is shown. Figure 1 As shown, some embodiments of the present disclosure provide a display device 1, which can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. For example, the display device 1 can be a display screen, a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or any other product or component with a display function.

[0048] like Figure 1As shown, the display device 1 includes a display panel 10. The display panel 10 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, a micro light emitting diode (MicroLED) display panel, etc., and the present disclosure does not make any specific limitations on this.

[0049] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 10 as an OLED display panel as an example.

[0050] Figure 2 Schematic diagram of a plan view of a display panel according to some embodiments of the present disclosure is shown. Figure 2 As shown, the display panel 10 may include a display region DR and a peripheral region NR. The display region DR is the area of ​​the display panel 10 used to display images, and the peripheral region NR is the area of ​​the display panel 10 other than the display region DR. The peripheral region NR may be located on at least one side (e.g., one side, or multiple sides) of the display region DR. For example, the peripheral region NR may be disposed around the display region DR.

[0051] The display region DR is provided with sub-pixels of multiple luminous colors, each of which can display a single color. For example, the sub-pixels of multiple luminous colors may include a first sub-pixel p1 that emits a first color, a second sub-pixel p2 that emits a second color, and a third sub-pixel p3 that emits a third color. The first, second, and third colors are three primary colors, such as red, blue, and green.

[0052] For the sake of convenience, the above-mentioned multiple sub-pixels are described in this disclosure as being arranged in an array. In this case, sub-pixels arranged in a row along the horizontal direction X can be referred to as sub-pixels in the same row; sub-pixels arranged in a column along the vertical direction Y can be referred to as sub-pixels in the same column. Figure 2 As shown, the display panel 10 further includes a plurality of scan lines GL and a plurality of data lines DL. The plurality of scan lines GL and the plurality of data lines DL intersect with each other to define a plurality of pixel areas distributed in an array in the display region DR.

[0053] Each sub-pixel includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light. The control electrode of the same transistor in the pixel circuit of the sub-pixels in the same row is electrically connected to the same scan line GL. The first electrode (e.g., source electrode) of the data write transistor in the pixel circuit of the sub-pixels in the same column is electrically connected to the same data line DL.

[0054] In some embodiments, the above-mentioned pixel circuit includes multiple electronic components such as transistors and capacitors. For example, the pixel circuit may include three transistors and one capacitor, forming a 3T1C (i.e., one driving transistor, two switching transistors and one capacitor). For another example, the pixel driving circuit may also include more than three transistors and at least one capacitor, such as 4T1C (i.e., one driving transistor, three switching transistors and one capacitor), 5T1C (i.e., one driving transistor, four switching transistors and one capacitor), 7T1C (i.e., one driving transistor, six switching transistors and one capacitor) or 8T1C (i.e., one driving transistor, seven switching transistors and one capacitor), etc. These transistors in the pixel circuit may be low-temperature polysilicon thin film transistors, or oxide thin film transistors, or low-temperature polysilicon thin film transistors and oxide thin film transistors.

[0055] Among them, the active layer of the low-temperature polysilicon thin-film transistor adopts low-temperature polysilicon (English: Low Temperature Poly-Silicon, abbreviated as: LTPS), and the active layer of the oxide thin-film transistor adopts oxide semiconductor (English: Oxide), such as indium gallium zinc oxide, indium gallium tin oxide, etc. Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. The LTPO pixel circuit includes at least one low-temperature polysilicon thin-film transistor (i.e., P-type transistor) and at least one oxide thin-film transistor (i.e., N-type transistor), which can take advantage of the advantages of both to achieve low-frequency driving and reduce power consumption, which is conducive to improving display quality.

[0056] Figure 3 A circuit diagram of an exemplary LTPO pixel circuit is shown. Figure 3 Taking a pixel driving circuit including eight transistors and one capacitor as an example, the LTPO pixel circuit is schematically described. In the following description, a pixel circuit is any one of the pixel circuits located in the Nth row of sub-pixels, where N is a positive integer.

[0057] like Figure 3As shown, the control electrodes of the first transistor T1' and the seventh transistor T7' in the pixel circuit are electrically connected to the reset signal terminal Reset, the control electrode of the second transistor T2' is electrically connected to the first scan signal terminal Gate1, the control electrode of the third transistor T3' is electrically connected to the N1 node, the control electrode of the fourth transistor T4' is electrically connected to the second scan signal terminal Gate2, the control electrodes of the fifth transistor T5' and the sixth transistor T6' are electrically connected to the emission control signal terminal EM, and the control electrode of the eighth transistor T8' is electrically connected to the third scan signal terminal Gate3. The first electrode of the first transistor T1' is electrically connected to the first initialization voltage terminal Vint1, and the second electrode of the first transistor T1', the second electrode of the second transistor T2', and one end of the capacitor C are electrically connected to the N1 node. The other end of the capacitor C and the first electrode of the fifth transistor T5' are electrically connected to the power supply voltage terminal VDD. The first electrode of the second transistor T2' is electrically connected to the second electrode of the third transistor T3' and the first electrode of the sixth transistor T6'. A first electrode of the third transistor T3', a second electrode of the fourth transistor T4', a second electrode of the fifth transistor T5', and a second electrode of the eighth transistor T8' are electrically connected. A first electrode of the fourth transistor T4' is electrically connected to the data voltage terminal Vdata. A second electrode of the sixth transistor T6' and a second electrode of the seventh transistor T7' are connected to the anode of the light-emitting element. A first electrode of the seventh transistor T7' is electrically connected to the second initialization voltage terminal Vint2. A first electrode of the eighth transistor T8' is electrically connected to the third initialization voltage terminal Vint3.

[0058] Among them, the first transistor T1', the seventh transistor T7', and the eighth transistor T1' are reset transistors, the second transistor T2' is a compensation transistor, the third transistor T3' is a drive transistor, the fourth transistor T4' is a data write transistor, and the fifth transistor T5' and the sixth transistor T6' are light-emitting control transistors. T1' and T2' are N-type oxide thin-film transistors, and T3', T4', T5', T6', T7', and T8' are P-type polysilicon thin-film transistors.

[0059] It should be noted that the first scan signal terminal Gate1 of the pixel circuit in the sub-pixel in row N is coupled to the scan line GL_n(N), and the second scan signal terminal Gate2 of the pixel circuit in the sub-pixel in row N is coupled to the scan line GL_p(N). The scan line GL_n(N) transmits a first scan signal suitable for N-type transistors to the first scan signal terminal Gate1. The scan line GL_p(N) transmits a second scan signal suitable for P-type transistors to the second scan signal terminal Gate2.

[0060] like Figure 2As shown, the display panel 10 may further include a gate drive circuit SC and a data drive circuit DC located in the peripheral region NR. In some embodiments, the gate drive circuit SC may be arranged on the side along the extension direction of the scan line GL, and the data drive circuit DC may be arranged on the side along the extension direction of the data line DL to drive the pixel circuit in the display panel 10 to display. The gate drive circuit SC is connected to the pixel circuit through the scan line GL to provide a scan signal, and the data drive circuit DC is connected to the pixel circuit through the data line DL to provide a data signal. The gate drive circuit SC may be arranged unilaterally, as shown in FIG. Figure 2 Alternatively, it can be set on both sides, depending on the actual product needs.

[0061] In some embodiments, the gate driver circuit SC may be a GOA (Gate Driver on Array) circuit, that is, the gate driver circuit SC is directly integrated into the array substrate of the display panel 10. The following embodiments are all described using the gate driver circuit SC as a GOA circuit as an example.

[0062] In some embodiments, the gate drive circuit SC may include at least two cascaded shift registers G. For example, Figure 4 The schematic diagram of the gate drive circuit of some embodiments of the present disclosure is shown. The gate drive circuit SC includes N cascaded shift registers (G1, G2, ..., G(N)). In each adjacent shift register, the signal input terminal INPUT of the next-stage shift register Gi is electrically connected to the shift output terminal CR of the previous-stage shift register Gi-1, where i is 2 to N. The signal input terminal INPUT of the first-stage shift register G1 is electrically connected to the frame start signal line STV.

[0063] The display panel 10 may further include a plurality of clock signal lines, for example, Figure 4 The first clock signal line CK1 and the second clock signal line CK2 shown, the first clock signal clk1 transmitted by the first clock signal line CK1 and the second clock signal clk2 transmitted by the second clock signal line CK2 can be alternately applied to N cascaded shift registers (G1, G2...G(N)). For example, the first clock signal clk1 can be applied to the first clock terminal CLK1 of the odd-numbered stages, and the second clock signal clk2 can be applied to the second clock terminal CLK2 of the odd-numbered stages. The second clock signal clk2 can be applied to the first clock terminal CLK1 of the even-numbered stages, and the first clock signal clk1 can be applied to the second clock terminal CLK2 of the even-numbered stages.

[0064] If the pixel circuit of a sub-pixel is an LTPO pixel circuit, a gate driver circuit SC is required to provide a first scan signal for an N-type transistor and a second scan signal for a P-type transistor. If a set of gate driver circuits SC can only output one set of scan signals, two sets of gate driver circuits SC are required to output the first scan signal and the second scan signal, respectively. This requires more border width, which is not conducive to the development of narrow borders for products.

[0065] Therefore, in order to reduce the number of gate drive circuits SC required to be provided in the border area, thereby minimizing the border width, it is proposed to output the first scanning signal and the second scanning signal simultaneously through a group of gate drive circuits SC. Figure 4 As shown, each shift register includes: a first output terminal OUTPUT1 and a second output terminal OUTPUT2, which output a first output signal and a second output signal. In the case where the pixel circuit is an LTPO pixel circuit, the first output terminal OUTPUT1 and the second output terminal OUTPUT2 of each shift register in the gate drive circuit are electrically connected to the pixel circuits of the sub-pixels in the same row, and can simultaneously provide the pixel circuits of the sub-pixels in the row with a first scan signal (applicable to N-type transistors) and a second scan signal (applicable to P-type transistors). Figure 3 Taking the LTPO pixel circuit shown as an example, the first output terminal OUTPUT1 and the second output terminal OUTPUT2 of the shift register can be electrically connected to the first scan signal terminal Gate1 and the second scan signal terminal Gate2 of the pixel circuit of the same row of sub-pixels through the scan line GL_n and the scan line GL_p respectively.

[0066] Figure 5 FIG2 shows a schematic structural diagram of a shift register according to some embodiments of the present disclosure. Figure 6 1 shows a timing diagram of a shift register of some embodiments of the present disclosure. Figure 5 As shown, the shift register 100 provided by some embodiments of the present disclosure includes: an input circuit 110 , an output control circuit 120 , a first output circuit 130 , and a second output circuit 140 .

[0067] The input circuit 110 is electrically connected to the input terminal INPUT, the second clock terminal CLK2 and the first node Qa. The input circuit 110 is configured to control the level of the first node Qa under the control of the second clock signal clk2 provided by the second clock terminal CLK2.

[0068] For example, under the control of the second clock signal clk2, the input circuit 110 charges the first node Qa through the input signal provided by the input terminal INPUT. When the input signal is at a non-working level, the first node Qa is controlled to also output the non-working level. When the input signal jumps from the non-working level to the working level, the first node Qa is controlled to also output the working level. When the input signal jumps from the working level to the non-working level again, the first node Qa is controlled to maintain outputting the above-mentioned working level. When the input signal continues to be a non-working level, the first node Qa is controlled to output the working level.

[0069] Figure 6 Taking the working level of the input signal as a high level as an example, during the period t1 to t2, the input signal is a low level, and the input circuit 110 can control the first node Qa to output a low level. During the period t3, the input signal is a high level, and the input circuit 110 can control the first node Qa to output a high level. During the period t4, the input signal jumps to a low level, and the input circuit 110 can control the first node Qa to maintain the output high level. From the period t5 to the end of the scan of the current frame, the input signal is a low level, and the input circuit 110 can control the first node Qa to output a low level.

[0070] The output control circuit 120 is electrically connected to the first node Qa and the second node Qb. The output control circuit 120 is configured to control the level of the second node under the control of the level of the first node. When the first node Qa outputs a high level, the second node Qb outputs a low level. When the first node Qa outputs a low level, the second node Qb outputs a high level.

[0071] For example, the output control circuit 120 may also be connected to a first voltage terminal VGH and a second voltage terminal VGL, where the first voltage terminal provides a first voltage that is greater than a second voltage provided by the second voltage terminal VGL. When the first node Qa is at a low level, the output control circuit 120 transmits the first voltage provided by the first voltage terminal VGH to the second node Qb, thereby raising the level of the second node Qb, i.e., causing the second node Qb to be at a high level. When the first node Qa is at a high level, the output control circuit 120 transmits the second voltage provided by the second voltage terminal VGL to the second node Qb, thereby lowering the level of the second node Qb, i.e., causing the second node Qb to be at a low level.

[0072] It should be noted that the high-level voltage value of the first node Qa and the low-level voltage value of the second node Qb may be the same or different, and the low-level voltage value of the first node Qa and the high-level voltage value of the second node Qb may be the same or different, depending on the voltage value of the signal transmitted to the first node Qa and the second node Qb.

[0073] For example, in the embodiment of the present disclosure, the low-level voltage value of the second clock terminal CLK2 can be: -12 to -10.56V, for example, it can be -12V, -11V or -10.56V, and the high-level voltage value can be: 6 to 6.5V, for example, it can be 6V, 6.2V or 6.5V, etc.; the low-level voltage value of the first clock terminal CLK1 can be: -11.5 to -10.6V, for example, it can be -11.5V, -11V or -10.6V, etc., and the high-level voltage value can be: 6.6 to 7.2V, for example, it can be 6.6V, 7V or 7.2V, etc.; the voltage value of the first voltage terminal VGH can be: 6.5 to 7V, for example, it can be 6.5V, 6.8V or 7V, etc.; the voltage value of the second voltage terminal VGL can be: -12V to -10.8V, for example, it can be -12V, -11V or -10.8V, etc.

[0074] The first output circuit 130 is electrically connected to a first clock terminal CLK1, a second clock terminal CLK2, a second node Qb, and a third node Qc. The first output circuit 130 is configured to control the level of the third node Qc under the control of the level of the second node Qb and the first clock signal clk1 provided by the first clock terminal CLK1. The third node Qc is electrically connected to a first output terminal OUTPUT1. The first output terminal OUTPUT1 is configured to output a first output signal.

[0075] For example, when the second node Qb is at a low level, or when the second node Qb is at a high level and the first clock signal clk1 is at a low level, the first output circuit 130 transmits the second clock signal clk2 to the third node Qc, and the level of the third node Qc is consistent with the level of the second clock signal clk2; and when the second node Qb is at a high level and the first clock signal clk1 is at a high level, the first output circuit 130 can control the third node Qc to maintain the level of the previous moment.

[0076] In some embodiments, the first clock signal clk1 and the second clock signal clk2 are square wave signals with alternating high and low levels. When the first clock signal clk1 is at a high level, the second clock signal clk2 is at a low level. When the first clock signal clk1 is at a low level, the second clock signal clk2 is at a high level. Figure 6As shown, the high level period and low level period of the first clock signal clk1 may overlap with the low level period and high level period of the second clock signal clk2, respectively. Of course, in other embodiments, the duty cycle of the first clock signal clk1 may be different from the duty cycle of the second clock signal clk2. When the first clock signal clk1 is at a high level, the second clock signal clk2 is at a low level. When the first clock signal clk1 jumps from a high level to a low level, the second clock signal clk2 may first maintain a low level and then jump to a high level, and jump back to a low level before the first clock signal clk1 jumps from a low level to a high level.

[0077] The second output circuit 140 is electrically connected to the third node Qc and the second output terminal OUTPUT2. The second output circuit 140 is configured to output a second output signal at the second output terminal OUTPUT2 under the control of the level of the third node Qc.

[0078] The second output signal output by the second output terminal OUTPUT2 is in phase with the first output signal output by the first output terminal OUTPUT1. "In phase with each other" means that when the second output signal is high, the first output signal is low, and when the second output signal is low, the first output signal is high. In other words, the high and low periods of the second output signal overlap with the low and high periods of the first output signal, respectively.

[0079] For example, the second output circuit 140 is further electrically connected to the first voltage terminal VGH and the second voltage terminal VGL. When the third node Qc is at a low level, the second output circuit 140 transmits the first voltage of the first voltage terminal VGH to the second output terminal OUTPUT2, causing the second output terminal OUTPUT2 to output a high level. When the third node Qc is at a high level, the second output circuit 140 transmits the second voltage of the second voltage terminal VGL to the second output terminal OUTPUT2, causing the second output terminal OUTPUT2 to output a low level.

[0080] like Figure 6 As shown, taking the working level of the input signal as a high level as an example, the input signal jumps from a low level to a high level in the t3 period, and jumps from a high level back to a low level in the t4 period. The first node Qa is a high level in the t3 and t4 periods, and the second node Qb is a low level in the t3 and t4 periods. Under the control of the first clock signal clk1 and the second clock signal clk2, the first output signal maintains a high level in the t3 period, and the second output signal maintains a low level in the t3 period. After the levels of the first clock signal clk1 and the second clock signal clk2 are flipped in the t4 period, the first output signal jumps to a low level and the second output signal jumps to a high level, thereby realizing shift registration.

[0081] Therefore, by setting the above-mentioned input circuit 110, output control circuit 120, first output circuit 130 and second output circuit 140, the first output signal and the second output signal with inverted levels can be output simultaneously, which is beneficial to reducing the number of GOA groups and reducing the border width.

[0082] In some embodiments, the second output terminal OUTPUT2 may include a scan signal output terminal Gout1 and a shift output terminal CR, so that the second output signal is output to the scan signal output terminal Gout1 and the shift output terminal CR, respectively, to improve the driving capability of the shift register 100. For example, the shift output terminal CR is used to provide an input signal for the next-stage shift register 100 and a reset signal for the previous-stage shift register 100 unit, and the scan signal output terminal Gout1 is used to provide a scan signal for the pixel circuit of a row of sub-pixels in the display panel. The first output terminal OUTPUT1 can serve as another scan signal output terminal Gout2, used to provide another scan signal for the pixel circuit of a row of sub-pixels in the display panel. For example, the two scan signal output terminals Gout1 and Gout2 can be respectively Figure 3 The first scan signal terminal Gate1 and the second scan signal terminal Gate2 in the LTPO pixel circuit shown provide scan signals.

[0083] Figure 7 FIG. 1 shows a circuit diagram of a shift register 100 according to some embodiments of the present disclosure. Figure 7 As shown, the input circuit 110 may include a first transistor T1 , a control electrode of the first transistor T1 electrically connected to the second clock terminal CLK2 , a first electrode electrically connected to the input terminal INPUT, and a second electrode electrically connected to the first node Qa.

[0084] For example, the first transistor T1 may be an N-type transistor, such as an oxide thin film transistor. Since the operating level of the N-type transistor is a high level, when the second clock signal clk provided by the second clock terminal CLK2 is a high level, the first transistor T1 is turned on, and the input signal provided by the input terminal INPUT is transmitted to the first node Qa. When the second clock signal clk2 provided by the second clock terminal CLK2 is a low level, the first transistor T1 is turned off.

[0085] like Figure 7 As shown, the input circuit 110 may further include a first capacitor C1, one end of the first capacitor C1 being electrically connected to the first voltage terminal VGH, and the other end being electrically connected to the first node Qa. When the first transistor T1 is turned off, the voltage of the first capacitor C1 can maintain the voltage level of the first node Qa at the previous moment.

[0086] For example, during period t2, the second clock signal clk2 is at a low level, the first transistor T1 is turned off, and due to the voltage holding effect of the first capacitor C1, the first node Qa can still maintain the low level of the previous moment (period t1).

[0087] like Figure 7 As shown, the output control circuit 120 may include a second transistor T2 and a third transistor T3. The control electrode of the second transistor T2 is electrically connected to the first node Qa, the first electrode is electrically connected to the first voltage terminal VGH, and the second electrode is electrically connected to the second node Qb. The control electrode of the third transistor T3 is electrically connected to the first node Qa, the first electrode is electrically connected to the second node Qb, and the second electrode is electrically connected to the second voltage terminal VGL. The third transistor T2 and the second transistor T3 have different conduction levels, that is, one of the second and third transistors is a P-type transistor and the other is an N-type transistor. In this way, under the control of the voltage level of the first node Qa, the second and third transistors can be selectively turned on, achieving the inversion of the voltage levels of the second node Qb and the first node Qa. That is, when the first node Qa is at a high level, the second node Qb is at a low level, and when the first node Qa is at a low level, the second node Qb is at a high level.

[0088] Figure 7 Taking the second transistor T2 as a P-type transistor and the third transistor T3 as an N-type transistor as an example, when the first node Qa is at a low level, the second transistor T2 is turned on, the third transistor T3 is turned off, and the second node Qb is at a high level; when the first node Qa is at a high level, the second transistor T2 is turned off, the third transistor T3 is turned on, and the second node Qb is at a low level.

[0089] In some embodiments, Figure 7 The third transistor T3 can be a dual-gate transistor, including a top gate and a bottom gate, wherein the top gate is electrically connected to the first node Qa as the control electrode of the third transistor T3, and the bottom gate is electrically connected to the second voltage terminal VGL, so that a stable low level is connected to the bottom gate, which is beneficial to improving the threshold drift and ensuring the stability of the signal of the first node Qa.

[0090] like Figure 7 As shown, the first output circuit 130 may include: a first control subcircuit 131 and a second control subcircuit 132 .

[0091] The first control sub-circuit 131 is electrically connected to the third node Qc and the first clock terminal CLK1 , and is configured to control the level of the third node Qc under the control of the first clock signal clk1 .

[0092] For example, the first control sub-circuit 131 can also be electrically connected to the second clock terminal CLK2 or the first voltage terminal VGH. When the first clock signal clk1 provided by the first clock terminal CLK1 is the operating level of the first control sub-circuit 131, the first control sub-circuit 131 is turned on and the second clock terminal CLK2 or the first voltage terminal VGH is transmitted to the third node Qc to pull up the level of the third node Qc.

[0093] like Figure 7 As shown, the first control subcircuit 131 may include a fourth transistor T4, whose control electrode is electrically connected to the first clock terminal CLK1, the first electrode is electrically connected to the second clock terminal CLK2 or the first voltage terminal VGH, and the second electrode is electrically connected to the third node Qc.

[0094] The second control sub-circuit 132 is electrically connected to the second node Qb, the third node Qc and the second clock terminal CLK2, and is configured to control the level of the third node Qc under the control of the level of the second node Qb.

[0095] For example, when the level of the second node Qb is the operating level of the second control subcircuit 132 , the second control subcircuit 132 is turned on to transmit the second clock signal clk2 to the third node Qc to control the level of the third node Qc.

[0096] like Figure 7 As shown, the second control subcircuit 132 may include a fifth transistor T5 , a control electrode of the fifth transistor T5 electrically connected to the second node Qb, a first electrode electrically connected to the third node Qc, and a second electrode electrically connected to the second clock terminal CLK2 .

[0097] It should be noted that the conduction levels of the fourth transistor and the fifth transistor are the same. “The same conduction level” means that both are high-level conduction or low-level conduction, and does not limit the voltage value of the conduction level. The voltage values ​​of the conduction levels can be the same, or there can be differences. For example, when the operating level of the input signal is high, the fourth transistor and the fifth transistor can be P-type transistors, such as Figure 6 As shown, accordingly, the operating level of the first output signal is a low level, and the operating level of the second output signal is a high level. For another example, when the operating level of the input signal is a low level, the fourth transistor and the fifth transistor can also be N-type transistors, and the first clock terminal CLK1 and the second clock terminal CLK2 to which they are connected are swapped. Accordingly, the operating level of the first output signal is a high level, and the operating level of the second output signal is a low level.

[0098] In some embodiments, the first output circuit 130 may further include a storage sub-circuit 133. The storage sub-circuit 133 is electrically connected to the second node Qb and the third node Qc and is configured to store the level of the third node Qc. The storage sub-circuit 133 can maintain the level of the third node Qc at a previous moment when the first control sub-circuit 131 and the second control sub-circuit 132 are disconnected.

[0099] like Figure 7 As shown, the storage subcircuit 133 may include a second capacitor C2, one end of which is electrically connected to the second node Qb, and a second end of which is electrically connected to the third node Qc. Due to the voltage retention effect of the second capacitor C2, when the first control subcircuit 131 and the second control subcircuit 132 are disconnected, the third node Qc maintains the voltage level at the previous moment.

[0100] For example, see Figure 6 and Figure 7 In the period t2, the second node Qb is at a high level, the first clock signal clk1 is at a high level, the fourth transistor T4 and the fifth transistor T5 are turned off, and due to the voltage holding effect of the second capacitor C2, the third node Qc maintains the high level of the previous moment.

[0101] like Figure 7 As shown, the second output circuit 140 may include a sixth transistor T6 and a seventh transistor T7. The sixth transistor T6 has a control electrode electrically connected to the third node Qc, a first electrode electrically connected to the first voltage terminal VGH, and a second electrode electrically connected to the second output terminal OUTPUT2. The seventh transistor T7 has a control electrode electrically connected to the third node Qc, a first electrode electrically connected to the second output terminal OUTPUT2, and a second electrode electrically connected to the second voltage terminal VGL.

[0102] The sixth transistor T6 and the seventh transistor T7 have different conduction levels, ie, one is high-level and the other is low-level. For example, one of the sixth transistor T6 and the seventh transistor T7 is a P-type transistor and the other is an N-type transistor. Figure 7 In the figure, the sixth transistor T6 is a P-type transistor and the seventh transistor T7 is an N-type transistor.

[0103] In some embodiments, in order to pull down the level of the second output terminal OUTPUT2, Figure 7 The seventh transistor T7 needs to remain in the on state for a long time, and its threshold voltage is prone to negative drift. The seventh transistor T7 can be a dual-gate transistor, including a top gate and a bottom gate. The top gate serves as the control electrode of the seventh transistor T7 and is electrically connected to the third node Qc, and the bottom gate is electrically connected to the second voltage terminal VGL. By connecting a constant low level to the bottom gate, the negative drift problem caused by long-term on-state is alleviated, which is conducive to improving the stability of the signal output.

[0104] Figure 7 The illustrated embodiment uses seven transistors (T1 to T7) and two capacitors (C1 and C2), wherein T1, T3, and T7 are N-type transistors, and T2, T4, T5, and T6 are P-type transistors. This can effectively reduce the number of transistors included in the shift register 100 on the basis of simultaneously outputting a first output signal and a second output signal with inverted levels, thereby facilitating further reduction in the border width of the product.

[0105] Figures 8 to 13 Shown respectively Figure 7 The shift register 100 shown in FIG. Figure 6 Working status diagram of the t1-t6 period. Figures 8 to 13 The transistors marked with slashes in the figure indicate that they are cut off during this period, and the transistors not marked with slashes indicate that they are turned on during this period. Figure 6 as well as Figures 8 to 13 ,right Figure 7 The working principle of the shift register 100 shown is described below.

[0106] See Figure 6 and Figure 8 In the t1 period, the first clock terminal CLK1 is at a low level, the second clock terminal CLK2 is at a high level, and the input terminal INPUT inputs a low level. At this time, the first transistor T1 is turned on, and the second voltage of the second voltage terminal VGL is written into the first node Qa, and the first node Qa outputs a low level. The second transistor is turned on, the third transistor T3 is turned off, and the second node Qb outputs a high level, so that the fifth transistor T5 is turned off. The T4 transistor is turned on, and the high level of the second clock terminal CLK2 is written into the third node Qc by the fourth transistor T4, that is, the first output terminal OUTPUT1 (i.e. Figure 6 and Figure 8 The sixth transistor T6 is turned off, the seventh transistor T7 is turned on, and the second output terminal OUTPUT2 (i.e. Figure 6 and Figure 8 That is, during the period t1, the voltage relationship between the first node Qa, the second node Qb, the third node Qc, the first output terminal OUTPUT1, and the second output terminal OUTPUT2 is: Qa=VGL, Qb=VGH, Qc=OUTPUT1=VGH, OUTPUT2=CR=VGL.

[0107] See Figure 6 and Figure 9In the period t2, the first clock terminal CLK1 is at a high level, the second clock terminal CLK2 is at a low level, and the input terminal INPUT still maintains a low level. At this time, the first transistor T1 is turned off. Due to the voltage maintenance effect of the first capacitor C1, the first node Qa maintains the low level of the previous moment. The second transistor T2 is turned on, the third transistor T3 is turned off, and the second node Qb outputs a high level. The fourth transistor T4 and the fifth transistor T5 are turned off. The third node Qc on the right side of the second capacitor C2 maintains the high level of the previous moment due to the voltage maintenance effect of the second capacitor C2, that is, the first output terminal OUTPUT1 (i.e. Figure 6 and Figure 9 The sixth transistor T6 is turned off, the seventh transistor T7 is turned on, and the second output terminal OUTPUT2 (i.e. Figure 6 and Figure 9 That is, during period t1, the first node Qa, the second node Qb, the third node Qc, the first output terminal OUTPUT1, and the second output terminal OUTPUT2 can maintain the level of period t1, Qc=OUTPUT1=VGH, OUTPUT2=CR=VGL.

[0108] See Figure 6 and Figure 10 In the t3 period, the first clock terminal CLK1 is at a low level, the second clock terminal CLK2 is at a high level, and the input terminal INPUT inputs a high level. At this time, the first transistor T1 is turned on, and the first node Qa outputs a high level. The second transistor T2 is turned off, the third transistor T3 is turned on, the second node Qb outputs a low level, the fifth transistor T5 is turned on, and at the same time, CLK1 is at a low level, so that the fourth transistor T4 is turned on, and the third node Qc outputs a high level, that is, the first output terminal OUTPUT1 (i.e. Figure 6 and Figure 10 The sixth transistor T6 is turned off, the seventh transistor T7 is turned on, and the second output terminal OUTPUT2 (i.e. Figure 6 and Figure 10 That is, during the period t3, the voltage relationships among the first node Qa, the second node Qb, the third node Qc, the first output terminal OUTPUT1, and the second output terminal OUTPUT2 are: Qa=VGH, Qb=VGL, Qc=OUTPUT1=VGH, OUTPUT2=CR=VGL.

[0109] See Figure 6 and Figure 11, in the t4 period, the first clock terminal CLK1 is at a high level, the second clock terminal CLK2 is at a low level, and the input terminal INPUT turns to a low level. The first transistor T1 is turned off, and due to the voltage maintenance effect of the first capacitor C1, the first node Qa maintains the high level of the previous moment. The second transistor T2 is turned off, the third transistor T3 is turned on, and the second node Qb outputs a low level. The fourth transistor T4 is turned off, the fifth transistor T5 is turned on, and the third node Qc outputs a low level, that is, the first output terminal OUTPUT1 (i.e. Figure 6 and Figure 11 The sixth transistor T6 is turned on, the seventh transistor T7 is turned off, and the second output terminal OUTPUT2 (i.e. Figure 6 and Figure 11 Thus, compared with the high level inputted by the input terminal INPUT during the t3 period, the first output terminal OUTPUT1 and the second output terminal OUTPUT2 realize shift registration.

[0110] See Figure 6 and Figure 12 In the t5 period, the first clock terminal CLK1 is at a low level, the second clock terminal CLK2 is at a high level, and the input terminal INPUT inputs a low level. The first transistor T1 is turned on, and the first node Qa outputs a low level. The second transistor T2 is turned on, the third transistor T3 is turned off, and the second node Qb outputs a high level. The fourth transistor is turned on, the fifth transistor T5 is turned off, and the third node Qc outputs a high level, that is, the first output terminal OUTPUT1 (i.e. Figure 6 and Figure 12 The sixth transistor T6 is turned off, the seventh transistor T7 is turned on, and the second output terminal OUTPUT2 (i.e. Figure 6 and Figure 12 Gout1 and CR in the output are low level.

[0111] See Figure 6 and Figure 13 , in the t6 period, the first clock terminal CLK1 is at a high level, the second clock terminal CLK2 is at a low level, and the input terminal INPUT inputs a low level. The first transistor T1 is turned off, and due to the voltage maintenance effect of the first capacitor C1, the first node Qa maintains the low level of the previous moment. The second transistor T2 is turned on, the third transistor T3 is turned off, and the second node Qb outputs a high level. The fourth transistor T4 and the fifth transistor T5 are turned off, and due to the voltage maintenance effect of the second capacitor C2, the third node Qb maintains the high level of the previous moment. That is, the first output terminal OUTPUT1 (i.e. Figure 6 and Figure 13 The sixth transistor T6 is turned off, the seventh transistor T7 is turned on, and the second output terminal OUTPUT2 (i.e. Figure 6 and Figure 13 In other words, due to the voltage maintenance effect of the first capacitor C1 and the second capacitor C2, the levels of the main nodes Qa, Qb, and Qc do not change, and thus the output remains unchanged. During the display period of the same frame, as time passes, the pulses of the first clock terminal CLK1 and the second clock terminal CLK2 change, but because the level of the input terminal INPUT does not change, it will not cause the level of the first output terminal OUTPUT1 and the second output terminal OUTPUT2 to change.

[0112] Figure 14 Schematic diagrams of the structure of the shift register 100 of other embodiments of the present disclosure are shown. Figure 14 As shown, in Figure 5 On the basis of the shift register 100 provided in the corresponding embodiment, the shift register 100 may further include a compensation circuit 150. The compensation circuit 150 is electrically connected to the first node Qa, the first clock terminal CLK1, the second clock terminal CLK2, and the third node Qc, and is configured to compensate for the level of the third node Qc under the control of the level of the first node Qa, the first clock signal clk1, and the second clock signal clk2.

[0113] For example, Figure 6 As shown, when the working level of the input signal is high, the working level of the first output signal output by the first output terminal OUTPUT1 is low, and the working level of the second output signal output by the second output terminal OUTPUT2 is high, within the display period of one frame of image, the third node Qc, i.e., the first output signal, needs to be at a high level for a relatively long time. By setting the compensation circuit 150, the level of the third node Qc is pulled up for compensation, which is beneficial to ensure that the third node Qc, i.e., the first output signal, stably outputs a high level during the non-working period, and reduces the risk of leakage of the transistor in the connected pixel circuit due to the inability of the third node Qc to stably maintain a high level during the non-working period, i.e., the inability of the first output terminal OUTPUT1 to stably maintain a high level.

[0114] Figure 15 FIG. 1 shows a circuit diagram of a shift register 100 according to some other embodiments of the present disclosure. Figure 15 The embodiment shown in Figure 7 On the basis of the illustrated embodiment, a compensation circuit 150 is additionally provided.

[0115] like Figure 15As shown, the compensation circuit 150 may include an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The control electrode of the eighth transistor T8 is electrically connected to the first node Qa, and the first electrode is electrically connected to the second clock terminal CLK2. The control electrode of the ninth transistor T9 is electrically connected to the second electrode of the eighth transistor T8, and the first electrode is electrically connected to the first clock terminal CLK1. The control electrode of the tenth transistor T10 is electrically connected to the first clock terminal CLK1, the first electrode is electrically connected to the second electrode of the ninth transistor T9, and the second electrode is electrically connected to the third node Qc.

[0116] In some embodiments, the conduction level of the tenth transistor T10 is different from that of the eighth transistor T8 and the ninth transistor T9. Figure 15 As shown, the tenth transistor T10 may be an N-type transistor, and the eighth transistor T8 and the ninth transistor T9 may be P-type transistors.

[0117] Taking the tenth transistor T10 as an N-type transistor, the eighth transistor T8 and the ninth transistor (T5-1) as P-type transistors as an example, when the first clock terminal CLK1 is at a high level, the second clock terminal CLK2 is at a low level, the fourth transistor T4 and the fifth transistor T5 are turned off, and the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are turned on, the high level of the first clock terminal CLK1 can be transmitted to the third node Qc via the ninth transistor T9 and the tenth transistor T10, thereby further ensuring the voltage maintenance function of the second capacitor C2 on the basis of the third node Qc and the first output terminal OUTPUT1 (i.e. Figure 15 The stability of the high level output of Gout2).

[0118] In some other embodiments, when the above-mentioned compensation circuit 150 is set, the storage sub-circuit 133 in the first output circuit 130, such as the second capacitor C2, may not be required. When the first control sub-circuit 131 and the second control sub-circuit 132 are disconnected, the compensation circuit 150 controls the level of the third node Qc, which can actually be set as needed.

[0119] Figure 16 shows a circuit diagram of a shift register 100 according to some further embodiments of the present disclosure; Figure 17 Shown Figure 16 1 is a timing diagram of the shift register 100 in FIG. Figure 16 The embodiment shown in Figure 15 On the basis of the illustrated embodiment, an eleventh transistor T11 and a twelfth transistor T12 are additionally provided.

[0120] exist Figure 16In the illustrated embodiment, the second output circuit 140 may include: an eleventh transistor T11, a sixth transistor T6, a seventh transistor T7, and a twelfth transistor T12. The control electrode of the eleventh transistor T11 is electrically connected to the first voltage terminal VGH, the first electrode is electrically connected to the third node Qc, and the second electrode is electrically connected to the fourth node Qc'. The control electrode of the sixth transistor T6 is electrically connected to the fourth node Qc', the first electrode is electrically connected to the first voltage terminal VGH, and the second electrode is electrically connected to the second output terminal OUTPUT2 (i.e., Figure 16 The control electrode of the seventh transistor T7 is electrically connected to the fourth node Qc', the first electrode is electrically connected to the second voltage terminal VGL, and the second electrode is electrically connected to the second output terminal OUTPUT2. The control electrode of the twelfth transistor T12 is electrically connected to the second electrode of the ninth transistor T9, the first electrode is electrically connected to the second voltage terminal VGL, and the second electrode is electrically connected to the second output terminal OUTPUT2 (i.e. Figure 16 Gout1 and CR in are electrically connected.

[0121] The conduction level of the sixth transistor T6 is different from that of the seventh transistor T7 , the eleventh transistor T11 , and the twelfth transistor T12 . Figure 16 In the example, the sixth transistor T6 is a P-type transistor, and the seventh transistor T7, the eleventh transistor T11, and the twelfth transistor T12 are N-type transistors. In this case, the first voltage provided by the first voltage terminal VGH is greater than the high-level voltage of the second clock signal provided by the second clock terminal CLK2, and less than the high-level voltage of the first clock signal provided by the first clock terminal CLK1. Thus, when the third node Qc outputs the high-level voltage provided by the first clock terminal CLK1, the voltage difference between the control electrode and the first electrode of the eleventh transistor T11 (i.e., Vgs) is less than 0, thereby turning off the eleventh transistor T11. When the third node Qc outputs the high-level voltage provided by the second clock terminal CLK2, the voltage difference between the control electrode and the first electrode of the eleventh transistor T11 is greater than 0, thereby turning on the eleventh transistor T11.

[0122] By adding the eleventh transistor T11 and the twelfth transistor T12, two output channels can be provided for the low level of the second output terminal OUTPUT2, thereby realizing the alternating operation of the seventh transistor T7 and the twelfth transistor T12, which is beneficial to further ensure the stability of the signal output by the second output terminal OUTPUT2.

[0123] It should be noted that in Figure 15 and Figure 16 In a corresponding embodiment, the first electrode of the fourth transistor T4 can be connected to the first voltage terminal VGH, such as Figure 15 and Figure 16 As shown, alternatively, the second clock terminal CLK2 can also be connected.

[0124] Figures 18 to 21 Shown respectively Figure 16 The shift register 100 in Figure 17 Working status diagram of the t1'-t4' period. Figures 18 to 21 The transistors marked with slashes in the figure indicate that they are cut off during this period, and the transistors not marked with slashes indicate that they are turned on during this period. Figure 17 as well as Figures 18 to 21 ,right Figure 15 The working principle of the shift register 100 shown in FIG is described. Figure 16 Compared to Figure 7 The newly added transistor states at different time periods are explained. Figure 7 The same parts will not be repeated here.

[0125] like Figure 17 and Figure 18 In the period t1', the first clock terminal CLK1 is at a low level, the second clock terminal CLK2 is at a high level, and the input terminal INPUT inputs a low level. At this time, the first node Qa is at a low level, the eighth transistor (T3-1) is turned on, the ninth transistor T9, the tenth transistor T10, and the twelfth transistor T12 are turned off, the fourth transistor T4 is turned on, and the third node Qc outputs a high level provided by the first voltage terminal VGH, that is, the first output terminal OUTPUT1 (i.e. Figure 17 and Figure 18 The Gout2 in the figure also outputs a high level provided by the first voltage terminal VGH. The control electrode of the eleventh transistor T11 also receives the high level provided by the first voltage terminal VGH. The voltage difference between the control electrode and the first electrode (i.e., Vgs) is equal to 0. The eleventh transistor T11 is turned on, the fourth node Qc' outputs a high level, the seventh transistor T7 is turned on, and the low level provided by the second voltage terminal VGL is transmitted to the second output terminal OUTPUT2 (i.e., Figure 17 and Figure 18 Gout1 and CR) output in.

[0126] like Figure 17 and Figure 19 In the period t2', the first clock terminal CLK1 is at a high level, the second clock terminal CLK2 is at a low level, and the input terminal INPUT still maintains a low level. At this time, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are turned on. On the basis of the voltage holding effect of the second capacitor C2, the high level provided by the first clock terminal CLK1 is transmitted to the third node Qc via the ninth transistor T9 and the tenth transistor T10, and the third node Qc is pulled up for compensation, so that the first output terminal OUTPUT1 (i.e. Figure 17 and Figure 19Gout2 in the figure can stably output the high level provided by the first clock terminal CLK1. At the same time, since the control electrode voltage of the eleventh transistor T11 is less than the first electrode voltage (Vgs is less than 0), the eleventh transistor T11 is turned off, thereby turning off the sixth transistor T6 and the seventh transistor T7, and the twelfth transistor T12 is turned on, and the low level provided by the second voltage terminal VGL is transmitted to the second output terminal OUTPUT2 (i.e. Figure 17 and Figure 19 Gout1 and CR) output in.

[0127] like Figure 17 and Figure 20 In the t3' period, the first clock terminal CLK1 is at a low level, the second clock terminal CLK2 is at a high level, and the input terminal INPUT inputs a high level. At this time, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, and the twelfth transistor T12 are turned off, and the eleventh transistor T11 and the seventh transistor T7 are turned on. The third node Qc and the first output terminal OUTPUT1 (i.e. Figure 17 and Figure 20 The low level provided by the second voltage terminal VGL is transmitted to the second output terminal OUTPUT2 (i.e., Figure 17 and Figure 20 Gout1 and CR) output in.

[0128] like Figure 17 and Figure 21 In the t4' period, the first clock terminal CLK1 is at a high level, the second clock terminal CLK2 is at a low level, and the input terminal INPUT turns to a low level. At this time, the eighth transistor T8, the ninth transistor T9, the seventh transistor T7, and the twelfth transistor T12 are turned off, and the tenth transistor T10, the eleventh transistor T11, and the sixth transistor T6 are turned on. The third node Qc and the first output terminal OUTPUT1 (i.e. Figure 17 and Figure 21 Gout2 in the output terminal OUTPUT2) outputs the low level provided by the second clock terminal CLK2, and the second output terminal OUTPUT2 (ie Figure 17 and Figure 21 Gout1 and CR in the output are high level provided by the first voltage terminal VGH, thereby realizing shift register.

[0129] Since the first voltage provided by the first voltage terminal VGH is lower than the high level voltage of the first clock signal provided by the first clock terminal CLK1, Figure 17 The high-level voltage output by Gout2 during the t2' period is slightly higher than the high-level voltage output during the t1' period and the t3' period.

[0130] In some embodiments, the shift register 100 may further include a reset circuit (not shown in the figure) electrically connected to the reset terminal (not shown in the figure) and the third node Qc. The reset circuit is configured to reset the third node under the control of a reset signal provided by the reset terminal, thereby resetting the signals at the first output terminal OUTPUT1 and the second output terminal OUTPUT2.

[0131] For example, in Figure 7 、 Figure 15 as well as Figure 16 Based on the corresponding embodiment, the reset circuit may include a thirteenth transistor (not shown in the figure), the control electrode of the thirteenth transistor is electrically connected to the reset terminal, the first electrode is electrically connected to the first voltage terminal VGH, and the second electrode is electrically connected to the third node Qc. When the level input to the reset terminal controls the thirteenth transistor to be turned on, the high level voltage of the first voltage terminal VGH is input to the third node Qc, resetting the third node Qc.

[0132] For example, when the display device is turned on, the reset terminal can be controlled to provide an operating voltage level that turns on the thirteenth transistor, thereby resetting the third node Qc of each stage of the shift register 100. At other times, the reset terminal can be controlled to provide a non-operating voltage level, thereby turning off the thirteenth transistor. For another example, the reset terminal can be controlled to provide an operating voltage level that turns on the thirteenth transistor after each frame of scanning is completed, thereby resetting the third node Qc of each stage of the shift register 100 after each frame of scanning is completed.

[0133] In addition, some embodiments of the present disclosure further provide a shift register driving method, which can be used to drive the shift register 100 provided by the embodiments of the present disclosure. The driving method includes: the input circuit 110 charges the first node Qa through the input signal provided by the input terminal INPUT under the control of the second clock signal clk2 provided by the second clock terminal CLK2; the output control circuit 120 controls the level of the second node Qb under the control of the level of the first node Qa; the first output circuit 130 outputs a first output signal at the first output terminal OUTPUT1 under the control of the level of the second node Qb and the first clock signal clk1 provided by the first clock terminal CLK1; and the second output circuit 140 outputs a second output signal at the second output terminal OUTPUT2 that is inverted to the level of the first output signal under the control of the first output signal.

[0134] It should be noted that, for a detailed description of the driving method and technical effects of the shift register 100 provided in the embodiment of the present disclosure, reference can be made to the description of the working principle of the shift register 100 in the embodiment of the present disclosure, which will not be repeated here.

[0135] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. The scope of protection of the present disclosure should be based on the scope of protection of the claims. Those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. Those skilled in the art will understand that the combination of features of different embodiments is within the scope of the present disclosure and forms different embodiments.

Claims

1. A shift register, characterized in that: include: an input circuit electrically connected to the input terminal, the second clock terminal, and the first node, and configured to control the level of the first node under the control of a second clock signal provided by the second clock terminal; an output control circuit electrically connected to the first node and the second node, and configured to control the level of the second node under the control of the level of the first node; a first output circuit electrically connected to the first clock terminal, the second clock terminal, the second node, and a third node, and configured to control the level of the third node under the control of the level of the second node and the first clock signal provided by the first clock terminal, wherein the third node is electrically connected to the first output terminal, and the first output terminal is configured to output a first output signal; The second output circuit is electrically connected to the third node and the second output end, and is configured to output a second output signal at the second output end under the control of the level of the third node, wherein the level of the second output signal is inverted to that of the first output signal.

2. The shift register according to claim 1, wherein: The input circuit includes a first transistor, wherein a control electrode of the first transistor is electrically connected to the second clock terminal, a first electrode is electrically connected to the input terminal, and a second electrode is electrically connected to the first node.

3. The shift register according to claim 2, wherein: The first transistor is an N-type transistor.

4. The shift register according to claim 1, wherein: The input circuit further includes: a first capacitor, one end of the first capacitor is electrically connected to the first voltage terminal, and the other end of the first capacitor is electrically connected to the first node.

5. The shift register according to claim 1, wherein: The output control circuit includes: a second transistor, wherein a control electrode of the second transistor is electrically connected to the first node, a first electrode is electrically connected to the first voltage terminal, and a second electrode is electrically connected to the second node; A third transistor, wherein the control electrode of the third transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the second voltage terminal, and the conduction level of the third transistor is different from that of the second transistor.

6. The shift register according to claim 5, wherein: One of the second transistor and the third transistor is a P-type transistor, and the other is an N-type transistor.

7. The shift register according to claim 1, wherein: The first output circuit includes: a first control subcircuit, electrically connected to the third node and the first clock terminal, and configured to control the level of the third node under the control of the first clock signal; a second control subcircuit, electrically connected to the second node, the third node, and the second clock terminal, and configured to control the level of the third node under the control of the level of the second node; The storage sub-circuit is electrically connected to the second node and the third node, and is configured to store the level of the third node.

8. The shift register according to claim 7, wherein: The first control subcircuit includes: a fourth transistor, wherein the control electrode of the fourth transistor is electrically connected to the first clock terminal, the first electrode is electrically connected to the second clock terminal or the first voltage terminal, and the second electrode is electrically connected to the third node.

9. The shift register according to claim 8, wherein: The second control subcircuit includes: a fifth transistor, the control electrode of the fifth transistor is electrically connected to the second node, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the second clock end; the conduction level of the fifth transistor is the same as that of the fourth transistor.

10. The shift register according to claim 7, wherein: The storage sub-circuit includes a second capacitor, one end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the third node.

11. The shift register according to claim 1, wherein: Also includes: A compensation circuit is electrically connected to the first node, the first clock end, the second clock end and the third node, and is configured to compensate for the level of the third node under the control of the level of the first node, the first clock signal and the second clock signal.

12. The shift register according to claim 11, wherein: The compensation circuit comprises: an eighth transistor, wherein a control electrode of the eighth transistor is electrically connected to the first node, and a first electrode of the eighth transistor is electrically connected to the second clock terminal; a ninth transistor, wherein a control electrode of the ninth transistor is electrically connected to the second electrode of the eighth transistor, and a first electrode of the ninth transistor is electrically connected to the first clock terminal; a tenth transistor, wherein a control electrode of the tenth transistor is electrically connected to the first clock terminal, a first electrode of the tenth transistor is electrically connected to the second electrode of the ninth transistor, and a second electrode of the tenth transistor is electrically connected to the third node; The tenth transistor has a different conduction level from that of the eighth transistor and the ninth transistor.

13. The shift register according to claim 12, wherein: The second output circuit includes: an eleventh transistor, wherein a control electrode of the eleventh transistor is electrically connected to the first voltage terminal, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to the fourth node; a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the fourth node, a first electrode of the sixth transistor is electrically connected to the first voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second output terminal; a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the fourth node, a first electrode is electrically connected to the second voltage terminal, and a second electrode is electrically connected to the second output terminal; a twelfth transistor, wherein a control electrode of the twelfth transistor is electrically connected to the second electrode of the ninth transistor, a first electrode of the twelfth transistor is electrically connected to the second voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the second output terminal; The sixth transistor has a different conduction level from the seventh transistor, the eleventh transistor, and the twelfth transistor.

14. The shift register according to claim 13, wherein: The sixth transistor is a P-type transistor, and the seventh transistor, the eleventh transistor and the twelfth transistor are N-type transistors; the first voltage provided by the first voltage terminal is greater than the second voltage provided by the second voltage terminal, the first voltage is greater than the high-level voltage of the second clock signal provided by the second clock terminal, and is less than the high-level voltage of the first clock signal provided by the first clock terminal.

15. The shift register according to any one of claims 1 to 12, characterized in that: The second output circuit includes: a sixth transistor, wherein a control electrode of the sixth transistor is electrically connected to the third node, a first electrode is electrically connected to the first voltage terminal, and a second electrode is electrically connected to the second output terminal; a seventh transistor, wherein a control electrode of the seventh transistor is electrically connected to the third node, a first electrode is electrically connected to the second output terminal, and a second electrode is electrically connected to the second voltage terminal; A first voltage provided by the first voltage terminal is greater than a second voltage provided by the second voltage terminal, and conduction levels of the sixth transistor and the seventh transistor are different.

16. The shift register according to claim 15, wherein: The seventh transistor is a dual-gate transistor including a top gate and a bottom gate. The top gate of the seventh transistor serves as a control electrode and is electrically connected to the third node, and the bottom gate is electrically connected to the second voltage terminal.

17. The shift register according to claim 5, wherein: The third transistor is a dual-gate transistor including a top gate and a bottom gate. The top gate of the third transistor serves as a control electrode and is electrically connected to the first node, and the bottom gate is electrically connected to the second voltage terminal.

18. A gate drive circuit, characterized in that: A shift register comprising at least two cascaded shift registers according to any one of claims 1 to 17.

19. A display device, characterized in that: It comprises the gate drive circuit according to claim 18 and a plurality of sub-pixels arranged in an array, wherein the sub-pixels include pixel circuits, the first output terminal and the second output terminal of each shift register in the gate drive circuit are electrically connected to the pixel circuits of the sub-pixels in the same row, and the pixel circuits include at least one N-type transistor and at least one P-type transistor.

20. A shift register driving method, characterized in that: Applied to the shift register according to any one of claims 1 to 17, the method comprising: The input circuit charges the first node through the input signal provided by the input terminal under the control of the second clock signal provided by the second clock terminal; The output control circuit controls the level of the second node under the control of the level of the first node; The first output circuit outputs a first output signal at the first output terminal under the control of the level of the second node and the first clock signal provided by the first clock terminal; Under the control of the first output signal, the second output circuit outputs a second output signal at the second output terminal that is inversely proportional to the level of the first output signal.

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