A frame timing-based cascading partition image extraction method

Abstract

The application discloses a kind of cascade partition image extraction methods based on frame timing, comprising: S1, pixel in horizontal direction is extracted using horizontal pixel extraction module, create row data counter, when the count of the row data counter reaches preset value, obtain an output pixel;S2, the time interval of the pixel extraction of horizontal direction and vertical direction and the reading function of BRAM are used to obtain the time of first vertical extraction, in the time, first part of vertical discontinuous pixel point is changed into continuous, and first vertical area backlight extraction is carried out;S3, using BRAM, second part of vertical discontinuous pixel point is changed into continuous, and second vertical area backlight extraction is carried out, to realize backlight extraction work.The application is used in partition dynamic light adjusting display, and pixel value is converted into backlight gray value in real time.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of driving devices of partition dynamic light modulation LCD, and mainly relates to a cascaded partition image extraction method based on frame timing. BACKGROUND

[0002] Partition dynamic light modulation refers to a technology of changing the brightness of each small area in backlight according to the picture displayed in liquid crystal. In the implementation mode, the partition dynamic light modulation converts a fixed number of pixel points in each matrix in the input picture into a single gray value. In this way, the LCD can compensate for the problem of poor contrast of the displayed picture.

[0003] At present, the partition dynamic light modulation can be realized by TCON, FPGA and the like. The TCON is a special chip, and the driving capability of a single TCON is limited and the architecture is fixed, and the TCON does not have flexibility. The FPGA is a programmable device, and due to its excellent parallel computing capability, the FPGA is widely applied in the field of image processing. When the partition dynamic light modulation display displays a video picture, the response time of the driving device is required. At this time, when the FPGA is used as the driving device, the problem that the refreshing sequence of the LCD is inconsistent with the longitudinal sequence of the partition dynamic light modulation is encountered, and therefore, it is particularly important to realize a hardware architecture capable of real-time processing in the FPGA.

[0004] Since the FPGA is very suitable for a large amount of parallel operation, but the picture refreshing sequence of the LCD is continuous in the horizontal direction and discontinuous in the vertical direction, if the process of extracting backlight uses a full parallel method, the speed of image processing cannot keep up with the picture refreshing. Therefore, the existing technology usually adopts the method of caching one frame or multiple frames of pictures. The disadvantages of this method are as follows: first, caching pictures requires external memory devices, and DDR is usually used to realize the caching, and when the picture resolution is very large, a lot of memory resources are occupied. Secondly, caching pictures will make the refreshing speed of backlight always slower than the refreshing speed of pictures in the LCD, and the real-time performance is lost, and the display will also have problems when displaying some animations with large instantaneous changes. SUMMARY

[0005] In view of the technical problems in the prior art, the present application provides a cascaded partition image extraction method based on frame timing.

[0006] According to an aspect of the present application, a cascaded partition image extraction method based on frame timing is provided, comprising:

[0007] S1, a horizontal pixel extraction module is used to extract pixel points in the horizontal direction, and a row data counter is created, and when the count of the row data counter reaches a preset value, an output pixel is obtained;

[0008] S2, extracting the time interval between the input and output data by using the lateral pixel extraction module, during the time, according to the read-write characteristics of the BRAM, the first part of the longitudinal discontinuous pixel points is changed to continuous, and the first longitudinal area backlight extraction is carried out;

[0009] S3, using the BRAM to change the second part of the longitudinal discontinuous pixel points to continuous, and carrying out the second longitudinal area backlight extraction, to realize the backlight extraction work.

[0010] Further, the step S1 further comprises: using a gray data register to buffer the pixels, and when the row data counter reaches a preset value, outputting the value in the gray data register to the backlight output data pin.

[0011] The specific steps of using the gray data register to buffer the pixels are as follows:

[0012] During the counting of the row data counter, the value buffered in the gray data register is subjected to area backlight extraction with the value in the backlight data accumulation register, and the extracted result is stored in the backlight data accumulation register for reuse in the next clock cycle.

[0013] At the same time, a row data counter is used, and every time the row data counter accumulates to a preset value 1, a clock cycle of output data flag signal is pulled up, representing the generation of an output pixel.

[0014] Further, the lateral pixel extraction module defines a backlight row parameter, which is used for the module to reuse different resolutions when extracting pixels.

[0015] The use of the gray data register to buffer the pixels is for the synchronization of the pixel value and the counter.

[0016] Further, the acquisition of the time interval in the step S2 specifically comprises: using a write operation counter to count the output data flag signal in the lateral pixel extraction module, and when the count reaches a preset value, it is the time of the first longitudinal extraction.

[0017] In the resources of the FPGA, the BRAM is a kind of memory, which has small area and high read-write speed. For the write operation of the BRAM, the enable signal, data and address signal can be written in the same clock cycle, so that the data can be stored in the specified address in the BRAM. For the read operation of the BRAM, the enable signal and address signal can be written in the same clock cycle, so that the data in the specified address can be read out.

[0018] For the transverse pixel extraction module used in the transverse extraction of pixel value, the output data flag signal and the corresponding data backlight output data have been written, and only the address signal needs to be added to complete the write operation of the BRAM.

[0019] Further, the first part of the longitudinal discontinuous pixel points is changed to continuous, including adding an address signal in the BRAM read-write control module, and the address signal is obtained by the following steps:

[0020] A row counter and a column counter are established, the row counter is counted by 1 when receiving the output data flag signal, and is cleared when the accumulation reaches a preset value;

[0021] The column counter is counted by 1 when the row counter is cleared each time, and is cleared when the accumulation reaches a column preset value, thereby generating an address signal.

[0022] And the detailed reading work time can be determined by the row counter and the column counter, and a work effective signal is established, which can be used as a flag signal sent to the BRAM after being delayed for one clock cycle and being synchronized with the address signal.

[0023] S3, the second part of the longitudinal discontinuous pixel points is changed to continuous by using the BRAM, and the second longitudinal area backlight extraction is performed to realize the backlight extraction work.

[0024] The BRAM read-write control module can process the input data in real time, and the time for effectively outputting the data is further shortened. The second part of the longitudinal discontinuous pixel points is changed to continuous, which is similar to the first part in the overall function, and a shallower depth can be used for the selection of the BRAM.

[0025] According to the second aspect of the present application, a cascaded partition image extraction device based on frame timing is provided, comprising:

[0026] The transverse pixel extraction unit is configured to extract the pixel points in the transverse direction by using the transverse pixel extraction module, and a row data counter is created, and an output pixel is obtained when the count of the row data counter reaches a preset value.

[0027] The first longitudinal pixel extraction unit is configured to extract the time interval between the input and output data by using the transverse pixel extraction module, and in the time interval, the first part of the longitudinal discontinuous pixel points is changed to continuous according to the read-write characteristics of the BRAM, and the first longitudinal area backlight extraction is performed.

[0028] The second longitudinal pixel extraction unit is configured to change the second part of the longitudinal discontinuous pixel points to continuous by using the BRAM, and perform the second longitudinal area backlight extraction to realize the backlight extraction work.

[0029] According to a third aspect of the present application, a computer readable storage medium is provided, having stored thereon one or more computer programs which, when executed by a computer processor, implement any of the above methods.

[0030] The one or more technical solutions described above in the embodiments of the present application have at least one of the following technical effects:

[0031] The application is used in a partitioned dynamic light adjusting display, pixel values are converted to backlight gray scale values in real time, for a scheme using FPGA as a core device for processing video signals in a partitioned dynamic light adjusting display driving system, the relationship between the refreshing sequence of the LCD and the extraction sequence of the backlight value is analyzed, the backlight extraction algorithm is successfully embedded in the hardware architecture in real time through the cascaded partition operation based on the frame timing, and the backlight extraction work in real time without frame cache is realized. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the application. Other embodiments and many of the intended advantages of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0033] Figure 1 A cascaded partition image extraction flowchart based on frame timing according to one embodiment of the present application is shown;

[0034] Figure 2 A timing diagram of a transverse backlight extraction module according to one specific embodiment of the present application is shown;

[0035] Figure 3 A timing diagram of the input and output pixels in a transverse pixel extraction module according to one specific embodiment of the present application is shown;

[0036] Figure 4 A flowchart diagram of the reading BRAM data operation in a BRAM read-write control module according to one specific embodiment of the present application is shown;

[0037] Figure 5 A cascaded partition image extraction diagram according to one specific embodiment of the present application is shown;

[0038] Figure 6 A backlight extraction diagram according to one specific embodiment of the present application is shown;

[0039] Figure 7Fig. 1 shows a schematic diagram of a three-stage area backlight extraction module according to one embodiment of the present application;

[0040] Figure 8 Fig. 5 shows a schematic diagram of a whole part simulation result of a pixel extraction module reading operation according to one embodiment of the present application;

[0041] Figure 9 Fig. 6 shows a schematic diagram of a frame timing based cascaded partition image extraction device according to one embodiment of the present application. DETAILED DESCRIPTION

[0042] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended for the purpose of interpretation of the present application and are not intended to limit the present application. In addition, it should be noted that only the parts related to the present application are shown in the accompanying drawings for the purpose of description.

[0043] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0044] The present embodiment takes a video information with a resolution of 800x480 and a refresh rate of 60Hz as an example, which needs to process 60 pictures in 1 second. Since the pixel information in the display system is refreshed line by line, the corresponding data on the column is discontinuous each time the area backlight extraction algorithm is used.

[0045] Figure 1 Fig. 4 shows a schematic diagram of a frame timing based cascaded partition image extraction process according to one embodiment of the present application, as shown in Figure 1

[0046] S1, extracting pixel points in the horizontal direction by using a horizontal pixel extraction module, creating a row data counter, and obtaining an output pixel when the count of the row data counter reaches a preset value;

[0047] Fig. 3 shows a timing diagram of the horizontal backlight extraction module, as shown in Figure 2

[0048] The step S1 further includes: buffering the pixel by using a gray data register, and outputting the value in the gray data register to a backlight output data pin when the row data counter reaches the preset value.

[0049] The buffering of the pixel by using the gray data register includes the following specific steps:

[0050] ​​During the counting of the row data counter, the value stored in the grayscale data register is regionally extracted with the value in the backlight data accumulation register, and the result of the extraction is stored in the backlight data accumulation register for use again in the next clock cycle.

[0051] In this embodiment, the grayscale picture with a resolution of 800x480 needs to be converted into a picture with a resolution of 26x480, so the horizontal pixel extraction module needs to convert 800 horizontal pixels into 26 pixels, that is, one pixel for every 30 pixels, so the backlight row parameter is set to 30. The parameter is defined so that the module can be reused for different resolutions.

[0052] Then, the row data counter is used. When the row data counter is incremented to 30, it is reset to 1, and the output data flag signal is pulled high for one clock cycle, indicating the generation of one output pixel.

[0053] The grayscale data register is used to synchronize the pixel value and the counter. When the counter is valid, the value of the grayscale data register is regionally extracted with the value in the backlight data accumulation register, and the result is stored in the backlight data accumulation register for use again in the next clock cycle. In fact, the value in the backlight data accumulation register is only an intermediate variable, and is a valid extraction value only when the counter is 30. Therefore, when the counter reaches 30, the value is assigned to the output backlight output data pin, as shown in the timing relationship between the input and output of the horizontal pixel extraction module. Figure 3

[0054] After the continuous horizontal pixels are extracted, the discontinuous vertical pixels also need to be extracted, that is, the resolution of 26x480 is converted into a resolution of 26x10, and one pixel is obtained for every 48 vertical pixels.

[0055] For the timing analysis of the input and output pixels in the horizontal pixel extraction module, if the output data flag signal is defined as the time of updating the output pixel, there are 29 clock cycles between two output pixels that are not updated and are idle, and the discontinuous pixels on the column can be processed in this idle clock.

[0056] Now the pixel data on the column is discontinuous, and we can choose to use a BRAM to make the data on the column continuous. If we directly store every 26x48 pixel data into the BRAM, there is no time to read out the data, because the next row of pixel data corresponding to the partition will be refreshed immediately.

[0057] ​When the pixel data processed by the transverse pixel extraction module is refreshed to the 48th row and the 1st column, the data in the first partition has been stored into the BRAM. When the next pixel data is refreshed to the 48th row and the 2nd column, there is an interval of 29 clock cycles. If the data of the first column corresponding to the first 48 rows is selected to be taken out at this time, it is not allowed in time because the operation needs 48 clock cycles. Therefore, the BRAM can be selected to be stored and read in two sections, 24 rows of data are written each time, and the data is read starting from the 24th row by using the interval time between the pixel points.

[0058] Firstly, the output data flag signal and the corresponding backlight output data in the transverse pixel extraction module used in the transverse extraction of pixel values have been written, and only the address signal needs to be added to complete the write operation of the BRAM. Every 24 rows of data are stored, and then the first row is written again to cover the previous data. At the same time, the video control signal is specified by using a shift register to delay the clock period to synchronize the output of the pixel data.

[0059] S2, the time interval between the input and output data is extracted by using the transverse pixel extraction module, and during the time, the first part of the longitudinally discontinuous pixel points is changed to be continuous according to the read-write characteristics of the BRAM, and the first longitudinal area backlight extraction is performed;

[0060] The time interval in the step S2 is obtained by using a write operation counter to count the output data flag signal in the transverse pixel extraction module, and when the count reaches a preset value, the time for the first longitudinal extraction is obtained.

[0061] In this embodiment, secondly, for the first part of the longitudinal area backlight extraction, the 26x480 grayscale picture needs to be converted into 26x20, and in the longitudinal resolution, every 24 pixel points become 1 point. Since the transverse pixel extraction module stores every 24 rows of data into the BRAM and then refreshes from the 1st row, the BRAM size required for the input image of 800x480 is 24x26 depth and 8 bits wide. In order to adapt to other resolutions, the depth of the BRAM can be appropriately deepened, and the depth is temporarily selected to be 1024.

[0062] As shown in Figure 4 When the count is 26x23, it means that the transverse pixel extraction module has sent the data of the 24th row and the 1st column to the BRAM, and the reading operation of this module starts at this time. When the count is (26x24-1), it means that the transverse pixel extraction module has sent all 24 rows of data, and the reading operation is ended and reset to zero.

[0063] The first part of the longitudinal discontinuous pixel points is changed to continuous, which includes adding an address signal in the BRAM read-write control module, and the address signal is obtained by the following steps:

[0064] A row counter and a column counter are established, the row counter is counted up by 1 when receiving an output data flag signal, and is cleared when accumulated to a preset value;

[0065] The column counter is counted up by 1 when the row counter is cleared each time, and is cleared when accumulated to a column preset value, thereby generating an address signal.

[0066] In this embodiment, the address numbers required when reading the first column of data are 0, 26, 52, 78, etc. First, a row counter and a column counter of the BRAM are established. The row counter is counted up by 1 when receiving an output data flag signal each time, and is cleared when accumulated to 24. The column counter is counted up by 1 when the row counter is counted to 24 each time, and is cleared when accumulated to 26. Thus, the address signal of the BRAM can be generated, and the formula is as follows:

[0067] addr_ctrl = 26 x h_addr_cnt + v_addr_cnt

[0068] Wherein, addr_ctrl is the address signal, h_addr_cnt is the row count value, and v_addr_cnt is the column count value.

[0069] The detailed reading work time is determined by the row count value and the column count value, and a work valid signal is established. After the signal is delayed by one clock cycle and synchronized with the address signal, it can be used as a flag signal sent to the BRAM.

[0070] The BRAM read-write control module can process the input data in real time, and the time for effectively outputting data is further shortened.

[0071] S3, the second part of the longitudinal discontinuous pixel points is changed to continuous by using the BRAM, and the second longitudinal area backlight extraction is performed to realize the backlight extraction work.

[0072] The second part of the longitudinal discontinuous pixel points is changed to continuous and the second longitudinal area backlight extraction is performed to change the 26x20 gray scale image to 26x10, which is similar to the first part in overall function. For the selection of the BRAM, a shallower depth can be used, and in this embodiment, a BRAM with a depth of 256 is used.

[0073] In this embodiment, as shown in Figure 5 The schematic diagram of each step of the cascaded partition image extraction is shown, Figure 6 The backlight extraction schematic diagram is shown, which includes the pixel point display order of a picture in the display (left picture) and the effect diagram after the area backlight extraction (right picture).

[0074] As shown in the three-stage design as Figure 7 The pixel extraction module with three-stage design can reorder the data on the column using the gap of the piecewise embedding algorithm, and can process the video gray signal into the backlight signal in real time, as shown in Fig. 8 which shows the simulation results of the overall part of the reading operation. And in terms of resource occupation, only a small amount of BRAM resources and some low-bit-width registers are used, greatly reducing the resource consumption.

[0075] As shown in the three-stage design as Figure 9 A cascaded partition image extraction device based on frame timing is shown, which comprises:

[0076] The transverse pixel extraction unit is configured to extract the pixel points in the transverse direction using the transverse pixel extraction module, and create a row data counter. When the count of the row data counter reaches a preset value, an output pixel is obtained.

[0077] The first longitudinal pixel extraction unit is configured to extract the time gap between the input and output data using the transverse pixel extraction module. During the time, according to the read-write characteristics of the BRAM, the first part of the longitudinal discontinuous pixel points is changed to continuous, and the first longitudinal area backlight extraction is performed.

[0078] The second longitudinal pixel extraction unit is configured to use the BRAM to change the second part of the longitudinal discontinuous pixel points to continuous, and perform the second longitudinal area backlight extraction, thereby realizing the backlight extraction work.

[0079] The flowcharts and block diagrams in the drawings illustrate the possible implementation architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different order than that shown in the figure. For example, two blocks indicated in succession can actually be executed substantially in parallel, and sometimes they can be executed in reverse order, depending on the function involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0080] The modules involved in the embodiments described in the present application can be implemented in software or in hardware.

[0081] The above description is only the preferred embodiment of the present application and the explanation of the technical principles. It should be understood by those skilled in the art that the scope of the protection of the present application is not limited to the technical solutions formed by the specific combinations of the above technical features. It should also cover other technical solutions formed by the combinations of the above technical features or their equivalent features without departing from the concept of the present application. For example, the technical solutions formed by the mutual replacement of the above features and the technical features with similar functions disclosed (but not limited to) in the present application.

Claims

1. A frame timing based cascaded partitioned image extraction method, characterized in that, The method comprises the following steps: S1, extracting pixels in the horizontal direction by using a horizontal pixel extraction module, creating a row data counter, and obtaining an output pixel when the count of the row data counter reaches a preset value; S2, extracting a time interval between input and output data by using the horizontal pixel extraction module, and, within the time interval, converting first part of longitudinally discontinuous pixels into continuous pixels according to the read-write characteristics of a BRAM, and performing first longitudinal area backlight extraction; S3, converting second part of longitudinally discontinuous pixels into continuous pixels by using the BRAM, and performing second longitudinal area backlight extraction, thereby realizing backlight extraction.

2. The extraction method of claim 1, wherein: The horizontal pixel extraction module defines backlight row parameters, which are used for the module to reuse different resolutions when extracting pixels.

3. The extraction method of claim 1, wherein: The step S1 further comprises: buffering pixels by using a grayscale data register, and outputting the value in the grayscale data register to a backlight output data pin when the row data counter reaches the preset value.

4. The extraction method of claim 3, wherein: The buffering of pixels by using the grayscale data register comprises the following steps: During the counting of the row data counter, the value buffered in the grayscale data register is subjected to area backlight extraction together with the value in a backlight data accumulation register, and the result of the extraction is stored in the backlight data accumulation register for reuse in the next clock cycle.

5. The extraction method of claim 1, wherein: The acquisition of the time interval in the step S2 specifically comprises: counting an output data flag signal in the horizontal pixel extraction module by using a write operation counter, and the time for the first longitudinal extraction is obtained when the count reaches a preset value.

6. The extraction method of claim 1, wherein: The conversion of the first part of longitudinally discontinuous pixels into continuous pixels comprises: adding an address signal in a BRAM read-write control module, and the acquisition of the address signal comprises: establishing a row counter and a column counter, counting up when the row counter receives an output data flag signal, and resetting when the count reaches a preset value; counting up when the column counter resets every time the row counter resets, and resetting when the count reaches a column preset value, thereby generating an address signal.

7. A frame timing based cascaded partitioned image extraction apparatus, characterized by, The method comprises: a horizontal pixel extraction unit configured to extract pixels in the horizontal direction by using a horizontal pixel extraction module, create a row data counter, and obtain an output pixel when the count of the row data counter reaches a preset value; a first longitudinal pixel extraction unit configured to extract a time interval between input and output data by using the horizontal pixel extraction module, and, within the time interval, convert first part of longitudinally discontinuous pixels into continuous pixels according to the read-write characteristics of a BRAM, and perform first longitudinal area backlight extraction; a second longitudinal pixel extraction unit configured to convert second part of longitudinally discontinuous pixels into continuous pixels by using the BRAM, and perform second longitudinal area backlight extraction, thereby realizing backlight extraction.

8. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the method of any one of claims 1-6.

9. A computing system comprising a processor and a memory, the processor configured to perform the method of any one of claims 1-6.

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