Pixel architecture and pixel driving method

Abstract

The present disclosure provides a pixel architecture and a pixel driving method, wherein a column scan line is connected to a sub-pixel of a corresponding column, a plurality of pixels can be divided into a plurality of pixel sub-areas, a pixel sub-area includes N pixels, a pixel includes three sub-pixels of different colors, the sub-pixels of any one of the odd-bit pixel sub-area and the even-bit pixel sub-area are connected to the row scan line of the corresponding row, the sub-pixels of the other pixel sub-area are connected to the row scan line of the next row, and the data lines are respectively connected to the column scan lines of two columns, and the difference between the columns where the column scan lines of the two columns are located is 3N. It can be seen that the pixel polarity and data lines in the pixel architecture can achieve uniform spatial distribution, which can effectively avoid vertical shaking head and flicker problems. Moreover, the sub-pixels connected to a single data line have the same color, which can well ensure the realization of the DLG function and better improve the display effect of the display panel based on the pixel architecture.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel architecture and a pixel driving method. Background Art

[0002] As competition among LCD panel manufacturers intensifies, cost control becomes increasingly stringent. Conventional panel pixel architecture has evolved from 1G1D to 2G1D, or DRD (double rate driving) architecture. This architecture uses two rows of scan lines (gate lines) to activate a complete row of pixels. This reduces the number of data lines by half while doubling the number of scan lines. The additional scan lines can be implemented using a gate-less mechanism with GOA (Gate Driven on Array) circuitry designed on the side, thus saving source IC costs. The subpixels in the currently common DRD architecture are arranged in a long-short-hand pattern.

[0003] Currently, the driving of pixels is to open the scan lines line by line. There is an existing DLG technology (dual linegate, double refresh) which opens two scan lines at the same time. For example, on a 4K2K 60Hz (3840*2160) panel platform, it originally requires 2160 lines to be scanned line by line to display a complete frame of image, and it can be refreshed 60 times per second. When the DLG technology is applied, the front-end soc (system on chip, responsible for video decoding, signal processing, etc.) will process the display data into 4K1K (3940*1080). At this time, it only needs to scan 1080 lines to display a complete frame of image, so the refresh rate can be doubled to 120Hz, which means it can be refreshed 120 times per second.

[0004] However, in the commonly used 2G1D pixel structure (for example, 2G1D with subpixels arranged in a long-short-hand pattern), the uneven spatial distribution of pixel polarity and data lines can lead to vertical head-shaking and flickering issues. Furthermore, in this long-short-hand 2G1D structure, since each data line connects to a different color subpixel, the data line drive voltage must change row by row within a frame. This cannot be achieved with the existing timing when the DLG function is enabled. Summary of the Invention

[0005] To overcome the problems existing in the related art, the present disclosure provides a pixel architecture and a pixel driving method.

[0006] According to a first aspect of an embodiment of the present disclosure, a pixel architecture is provided, comprising a plurality of row scan lines and a plurality of column scan lines, and a plurality of pixels driven by the plurality of row scan lines and the plurality of column scan lines, wherein the pixels include three sub-pixels of different colors, and the sub-pixels in the same column have the same color.

[0007] The column scan lines are connected to the sub-pixels in the corresponding columns;

[0008] Along the extension direction of the column scan lines, the plurality of pixels are divided into a plurality of rows of pixel regions, and along the extension direction of the row scan lines, each row of pixel regions is divided into a plurality of pixel sub-regions, and the plurality of pixel sub-regions are divided into odd-numbered pixel sub-regions and even-numbered pixel sub-regions based on their arrangement positions, and the pixel sub-regions include N pixels, where N is a positive integer greater than or equal to 1;

[0009] In the pixel area of ​​the Xth row, sub-pixels of a first type are connected to the row scan line of the 2X-1th row, and sub-pixels of a second type are connected to the row scan line of the 2Xth row; wherein the sub-pixels of the first type are sub-pixels of either the odd-numbered pixel sub-area or the even-numbered pixel sub-area, and the sub-pixels of the second type are sub-pixels of the other pixel sub-area;

[0010] The pixel architecture includes a plurality of data lines, the number of which is half the number of the column scan lines, wherein each data line is connected to two column scan lines respectively, and the difference between the columns where the two column scan lines are located is 3N.

[0011] In an optional embodiment, of the two column scan lines connected to the same data line,

[0012] The column scan line in the smaller column is connected to the data line via a first switch unit; and / or,

[0013] The larger column scan line and the data line are connected via a second switch unit.

[0014] In an optional embodiment,

[0015] The control terminals of the plurality of first switch units in the pixel architecture are all electrically connected to the first control line; and / or,

[0016] The control ends of the plurality of second switch units in the pixel architecture are all electrically connected to the second control line.

[0017] In an optional embodiment,

[0018] The first control lines include first in-plane control lines located in the panel and first out-of-plane control lines located outside the panel, the first out-of-plane control lines being provided in a chip-on-film manner; and / or,

[0019] The second control lines include second in-plane control lines located in the panel and second out-of-plane control lines located outside the panel. The second out-of-plane control lines are provided in a chip-on-film manner.

[0020] In an optional embodiment,

[0021] The first switching unit includes a first switching transistor; and / or,

[0022] The second switching unit includes a second switching transistor.

[0023] In an optional embodiment, the pixel architecture includes an inversion architecture.

[0024] According to a second aspect of an embodiment of the present disclosure, a pixel driving method is provided. The pixel driving method is applied to the pixel architecture according to any one of the first aspects, wherein the row scan lines in the pixel architecture are divided into a plurality of row scan line groups, wherein when M is an odd number greater than or equal to 1, the row scan lines in the 2M-1th row and the 2M+1th row are used as the Mth row scan line group; and when M is an even number greater than or equal to 1, the row scan lines in the Mth row and the M+2th row are used as the Mth row scan line group. The pixel driving method includes:

[0025] When driving is performed using a frequency doubling refresh technology, display data is sequentially input to each of the corresponding row scan line groups.

[0026] In an optional embodiment, sequentially inputting display data to each corresponding row scan line group includes:

[0027] When display data is input to the odd-numbered row scan line group, the first switch unit in the pixel structure is controlled to be in an on state, and the second switch unit in the pixel structure is controlled to be in an off state; and / or,

[0028] When display data is input to the row scan line group of even bits, the second switch unit in the pixel structure is controlled to be in a conducting state, and the first switch unit in the pixel structure is controlled to be in a cut-off state.

[0029] In an optional embodiment, the pixel driving method includes:

[0030] When driving is performed in a row-by-row manner, display data is sequentially input to each corresponding row of scan lines.

[0031] In an optional embodiment, sequentially inputting display data to each corresponding row of scan lines includes:

[0032] When display data is input to the odd-numbered row scan lines, the first switch unit in the pixel structure is controlled to be in an on state, and the second switch unit in the pixel structure is controlled to be in an off state; and / or,

[0033] When display data is input to the even-numbered row scan line, the second switch unit in the pixel structure is controlled to be in an on state, and the first switch unit in the pixel structure is controlled to be in an off state.

[0034] The technical solution provided by the embodiments of the present disclosure may include the following beneficial effects: In the present disclosure, the column scan line is connected to the sub-pixels of the corresponding column, and multiple pixels can be divided into multiple pixel sub-areas. The pixel sub-area includes N pixels, and the pixel includes three sub-pixels of different colors. The sub-pixels of any pixel sub-area in the odd-bit pixel sub-area and the even-bit pixel sub-area are connected to the row scan line of the corresponding row, and the sub-pixels of the other pixel sub-area are connected to the row scan line of the next row, and the data lines are respectively connected to the column scan lines of the two columns, and the difference between the columns where the column scan lines of the two columns are located is 3N. It can be seen that the pixel polarity and data lines in the pixel architecture can achieve uniform spatial distribution, which can effectively avoid the shaking head and flicker problems in the vertical direction (that is, the extension direction of the column scan line). Moreover, in the pixel architecture, the sub-pixels connected by a single data line have the same color, which can well ensure the realization of the DLG function and better improve the display effect of the display panel based on the pixel architecture.

[0035] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0037] Figure 1 is a schematic diagram showing a pixel architecture according to an exemplary embodiment.

[0038] Figure 2 is a timing waveform diagram of display data according to another exemplary embodiment.

[0039] Figure 3 FIG. 4 is a schematic diagram showing conversion of display data during normal display according to an exemplary embodiment.

[0040] Figure 4 FIG. 1 is a schematic diagram showing conversion of display data when driven by the DLG technology according to an exemplary embodiment.

[0041] Figure 5 is a schematic diagram showing a pixel architecture according to an exemplary embodiment.

[0042] Figure 6 FIG. 1 is a schematic diagram showing a comparison of timing waveforms of display data according to an exemplary embodiment.

[0043] Figure 7 FIG. 1 is a schematic diagram showing routing of a first out-of-plane control line and a second out-of-plane control line according to an exemplary embodiment.

[0044] Description of reference numerals:

[0045] 10. Pixel area; 100. Pixel sub-area; K1. First switch unit; K2. Second switch unit; Z1. First control line; Z2. Second control line; Z11. First off-plane control line; Z21. Second off-plane control line; ZL. Left control line board; ZR. Right control line board; SD. Source driver; CB. Control board. DETAILED DESCRIPTION

[0046] The following will describe the embodiments of the present application with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand the other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for the purpose of illustrating the present application and are not intended to limit the scope of protection of the present application.

[0047] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0048] The following will describe the embodiments of the present application with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand the other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be understood that the preferred embodiments are only for the purpose of illustrating the present application and are not intended to limit the scope of protection of the present application.

[0049] The present disclosure provides a pixel architecture and a pixel driving method. In the present disclosure, a column scan line (source line) is connected to the sub-pixels of the corresponding column. Multiple pixels can be divided into multiple pixel sub-regions, each of which includes N pixels. Each pixel includes three sub-pixels of different colors. The sub-pixels in either the odd-bit pixel sub-region or the even-bit pixel sub-region are connected to the row scan line of the corresponding row, while the sub-pixels in the other pixel sub-region are connected to the row scan line of the next row. Furthermore, data lines are connected to the column scan lines of two columns, and the difference between the columns where the column scan lines of the two columns are located is 3N.

[0050] It can be seen from this that the pixel polarity and data lines in this pixel architecture can achieve uniform spatial distribution, which can effectively avoid shaking head and flickering problems in the vertical direction (i.e., the extension direction of the column scan line). Moreover, in this pixel architecture, the sub-pixels connected by a single data line have the same color, which can well ensure the realization of the DLG function and better improve the display effect of the display panel based on this pixel architecture.

[0051] Example 1

[0052] This embodiment provides a pixel architecture and a pixel driving method thereof. Figure 1 As shown, the pixel structure may include multiple row scan lines and multiple column scan lines, and multiple pixels driven by the multiple row scan lines and multiple column scan lines. The pixel may include three sub-pixels of different colors, and the sub-pixels in the same column in the pixel structure have the same color. For example, multiple pixels in the pixel structure may include: Figure 1 The array is arranged in the manner shown, where a pixel may include a red sub-pixel, a blue sub-pixel and a green sub-pixel.

[0053] In the extending direction of the column scan line (i.e., the vertical direction or vertical direction), the plurality of pixels can be divided into a plurality of rows of pixel regions 10. It should be noted that the specific division method can be set according to actual needs and is not limited to this. For example, each row of pixels can be recorded as a pixel region 10.

[0054] Among them, along the extension direction of the row scan line (i.e., the horizontal direction or the lateral direction), each row of pixel areas 10 can be divided into a plurality of pixel sub-areas 100. And the pixel sub-area 100 may include N pixels, where N is a positive integer greater than or equal to 1. It should be noted that the specific division method can be set according to actual needs and is not limited to this. For example, in the pixel area 10, each pixel can be recorded as a pixel sub-area 100, and each pixel sub-area 100 includes one pixel. For another example, in the pixel area 10, every two adjacent pixels can be recorded as a pixel sub-area 100, that is, each pixel sub-area 100 includes two pixels.

[0055] The plurality of pixel sub-regions 100 in the pixel region 10 can be divided into odd-numbered pixel sub-regions 100 and even-numbered pixel sub-regions 100 based on their arrangement positions. The odd-numbered pixel sub-regions 100 are pixel sub-regions 100 whose arrangement positions are located at odd-numbered positions, such as the first pixel sub-region 100, the third pixel sub-region 100, the fifth pixel sub-region 100, and so on. The even-numbered pixel sub-regions 100 are pixel sub-regions 100 whose arrangement positions are located at even-numbered positions, such as the second pixel sub-region 100, the fourth pixel sub-region 100, the sixth pixel sub-region 100, and so on.

[0056] In the pixel area 10 of the Xth row, the first type of sub-pixels are connected to the row scan line of the 2X-1th row, and the second type of sub-pixels are connected to the row scan line of the 2Xth row. The first type of sub-pixels are sub-pixels in either the odd-numbered pixel sub-area 100 or the even-numbered pixel sub-area 100, and the second type of sub-pixels are sub-pixels in the other of the odd-numbered pixel sub-area 100 and the even-numbered pixel sub-area 100.

[0057] In this pixel architecture, a column scan line is connected to sub-pixels in a corresponding column. That is, the sub-pixels connected to a single column scan line are all of the same color.

[0058] In addition, the pixel architecture may include multiple data lines for transmitting display data to the column scan lines. The data lines may be connected to the column scan lines of two columns, respectively. Thus, in the pixel architecture, the number of data lines may be half the number of column scan lines, thereby reducing the number of data lines.

[0059] The difference between the columns of the two column scan lines connected to a single data line can be 3N. That is, in the two column scan lines connected to each data line, the sub-pixels in the same row connected to each column scan line belong to different pixel sub-regions 100, and each data line can be connected to two columns of sub-pixels of the same color through two column scan lines.

[0060] The pixel polarity and data lines in this pixel architecture can achieve uniform spatial distribution, which can effectively avoid the shaking head and flickering problems in the vertical direction (i.e., the extension direction of the column scan line). Moreover, in this pixel architecture, the sub-pixels connected by a single data line have the same color, which can well ensure the realization of the DLG function and better improve the display effect of the display panel based on this pixel architecture.

[0061] In some embodiments,

[0062] refer to Figure 1As shown, each pixel sub-region 100 may include two pixels (i.e., N is 2), and each pixel includes three sub-pixels of different colors, namely a red sub-pixel, a blue sub-pixel, and a green sub-pixel. In this embodiment, each row of pixels is recorded as a pixel region 10. Each pixel region 10 is divided into multiple pixel sub-regions 100 in units of two pixels. Each pixel sub-region 100 includes two adjacent pixels, that is, it includes six adjacent sub-pixels.

[0063] In this embodiment, 4320 row scan lines, 11520 column scan lines, and 5760 data lines may be included.

[0064] Among them, the first column scan line S1 is connected to the sub-pixels in the first column (for example, all of them may be red (R) sub-pixels), the second column scan line S2 is connected to the sub-pixels in the second column (for example, all of them may be green (G) sub-pixels), the third column scan line S3 is connected to the sub-pixels in the third column (for example, all of them may be blue (B) sub-pixels), the fourth column scan line S4 is connected to the sub-pixels in the fourth column (for example, all of them may be red sub-pixels), the fifth column scan line S5 is connected to the sub-pixels in the fifth column (for example, all of them may be green sub-pixels), the sixth column scan line S6 is connected to the sub-pixels in the sixth column (for example, all of them may be blue sub-pixels), and so on.

[0065] Among them, the first row scan line G1 is connected to the sub-pixels in all odd-numbered pixel sub-areas 100 in the first row, that is, the first row scan line G1 is connected to the first to sixth, thirteenth to eighteenth... and so on sub-pixels in the first row; the second row scan line G2 is connected to the sub-pixels in all even-numbered pixel sub-areas 100 in the first row, that is, the second row scan line G2 is connected to the seventh to twelfth, nineteenth to twenty-fourth... and so on sub-pixels in the first row; the third row scan line G3 is connected to the sub-pixels in all odd-numbered pixel sub-areas 100 in the second row; the fourth row scan line G4 is connected to the sub-pixels in all even-numbered pixel sub-areas 100 in the second row; and so on.

[0066] Each data line can be connected to two column scan lines, and the difference between the columns of these two column scan lines is 6. For example, the Yth data line can be connected to the Yth column scan line and the Y+6th column scan line, that is, the first data line D1 can be connected to the first column scan line S1 and the seventh column scan line S7, the second data line D2 can be connected to the second column scan line S2 and the eighth column scan line S8, and so on.

[0067] refer to Figure 1As shown, in this embodiment, a novel DRD structure can be implemented by adopting an inversion method (e.g., column inversion method) pixel architecture to facilitate the realization of the DLG function. In normal display (i.e., when driven in a row-by-row manner), the row scan lines can be turned on row by row from top to bottom, that is, the timing controller sequentially inputs display data to each corresponding row scan line.

[0068] like Figure 2 and 3 The following is a schematic diagram of the timing and data during normal display. Figure 3 The arrows above the center represent the data the SoC provides to the timing controller (TCON), while the arrows below represent the data the TCON provides to the interface. Taking the first data line D1 as an example, the SoC outputs data R11, R21, and R31 in sequence. After remapping (drawing) the data from the TCON, the TCON outputs data R11, R13, R21, and R23 in sequence.

[0069] It should be noted that in subpixels Pij, the main body P represents the color of the subpixel, the first data in the subscript i represents the physical row of the subpixel, and the second data in the subscript j represents the arrangement position of the subpixel in the physical row. For example, R23 represents the third red subpixel in the second physical row. For another example, G12 represents the second green subpixel in the first physical row. For another example, B22 represents the second blue subpixel in the second physical row.

[0070] In this embodiment, reference Figure 1 As shown, when the DLG function needs to be turned on (ie, when driving with the DLG technology is required), display data is input to each corresponding row scan line group in sequence.

[0071] In which, the row scan lines in the pixel architecture are divided into multiple row scan line groups, wherein, when M is an odd number greater than or equal to 1, the row scan lines of the 2M-1th row and the 2M+1th row are used as the Mth row scan line group; when M is an even number greater than or equal to 1, the row scan lines of the Mth row and the M+2th row are used as the Mth row scan line group.

[0072] For example, when driving with DLG technology, the gate side needs to turn on the row scan lines in the row scan line group one by one, that is, first turn on the first row scan line G1 and the third row scan line G3 at the same time, then turn on the second row scan line G2 and the fourth row scan line G4 at the same time, then turn on the fifth row scan line G5 and the seventh row scan line G7 at the same time, then turn on the sixth row scan line G6 and the eighth row scan line G8 at the same time, and so on. In this case, the timing controller needs to remap the data. Figure 4As shown, taking the first data line D1 as an example, the data that the timing controller needs to map out are R11, R13, R21 and R23.

[0073] It should be noted that if the pixel architecture of this embodiment wants to realize the DLG function, it can be combined with a multi-input and multi-output L / S (Level Shifter, i.e., level conversion), so that each timing signal can be controlled separately, or it can be combined with a specific low-input and multi-output L / S that supports the first row scan line G1 and the third row scan line G3 to be turned on at the same time. There is no limitation on this.

[0074] The pixel polarity and data lines in this pixel architecture can achieve uniform spatial distribution, which can effectively avoid the shaking head and flickering problems in the vertical direction (i.e., the extension direction of the column scan line). Moreover, in this pixel architecture, the sub-pixels connected by a single data line have the same color, which can well ensure the realization of the DLG function and better improve the display effect of the display panel based on this pixel architecture.

[0075] Example 2

[0076] This embodiment provides a pixel architecture and a pixel driving method. Figure 5 As shown, the difference between this pixel architecture and embodiment 1 is that, among the two column scan lines connected to the same data line, the column scan line with a smaller column can be connected to the data line through a first switch unit K1, and / or the column scan line with a larger column can be connected to the data line through a second switch unit K2, so as to control the on-off between the data line and the column scan line.

[0077] The first switch unit K1 may include a first switch transistor or other switch units, which is not limited thereto. The second switch unit K2 may include a second switch transistor or other switch units, which is not limited thereto.

[0078] For example, the first data line D1 is connected to the first column scan line S1 and the seventh column scan line S7, respectively, wherein the first column scan line S1 and the first data line D1 can be connected through the first switch unit K1, and the seventh column scan line S1 and the first data line D1 can be connected through the second switch unit K2. In this way, when the first data line D1 needs to transmit display data to the first column scan line S1, the first switch unit K1 can be controlled to be in the on state, and the second switch unit K2 can be controlled to be in the off state; when the first data line D1 needs to transmit display data to the seventh column scan line S7, the first switch unit K1 can be controlled to be in the off state, and the second switch unit K2 can be notified to be in the on state, so as to better avoid mutual influence.

[0079] It should be noted that Figure 6The waveforms of the display data corresponding to the first row scan line G1 and the display data corresponding to the second row scan line G2 are ideal waveforms. In reality, they will be deformed by the delay on the row scan line, such as Figure 6 The waveform of the actual corresponding data is shown in FIG. Due to the influence of delay, when the first row scan line G1 is turned on, the data of the first row is sequentially charged to the first column scan line S1 to the sixth column scan line S6 through the first data line D1 to the sixth data line D6, and the seventh data line D7 to the twelfth data line D12 sequentially charge the thirteenth column scan line S13 to the eighteenth column scan line S18. When the second row scan line G2 is turned on, the data of the second row is sequentially charged to the seventh column scan line S7 to the twelfth column scan line S12 through the first data line D1 to the sixth data line D6, and the seventh data line D7 to the twelfth data line D12 sequentially charge the nineteenth column scan line S19 to the twenty-fourth column scan line S24.

[0080] Among them, when the first row scan line G1 starts to turn off and the second row scan line G2 is then turned on, the first row scan line G1 will be affected by the delay and delayed to turn off. In this way, the data of the second row will pass through the first column scan line S1 to the sixth column scan line 16 to change the voltage of the sub-pixel in the first row, affecting the display effect.

[0081] In the pixel structure of this embodiment, by providing the first switch unit K1 and the second switch unit K2, the impact of delay on the display effect can be effectively avoided. Specifically, when driving in a normal display mode, when display data is input to an odd-numbered row scan line, the first switch unit K1 in the control pixel structure is in an on state, and the second switch unit K2 in the control pixel structure is in an off state. When display data is input to an even-numbered row scan line, the second switch unit K2 in the control pixel structure is in an on state, and the first switch unit K1 in the control pixel structure is in an off state.

[0082] When driving with the DLG technology, when display data is input to an odd-numbered row scan line group, the first switch unit K1 in the control pixel structure is in an on state, and the second switch unit K2 in the control pixel structure is in an off state. When display data is input to an even-numbered row scan line group, the second switch unit K2 in the control pixel structure is in an on state, and the first switch unit K1 in the control pixel structure is in an off state.

[0083] For example, taking the red sub-pixel connected to the first column scan line S1 and the red sub-pixel connected to the seventh column scan line S7 as an example, when the first row scan line G1 is turned on, the first switch unit K1 between the first column scan line S1 and the first data line D1 is controlled to be in the on state, and the second switch unit K2 between the first seven column scan lines S7 and the first data line D1 is controlled to be in the off state, and the first data line D1 charges the red sub-pixel connected to the first column scan line S1, then the first row scan line G1 is slowly closed, and the second row scan line G2 is slowly opened, and the above-mentioned first switch unit K1 is controlled to be in the off state, and the above-mentioned second switch unit K2 is controlled to be in the on state, and the first data line D1 charges the red sub-pixel connected to the seventh column scan line S7.

[0084] refer to Figure 6 As can be seen from the waveform diagram of the data of this embodiment, in this pixel structure, because the conversion between the on state and the off state of the first switch unit K1 and the second switch unit K2 is almost unaffected by the delay on the transmission line, when the first row scan line G1 is slowly closed, the first switch unit K1 is already in the off state and the second switch unit K2 is already in the on state. At this time, the data of the first data line D1 will not be mistakenly charged to the red sub-pixel connected to the first column scan line G1, which can effectively prevent mistaken charging and improve the display effect.

[0085] Example 3

[0086] This embodiment provides a pixel architecture and a pixel driving method. Figure 5 and Figure 7 As shown, the difference between this pixel architecture and the second embodiment is that, in this pixel architecture, the control terminals of the plurality of first switch units K1 can all be electrically connected to the first control line Z1; and / or the control terminals of the plurality of second switch units K2 can all be electrically connected to the second control line Z2. In this way, the first switch units K1 can be uniformly controlled via the first control line Z1, and the second switch units K2 can be uniformly controlled via the second control line Z2.

[0087] Among them, the first control line Z1 may include a first in-plane control line located inside the panel and a first out-of-plane control line located outside the panel. The first out-of-plane control line is set in the form of a chip on film (COF (Chip On Flex, or Chip On Film), often called chip on film, which is a grain soft film packaging technology that fixes the integrated circuit (IC) on a flexible circuit board). It can shorten the wiring, reduce the wiring impedance, and reduce the attenuation of the signals of the first control line Z1 and the second control line Z2, so as to better realize the control of the first switch unit K1 and the second switch unit K2.

[0088] In some embodiments,

[0089] The routing of the first control line Z1 and the second control line Z2 is as follows Figure 4 and Figure 6 As shown, the first out-of-plane control line Z11 and the second out-of-plane control line Z21 are output from the timing controller on the control board CB, pass through the FFC (FFC (Flexible Flat Cable) flexible flat cable) wire to the left control line board XL / right control line board XR, enter the panel from each source driver SD, and are respectively connected to the first in-plane control line Z12 and the second in-plane control line Z22 in the panel, wherein the first out-of-plane control line Z11 is connected to the first in-plane control line Z12 to form the first control line Z1, and the second out-of-plane control line Z21 is connected to the second in-plane control line Z22 to form the second control line Z2. The first in-plane control line Z12 and the second in-plane control line Z22 are used Figure 5 The first in-plane control line Z12 is connected to the control end of the first switch unit K1 (for example, the base of the first switch transistor), and the second in-plane control line Z22 is connected to the control end of the second switch unit K2 (for example, the base of the second switch transistor).

[0090] It should be noted that because the trace impedance within a panel (e.g., a glass panel) is greater than that on a circuit board, and the first control line Z1 and the second control line Z2 in this embodiment are intended to be fed to the column scan line located in the center of the panel, if the first control line Z1 and the second control line Z2 are only fed into the plane at the leftmost and rightmost sides of the panel and then cross to the column scan line located in the center of the panel, the signals transmitted by the first control line Z1 and the second control line Z2 obtained at the column scan line in the center of the panel will be severely affected by the trace impedance. By the time the signals reach the centermost column scan line, they may have been severely attenuated, resulting in insufficient signals to control the states of the corresponding first switch unit K1 and the second switch unit K2. However, the solution of this embodiment can shorten the traces within the panel, reduce the trace impedance, and reduce the attenuation of the signals in the first control line Z1 and the second control line Z2, thereby achieving more precise control of the first switch unit K1 and the second switch unit K2, thereby better preventing mischarging.

[0091] Professionals should also be further aware that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] It should be noted that references in this specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and the like indicate that the described embodiments may include a particular feature, structure, or characteristic, but not necessarily every embodiment includes that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not.

[0093] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more limitations, an element defined by the sentence "comprises a..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0094] The above embodiments are only preferred embodiments for fully illustrating the present application, and the protection scope of the present application is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art based on the present application are within the protection scope of the present application.

Claims

1. A pixel architecture comprising a plurality of row scan lines and a plurality of column scan lines, and a plurality of pixels driven by the plurality of row scan lines and the plurality of column scan lines, wherein the pixels include three sub-pixels of different colors, and the sub-pixels in the same column have the same color, characterized in that: The column scan lines are connected to the sub-pixels in the corresponding columns; Along the extension direction of the column scan lines, the plurality of pixels are divided into a plurality of rows of pixel regions, and along the extension direction of the row scan lines, each row of pixel regions is divided into a plurality of pixel sub-regions, and the plurality of pixel sub-regions are divided into odd-numbered pixel sub-regions and even-numbered pixel sub-regions based on their arrangement positions, and the pixel sub-regions include N pixels, where N is a positive integer greater than or equal to 1; In the pixel area of ​​the Xth row, sub-pixels of a first type are connected to the row scan line of the 2X-1th row, and sub-pixels of a second type are connected to the row scan line of the 2Xth row; wherein the sub-pixels of the first type are sub-pixels of either the odd-numbered pixel sub-area or the even-numbered pixel sub-area, and the sub-pixels of the second type are sub-pixels of the other pixel sub-area; The pixel architecture includes a plurality of data lines, the number of which is half the number of the column scan lines, wherein each data line is connected to two column scan lines respectively, and the difference between the columns where the two column scan lines are located is 3N.

2. The pixel architecture according to claim 1, wherein: Of the two column scan lines connected to the same data line, The column scan line in the smaller column is connected to the data line via a first switch unit; and / or, The larger column scan line and the data line are connected via a second switch unit.

3. The pixel architecture according to claim 2, wherein: The control terminals of the plurality of first switch units in the pixel architecture are all electrically connected to the first control line; and / or, The control ends of the plurality of second switch units in the pixel architecture are all electrically connected to the second control line.

4. The pixel architecture according to claim 3, wherein: The first control lines include first in-plane control lines located in the panel and first out-of-plane control lines located outside the panel, the first out-of-plane control lines being provided in a chip-on-film manner; and / or, The second control lines include second in-plane control lines located in the panel and second out-of-plane control lines located outside the panel. The second out-of-plane control lines are provided in a chip-on-film manner.

5. The pixel architecture according to claim 2, wherein: The first switching unit includes a first switching transistor; and / or, The second switching unit includes a second switching transistor.

6. The pixel architecture according to any one of claims 1 to 5, wherein: The pixel architecture includes an inversion architecture.

7. A pixel driving method, characterized in that: The pixel driving method is applied to the pixel architecture according to any one of claims 1 to 6, wherein the row scan lines in the pixel architecture are divided into a plurality of row scan line groups, wherein when M is an odd number greater than or equal to 1, the row scan lines in the 2M-1th row and the 2M+1th row are used as the Mth row scan line group; and when M is an even number greater than or equal to 1, the row scan lines in the Mth row and the M+2th row are used as the Mth row scan line group. The pixel driving method comprises: When driving is performed using a frequency doubling refresh technology, display data is sequentially input to each of the corresponding row scan line groups.

8. The pixel driving method according to claim 7, wherein: The step of sequentially inputting display data to each corresponding row scan line group includes: When display data is input to the odd-numbered row scan line group, the first switch unit in the pixel structure is controlled to be in an on state, and the second switch unit in the pixel structure is controlled to be in an off state; and / or, When display data is input to the row scan line group of even bits, the second switch unit in the pixel structure is controlled to be in a conducting state, and the first switch unit in the pixel structure is controlled to be in a cut-off state.

9. The pixel driving method according to claim 7 or 8, wherein: The pixel driving method includes: When driving is performed in a row-by-row manner, display data is sequentially input to each corresponding row of scan lines.

10. The pixel driving method according to claim 9, wherein: The step of sequentially inputting display data to each corresponding row of scan lines includes: When display data is input to the odd-numbered row scan lines, the first switch unit in the pixel structure is controlled to be in an on state, and the second switch unit in the pixel structure is controlled to be in an off state; and / or, When display data is input to the even-numbered row scan line, the second switch unit in the pixel structure is controlled to be in an on state, and the first switch unit in the pixel structure is controlled to be in an off state.

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