Transistor and method of manufacturing the same

Abstract

The present disclosure provides a transistor and a manufacturing method thereof, and relates to the technical field of semiconductor technology, and aims to solve the technical problems of a large variation range of threshold voltage and a large gate-induced drain leakage current. The transistor comprises a substrate, the substrate comprising an active region with a first recess; a first source-drain region and a second source-drain region located on two sides of the first recess respectively, the distance between the first source-drain region and the first recess being smaller than the distance between the second source-drain region and the first recess; a gate, the gate comprising a first part located in the first recess and a second part located on the first part, the length of the second part being greater than the length of the first part, and the center line of the second part being located on the same side of the center line of the first part as the second source-drain region; and a gate dielectric layer located between the gate and the active region. The second part protects the active region between the second source-drain region and the first recess, and without increasing the depth of the second active region, the variation range of the threshold voltage is reduced, and the gate-induced drain leakage current is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a transistor and a method for manufacturing the same. Background Technology

[0002] With the continuous development of technology, semiconductor structures, especially memory, are being used more and more widely. Memory consists of multiple transistors. A transistor typically includes a source region, a drain region, a channel region located between the source and drain regions, a gate dielectric layer located at least on the channel region, and a gate located on the gate dielectric layer. The transistor uses the electric field formed by the gate to control the amount of induced charge in the channel region, thereby changing the state of the channel region and thus controlling the drain current.

[0003] However, with the miniaturization of transistor size, the threshold voltage of transistors varies over a wide range, and the gate-induced drain leakage current (GIDL) is large, which often affects the performance of transistors. Summary of the Invention

[0004] In view of the above problems, this disclosure provides a transistor and a method for manufacturing the same, so as to reduce the range of threshold voltage variation and reduce gate-induced drain leakage current.

[0005] According to some embodiments, a first aspect of this disclosure provides a method comprising:

[0006] A substrate, the substrate including an active region having a first groove;

[0007] Along the first direction, there are a first source / drain region and a second source / drain region located on both sides of the first groove, and the distance between the first source / drain region and the first groove is smaller than the distance between the second source / drain region and the first groove.

[0008] The gate includes a first portion located within the first recess and a second portion located on the first portion, wherein the length of the second portion is greater than the length of the first portion along the first direction, and the center line of the second portion is located on the same side of the center line of the first portion as the second source / drain region.

[0009] The gate dielectric layer located between the gate and the active region.

[0010] In some possible embodiments, the gate further includes an isolation layer covering the sides and top of the second portion, the orthographic projection of the isolation layer onto the active region covering at least a portion of the second source / drain region.

[0011] In some possible embodiments, the first source / drain region includes a first lightly doped region and a first heavily doped region;

[0012] The first heavily doped region and the first lightly doped region have a partial overlap, and the depth of the first heavily doped region is greater than the depth of the first lightly doped region. Along the first direction, a portion of the first lightly doped region is located between the first heavily doped region and the first groove.

[0013] In some possible embodiments, one end of the first lightly doped region extends into the first groove.

[0014] In some possible embodiments, the transistor further includes: a first injection region located below the first source / drain region, and a second injection region located below the second source / drain region;

[0015] The conductivity type of the ions implanted in the first and second implantation regions is opposite to that of the active region, and the conductivity type of the first and second implantation regions is the same as that of the active region, so that the conductivity of the first and second implantation regions is lower than that of the active region.

[0016] In some possible embodiments, the distance from the bottom surface of the first injection region and the second injection region to the top surface of the active region is greater than the depth of the first groove.

[0017] In some possible embodiments, the second source / drain region includes a second lightly doped region, which is spaced apart from the first groove.

[0018] In some possible embodiments, the second source / drain region further includes a second heavily doped region;

[0019] The second heavily doped region and the second lightly doped region have a partial overlap, and the depth of the second heavily doped region is greater than the depth of the second lightly doped region. Along the first direction, a portion of the second lightly doped region is located between the second heavily doped region and the first groove.

[0020] In some possible embodiments, the second source / drain region includes a second heavily doped region, which is spaced apart from the first groove.

[0021] In some possible embodiments, the doping concentration of the second heavily doped region is different from that of the first heavily doped region.

[0022] The transistors provided in this disclosure have at least the following advantages:

[0023] The transistor provided in this disclosure includes a substrate, a gate, a gate dielectric layer, a first source-drain region, and a second source-drain region. The substrate includes an active region with a first groove. The first source-drain region and the second source-drain region are respectively disposed on both sides of the first groove along a first direction, and the distance between the first source-drain region and the first groove is less than the distance between the second source-drain region and the first groove. The gate includes a first portion located within the first groove and a second portion located on the first portion. Along the first direction, the length of the second portion is greater than the length of the first portion, and the centerline of the second portion is located on the same side as the centerline of the second source-drain region. The second source-drain region is further from the first groove, and the portion of the second portion protruding from the first portion along the first direction is more located between the first groove and the second source-drain region. This portion of the second portion can protect the active region, reducing damage to the active region, thereby reducing channel region damage and reducing the threshold voltage variation range. Furthermore, it eliminates the need to increase the dimension of the second source-drain region along the depth direction, avoiding excessive overlap between the second source-drain region and the first portion along the depth direction. When the second source-drain region is used as a drain region, it can reduce the gate-induced drain leakage current. Furthermore, by increasing the size of the first source / drain region along the depth direction, damage to the active region can be reduced, further reducing the range of threshold voltage variation.

[0024] According to some embodiments, a second aspect of this disclosure provides a method for manufacturing a transistor, comprising:

[0025] A substrate is provided, the substrate including an active region having a first groove;

[0026] A gate dielectric layer is formed at least on the sidewall and bottom of the first groove, and the gate dielectric layer located in the first groove surrounds the second groove;

[0027] A gate is formed on the gate dielectric layer, and a first source / drain region and a second source / drain region are formed within the active region; wherein, along a first direction, the first source / drain region and the second source / drain region are respectively located on both sides of the first groove, and the distance between the first source / drain region and the first groove is less than the distance between the second source / drain region and the first groove; the gate includes a first portion located within the first groove, and a second portion located on the first portion, wherein, along the first direction, the length of the second portion is greater than the length of the first portion, and the centerline of the second portion and the second source / drain region are located on the same side of the centerline of the first portion.

[0028] In some possible embodiments, a gate is formed on the gate dielectric layer, and a first source / drain region and a second source / drain region are formed within the active region, including:

[0029] A gate conductive layer is formed on the gate dielectric layer, the gate conductive layer filling the second groove and covering the gate dielectric layer outside the second groove;

[0030] Remove part of the gate conductive layer, retaining the first portion located within the second groove and the second portion located on the first portion;

[0031] Using the second part as a mask, a first lightly doped region and a second lightly doped region are formed in the active region. Along the first direction, the distance between the first lightly doped region and the first groove is smaller than the distance between the second lightly doped region and the first groove.

[0032] An isolation layer is formed on the side and top surface of the second portion, and the isolation layer, the second portion, and the first portion form the gate.

[0033] Using the isolation layer as a mask, a first heavily doped region is formed at least in the active region. The first heavily doped region and the first lightly doped region have a partial overlap. The first heavily doped region and the first lightly doped region form the first source / drain region, and at least the second lightly doped region forms the second source / drain region.

[0034] In some possible embodiments, using the isolation layer as a mask, a first heavily doped region is formed at least within the active region, the first heavily doped region having partial overlap with the first lightly doped region, and at least a second lightly doped region forms the second source / drain region, including:

[0035] Using the isolation layer as a mask, a first heavily doped region and a second heavily doped region are formed in the active region. The first heavily doped region and the first lightly doped region have a partial overlap, and the second heavily doped region and the second lightly doped region have a partial overlap. The first heavily doped region and the first lightly doped region form the first source / drain region, and the second heavily doped region and the second lightly doped region form the second source / drain region.

[0036] In some possible embodiments, a gate is formed on the gate dielectric layer, and a first source / drain region and a second source / drain region are formed within the active region, including:

[0037] A gate conductive layer is formed on the gate dielectric layer, the gate conductive layer filling the second groove and covering the gate dielectric layer outside the second groove;

[0038] Remove part of the gate conductive layer, retaining the first portion located within the second groove and the second portion located on the first portion;

[0039] Using the second part as a mask, a first lightly doped region is formed within the active region;

[0040] An isolation layer is formed on the side and top surface of the second portion, and the isolation layer, the second portion, and the first portion form the gate.

[0041] Using the isolation layer as a mask, a first heavily doped region and a second heavily doped region are formed in the active region. The first heavily doped region and the first lightly doped region have a partial overlap. The first heavily doped region and the first lightly doped region form the first source / drain region, and the second heavily doped region forms the second source / drain region.

[0042] In some possible embodiments, a substrate is provided, the substrate including an active region, and after the active region has a first groove, it further includes:

[0043] A first implantation region and a second implantation region are formed inside the active region and on both sides of the first groove by an ion implantation process. The conductivity type of the ions implanted in the first implantation region and the second implantation region is opposite to that of the active region, and the conductivity type of the first implantation region and the second implantation region is the same as that of the active region, so that the conductivity of the first implantation region and the second implantation region is lower than that of the active region.

[0044] The transistor fabrication method provided in this disclosure has at least the following advantages:

[0045] In the transistor fabrication method provided in this disclosure, the formed second source / drain region is located far from the first groove, and the portion of the second part protruding from the first part along the first direction is more located between the first groove and the second source / drain region. This second part can protect the active region, reducing damage to the active region, thereby reducing damage to the channel region and lowering the threshold voltage variation range. Simultaneously, it can also avoid excessive overlap between the second source / drain region and the first part along the depth direction. When the second source / drain region is used as the drain region, it can reduce the gate-induced drain leakage current. Furthermore, by increasing the dimension of the first source / drain region along the depth direction, damage to the channel region adjacent to the first source / drain region can be further reduced, thereby lowering the threshold voltage variation range. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of a transistor in related technologies;

[0047] Figure 2 This is a schematic diagram of the deepening of the drain region in a transistor in related technologies;

[0048] Figure 3 This is a schematic diagram of a first structure of a transistor in one embodiment of the present disclosure;

[0049] Figure 4 This is a schematic diagram of a second structure of a transistor in one embodiment of the present disclosure;

[0050] Figure 5This is a schematic diagram of a third structure of a transistor in one embodiment of the present disclosure;

[0051] Figure 6 This is a schematic diagram of a fourth structure of a transistor in one embodiment of the present disclosure;

[0052] Figure 7 This is a schematic diagram of a fifth structure of a transistor according to an embodiment of the present disclosure;

[0053] Figure 8 This is a flowchart of a method for manufacturing a transistor according to an embodiment of the present disclosure;

[0054] Figure 9 This is a schematic diagram of the substrate structure in one embodiment of the present disclosure;

[0055] Figure 10 This is a schematic diagram of the structure after the gate dielectric layer is formed in one embodiment of the present disclosure;

[0056] Figure 11 This is a schematic diagram of the structure after the gate conductive layer is formed in one embodiment of the present disclosure;

[0057] Figure 12 This is a schematic diagram of the structure after forming the first part and the second part in one embodiment of the present disclosure;

[0058] Figure 13 This is a diagram illustrating a first fabrication process for forming the first source / drain region and the second source / drain region in an embodiment of this disclosure.

[0059] Figure 14 This is a diagram illustrating a second fabrication process for forming the first and second source / drain regions in one embodiment of the present disclosure.

[0060] Figure 15 This is a diagram illustrating a third fabrication process for forming the first and second source / drain regions in one embodiment of this disclosure.

[0061] Figure 16 This is a schematic diagram of a structure after the formation of the first injection region and the second injection region in one embodiment of the present disclosure;

[0062] Figure 17 This is a schematic diagram of another structure after the formation of the first injection region and the second injection region in one embodiment of the present disclosure;

[0063] Figure 18 This is a schematic diagram of the structure of a transistor after the formation of the first source-drain region and the second source-drain region in one embodiment of the present disclosure;

[0064] Figure 19 This is a schematic diagram of another structure of the transistor after the formation of the first source-drain region and the second source-drain region in one embodiment of the present disclosure;

[0065] Figure 20 This is a schematic diagram of another structure of the transistor after the formation of the first source-drain region and the second source-drain region in one embodiment of the present disclosure.

[0066] Explanation of reference numerals in the attached figures:

[0067] 10 - Substrate; 11 - Active region;

[0068] 12-First groove; 13-Shallow groove isolation structure;

[0069] 20 - Gate dielectric layer; 21 - Second groove;

[0070] 30 - Gate; 31 - First part;

[0071] 32 - Part Two; 33 - Isolation Layer;

[0072] 34 - Gate conductive layer; 40 - First source / drain region;

[0073] 41 - First lightly doped region; 42 - First heavily doped region;

[0074] 50 - Second source / drain region; 51 - Second lightly doped region;

[0075] 52 - Second doped region; 61 - First implantation region;

[0076] 62 - Second injection zone; 63 - Third injection zone;

[0077] 71 - Source region; 72 - Drain region. Detailed Implementation

[0078] The related technologies have problems such as a large range of threshold voltage variation and a large gate-induced drain leakage current. The reason is that as the size of transistors is miniaturized, the channel length is reduced, and the short channel effect, punch-through effect, and drain-induced barrier lowering (DIBL) effect all increase the range of threshold voltage variation.

[0079] To reduce the range of threshold voltage variation, such as Figure 1 As shown, a portion of the gate 30 is typically disposed within the active region 11. This is done to reduce damage to the channel region during gate 30 formation, such as... Figure 2 As shown, the depths of the source region 71 and the drain region 72 are increased. However, with the increased depth of the drain region 72, there is a greater overlap between the drain region 72 and the portion of the gate 30 located in the active region 11 along the depth direction, resulting in a larger gate-induced drain leakage current.

[0080] This disclosure provides a transistor in which a second source-drain region and a first source-drain region are located on opposite sides of a first groove in an active region, with the second source-drain region being farther from the first groove than the first source-drain region. A portion of the gate is disposed within the first groove of the active region, and the centerline of the gate outside the first groove and the centerline of the second source-drain region are located on the same side of the centerline of the gate inside the first groove. This allows the gate outside the first groove to be more located between the first groove and the second source-drain region, thus protecting the active region, reducing or avoiding damage to the active region, and lowering the threshold voltage variation range. Simultaneously, it avoids excessive overlap between the second source-drain region and the gate inside the first groove along the depth direction, which, when used as a drain region, can reduce gate-induced drain leakage current.

[0081] To make the above-mentioned objects, features, and advantages of the embodiments of this disclosure more apparent and understandable, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0082] See Figure 3 This disclosure provides a transistor comprising a substrate 10, a gate 30, a gate dielectric layer 20, a first source / drain region 40, and a second source / drain region 50. The substrate 10 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon germanide substrate, a germanium-on-insulator (GOI) substrate, or a silicon-on-insulator (SOI) substrate, etc.

[0083] The substrate 10 includes an active area 11 (AA), which can be formed through a patterning process and then subjected to an ion implantation process to make the conductivity type of the active area 11 N-type or P-type, thereby forming the conductivity type of the channel region. For example, if the conductivity type of the active area 11 is P-type, then the active area 11 forms a P-well. The substrate 10 also includes a shallow trench isolation (STI) structure 13 that isolates the active area 11.

[0084] The active region 11 has a first groove, such as Figure 3 As shown, the first groove is located on the top surface of the active region 11, and the first groove can be formed by an etching process. The first groove is used to accommodate a portion of the gate 30, so that a portion of the gate 30 extends into the active region 11. The depth of the first groove is less than the ion implantation depth of the active region 11, so that a portion of the active region 11 below the first groove can form a partial channel region.

[0085] Continue reading Figure 3 The gate 30 includes a first portion 31 (such as...) Figure 3 (As shown in the dashed box), and a second portion 32 located on the first portion 31, the first portion 31 being located within the first groove, and the second portion 32 being located outside the first groove. The first portion 31 and the second portion 32 are an integral structure, that is, the first portion 31 and the second portion 32 form a whole. By placing a portion of the gate 30 within the active region 11, the length of the channel region is increased, thereby reducing short-channel effects, etc., and reducing the range of threshold voltage variation.

[0086] Along the first direction, the length of the second portion 32 is greater than the length of the first portion 31, such that at least one end of the second portion 32 protrudes beyond the first portion 31 and extends above the active region 11. The first direction is perpendicular to the stacking direction of the first portion 31 and the second portion 32. For example, the first portion 31 and the second portion 32 are along the vertical direction (…). Figure 3 If the Z-direction is stacked as shown, then the first direction is the horizontal direction. Figure 3 (shown in the X direction). In some examples, along the first direction, one end of the second portion 32 extends onto the active region 11, and the other end of the first portion 31 is flush with the corresponding end of the first portion 31.

[0087] Along the first direction, the centerline of the second part 32 (e.g.) Figure 3 (as shown by the midpoint line) and the center line of the first part 31 (as shown by the dashed line) Figure 3 (As shown by the double-dotted line) The two portions are spaced apart, meaning the center line of the second portion 32 does not coincide with the center line of the first portion 31 along the first direction. When the first direction is horizontal, the center line of the second portion 32 can be located to the left or right of the center line of the first portion 31. This arrangement biases the second portion 32 relative to the first portion 31, improving the transistor's asymmetry and protecting the active region 11 on one side of the first groove. This reduces damage to the channel region within the active region 11 during fabrication and improves the transistor's reliability.

[0088] In some examples, the gate 30 further includes an isolation layer 33 that covers the top surface of the side of the second portion 32. The isolation layer 33 can be a silicon nitride layer or a silicon oxynitride layer. By providing the isolation layer 33, during high-concentration ion implantation of the active region 11, the isolation layer 33 can serve as a mask layer to determine the ion implantation location; furthermore, it can also serve as a protective layer to prevent implantation into the first portion 31 and the second portion 32, thereby ensuring the performance of both portions 31 and 32.

[0089] Continue reading Figure 3A gate dielectric layer 20 is disposed between the gate 30 and the active region 11 to insulate and isolate the gate 30 and the active region 11. A portion of the gate dielectric layer 20 and a first portion 31 of the gate 30 fill the first groove; that is, the sidewalls and bottom of the first groove are covered by the gate dielectric layer 20, and the first portion 31 of the gate 30 completely fills the first groove covered by the gate dielectric layer 20. When the gate 30 includes an isolation layer 33, the isolation layer 33, the first portion 31, and the second portion 32 are all located on the side of the gate dielectric layer 20 away from the active region 11.

[0090] In some examples, the gate dielectric layer 20 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The materials of both the first part 31 and the second part 32 include conductive materials, such as tungsten, copper, aluminum, doped silicon, or a combination thereof.

[0091] Continue reading Figure 3 The first source / drain region 40 and the second source / drain region 50 are disposed within the active region 11 and are located on opposite sides of the first groove along the first direction. That is, along the first direction, the first source / drain region 40 is located on one side of the first groove, and the second source / drain region 50 is located on the other side of the first groove. One of the first source / drain region 40 and the second source / drain region 50 is electrically connected to the source electrode, and the other is electrically connected to the drain electrode.

[0092] Along the first direction, the distances of the first source / drain region 40 and the second source / drain region 50 from the first groove are not equal, and the one farther from the first groove is located on the same side of the centerline of the second portion 32 as the first portion 31. In this embodiment, the distance between the first source / drain region 40 and the first groove is less than the distance between the second source / drain region 50 and the first groove, and the centerline of the second portion 32 is located on the same side of the centerline of the first portion 31 as the second source / drain region 50, for example, located on... Figure 3 As shown on the right. The distance between the first source / drain region 40 and the first groove refers to the distance between the ends of the first source / drain region 40 and the first groove that are close to each other along the first direction, and the distance between the second source / drain region 50 and the first groove refers to the distance between the ends of the second source / drain region 50 and the first groove that are close to each other along the first direction.

[0093] like Figure 3 As shown, the second source / drain region 50 is far from the first groove, and the channel region is as follows: Figure 3As shown by the thick dashed line, on the one hand, the length of the channel region is increased, overcoming the short-channel effect. On the other hand, the active region 11 located between the second source / drain region 50 and the first groove can avoid damage through the second part 32, thereby reducing damage to the channel region and reducing the range of threshold voltage variation, without needing to increase the depth of the second source / drain region 50 within the active region 11, thus reducing the gate-induced drain leakage current. By increasing the depth of the first source / drain region 40 within the active region 11, damage to the active region 11 below the first source / drain region 40 can be reduced, thereby reducing the range of threshold voltage variation.

[0094] In some examples, the second portion 32, projected onto the active region 11, partially covers the second source / drain region 50 to ensure that the second portion 32 is present on both the active region 11 between the first recess and the second source / drain region 50, so that the active region 11 below the second portion 32 is not damaged during the etching process to form the second portion 32. In embodiments where the gate 30 includes an isolation layer 33 covering the sides and top surface of the second portion 32, the projected onto the active region 11 of the isolation layer 33 at least covers a portion of the second source / drain region 50. Figure 2 As shown, the orthographic projection of the isolation layer 33 onto the active region 11 covers a portion of the second source / drain region 50 and also a portion of the first source / drain region 40.

[0095] Continue reading Figure 3 The first source / drain region 40 includes a first lightly doped region 41 and a first heavily doped region 42. The first heavily doped region 42 and the first lightly doped region 41 have a partial overlap, and the depth of the first heavily doped region 42 is greater than the depth of the first lightly doped region 41. Along the first direction, a portion of the first lightly doped region 41 is located between the first heavily doped region 42 and the first groove 12.

[0096] The first heavily doped region 42 and the first lightly doped region 41 have the same conductivity type, which is opposite to that of the active region 11. For example, if the active region 11 has a P-type conductivity, both the first heavily doped region 42 and the first lightly doped region 41 have an N-type conductivity. The doping concentration of the first heavily doped region 42 is greater than that of the first lightly doped region 41. By setting the first lightly doped region 41, the hot carrier effect and short-channel effect of the transistor can be reduced.

[0097] In some examples, along the first direction, the length of the first lightly doped region 41 is greater than the length of the first heavily doped region 42, and a portion of the first lightly doped region 41 is located between the first heavily doped region 42 and the first groove. Along the direction perpendicular to the active region 11, the depth of the first heavily doped region 42 is greater than the depth of the first lightly doped region 41. For example, the upper end of the first heavily doped region 42 is flush with the upper end of the first lightly doped region 41, and the lower end of the first heavily doped region 42 protrudes beyond the lower end of the first lightly doped region 41.

[0098] In some examples, see Figure 3 One end of the first lightly doped region 41 extends to the first groove 12. Along the first direction, the area between the first heavily doped region 42 and the first groove 12 is the first lightly doped region 41, so as to give full play to the function of the first lightly doped region 41.

[0099] See Figure 4 and Figure 5 In some possible embodiments, the second source / drain region 50 includes a second lightly doped region 51, which is spaced apart from the first groove to make the first source / drain region 40 and the second source / drain region 50 asymmetrical, facilitating the adjustment of the performance of the first source / drain region 40 and the second source / drain region 50. The conductivity type of the second lightly doped region 51 is different from that of the active region 11; for example, the active region 11 is P-type, and the second lightly doped region is N-type.

[0100] In some examples, the second source / drain region 50 further includes a second heavily doped region 52, which partially overlaps with the second lightly doped region 51, and the depth of the second heavily doped region 52 is greater than the depth of the second lightly doped region 51. Along the first direction, a portion of the second lightly doped region 51 is located between the second heavily doped region 52 and the first groove.

[0101] The second heavily doped region 52 and the second lightly doped region 51 have the same conductivity type, but the opposite conductivity type to that of the active region 11. For example, if the active region 11 has a P-type conductivity, the second heavily doped region 52 and the second lightly doped region 51 both have an N-type conductivity. The doping concentration of the second heavily doped region 52 is greater than that of the second lightly doped region 51. The inclusion of the second lightly doped region 51 can further reduce the hot carrier effect and short-channel effect of the transistor.

[0102] Along the first direction, the length of the second lightly doped region 51 is greater than the length of the second heavily doped region 52, and a portion of the second lightly doped region 51 is located between the second heavily doped region 52 and the first groove 12. Along the direction perpendicular to the active region 11, the depth of the second heavily doped region 52 is greater than the depth of the second lightly doped region 51. For example, the upper end of the second heavily doped region 52 is flush with the upper end of the second lightly doped region 51, and the lower end of the second heavily doped region 52 protrudes beyond the lower end of the second lightly doped region 51.

[0103] With this configuration, a first lightly doped region 41 and a first heavily doped region 42 are provided on one side of the first groove, and a second lightly doped region 51 and a second heavily doped region 52 are provided on the other side of the first groove. The first lightly doped region 41 and the second lightly doped region 51 can be fabricated simultaneously, and the first heavily doped region 42 and the second heavily doped region 52 can be fabricated simultaneously, thereby improving the production efficiency of transistors.

[0104] In some other possible embodiments, see [reference] Figure 5The second source / drain region includes a second heavily doped region 52, which is spaced apart from the first groove. For example... Figure 5 As shown, the first source / drain region 40 includes a first heavily doped region 42 and a first lightly doped region 41, and the second source / drain region includes a second heavily doped region 52. The first source / drain region 40 and the second source / drain region are asymmetric. Specifically, the doping concentration of the second heavily doped region 52 is different from that of the first heavily doped region 42, further improving the asymmetry of the transistor and thus enhancing its reliability. For example, the doping concentration of the second heavily doped region 52 is less than that of the first heavily doped region 42.

[0105] See Figure 6 The transistor also includes a first implantation region 61 located below the first source / drain region 40. The conductivity type of the ions implanted in the first implantation region 61 is opposite to that of the active region 11, and the conductivity type of the first implantation region 61 is the same as that of the active region 11, so that the conductivity of the first implantation region 61 is lower than that of the active region 11. The transistor also includes a second implantation region 62 located below the second source / drain region 50. The conductivity type of the ions implanted in the second implantation region 62 is opposite to that of the active region 11, and the conductivity type of the second implantation region 62 is the same as that of the active region 11, so that the conductivity of the second implantation region 62 is lower than that of the active region 11. By setting the first implantation region 61 and the second implantation region 62, the threshold voltage can be further adjusted to reduce the range of threshold voltage variation.

[0106] The first implantation region 61 and the second implantation region 62 are both located within the active region 11. One end of each of the first implantation region 61 and the second implantation region 62 can extend to the first groove 12, and the other end of each can extend to the side of the active region 11 to facilitate the formation of the first implantation region 61 and the second implantation region 62. The first implantation region 61 and the second implantation region 62 can be formed by ion implantation into the active region 11, with the implanted ions having a conductivity type opposite to that of the active region 11. The conductivity of the first implantation region 61 and the second implantation region 62 is reduced by the neutralization reaction between the implanted ions and the dopant ions in the active region 11.

[0107] The first implantation region 61 is located below the first source / drain region 40, and the first implantation region 61 may partially overlap with the first source / drain region 40. For example, the first implantation region 61 is spaced apart from the first lightly doped region 41 and partially overlaps with the first heavily doped region 42. The second implantation region 62 is located below the second source / drain region 50, and the second implantation region 62 may partially overlap with the second source / drain region 50.

[0108] In some examples, the distance from the bottom surface of the first injection region 61 and the second injection region 62 to the top surface of the active region 11 is greater than the depth of the first groove. For example... Figure 6 As shown, the top surfaces of the first injection region 61 and the second injection region 62 are lower than the top surface of the active region 11, and the bottom surfaces of the first injection region 61 and the second injection region 62 are lower than the bottom surface of the first groove 12.

[0109] In some examples, see Figure 7 The transistor also includes a third injection region 63 located below the first groove. The conductivity type of the third injection region 63 is the same as that of the active region 11, but the conductivity of the third injection region 63 is lower than that of the active region 11. The third injection region 63 is spaced apart from the bottom of the first groove 12, and the third injection region 63 is not connected to either the first injection region 61 or the second injection region 62, so as to ensure that a channel region is formed between the first injection region 61, the second injection region 62, and the active region 11 located above the third injection region 63, thereby ensuring the performance of the transistor.

[0110] In summary, the transistor in this embodiment includes a substrate 10, a gate 30, a gate dielectric layer 20, a first source / drain region 40, and a second source / drain region 50. The substrate 10 includes an active region 11 with a first groove. The first source / drain region 40 and the second source / drain region 50 are respectively disposed on both sides of the first groove along a first direction, and the distance between the first source / drain region 40 and the first groove is less than the distance between the second source / drain region 50 and the first groove. The gate 30 includes a first portion 31 located within the first groove and a second portion 32 located on the first portion 31. Along the first direction, the length of the second portion 32 is greater than the length of the first portion 31, and the centerline of the second portion 32 is located on the same side of the centerline of the first portion 31 as the second source / drain region 50. The second source / drain region 50 is located further away from the first groove, and the portion of the second portion 32 that protrudes from the first portion 31 along the first direction is more situated between the first groove and the second source / drain region 50. This portion of the second portion 32 can protect the active region 11, reducing damage to the active region 11, thereby reducing damage to the channel region and lowering the threshold voltage variation range. Simultaneously, it avoids excessive overlap between the second source / drain region 50 and the first portion 31 along the depth direction. When the second source / drain region 50 is used as a drain region, it can reduce the gate-induced drain leakage current. Furthermore, by increasing the dimension of the first source / drain region 40 along the depth direction, damage to the active region 11 can be reduced, further lowering the threshold voltage variation range.

[0111] This disclosure also provides a method for manufacturing a transistor, see embodiments thereof. Figure 8 The method for manufacturing this transistor may include the following steps:

[0112] Step S100: Provide a substrate, the substrate including an active region having a first groove.

[0113] See Figure 9The substrate 10 can be a silicon substrate, germanium substrate, silicon carbide substrate, silicon germanium substrate, germanium-on-insulator substrate, or silicon-on-insulator substrate, etc. The substrate 10 includes an active region 11, which has a first groove 12. The substrate 10 also includes a shallow trench isolation structure 13 to isolate the active region 11.

[0114] In some possible implementations, an active region 11 is formed within the substrate 10 using a patterning process, and then the active region 11 is doped using an ion implantation process to make its conductivity type N-type or P-type, thereby forming the conductivity type of the channel region. The active region 11 is etched to form a first groove 12, the depth of which is less than the ion implantation depth of the active region 11, so that the portion of the active region 11 below the first groove 12 can form a channel region.

[0115] Step S200: A gate dielectric layer is formed at least on the sidewall and bottom of the first groove, and the gate dielectric layer located in the first groove surrounds the second groove.

[0116] See Figure 9 and Figure 10 A gate dielectric layer 20 is formed on the sidewalls and bottom of the first groove 12, as well as on the active region 11 outside the first groove 12, for example, by a deposition process. The gate dielectric layer 20 located within the first groove 12 forms a second groove 21. The gate dielectric layer 20 is made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or a combination of the above materials.

[0117] Step S300: A gate is formed on the gate dielectric layer, and a first source / drain region and a second source / drain region are formed in the active region; wherein, along the first direction, the first source / drain region and the second source / drain region are respectively located on both sides of the first groove, and the distance between the first source / drain region and the first groove is less than the distance between the second source / drain region and the first groove; the gate includes a first portion located in the first groove and a second portion located on the first portion, along the first direction, the length of the second portion is greater than the length of the first portion, and the center line of the second portion and the second source / drain region are located on the same side of the center line of the first portion.

[0118] See Figure 8 , Figures 10 to 13 The gate 30 is located on the side of the gate dielectric layer 20 away from the active region 11, so as to be insulated from the active region 11. The gate 30 includes a first portion 31 and a second portion 32 located on the first portion 31, the first portion 31 being located in the first recess 12 (e.g., Figure 8 As shown, the second portion 32 is located outside the first groove 12. By placing a portion of the gate 30 within the active region 11, the length of the channel region is increased, thereby reducing short-channel effects and thus reducing the range of threshold voltage variation.

[0119] Along the first direction, the length of the second portion 32 is greater than the length of the first portion 31, such that at least one end of the second portion 32 protrudes beyond the first portion 31 and extends above the active region 11. The first direction is perpendicular to the stacking direction of the first portion 31 and the second portion 32; for example, the first direction is a horizontal direction. Figure 13 (As shown in the X direction). Along the first direction, the center line of the second part 32 is spaced apart from the center line of the first part 31, that is, the center line of the second part 32 and the center line of the first part 31 do not coincide along the first direction. With this configuration, the second part 32 is biased relative to the first part 31, which improves the asymmetry of the transistor, reduces damage to the channel region in the active region 11 during fabrication, and improves the reliability of the transistor.

[0120] The first source / drain region 40 and the second source / drain region 50 are disposed within the active region 11 and are located on opposite sides of the first groove 12 along the first direction. That is, along the first direction, the first source / drain region 40 is located on one side of the first groove 12, and the second source / drain region 50 is located on the other side of the first groove 12. The distance between the first source / drain region 40 and the first groove 12 is less than the distance between the second source / drain region 50 and the first groove 12, and the centerline of the second portion 32 and the second source / drain region 50 are located on the same side of the centerline of the first portion 31.

[0121] In summary, in this embodiment, the second source / drain region 50 is located further away from the first groove 12, and the second portion 32, which protrudes from the first portion 31 along the first direction, is more located between the first groove 12 and the second source / drain region 50. This second portion 32 can protect the active region 11, reducing damage to the active region 11, thereby reducing damage to the channel region and lowering the threshold voltage variation range. Simultaneously, it can also avoid excessive overlap between the second source / drain region 50 and the first portion 31 along the depth direction. When the second source / drain region 50 is used as the drain region, it can reduce the gate-induced drain leakage current. Furthermore, by increasing the dimension of the first source / drain region 40 along the depth direction, damage to the channel region adjacent to the first source / drain region 40 can be further reduced, further lowering the threshold voltage variation range.

[0122] In some possible embodiments, a gate is formed on the gate dielectric layer, and a first source / drain region and a second source / drain region are formed within the active region (step S300), including:

[0123] Step S301: A gate conductive layer is formed on the gate dielectric layer, the gate conductive layer filling the second groove and covering the gate dielectric layer outside the second groove.

[0124] See Figures 10 to 12The gate conductive layer 34 can be formed on the gate dielectric layer 20 by processes such as deposition. The gate conductive layer 34 fills the second groove 21 and covers the gate dielectric layer 20 outside the second groove 21. The surface of the gate conductive layer 34 facing away from the active region 11 can be planar.

[0125] Step S302: Remove part of the gate conductive layer, retaining the first part located in the second groove and the second part located on the first part.

[0126] For example, 12 to Figure 14 As shown, the gate conductive layer 34 is etched to remove part of the gate conductive layer 34 outside the second groove 21, while retaining the first portion 31 located in the second groove 21 and the second portion 32 located on the first portion 31.

[0127] It is understood that the second groove 21 is located within the first groove 12, and thus the first portion 31 is located within the first groove 12, while the second portion 32 is located outside the first groove 12. In some examples, the center line of the first portion 31 and the center line of the second portion 32 do not coincide, that is, the second portion 32 and the first portion 31 are asymmetrical, and the second portion 32 is offset relative to the first portion 31.

[0128] Step S303: Using the second part as a mask, a first lightly doped region and a second lightly doped region are formed in the active region. Along the first direction, the distance between the first lightly doped region and the first groove is smaller than the distance between the second lightly doped region and the first groove.

[0129] See Figure 8 and Figure 13 A first lightly doped region 41 and a second lightly doped region 51 are formed within the active region 11 via ion implantation. The conductivity types of the first lightly doped region 41 and the second lightly doped region 51 are opposite to those of the active region 11. Along the first direction, the first lightly doped region 41 and the second lightly doped region 51 are located on opposite sides of the first groove 12, that is, along the first direction, the first lightly doped region 41 and the second lightly doped region 51 are located on opposite sides of the second portion 32.

[0130] Along the first direction, the distance between the first lightly doped region 41 and the first groove 12 is less than the distance between the second lightly doped region 51 and the first groove 12. That is, the first lightly doped region 41 and the second lightly doped region 51 are asymmetrically distributed relative to the first groove 12, with the first lightly doped region 41 being closer to the first groove 12 and the second lightly doped region 51 being farther from the first groove 12. In some examples, the first lightly doped region 41 may extend into the first groove 12.

[0131] At least one of the first lightly doped region 41 and the second lightly doped region 51 may have a partial overlap with the second portion 32 in the orthogonal projection of the active region 11, that is, a portion of the first lightly doped region 41 and / or a portion of the second lightly doped region 51 is located directly below the second portion 32.

[0132] Understandably, since the first lightly doped region 41 and the second lightly doped region 51 are implanted with ions using the second portion 32 as a mask, and the second lightly doped region 51 is farther from the first groove 12 along the first direction, the centerline of the second portion 32 is located on the same side of the first portion 31 as the second lightly doped region 51. That is, along the first direction, the portion of the second portion 32 protruding from the first portion 31 is mostly located between the second lightly doped region 51 and the first groove 12, in order to protect the active region 11 between the second lightly doped region 51 and the first groove 12, reduce damage to the active region 11, and eliminate the need to increase the dimension of the second lightly doped region 51 along the depth direction.

[0133] Step S304: An isolation layer is formed on the side and top surfaces of the second part, and the isolation layer, the second part, and the first part form a gate.

[0134] See Figure 13 An isolation layer 33 is deposited on the side and top surfaces of the second portion 32, and the isolation layer 33, the second portion 32, and the first portion 31 form the gate 30. The orthogonal projection of the isolation layer 33 onto the active region 11 may partially overlap with both the first lightly doped region 41 and the second lightly doped region 51. The material of the isolation layer 33 may include silicon nitride or silicon oxynitride.

[0135] In this embodiment of the present disclosure, by forming an isolation layer 33, when a high concentration of ions is subsequently implanted into the active region 11, the isolation layer 33 can be used as a mask layer to determine the location of ion implantation; on the other hand, the isolation layer 33 can also be used as a protective layer to prevent ions from being implanted into the first part 31 and the second part 32, so as to ensure the performance of the first part 31 and the second part 32.

[0136] In some possible examples, after an isolation layer is formed on the side and top surfaces of the second portion, and the isolation layer, the second portion, and the first portion form the gate (step S304), the process further includes: etching the gate dielectric layer 20 to remove the gate dielectric layer 20 exposed outside the isolation layer 33. Figure 13 As shown, along the first direction, the two ends of the gate dielectric layer 20 are flush with the two ends of the isolation layer 33.

[0137] Step S305: Using the isolation layer as a mask, a first heavily doped region is formed at least in the active region. The first heavily doped region and the first lightly doped region have partial overlap. The first heavily doped region and the first lightly doped region form a first source / drain region. At least a second lightly doped region forms a second source / drain region.

[0138] See Figure 13 and Figure 14 Using the isolation layer 33 as a mask, a first heavily doped region 42 is formed at least within the active region 11 by ion implantation. The first heavily doped region 42 and the first lightly doped region 41 have the same conductivity type, and the doping concentration of the first heavily doped region 42 is greater than that of the first lightly doped region 41. The first heavily doped region 42 and the first lightly doped region 41 partially overlap. By setting the first lightly doped region 41, the hot carrier effect and short-channel effect of the transistor can be reduced.

[0139] In some examples, such as Figure 13 and Figure 14 As shown, along the first direction, the length of the first lightly doped region 41 is greater than the length of the first heavily doped region 42, so that a portion of the first lightly doped region 41 is located between the first heavily doped region 42 and the first recess 12. Along the direction perpendicular to the active region 11 ( Figure 13 (As shown in the Z direction), the depth of the first heavily doped region 42 is greater than the depth of the first lightly doped region 41. For example, the upper end of the first heavily doped region 42 is flush with the upper end of the first lightly doped region 41, and the lower end of the first heavily doped region 42 protrudes from the lower end of the first lightly doped region 41.

[0140] See also some possible implementation methods. Figure 13 Using the isolation layer 33 as a mask, a first heavily doped region 42 is formed at least within the active region 11. The first heavily doped region 42 and the first lightly doped region 41 partially overlap. At least the second lightly doped region 51 forms the second source / drain region 50 (step S305), including:

[0141] Using the isolation layer 33 as a mask, a first heavily doped region 42 and a second heavily doped region 52 are formed in the active region 11. The first heavily doped region 42 and the first lightly doped region 41 have a partial overlap, and the second heavily doped region 52 and the second lightly doped region 51 have a partial overlap. The first heavily doped region 42 and the first lightly doped region 41 form the first source / drain region 40, and the second heavily doped region 52 and the second lightly doped region 51 form the second source / drain region 50.

[0142] The second heavily doped region 52 corresponds to the second lightly doped region 51. The second heavily doped region 52 and the second lightly doped region 51 have the same conductivity type, and the doping concentration of the second heavily doped region 52 is greater than that of the second lightly doped region 51. Setting the second lightly doped region 51 can further reduce the hot carrier effect and short-channel effect of the transistor.

[0143] Along the first direction, the length of the second lightly doped region 51 is greater than the length of the second heavily doped region 52, such that a portion of the second lightly doped region 51 is located between the second heavily doped region 52 and the first groove 12. Along the direction perpendicular to the active region 11, the depth of the second heavily doped region 52 is greater than the depth of the second lightly doped region 51. For example, the upper end of the second heavily doped region 52 is flush with the upper end of the second lightly doped region 51, and the lower end of the second heavily doped region 52 protrudes beyond the lower end of the second lightly doped region 51.

[0144] With this configuration, a first lightly doped region 41 and a first heavily doped region 42 are formed on one side of the first groove 12, and a second lightly doped region 51 and a second heavily doped region 52 are formed on the other side of the first groove 12. The first lightly doped region 41 and the second lightly doped region 51 can be fabricated simultaneously, and the first heavily doped region 42 and the second heavily doped region 52 can be fabricated simultaneously, thereby improving the production efficiency of transistors.

[0145] For other possible implementations, see [link / reference]. Figure 14 Using the isolation layer 33 as a mask, a first heavily doped region 42 is formed at least within the active region 11. The first heavily doped region 42 and the first lightly doped region 41 partially overlap. At least the second lightly doped region 51 forms the second source / drain region 50 (step S305), including:

[0146] Using the isolation layer 33 as a mask, a first heavily doped region 42 is formed in the active region 11. The first heavily doped region 42 and the first lightly doped region 41 partially overlap. The first heavily doped region 42 and the first lightly doped region 41 form the first source / drain region 40, and the second lightly doped region 51 forms the second source / drain region 50. This configuration improves the asymmetry of the transistor, and the performance of the first source / drain region 40 and the second source / drain region 50 can be adjusted according to operational requirements.

[0147] In some possible embodiments, see Figure 10 , Figure 11 , Figure 12 and Figure 15 A gate 30 is formed on the gate dielectric layer 20, and a first source / drain region 40 and a second source / drain region 50 are formed in the active region 11 (step S300), including:

[0148] Step S301': A gate conductive layer is formed on the gate dielectric layer, the gate conductive layer filling the second groove and covering the gate dielectric layer outside the second groove.

[0149] Step S302': Remove part of the gate conductive layer, retaining the first part located in the second groove and the second part located on the first part.

[0150] Steps S301' and S302' can be referred to as steps S301 and S302 in the above embodiment, respectively, and will not be repeated here.

[0151] Step S303': Using the second part as a mask, a first lightly doped region is formed in the active region.

[0152] like Figure 15 As shown, a first lightly doped region 41 is formed within the active region 11 via ion implantation. The conductivity type of the first lightly doped region 41 is opposite to that of the active region 11. In some examples, the first lightly doped region 41 may extend to the first recess 12 (see...). Figure 9 ).

[0153] Step S304': An isolation layer is formed on the side and top surfaces of the second part, and the isolation layer, the second part, and the first part form a gate.

[0154] An isolation layer 33 is deposited on the side and top surfaces of the second portion 32. The orthogonal projection of the isolation layer 33 onto the active region 11 may partially overlap with the first lightly doped region 41. The isolation layer 33 is made of silicon nitride or silicon oxynitride.

[0155] Step S305': Using the isolation layer as a mask, a first heavily doped region and a second heavily doped region are formed in the active region. The first heavily doped region and the first lightly doped region have a partial overlap. The first heavily doped region and the first lightly doped region form the first source / drain region, and the second heavily doped region forms the second source / drain region.

[0156] like Figure 15 As shown, using the isolation layer 33 as a mask, a first heavily doped region 42 and a second heavily doped region 52 are formed in the active region 11 by ion implantation. The first heavily doped region 42 corresponds to the first lightly doped region 41, and the two have the same conductivity type. The doping concentration of the first heavily doped region 42 is greater than that of the first lightly doped region 41.

[0157] In some examples, the second doped region 52 has the same conductivity type as the first doped region 42, and the doping concentration of the second doped region 52 is different from that of the first doped region 42. For example, the doping concentration of the second doped region 52 is lower than that of the first doped region 42, in order to improve the asymmetry of the first source / drain region 40 and the second source / drain region 50. The performance of the first source / drain region 40 and the second source / drain region 50 can be adjusted according to the working requirements.

[0158] In some possible embodiments, a substrate is provided, the substrate including an active region, and after the active region has a first groove (step S100), the method further includes: forming a first implantation region and a second implantation region inside the active region and on both sides of the first groove by an ion implantation process, wherein the conductivity type of the ions implanted in the first implantation region and the second implantation region is opposite to the conductivity type of the active region, and the conductivity type of the first implantation region and the second implantation region is the same as the conductivity type of the active region, so that the conductivity of the first implantation region and the second implantation region is lower than the conductivity of the active region.

[0159] See Figure 16 In some possible examples, ion implantation is performed within the active region 11 to form a first implantation region 61 and a second implantation region 62. The ion implantation type of the first implantation region 61 and the second implantation region 62 is opposite to the conductivity type of the active region 11. For example, the conductivity type of the active region 11 is P-type. After N-type ion implantation is performed in a portion of the active region 11, that region forms the first implantation region 61 and the second implantation region 62. The conductivity type of the first implantation region 61 and the second implantation region 62 is still P-type, and the conductivity of both the first implantation region 61 and the second implantation region 62 is lower than that of the active region 11.

[0160] The first injection region 61 and the second injection region 62 are located inside the active region 11, meaning that the first injection region 61 and the second injection region 62 are not exposed on the top surface of the active region 11. By setting the first injection region 61 and the second injection region 62, the threshold voltage can be adjusted to reduce the range of threshold voltage variation. The distance from the bottom surface of the first injection region 61 and the second injection region 62 to the top surface of the active region 11 is greater than the depth of the first groove 12.

[0161] In some examples, see Figure 17 While ion implantation is performed in the active region 11 to form the first implantation region 61 and the second implantation region 62, a third implantation region 63 is also formed within the active region 11. The conductivity type of the third implantation region 63 is the same as that of the active region 11, but the conductivity of the third implantation region 63 is lower than that of the active region 11. The third implantation region 63 is spaced apart from the bottom of the first groove 12, and the third implantation region 63 is not connected to either the first implantation region 61 or the second implantation region 62, to ensure that a channel region is formed between the first implantation region 61, the second implantation region 62, and the active region 11 located above the third implantation region 63, thereby ensuring the performance of the transistor.

[0162] See Figure 18 , Figure 19 and Figure 20 The first injection region 61 is located below the first source / drain region 40, and the second injection region 62 is located below the second source / drain region 50. Both the first injection region 61 and the second injection region 62 can be in contact with the first groove 12.

[0163] In embodiments where the first source / drain region 40 includes a first lightly doped region 41 and a first heavily doped region 42, and the second source / drain region 50 includes a second lightly doped region 51 and a second heavily doped region 52, such as... Figure 18 As shown, the first implantation region 61 is spaced apart from the first lightly doped region 41 and is in contact with the first heavily doped region 42. The second implantation region 62 is spaced apart from the second lightly doped region 51 and is in contact with the second heavily doped region 52.

[0164] In an embodiment where the first source / drain region 40 includes a first lightly doped region 41 and a first heavily doped region 42, and the second source / drain region 50 includes a second lightly doped region 51, the depth of the second lightly doped region 51 is greater than the depth of the first lightly doped region 41. Figure 19 As shown, the first implantation region 61 is spaced apart from the first lightly doped region 41 and is in contact with the first heavily doped region 42. The second implantation region 62 is in contact with the second lightly doped region 51.

[0165] In embodiments where the first source / drain region 40 includes a first lightly doped region 41 and a first heavily doped region 42, and the second source / drain region 50 includes a second heavily doped region 52, as shown below... Figure 20 As shown, the first implantation region 61 is spaced apart from the first lightly doped region 41 and is in contact with the first heavily doped region 42. The second implantation region 62 is in contact with the second heavily doped region 52.

[0166] The embodiments or implementation methods described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0167] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A transistor, comprising: The transistor comprises: a substrate comprising an active region having a first recess; a first source / drain region and a second source / drain region located on two sides of the first recess along a first direction, a distance between the first source / drain region and the first recess is smaller than a distance between the second source / drain region and the first recess, the first source / drain region is a source region, and the second source / drain region is a drain region; a gate comprising a first part located in the first recess, and a second part located on the first part, a length of the second part is greater than a length of the first part along the first direction, and a center line of the second part is located on a same side of a center line of the first part as the second source / drain region; a gate dielectric layer located between the gate and the active region; a first implant region located below the first source / drain region and a second implant region located below the second source / drain region, the first implant region and the second implant region are both located in the active region, one end of the first implant region and the second implant region both extends to the first recess, the other end of the first implant region and the second implant region both extends to a side surface of the active region, a bottom surface of the first implant region and the second implant region is lower than a bottom surface of the first recess, and a region below the first recess is the active region; a conductive type of ions implanted in the first implant region and the second implant region is opposite to a conductive type of the active region, and a conductive type of the first implant region and the second implant region is same as the conductive type of the active region, so that a conductive capability of the first implant region and the second implant region is lower than a conductive capability of the active region.

2. The transistor of claim 1, wherein: the gate further comprises an isolation layer covering a side surface and a top surface of the second part, a normal projection of the isolation layer on the active region covers at least part of the second source / drain region.

3. The transistor of claim 1 or 2, wherein: the first source / drain region comprises a first lightly-doped region and a first heavily-doped region; the first heavily-doped region has a partial overlap region with the first lightly-doped region, and a depth of the first heavily-doped region is greater than a depth of the first lightly-doped region, and part of the first lightly-doped region is located between the first heavily-doped region and the first recess along the first direction.

4. The transistor of claim 3, wherein: one end of the first lightly-doped region extends to the first recess.

5. The transistor of claim 4, wherein: a distance between a bottom surface of the first implant region and the second implant region and a top surface of the active region is greater than a depth of the first recess.

6. The transistor of claim 5, wherein: the second source / drain region comprises a second lightly-doped region, and the second lightly-doped region is spaced apart from the first recess.

7. The transistor of claim 6, wherein: the second source / drain region further comprises a second heavily-doped region. The second heavily doped region has a partially overlapped region with the second lightly doped region, and a depth of the second heavily doped region is greater than a depth of the second lightly doped region, and along the first direction, a part of the second lightly doped region is located between the second heavily doped region and the first recess.

8. The transistor of claim 3, wherein: The second source-drain region comprises a second heavily doped region, and the second heavily doped region is arranged apart from the first recess.

9. The transistor of claim 8, wherein: The second heavily doped region has a doping concentration different from a doping concentration of the first heavily doped region.

10. The transistor of claim 1, wherein The transistor further comprises a third implanted region located in the active region below the first recess, the third implanted region is arranged apart from the first recess and is not in communication with the first implanted region and the second implanted region; The third implanted region has a same conductivity type as the active region, and the third implanted region has a lower conductivity than the active region.

11. A method of fabricating a transistor, comprising: Comprising: A substrate is provided, and the substrate comprises an active region, and the active region has a first recess; A first implanted region and a second implanted region are formed in the active region and on both sides of the first recess by an ion implantation process, one end of the first implanted region and the second implanted region extends to the first recess, the other end of the first implanted region and the second implanted region extends to a side surface of the active region, and a bottom surface of the first implanted region and the second implanted region is lower than a bottom surface of the first recess, wherein the first implanted region and the second implanted region are implanted with ions having a conductivity type opposite to a conductivity type of the active region, and the first implanted region and the second implanted region have the same conductivity type as the active region, so that the first implanted region and the second implanted region have a lower conductivity than the active region; a gate dielectric layer is formed at least on a sidewall and a bottom of the first recess, and the gate dielectric layer in the first recess is enclosed to form a second recess; A gate electrode is formed on the gate dielectric layer, and a first source-drain region and a second source-drain region are formed in the active region, the first source-drain region is a source region, and the second source-drain region is a drain region; wherein along a first direction, the first source-drain region and the second source-drain region are located on both sides of the first recess respectively, and a distance between the first source-drain region and the first recess is smaller than a distance between the second source-drain region and the first recess; the gate electrode comprises a first part located in the first recess, and a second part located on the first part, along the first direction, a length of the second part is greater than a length of the first part, and a center line of the second part is located on a same side of a center line of the first part as the second source-drain region.

12. The manufacturing method of claim 11, wherein: A gate electrode is formed on the gate dielectric layer, and a first source-drain region and a second source-drain region are formed in the active region, the first source-drain region is a source region, and the second source-drain region is a drain region; wherein along a first direction, the first source-drain region and the second source-drain region are located on both sides of the first recess respectively, and a distance between the first source-drain region and the first recess is smaller than a distance between the second source-drain region and the first recess; the gate electrode comprises a first part located in the first recess, and a second part located on the first part, along the first direction, a length of the second part is greater than a length of the first part, and a center line of the second part is located on a same side of a center line of the first part as the second source-drain region. ​ removing part of the gate conductive layer, leaving a first part in the second recess and a second part on the first part; forming a first light doped region and a second light doped region in the active region with the second part as a mask, the distance between the first light doped region and the first recess is less than the distance between the second light doped region and the first recess along the first direction; forming an isolation layer on the side and top surface of the second part, the isolation layer, the second part and the first part form the gate; forming a first heavy doped region in the active region with the isolation layer as a mask, the first heavy doped region has a partially overlapped region with the first light doped region, the first heavy doped region and the first light doped region form the first source / drain region, at least the second light doped region forms the second source / drain region.

13. The manufacturing method of claim 12, wherein forming a first heavy doped region and a second heavy doped region in the active region with the isolation layer as a mask, the first heavy doped region has a partially overlapped region with the first light doped region, the second heavy doped region has a partially overlapped region with the second light doped region, the first heavy doped region and the first light doped region form the first source / drain region, the second heavy doped region and the second light doped region form the second source / drain region.

14. The manufacturing method of claim 11, wherein forming a gate on the gate dielectric layer and forming a first source / drain region and a second source / drain region in the active region, comprises: forming a gate conductive layer on the gate dielectric layer, the gate conductive layer fills in the second recess and covers the gate dielectric layer outside the second recess; removing part of the gate conductive layer, leaving a first part in the second recess and a second part on the first part; forming a first light doped region in the active region with the second part as a mask; forming an isolation layer on the side and top surface of the second part, the isolation layer, the second part and the first part form the gate; forming a first heavy doped region and a second heavy doped region in the active region with the isolation layer as a mask, the first heavy doped region has a partially overlapped region with the first light doped region, the second heavy doped region forms the second source / drain region.

15. The manufacturing method of any one of claims 11-14, wherein ​ The first implant region and the second implant region are formed by ion implantation in the active region, and a third implant region is formed in the active region under the first recess at the same time, the third implant region is arranged apart from the first recess, and is not in communication with the first implant region and the second implant region, wherein the third implant region has the same conductivity type as the active region, and the third implant region has a lower conductivity than the active region.

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