MOSFET device with low Miller capacitance and preparation method thereof

Abstract

The present invention provides a MOSFET device with low Miller capacitance and a preparation method, comprising a heavily doped first conductivity type semiconductor substrate, a lightly doped first conductivity type semiconductor epitaxial layer, a heavily doped first conductivity type semiconductor vertical sinker, a gate dielectric layer, N-type polysilicon, a first conductivity type semiconductor body region, a second conductivity type semiconductor lightly doped drain region, a heavily doped second conductivity type semiconductor drain contact region, a heavily doped second conductivity type source region, P-type polysilicon, an insulating dielectric layer below a source metal field plate, a source metal field plate, a dielectric layer isolating the source metal field plate from the drain metal, a drain metal, and a source metal; the present invention provides a MOSFET device with low Miller capacitance, wherein the gate comprises two types of differently doped polysilicon, and the formed polysilicon PN junction introduces a polysilicon PN junction depletion region capacitance, which is connected in series with the original Miller capacitance of the device, thereby reducing the overall Miller capacitance.

Description

Technical Field

[0001] The present invention relates to power semiconductor technology, and in particular to a MOSFET device with low Miller capacitance and a preparation method thereof. Background Art

[0002] Power semiconductor devices are widely used in modern society. They are essential core components in power electronics technology and are primarily used in consumer electronics, industrial control, new energy vehicles, smart grids, and other adjacent fields. Emerging application areas such as intelligent equipment manufacturing, the Internet of Things, and renewable energy power generation are also becoming important markets for power semiconductors. As a key component of power semiconductors, the power MOSFET is one of the most popular power devices on the market today due to its high input impedance, low on-resistance, and fast switching speed.

[0003] According to the direction of current, power MOSFETs can be divided into lateral MOSFET and vertical MOSFET devices. The manufacturing process of lateral MOSFET is simpler and the cost is lower. Due to the smaller gate and drain overlap area, lateral MOSFET has a smaller Miller capacitance, resulting in faster switching speed and lower switching loss. However, the lateral trench limits the reduction of the width of the lateral MOSFET cell, making it difficult to increase the current density. The vertical channel in the vertical MOSFET device is conducive to reducing the cell width and reducing the on-resistance. However, the planar gate type vertical MOSFET device has JFET region resistance, which makes the on-resistance larger, and the trench type vertical MOSFET device has a significantly increased overlap area between the gate and the drain and source, which increases the gate capacitance of the trench type vertical MOSFET device, resulting in slower switching speed, increased switching loss, increased driving loss and other problems. In 2011, TI disclosed a new type of low on-resistance and low gate capacitance MOSFET device. This new device uses RESURF technology and field plate technology to allow current to flow through the substrate via the sinker region, simultaneously solving the problems of low current density in lateral MOSFET devices and large gate capacitance in vertical power MOSFET devices. In other words, this new device combines the advantages of low gate parasitic capacitance of lateral power MOSFET devices with the high current capability of vertical power MOSFET devices. However, the overlapping area between the gate and drain of this new device still produces a large Miller capacitance, resulting in slower switching speed and increased switching losses. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a MOSFET device with low Miller capacitance and a preparation method thereof.

[0005] In order to achieve the above-mentioned purpose of the invention, the technical solution of the present invention is as follows:

[0006] A low Miller capacitance MOSFET device includes a heavily doped first conductivity type semiconductor substrate 1, a lightly doped first conductivity type semiconductor epitaxial layer 2, a heavily doped first conductivity type semiconductor vertical sinker 3, a gate dielectric layer 4, N-type polysilicon 5, a first conductivity type semiconductor body region 6, a second conductivity type semiconductor lightly doped drain region 7, a heavily doped second conductivity type semiconductor drain contact region 8, a heavily doped second conductivity type source region 9, P-type polysilicon 10, an insulating dielectric layer 11 below a source metal field plate, a source metal field plate 12, a source metal field plate and drain metal isolation dielectric layer 13, a drain metal 14, and a source metal 15;

[0007] Among them, the lightly doped first conductive type semiconductor epitaxial layer 2 is located on the upper surface of the heavily doped first conductive type semiconductor substrate 1; the heavily doped first conductive type semiconductor vertical sinker 3 is located on the left side of the lightly doped first conductive type semiconductor epitaxial layer 2, and is connected to the heavily doped first conductive type semiconductor substrate 1 and the source metal field plate 12; the first conductive type semiconductor body region 6 is located in the upper left part of the lightly doped first conductive type semiconductor epitaxial layer 2, and is in contact with the heavily doped first conductive type semiconductor vertical sinker 3 and the source metal field plate 12 on the left side, and is in contact with the second conductive type semiconductor lightly doped drain region 7 on the right side; the second conductive type semiconductor lightly doped drain region 7 is located in the upper right part of the lightly doped first conductive type semiconductor epitaxial layer 2, and has a heavily doped second conductive type semiconductor drain contact region 8 on the upper right inside the second conductive type semiconductor lightly doped drain region 7; the heavily doped second conductive type source region 9 is located on the upper left side of the first conductive type semiconductor body region 6, and is heavily doped The left side of the second conductive type source region 9 is in contact with the source metal field plate 12; the N-type polysilicon 5 is isolated from the first conductive type semiconductor body region 6 by the gate dielectric layer 4; the P-type polysilicon 10 is located on the right side of the N-type polysilicon 5 and the two are in contact with each other; the upper surface of the gate dielectric layer 4 covers the insulating dielectric layer 11 below the source metal field plate, and the insulating dielectric layer 11 below the source metal field plate surrounds the N-type polysilicon 5 and the P-type polysilicon 10; the source metal field plate 12 is located on the upper surface of the insulating dielectric layer 11 below the source metal field plate; the upper surface of the insulating dielectric layer 11 below the source metal field plate covers the source metal field plate and drain metal isolation dielectric layer 13, and the source metal field plate and drain metal isolation dielectric layer 13 surround the source metal field plate 12; the drain metal 14 is located on the upper surface of the source metal field plate and drain metal isolation dielectric layer 13, extends into the semiconductor material through the contact hole and contacts the heavily doped second conductive type source region 9; the source metal 15 is located on the lower surface of the device.

[0008] As a preferred embodiment, the source metal field plate 12 , the drain metal 14 and the source metal 15 are made of aluminum, aluminum-copper alloy, or copper.

[0009] As a preferred embodiment, the gate dielectric layer 4 , the insulating dielectric layer 11 below the source metal field plate, and the source metal field plate and drain metal isolation dielectric layer 13 are made of silicon dioxide.

[0010] As a preferred embodiment, the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor.

[0011] As a preferred embodiment, the material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.

[0012] As a preferred method, the doping concentration of the heavily doped -3 , the doping concentration of lightly doped is less than 1e18 cm -3 .

[0013] A second object of the present invention is to provide a method for preparing a MOSFET device with low Miller capacitance, comprising the following steps:

[0014] (1) Preparation and epitaxial growth of single crystal silicon: a heavily doped first conductive type semiconductor substrate 1 with a crystal orientation of <100> Growing a lightly doped first conductivity type semiconductor epitaxial layer 2 with a certain thickness and doping concentration on a heavily doped first conductivity type semiconductor substrate 1;

[0015] (2) etching a trench in the lightly doped first conductivity type semiconductor epitaxial layer 2 and depositing a heavily doped first conductivity type semiconductor vertical sinker 3;

[0016] (3) Thermal oxidation growth of gate dielectric layer 4, deposition of gate N-type polysilicon 5 and etching;

[0017] (4) ion implantation and push-through formation of a first conductive type semiconductor body region 6;

[0018] (5) ion implantation and push-through formation of a second conductive type semiconductor lightly doped drain region 7;

[0019] (6) ion implantation and push-through formation of a heavily doped second conductivity type semiconductor drain contact region 8 and a heavily doped second conductivity type source region 9;

[0020] (7) depositing gate P-type polysilicon and etching to form P-type polysilicon 10;

[0021] (8) Depositing an insulating dielectric layer 11 below the source metal field plate on the device surface and etching it;

[0022] (9) Depositing the source metal field plate 12 on the device surface and etching it;

[0023] (10) Depositing a source metal field plate and a drain metal isolation dielectric layer 13 on the device surface for isolation;

[0024] (11) At the location where contact needs to be formed, that is, the surface of the heavily doped second conductive type semiconductor drain contact region 8, the surface is exposed by photolithography, the insulating dielectric layer at the corresponding position is etched, and a drain metal 14 is deposited on the device surface as a drain contact, and a source metal 15 is deposited at the bottom of the device as a source contact.

[0025] The following uses an example in which the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor to illustrate the working principle of the present invention from two aspects:

[0026] (1) Forward conduction of the device

[0027] The present invention provides a low-Miller-capacitance MOSFET device. During forward conduction, its electrodes are connected in the following manner: an N-type polysilicon electrode 5 serves as a control gate connected to the gate potential, a source metal electrode 15 connected to zero potential, and a drain metal electrode 14 connected to a high potential. When the gate potential increases to a value greater than the threshold voltage, an inversion layer channel forms on the side of the first-conductivity-type semiconductor body region 6 near the gate dielectric layer 4. Under the action of the high potential of the drain metal electrode 14, a current path is formed from the drain metal electrode 14 through the heavily-doped second-conductivity-type semiconductor drain contact region 8, the second-conductivity-type semiconductor lightly-doped drain region 7, the inversion layer, the heavily-doped second-conductivity-type source region 9, the source metal field plate 12, the heavily-doped first-conductivity-type semiconductor vertical sinker 3, the heavily-doped first-conductivity-type semiconductor substrate 1, and finally to the source metal electrode 15, generating a forward current and causing the device to conduct in the forward direction.

[0028] (2) Reverse blocking of the device

[0029] The present invention provides a low-Miller-capacitance MOSFET device. During reverse blocking, its electrodes are connected as follows: N-type polysilicon 5 is connected to zero potential, source metal 15 is connected to zero potential, and drain metal 14 is connected to a high potential. The breakdown voltage is primarily borne by the PN junction between the lightly doped drain region 7 of the second-conductivity-type semiconductor and the body region 6 of the first-conductivity-type semiconductor; the PN junction between the lightly doped drain region 7 of the second-conductivity-type semiconductor and the lightly doped epitaxial layer 2 of the first-conductivity-type semiconductor; and the junction formed by the heavily doped drain contact region 8 of the second-conductivity-type semiconductor, the lightly doped drain region 7 of the second-conductivity-type semiconductor, and the lightly doped epitaxial layer 2 of the first-conductivity-type semiconductor.

[0030] The beneficial effects of the present invention are:

[0031] Compared with traditional power MOSFET devices with heavily doped vertical sinkers, the present invention provides a low Miller capacitance MOSFET device, in which the gate is composed of N-type polysilicon 5 and P-type polysilicon 10 connected on the left and right, forming a polysilicon PN junction inside. When the voltage applied to the N-type polysilicon 5 is positive, the polysilicon PN junction is in a reverse biased state, and the PN junction depletion region will deplete the P-type polysilicon 10 downward, thereby introducing a polysilicon PN junction depletion region capacitor. This capacitor is connected in series with the original Miller capacitance, reducing the overall Miller capacitance of the device and accelerating the switching speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention provides a MOSFET device with low Miller capacitance;

[0033] Figure 2-Figure 12 This is a key process step in the manufacturing process of a low Miller capacitance MOSFET device provided by the present invention;

[0034] 1 is a heavily doped first conductivity type semiconductor substrate, 2 is a lightly doped first conductivity type semiconductor epitaxial layer, 3 is a heavily doped first conductivity type semiconductor vertical sinker, 4 is a gate dielectric layer, 5 is N-type polysilicon, 6 is a first conductivity type semiconductor body region, 7 is a second conductivity type semiconductor lightly doped drain region, 8 is a heavily doped second conductivity type semiconductor drain contact region, 9 is a heavily doped second conductivity type source region, 10 is P-type polysilicon, 11 is an insulating dielectric layer under the source metal field plate, 12 is the source metal field plate, 13 is a dielectric layer isolating the source metal field plate and the drain metal, 14 is the drain metal, and 15 is the source metal. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Example 1

[0037] A MOSFET device with low Miller capacitance, such as Figure 1As shown, it includes a heavily doped first conductivity type semiconductor substrate 1, a lightly doped first conductivity type semiconductor epitaxial layer 2, a heavily doped first conductivity type semiconductor vertical sinker 3, a gate dielectric layer 4, N-type polysilicon 5, a first conductivity type semiconductor body region 6, a second conductivity type semiconductor lightly doped drain region 7, a heavily doped second conductivity type semiconductor drain contact region 8, a heavily doped second conductivity type source region 9, P-type polysilicon 10, an insulating dielectric layer 11 under the source metal field plate, a source metal field plate 12, a source metal field plate and drain metal isolation dielectric layer 13, a drain metal 14, and a source metal 15;

[0038] Among them, the lightly doped first conductive type semiconductor epitaxial layer 2 is located on the upper surface of the heavily doped first conductive type semiconductor substrate 1; the heavily doped first conductive type semiconductor vertical sinker 3 is located on the left side of the lightly doped first conductive type semiconductor epitaxial layer 2, and is connected to the heavily doped first conductive type semiconductor substrate 1 and the source metal field plate 12; the first conductive type semiconductor body region 6 is located in the upper left part of the lightly doped first conductive type semiconductor epitaxial layer 2, and is in contact with the heavily doped first conductive type semiconductor vertical sinker 3 and the source metal field plate 12 on the left side, and is in contact with the second conductive type semiconductor lightly doped drain region 7 on the right side; the second conductive type semiconductor lightly doped drain region 7 is located in the upper right part of the lightly doped first conductive type semiconductor epitaxial layer 2, and has a heavily doped second conductive type semiconductor drain contact region 8 on the upper right inside the second conductive type semiconductor lightly doped drain region 7; the heavily doped second conductive type source region 9 is located on the upper left side of the first conductive type semiconductor body region 6, and is heavily doped The left side of the second conductive type source region 9 is in contact with the source metal field plate 12; the N-type polysilicon 5 is isolated from the first conductive type semiconductor body region 6 by the gate dielectric layer 4; the P-type polysilicon 10 is located on the right side of the N-type polysilicon 5 and the two are in contact with each other; the upper surface of the gate dielectric layer 4 covers the insulating dielectric layer 11 below the source metal field plate, and the insulating dielectric layer 11 below the source metal field plate surrounds the N-type polysilicon 5 and the P-type polysilicon 10; the source metal field plate 12 is located on the upper surface of the insulating dielectric layer 11 below the source metal field plate; the upper surface of the insulating dielectric layer 11 below the source metal field plate covers the source metal field plate and drain metal isolation dielectric layer 13, and the source metal field plate and drain metal isolation dielectric layer 13 surround the source metal field plate 12; the drain metal 14 is located on the upper surface of the source metal field plate and drain metal isolation dielectric layer 13, extends into the semiconductor material through the contact hole and contacts the heavily doped second conductive type source region 9; the source metal 15 is located on the lower surface of the device.

[0039] This embodiment also provides a method for preparing a MOSFET device with low Miller capacitance, comprising the following steps:

[0040] (1) Preparation and epitaxial growth of single crystal silicon: a heavily doped first conductive type semiconductor substrate 1 with a crystal orientation of <100> A lightly doped first conductivity type semiconductor epitaxial layer 2 with a certain thickness and doping concentration is grown on a heavily doped first conductivity type semiconductor substrate 1, such as Figure 2 As shown;

[0041] (2) Etching a trench in the lightly doped first conductivity type semiconductor epitaxial layer 2 and depositing a heavily doped first conductivity type semiconductor vertical sinker 3, such as Figure 3 As shown;

[0042] (3) Thermal oxidation growth of gate dielectric layer 4, deposition of gate N-type polysilicon 5 and etching, such as Figure 4 As shown;

[0043] (4) Ion implantation and junction formation to form a first conductive type semiconductor body region 6, such as Figure 5 As shown;

[0044] (5) Ion implantation and push-through formation of a second conductive type semiconductor lightly doped drain region 7, such as Figure 6 As shown;

[0045] (6) Ion implantation and push-through formation of heavily doped second conductivity type semiconductor drain contact region 8 and heavily doped second conductivity type source region 9, such as Figure 7 As shown;

[0046] (7) Deposit gate P-type polysilicon and etch to form P-type polysilicon 10, such as Figure 8 As shown;

[0047] (8) Deposit the insulating dielectric layer 11 below the source metal field plate on the device surface and etch it, as shown in the following example: Figure 9 As shown;

[0048] (9) Deposit the source metal field plate 12 on the device surface and etch it, as shown in the following example: Figure 10 As shown;

[0049] (10) Deposit source metal field plate and drain metal isolation dielectric layer 13 on the device surface for isolation, such as Figure 11 As shown;

[0050] (11) At the location where contact is required, i.e., the surface of the heavily doped second conductivity type semiconductor drain contact region 8, the surface is exposed by photolithography, the insulating dielectric layer at the corresponding location is etched, and a drain metal 14 is deposited on the device surface as a drain contact, and a source metal 15 is deposited at the bottom of the device as a source contact, as shown in FIG. Figure 12 shown.

[0051] The working principle of this embodiment is as follows:

[0052] The present invention provides a low Miller capacitance MOSFET device, taking as an example a case where the first conductive type semiconductor is a P-type semiconductor and the second conductive type semiconductor is an N-type semiconductor. During reverse blocking, the electrodes are connected as follows: the N-type polysilicon 5 is connected to zero potential, the source metal 15 is connected to zero potential, and the drain metal 14 is connected to a high potential. The breakdown voltage is primarily borne by the PN junction between the lightly doped drain region 7 of the second conductive type semiconductor and the body region 6 of the first conductive type semiconductor, the PN junction between the lightly doped drain region 7 of the second conductive type semiconductor and the lightly doped epitaxial layer 2 of the first conductive type semiconductor, and the junction formed by the heavily doped drain contact region 8 of the second conductive type semiconductor, the lightly doped drain region 7 of the second conductive type semiconductor, and the lightly doped epitaxial layer 2 of the first conductive type semiconductor. During forward conduction, the electrodes are connected as follows: the N-type polysilicon 5 acts as a control gate and is connected to the gate potential, the source metal 15 is connected to zero potential, and the drain metal 14 is connected to a high potential. When the gate potential increases to be greater than the threshold voltage, an inversion layer channel is formed on the side of the first conductive type semiconductor body region 6 close to the gate dielectric layer 4. Under the action of the high potential of the drain metal 14, a current path is formed from the drain metal 14 through the heavily doped second conductive type semiconductor drain contact region 8, the second conductive type semiconductor lightly doped drain region 7, the inversion layer, the heavily doped second conductive type source region 9, the source metal field plate 12, the heavily doped first conductive type semiconductor vertical sinker 3, the heavily doped first conductive type semiconductor substrate 1, to the source metal 15, generating a forward current and the device is forward-conducting.

[0053] Preferably, the materials of the source metal field plate 12 , the drain metal 14 and the source metal 15 are generally required to have low resistivity and high stability, such as aluminum, aluminum-copper alloy, and copper.

[0054] Preferably, the gate dielectric layer 4 , the insulating dielectric layer 11 below the source metal field plate, and the dielectric layer 13 isolating the source metal field plate from the drain metal can be made of silicon dioxide or other insulating dielectrics.

[0055] Preferably, the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor.

[0056] Preferably, the material of the entire device is bulk silicon, or silicon carbide, or gallium arsenide or silicon germanium.

[0057] Preferably, as a preferred embodiment, in the preparation method, the doping concentration of the heavily doped material is greater than 1e18 cm -3 , the doping concentration of lightly doped is less than 1e18 cm -3 .

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A MOSFET device with low Miller capacitance, characterized in that: The invention comprises a heavily doped first conductive type semiconductor substrate (1), a lightly doped first conductive type semiconductor epitaxial layer (2), a heavily doped first conductive type semiconductor vertical sinker (3), a gate dielectric layer (4), an N-type polysilicon (5), a first conductive type semiconductor body region (6), a second conductive type semiconductor lightly doped drain region (7), a heavily doped second conductive type semiconductor drain contact region (8), a heavily doped second conductive type source region (9), a P-type polysilicon (10), an insulating dielectric layer (11) below a source metal field plate, a source metal field plate (12), a source metal field plate and drain metal isolation dielectric layer (13), a drain metal (14), and a source metal (15); The lightly doped first conductive type semiconductor epitaxial layer (2) is located on the upper surface of the heavily doped first conductive type semiconductor substrate (1); the heavily doped first conductive type semiconductor vertical sinker (3) is located on the left side of the lightly doped first conductive type semiconductor epitaxial layer (2) and is connected to the heavily doped first conductive type semiconductor substrate (1) and the source metal field plate (12); the first conductive type semiconductor body region (6) is located on the upper left of the lightly doped first conductive type semiconductor epitaxial layer (2), and is in contact with the heavily doped first conductive type semiconductor vertical sinker (3) and the source metal field plate (12) on the left side, and is in contact with the second conductive type semiconductor lightly doped drain region (7) on the right side; the second conductive type semiconductor lightly doped drain region (7) is located on the upper right side of the lightly doped first conductive type semiconductor epitaxial layer (2), and a heavily doped second conductive type semiconductor drain contact region (8) is provided in the upper right side of the second conductive type semiconductor lightly doped drain region (7); the heavily doped second conductive type source region (9) is located on the upper left side of the first conductive type semiconductor body region (6), and is in contact with the heavily doped second conductive type semiconductor The left side of the source region (9) is in contact with the source metal field plate (12); the N-type polysilicon (5) and the first conductive type semiconductor body region (6) are isolated by the gate dielectric layer (4); the P-type polysilicon (10) is located on the right side of the N-type polysilicon (5) and the two are in contact with each other; the upper surface of the gate dielectric layer (4) covers the insulating dielectric layer (11) below the source metal field plate, and the insulating dielectric layer (11) below the source metal field plate surrounds the N-type polysilicon (5) and the P-type polysilicon (10); the source metal field plate (12) is located on the source metal field plate. The upper surface of the insulating dielectric layer (11) below the plate; the upper surface of the insulating dielectric layer (11) below the source metal field plate is covered with a source metal field plate and a drain metal isolation dielectric layer (13), and the source metal field plate and the drain metal isolation dielectric layer (13) surround the source metal field plate (12); the drain metal (14) is located on the upper surface of the source metal field plate and the drain metal isolation dielectric layer (13), extends into the semiconductor material through the contact hole and contacts the heavily doped second conductivity type source region (9); the source metal (15) is located on the lower surface of the device.

2. The low Miller capacitance MOSFET device according to claim 1, wherein: The materials of the source metal field plate (12), the drain metal (14) and the source metal (15) are selected from aluminum, aluminum-copper alloy, or copper.

3. The low Miller capacitance MOSFET device according to claim 1, wherein: The materials of the gate dielectric layer (4), the insulating dielectric layer (11) below the source metal field plate, and the source metal field plate and drain metal isolation dielectric layer (13) are silicon dioxide.

4. The low Miller capacitance MOSFET device according to claim 1, wherein: The first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor.

5. The low Miller capacitance MOSFET device according to claim 1, wherein: The material of the entire device is bulk silicon, silicon carbide, gallium arsenide or silicon germanium.

6. The low Miller capacitance MOSFET device according to claim 1, wherein: Heavily doped with a doping concentration greater than 1e18 cm -3 , the doping concentration of lightly doped is less than 1e18 cm -3 .

7. The method for preparing a low Miller capacitance MOSFET device according to any one of claims 1 to 6, characterized in that: The steps include: (1) Preparation and epitaxial growth of single crystal silicon, using a heavily doped first conductive type semiconductor substrate (1) with a crystal orientation of <100> Growing a lightly doped first conductive type semiconductor epitaxial layer (2) of a certain thickness and doping concentration on a heavily doped first conductive type semiconductor substrate (1); (2) etching a groove in the lightly doped first conductive type semiconductor epitaxial layer (2) and depositing a heavily doped first conductive type semiconductor vertical sinker (3); (3) thermally oxidizing and growing a gate dielectric layer (4), depositing gate N-type polysilicon (5) and etching; (4) ion implantation and push-through formation of a first conductive type semiconductor body region (6); (5) ion implantation and push-through formation of a second conductive type semiconductor lightly doped drain region (7); (6) ion implantation and push-through formation of a heavily doped second conductivity type semiconductor drain contact region (8) and a heavily doped second conductivity type source region (9); (7) depositing gate P-type polysilicon and etching to form P-type polysilicon (10); (8) depositing an insulating dielectric layer (11) below the source metal field plate on the device surface and etching it; (9) depositing a source metal field plate (12) on the device surface and etching it; (10) depositing a source metal field plate and a drain metal isolation dielectric layer (13) on the device surface for isolation; (11) At a location where contact is required, i.e., the surface of the heavily doped second conductive type semiconductor drain contact region (8), the surface is exposed by photolithography, the insulating dielectric layer at the corresponding location is etched, a drain metal (14) is deposited on the device surface as a drain contact, and a source metal (15) is deposited on the bottom of the device as a source contact.

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