A laser-induced local polycrystalline silicon passivated cell and a preparation method thereof

Abstract

The application provides a laser-induced local polycrystalline silicon passivation cell and a preparation method thereof, and the structure comprises a silicon wafer substrate, a silicon nitride layer on the front and back surfaces, and a metal electrode on the front and back surfaces; the front surface of the silicon wafer substrate is sequentially provided with a boron-doped emitter and an aluminum oxide layer from inside to outside; the back surface of the silicon wafer substrate is sequentially provided with a tunneling oxide layer and an n+poly layer from inside to outside, and the surface of the n+poly layer is formed with a spaced array of LIO etching grooves. Compared with a traditional TOPCon cell structure, the application utilizes laser-induced oxidation to oxidize local poly-Si into SiO / SiO2, and then utilizes low-temperature lye to corrode and remove part of poly in a non-laser area, so that the poly coverage area and thickness are reduced, the parasitic light absorption is reduced, the short-circuit current Isc of the cell is improved, and the cell efficiency, back surface efficiency and bifaciality are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solar cells, in particular to a laser-induced local polycrystalline silicon passivation cell and a preparation method thereof. BACKGROUND

[0002] A solar cell is a microelectronic device that directly converts light energy into electrical energy. After years of development, there are various structures, including PERC (Passivated Emitter and Rear Cell), TOPCon (Tunnel Oxide Passivated Contact Solar Cell), HJT (Heterojunction with Intrinsic Thin Layer), etc. At present, considering the battery efficiency and manufacturing cost, TOPCon cell is undoubtedly the mainstream.

[0003] At present, the downstream of the solar cell industry chain, such as components and power stations, has an increasing demand for double-sided cells and components. The efficiency of the cell back and the double-sided rate (η = back efficiency / front efficiency x 100%) are gradually increasing, but due to the use of n+poly layer back surface for passivation on the back of the TOPCon cell, the poly parasitic light absorption of light reduces the back efficiency. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a double-sided passivation cell prepared based on a physical deposition technology and a preparation method thereof.

[0005] The natural oxidation thickness of silicon is about 1 nm of ultra-thin oxide layer, and further oxide growth requires oxygen to diffuse to the oxide layer and "hot electrons" to be ejected from silicon. At a distance of 1-2 nm from the Si / SiO interface, the diffusion of O2 is blocked due to the lattice mismatch between Si / SiO. Under laser irradiation, hot electrons are generated in silicon, which can penetrate the barrier layer and dissociate oxygen molecules into O atoms. Therefore, some O2 molecules are dissociated into O atoms, and atomic oxygen has much smaller volume and can easily diffuse through the barrier layer to reach the Si / SiO interface, thereby further growing the oxide layer (laser-induced oxidation of silicon, LIO).

[0006] To achieve the above object, according to one aspect of the present application, the present application provides a laser-induced local polycrystalline silicon passivation cell, comprising a silicon wafer substrate, a silicon nitride layer on the front / back surface, and a metal electrode on the front / back surface, wherein the front surface of the silicon wafer substrate is sequentially provided with a boron-doped emitter and an aluminum oxide layer from inside to outside; the back surface of the silicon wafer substrate is sequentially provided with a tunneling oxide layer and an n+poly layer from inside to outside, and the surface of the n+poly layer is formed with an array of spaced LIO etching grooves.

[0007] In the present application, the thickness of the silicon wafer substrate is 130 μm, the thickness of the aluminum oxide layer is 10-11 nm, the thickness of the tunneling oxide layer is 1 nm, the thickness of the n+poly layer is 100 nm, and the depth of the LIO etching groove is 40-50 nm.

[0008] According to another aspect of the present application, the present application provides a preparation method of a laser-induced local polycrystalline silicon passivation cell, comprising the following steps performed sequentially:

[0009] (1) selecting a silicon wafer and performing texturing treatment;

[0010] (2) performing boron diffusion on the silicon wafer to form a boron-doped emitter on the front surface of the silicon wafer;

[0011] (3) performing single-side acid pickling on the silicon wafer to remove borosilicate glass on the back surface and side surface thereof;

[0012] (4) performing alkali polishing on the back surface of the silicon wafer;

[0013] (5) preparing a local TOPCon structure on the back surface of the silicon wafer by using PVD technology, i.e. preparing a tunneling oxide layer in a PO cavity, then preparing intrinsic amorphous silicon i-a-Si in a Paid cavity by using Ar+ to bombard a silicon target, and introducing PH3 gas to dope phosphorus elements and prepare n-type doped amorphous silicon n-a-Si;

[0014] (6) performing high-temperature annealing on the silicon wafer in an annealing furnace to change the n-type doped amorphous silicon n-a-Si into n-type doped polycrystalline silicon n+poly;

[0015] (7) performing laser-induced oxidation on the gate line area of the back surface of the silicon wafer by using an ultraviolet picosecond laser to change the polycrystalline silicon in the preset gate line area into SiO / SiO2 as a subsequent mask;

[0016] (8) performing wet cleaning on the silicon wafer, i.e. performing cleaning in a tank cleaning device, first using hydrogen peroxide and a weak alkali solution to clean organic impurities on the surface of the silicon wafer, then using a low-temperature alkali solution to etch the polycrystalline silicon layer in the non-laser-oxidized area on the back surface of the silicon wafer, after alkali etching, using hydrogen peroxide and a weak alkali solution to clean the silicon wafer to remove the influence of organic additives, and finally using HF / HCl solution to clean the silicon wafer to remove the oxides on the front and back surfaces;

[0017] (9) Deposit an aluminum oxide layer on the front side of a silicon wafer using ALD technology;

[0018] (10) Silicon nitride antireflection films were prepared on both the front and back sides of a silicon wafer using PECVD technology;

[0019] (11) Metal paste is applied to both the front and back sides of the silicon wafer using screen printing, and then metal electrodes are prepared after sintering.

[0020] Further, in step (1): the silicon wafer is texturized to remove the surface cutting damage layer and form a textured textured surface structure on its surface to reduce light loss; the silicon wafer is an n-type silicon wafer with a thickness of 130um and a sheet resistance of 1Ω / □.

[0021] Further, in step (3): silicon oxide on the back and sides of the silicon wafer is removed using a chain-type single-sided HF device, wherein the volume ratio of HF to deionized water is 1:10.

[0022] Further, in step (4): after the silicon wafer is alkaline polished, in the subsequent cleaning, the original solution ratio is deionized water:NaOH:H2O2 = 90:1:4, and finally the silicon wafer surface is cleaned with HCl+HF solution, in which deionized water:HCl:HF = 90:4:1, and the cleaning time is 80-100s.

[0023] Furthermore, in step (8), the etching is carried out in a low-temperature environment, with an etching temperature of 30 to 40°C.

[0024] Compared with the prior art, the technical effects of the present invention are as follows: Compared with the traditional TOPCon battery structure, the present invention uses laser-induced oxidation to oxidize local poly-Si into SiO / SiO2, and then uses low-temperature alkaline solution to remove part of the poly in the non-laser area by corrosion. Under the premise of satisfying poly passivation, the poly coverage area and thickness are reduced, parasitic light absorption is reduced, and the battery short-circuit current Isc is increased, thereby improving battery efficiency, back-side efficiency, and bifaciality. Attached Figure Description

[0025] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0026] Figure 1 This is a schematic diagram of the structure of the laser-induced localized polycrystalline silicon passivated cell of the present invention;

[0027] Figure 2 This is a comparison chart of the battery efficiency of the laser-induced localized polycrystalline silicon passivated cell and the conventional TOPCon cell in Example 1;

[0028] 10-Silicon substrate, 11-Boron-doped emitter, 12-Alumina layer, 21-Tunneling oxide layer, 22-n+poly layer, 13(23)-Silicon nitride layer, 14(25)-Metal electrode, 24-LIO etched groove. Detailed Implementation

[0029] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments, further clarifies the invention. Those skilled in the art should understand that the specific descriptions below are illustrative rather than restrictive, and should not be construed as limiting the scope of protection of the present invention.

[0030] The laser-induced localized polycrystalline silicon passivated solar cell of the present invention has the following structure: Figure 1 As shown, the silicon wafer substrate 10 includes a silicon nitride layer 13 (23) on the front and back sides, and a metal electrode 14 (25) on the front and back sides. A boron-doped emitter 11 and an aluminum oxide layer 12 are sequentially disposed on the front side of the silicon wafer substrate 10 from the inside to the outside. A tunneling oxide layer 21 and an n+poly layer 22 are sequentially disposed on the back side of the silicon wafer substrate 10 from the inside to the outside. An LIO etching groove 24 with an array of spacing is formed on the surface of the n+poly layer 22.

[0031] The thickness of the silicon substrate is 130 μm, the thickness of the aluminum oxide layer is 10–11 nm, the thickness of the tunneling oxide layer is 1 nm, the thickness of the n+poly layer is 100 nm, and the depth of the LIO etching groove is 40–50 nm.

[0032] The above-mentioned method for fabricating laser-induced localized polycrystalline silicon passivated solar cells includes the following steps performed sequentially:

[0033] (1) Select silicon wafers and texturing process;

[0034] (2) Boron diffusion is performed on the silicon wafer to form a boron-doped emitter on the front side of the silicon wafer;

[0035] (3) The silicon wafer is acid-washed on one side to remove the borosilicate glass on the back and sides;

[0036] (4) Perform alkaline polishing on the back side of the silicon wafer;

[0037] (5) A local TOPCon structure is prepared on the back side of a silicon wafer using PVD technology. That is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. PH3 gas is introduced to dope phosphorus to prepare n-type doped amorphous silicon na-Si.

[0038] (6) The silicon wafer is annealed at high temperature in an annealing furnace to transform n-type doped amorphous silicon na-Si into n-type doped polycrystalline silicon n+poly.

[0039] (7) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the back of the silicon wafer, so that the polycrystalline silicon in the preset gate area becomes SiO / SiO2, which is used as a subsequent mask.

[0040] (8) The silicon wafer is wet cleaned in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface of the silicon wafer. Then, a low-temperature alkaline solution is used to etch the polysilicon layer in the non-laser oxidation area on the back of the silicon wafer. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives. Finally, HF / HCl solution is used to clean the silicon wafer to remove the oxides on the front and back sides.

[0041] (9) Deposit an aluminum oxide layer on the front side of a silicon wafer using ALD technology;

[0042] (10) Silicon nitride antireflection films were prepared on both the front and back sides of a silicon wafer using PECVD technology;

[0043] (11) Metal paste is applied to both the front and back sides of the silicon wafer using screen printing, and then metal electrodes are prepared after sintering.

[0044] Example 1:

[0045] Step (1): Select an n-type silicon wafer with a thickness of 130μm and a sheet resistance of 1Ω / □ as the silicon wafer substrate, and perform texturing treatment on it to remove the surface cutting damage layer and form a textured textured surface structure on the surface.

[0046] Step (2): After cleaning the silicon wafer, the silicon wafer is placed in a boron diffusion tube for boron diffusion treatment. After diffusion, the sheet resistance of the silicon wafer is approximately 120Ω / □.

[0047] Step (3): Use a chain-type single-sided HF device to perform single-sided acid washing on the n-type silicon wafer obtained in step (2) to remove the borosilicate glass on its back and sides.

[0048] Step (4): After removing the borosilicate glass on the back and sides, place the silicon wafer in an alkaline polishing tank. After alkaline polishing, clean the wafer. The original solution ratio is deionized water:NaOH:H2O2 = 90:1:4. Finally, clean the silicon wafer surface with HCl+HF solution. The solution ratio is deionized water:HCl:HF = 90:4:1. The cleaning time is about 80-100 seconds. This removes the oxide layer on the back and retains a portion of the oxide layer on the front, so that the back of the silicon wafer can be on a flat surface in subsequent preparations.

[0049] Step (5): TOPCon structure is prepared on the back surface of silicon wafer using PVD technology, a front tunneling oxide layer is prepared in PO cavity, and then the silicon target is bombarded with Ar+ in Paid cavity to prepare an intrinsic amorphous silicon of a certain thickness on the back of silicon wafer. PH3 gas is introduced to dope phosphorus element and prepare doped amorphous silicon.

[0050] Step (6): Perform high-temperature annealing at 850°C for 2000 seconds to activate the doped atoms.

[0051] Step (7): Use an ultraviolet picosecond laser to perform laser-induced oxidation (LIO) on the gate area on the back of the silicon wafer, so that the poly-Si of the preset gate area on the back is transformed into SiO / SiO2, which is used as a subsequent mask.

[0052] Step (8): Wet cleaning of the silicon wafer is performed in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface. Then, a low-temperature alkaline solution is used to etch the non-laser area poly-Si on the back. Since the LIO in the laser area has turned into silicon oxide, it cannot be completely etched by the alkaline solution, and the n+ poly underneath is protected. The etching solution ratio is the same as that of the polishing solution. Since the alkaline solution will still corrode SiO in hot water, the etching is performed at a low temperature, about 30-40°C, to reduce the impact on the LIO area. The etching solution ratio is deionized water ~ NaOH:H2O2 = 90:1:4. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives. Finally, HF / HCl solution is used to clean the silicon wafer to remove the oxides on the front and back sides.

[0053] Step (9): Prepare an aluminum oxide passivation layer on the positive surface using an atomic layer deposition (ALD) device.

[0054] Step (10): Silicon nitride (SiNx) antireflection films are prepared on the front and back sides of the battery using plasma-enhanced chemical deposition (PECVD) to reduce light reflection.

[0055] Step (11): Apply metal paste to the front / back of the battery using screen printing equipment, process it at high temperature in a sintering furnace to prepare metal grid lines, so that the metal material combines with silicon to form an alloy, and export photogenerated carriers to complete the battery preparation.

[0056] like Figure 2 The diagram shows a comparison of the efficiency of a conventional TOPCon (baseline, BL) battery and the LIO-TOPCon battery prepared according to this invention. It can be seen that, compared to a conventional TOPCon battery, the process of this invention can improve battery efficiency by approximately 0.15%.

[0057] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.

Claims

1. A laser-induced localized polycrystalline silicon passivated solar cell, comprising a silicon wafer substrate, front / back silicon nitride layers, and front / back metal electrodes, characterized in that, The front side of the silicon substrate is provided with a boron-doped emitter and an aluminum oxide layer from the inside to the outside; the back side of the silicon substrate is provided with a tunneling oxide layer and an n+poly layer from the inside to the outside, and an array of LIO etching grooves are formed on the surface of the n+poly layer. The method for fabricating the laser-induced localized polycrystalline silicon passivated solar cell includes the following steps performed sequentially: (1) Selection of silicon wafers and texturing process; (2) Boron diffusion is performed on the silicon wafer to form a boron-doped emitter on the front side of the silicon wafer; (3) The silicon wafer is acid-washed on one side to remove the borosilicate glass on the back and sides; (4) Perform alkaline polishing on the back side of the silicon wafer; (5) A local TOPCon structure is prepared on the back side of a silicon wafer using PVD technology. That is, a tunneling oxide layer is prepared in the PO cavity, and then the silicon target is bombarded with Ar+ in the Paid cavity to prepare intrinsic amorphous silicon ia-Si. PH3 gas is introduced to dope phosphorus to prepare n-type doped amorphous silicon na-Si. (6) The silicon wafer is annealed at high temperature in an annealing furnace to transform n-type doped amorphous silicon na-Si into n-type doped polycrystalline silicon n+poly; (7) Use an ultraviolet picosecond laser to perform laser-induced oxidation on the gate area on the back of the silicon wafer, so that the polycrystalline silicon in the preset gate area becomes SiO / SiO2, which is used as a subsequent mask; (8) The silicon wafer is wet cleaned in a tank cleaning equipment. First, hydrogen peroxide and a weak alkaline solution are used to clean the organic impurities on the surface of the silicon wafer. Then, a low-temperature alkaline solution is used to etch the polysilicon layer in the non-laser oxidation area on the back of the silicon wafer. The etching is carried out in a low-temperature environment with an etching temperature of 30-40°C. After alkaline etching, hydrogen peroxide and a weak alkaline solution are used to clean the silicon wafer to remove the influence of organic additives. Finally, HF / HCl solution is used to clean the silicon wafer to remove the oxides on the front and back sides. In this process, after alkaline etching, the silicon oxide layer in the laser-oxidized area is retained, while the polysilicon layer in the non-laser-oxidized area is removed, thereby forming an array of spaced grooves. (9) Deposit an aluminum oxide layer on the front side of a silicon wafer using ALD technology; (10) Silicon nitride antireflection films were prepared on both the front and back sides of a silicon wafer using PECVD technology; (11) Metal paste is applied to both the front and back sides of the silicon wafer using screen printing, and then metal electrodes are prepared after sintering.

2. The laser-induced localized polycrystalline silicon passivated solar cell according to claim 1, characterized in that, The silicon substrate has a thickness of 130 μm, the aluminum oxide layer has a thickness of 10–11 nm, the tunneling oxide layer has a thickness of 1 nm, the n+poly layer has a thickness of 100 nm, and the LIO etch groove has a depth of 40–50 nm.

3. The laser-induced localized polycrystalline silicon passivated solar cell according to claim 1, characterized in that, In step (1): the silicon wafer is texturized to remove the surface cutting damage layer and form a textured textured surface structure on its surface to reduce light loss; the silicon wafer is an n-type silicon wafer with a thickness of 130um and a sheet resistance of 1Ω / □.

4. The laser-induced localized polycrystalline silicon passivated solar cell according to claim 1, characterized in that, In step (3): the silicon oxide on the back and sides of the silicon wafer is removed using a chain-type single-sided HF device, wherein the volume ratio of HF to deionized water is 1:

10.

5. The laser-induced localized polycrystalline silicon passivated solar cell according to claim 1, characterized in that, In step (4): after the silicon wafer is alkaline polished, in the subsequent cleaning, the original solution ratio is deionized water:NaOH:H2O2=90:1:

4. Finally, the silicon wafer surface is cleaned with HCl+HF solution, in which the ratio of deionized water:HCl:HF is 90:4:1, and the cleaning time is 80-100s.

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