A reference current source circuit

Abstract

The present invention discloses a reference current source circuit, including a startup circuit module, a bandgap reference circuit module and a voltage-to-current circuit module; the startup circuit module is connected to the bandgap reference circuit module, the bandgap reference circuit module is connected to the voltage-to-current circuit module, the bandgap reference circuit module is used to generate a temperature-independent voltage, and the voltage-to-current circuit module is used to generate a reference current according to a temperature-independent voltage; wherein the bandgap reference circuit module includes a plurality of NMOS tubes working in a subthreshold region, the gate-source voltage difference of the NMOS tube working in the subthreshold region presents a negative temperature characteristic, and the difference between the gate-source voltage differences of two NMOS tubes working in the subthreshold region presents a positive temperature characteristic. The present invention utilizes the NMOS tube in the subthreshold region to obtain a reference current, thereby avoiding the use of a BJT device, and solving the problem that the existing reference current source circuit needs to use a BJT device, resulting in a large occupied layout area.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a reference current source circuit. Background Art

[0002] like Figure 1 As shown, Figure 1 For the traditional reference current source circuit, Figure 1 In the reference current source circuit shown, MOS tube m1, MOS tube m2, MOS tube m3, MOS tube m4, transistor Q1, transistor Q2, and resistor R1 are used to generate a positive temperature coefficient current; MOS tube m5, MOS tube m6, MOS tube m7, MOS tube m8, transistor Q3, and resistor R2 are used to generate a negative temperature coefficient current; MOS tube m10 and MOS tube m9 are used to copy the positive temperature coefficient current and the negative temperature coefficient current, respectively; finally, they are superimposed at the output node to obtain a reference current that is independent of temperature.

[0003] exist Figure 1 The circuit needs to use three BJTs (BJT devices) and two resistors, which undoubtedly occupies a large layout area. In addition, considering the matching requirements between transistor Q1 and transistor Q2, dummy BJTs will be added, which undoubtedly further occupies a large layout area.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a reference current source circuit to at least solve the problem that the existing reference current source circuit needs to use a BJT device, resulting in a large occupied layout area.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] The embodiment of the present invention provides a reference current source circuit, including a startup circuit module, a bandgap reference circuit module and a voltage-to-current circuit module;

[0008] The startup circuit module is connected to the bandgap reference circuit module, the bandgap reference circuit module is connected to the voltage-to-current circuit module, the bandgap reference circuit module is used to generate a temperature-independent voltage, and the voltage-to-current circuit module is used to generate a reference current according to the temperature-independent voltage;

[0009] Among them, the bandgap reference circuit module includes multiple NMOS tubes working in the subthreshold region, the gate-source voltage difference of the NMOS tubes working in the subthreshold region presents a negative temperature characteristic, and the difference between the gate-source voltage differences of two NMOS tubes working in the subthreshold region presents a positive temperature characteristic.

[0010] Further, the startup circuit module includes a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a PMOS tube M5;

[0011] The gate and drain of the PMOS tube M1 are connected to the gate of the NMOS tube M2, the gate of the NMOS tube M2 is also connected to the drain of the NMOS tube M3, the source of the NMOS tube M2 is grounded, and the drain of the NMOS tube M2 is connected to the bandgap reference circuit module;

[0012] The gate of the NMOS tube M3 is connected to the gate of the NMOS tube M4 and the drain of the NMOS tube M4, and the source of the NMOS tube M3 is connected to the source of the NMOS tube M4 and then grounded;

[0013] The drain of the NMOS tube M4 is connected to the drain of the PMOS tube M5, the source of the PMOS tube M5 is connected to the source of the PMOS tube M1 and then connected to the current input end, and the gate of the PMOS tube M5 is connected to the bandgap reference circuit module.

[0014] Further, the bandgap reference circuit module includes a PMOS tube M6, a PMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M16, an NMOS tube M17, an NMOS tube M18, a PMOS tube M19, an NMOS tube M20, an NMOS tube M21, a PMOS tube M22 and an NMOS tube M23;

[0015] The gate of the PMOS tube M6, the gate of the PMOS tube M7, the gate of the PMOS tube M13, the gate of the PMOS tube M16, the gate of the PMOS tube M19 and the gate of the PMOS tube M22 are connected to each other;

[0016] The source of the PMOS tube M6, the source of the PMOS tube M7, the source of the PMOS tube M13, the source of the PMOS tube M16, the source of the PMOS tube M19 and the source of the PMOS tube M22 are connected to each other and then connected to the current input end;

[0017] The gate of the PMOS tube M6 is also connected to the gate of the PMOS tube M5 and the drain of the PMOS tube M7 respectively, the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M8 respectively, and the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M2;

[0018] The drain of the NMOS tube M8 is connected to the gate of the NMOS tube M8 and then connected to the gate of the NMOS tube M9. The source of the NMOS tube M8 is connected to the drain of the NMOS tube M10. The drain of the NMOS tube M9 is connected to the drain of the PMOS tube M7. The source of the NMOS tube M9 is connected to the drain of the NMOS tube M11.

[0019] The drain of the NMOS tube M10 is connected to the gate of the NMOS tube M10 and then connected to the gate of the NMOS tube M11. The source of the NMOS tube M10 is grounded. The source of the NMOS tube M11 is connected to the drain of the NMOS tube M12. The source of the NMOS tube M12 is grounded. The gate of the NMOS tube M12 is connected to the voltage-to-current circuit module.

[0020] The drain of the PMOS tube M13 is connected to the drain of the NMOS tube M14, the gate of the NMOS tube M14 is connected to the drain of the NMOS tube M14 and the gate of the NMOS tube M15 respectively, the source of the NMOS tube M14 is connected to the drain of the NMOS tube M15 and then to the source of the NMOS tube M18, and the source of the NMOS tube M15 is grounded;

[0021] The drain of the PMOS tube M16 is connected to the drain of the NMOS tube M17, the gate of the NMOS tube M17 is connected to the drain of the NMOS tube M17 and the gate of the NMOS tube M18 respectively, the source of the NMOS tube M17 is connected to the drain of the NMOS tube M18 and then connected to the source of the NMOS tube M21;

[0022] The drain of the PMOS tube M19 is connected to the drain of the NMOS tube M20, the gate of the NMOS tube M20 is connected to the drain of the NMOS tube M20 and the gate of the NMOS tube M21 respectively, the source of the NMOS tube M20 is connected to the drain of the NMOS tube M21 and then connected to the source of the NMOS tube M23;

[0023] The drain of the PMOS tube M22 is connected to the drain of the NMOS tube M23 and then connected to the voltage-to-current circuit module, and the gate of the NMOS tube M23 is connected to the drain of the NMOS tube M23.

[0024] Further, the voltage-to-current circuit module includes a first-stage amplification unit, a second-stage amplification unit, a buffer unit, a source follower unit, and a current mirror unit;

[0025] The first-stage amplifying unit is connected to the second-stage amplifying unit, the second-stage amplifying unit is connected to the buffer unit, the buffer unit is connected to the source follower unit, and the source follower unit is connected to the current mirror unit to output the generated reference current.

[0026] Furthermore, the voltage-to-current circuit module also includes a capacitor, which is connected between the first-stage amplifying unit and the buffer unit and is used for performing phase compensation.

[0027] Furthermore, the voltage-to-current circuit module further includes a first resistor R3, which is connected between the source follower unit and the buffer unit and is used as a source follower load.

[0028] Further, the first-stage amplifying unit includes a PMOS tube M24, a PMOS tube M25, a PMOS tube M26, an NMOS tube M27, and an NMOS tube M28;

[0029] The source of the PMOS tube M24 is connected to the current input terminal, the gate of the PMOS tube M24 is connected to the gate of the PMOS tube M22, the drain of the PMOS tube M24 is respectively connected to the source of the PMOS tube M25 and the source of the PMOS tube M26, the gate of the PMOS tube M25 is connected to the bandgap reference circuit module, and the gate of the PMOS tube M26 is connected to the source follower unit;

[0030] The drain of the PMOS tube M25 is connected to the first end of the capacitor and the drain of the NMOS tube M27 respectively, and the source of the NMOS tube M27 is grounded;

[0031] The gate of the NMOS tube M28 is connected to the drain of the NMOS tube M28 and then connected to the gate of the NMOS tube M27. The drain of the NMOS tube M28 is also connected to the drain of the PMOS tube M26. The source of the NMOS tube M28 is grounded.

[0032] Furthermore, the second-stage amplifying unit includes a PMOS tube M29 and an NMOS tube M30;

[0033] The gate of the PMOS tube M29 is connected to the gate of the PMOS tube M24, the source of the PMOS tube M29 is connected to the current input end, the drain of the PMOS tube M29 is respectively connected to the drain of the NMOS tube M30 and the buffer unit, the gate of the NMOS tube M30 is connected to the first end of the capacitor, and the source of the NMOS tube M30 is grounded.

[0034] Further, the buffer unit includes an NMOS tube M31 and an NMOS tube M32;

[0035] The gate of the NMOS tube M31 is connected to the drain of the PMOS tube M29 and the drain of the NMOS tube M30 respectively, the drain of the NMOS tube M31 is connected to the current input terminal through the second resistor R4, and the source of the NMOS tube M31 is connected to the second end of the capacitor;

[0036] The gate of the NMOS tube M32 is connected to the drain of the NMOS tube M32, and the source of the NMOS tube M32 is grounded.

[0037] Further, the source follower includes an NMOS tube M33, a gate of the NMOS tube M33 is connected to the gate of the NMOS tube M31, a drain of the NMOS tube M33 is connected to the current mirror unit, and a source of the NMOS tube M33 is grounded through a first resistor R3.

[0038] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0039] A reference current source circuit of the present invention, a bandgap reference voltage circuit module is realized by an NMOS tube working in a subthreshold region, and a negative temperature characteristic is presented by a gate-source voltage difference of the NMOS tube in the subthreshold region, and a difference between gate-source voltage differences of two NMOS tubes in the subthreshold region presents a positive temperature characteristic, which are superimposed in a certain proportion to generate a temperature-independent voltage, and the temperature-independent voltage is converted into a reference current by a voltage-to-current circuit to obtain the reference current, and a BJT is not used, thereby solving the problem that the existing reference current source circuit needs to use a BJT device, resulting in a large occupied layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A circuit diagram of an existing reference current source circuit;

[0042] Figure 2 The present invention is a circuit diagram of a reference current source circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0044] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0045] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0046] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0047] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0048] Traditional reference current source circuit such as Figure 1 As shown, MOS tube m1, MOS tube m2, MOS tube m3, MOS tube m4, transistor Q1, transistor Q2, and resistor are used to generate positive temperature coefficient current, MOS tube m5, MOS tube m6, MOS tube m7, MOS tube m8, transistor Q3, and transistor R2 are used to generate negative temperature coefficient current, MOS tube m10 and MOS tube m9 copy two kinds of currents respectively, and output them superimposed at the output node to obtain a reference current that is independent of temperature.

[0049] exist Figure 1 The relationship between the base-emitter voltage difference and the collector current of the BJT in is:

[0050]

[0051] Among them, V T is the thermal voltage, I c is the collector current of the BJT, I s is the reverse saturation current, V BE is the base-emitter voltage difference.

[0052] Figure 1 The positive temperature coefficient current generated in is:

[0053]

[0054] Wherein, N is the size ratio of transistor Q2 to transistor Q1.

[0055] Figure 1 The negative temperature coefficient current generated in is:

[0056]

[0057] The final output reference current is:

[0058] I=M*I PTAT +N*I CTAT

[0059] Wherein, m is the size ratio of the MOS tube m10 and the MOS tube m4, and N is the size ratio of the MOS tube m9 and the MOS tube m6.

[0060] From the above content, we can see that Figure 1 The circuit shown requires three BJT devices and two resistors, which will occupy a large layout area. In addition, considering the matching requirements between transistor Q1 and transistor Q2, a dummy BJT device will be added, which further increases the occupied layout area.

[0061] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0062] like Figure 2 As shown, an embodiment of the present invention provides a reference current source circuit, including a startup circuit module, a bandgap reference circuit module and a voltage-to-current circuit module; the startup circuit module is connected to the bandgap reference circuit module, the bandgap reference circuit module is connected to the voltage-to-current circuit module, the bandgap reference circuit module is used to generate a voltage that is independent of temperature, and the voltage-to-current circuit module is used to generate a reference current based on a voltage that is independent of temperature.

[0063] Among them, the bandgap reference circuit module includes multiple NMOS tubes working in the subthreshold region, the gate-source voltage difference of the NMOS tubes working in the subthreshold region presents a negative temperature characteristic, and the difference between the gate-source voltage differences of two NMOS tubes working in the subthreshold region presents a positive temperature characteristic.

[0064] The present application utilizes a bandgap reference circuit module to generate a reference current. By using a high-gain operational amplifier in a voltage-to-current circuit, the source voltage of the source follower is ensured to follow the bandgap reference voltage, so that the voltage across the first resistor R3 is equal to the bandgap reference voltage, thereby generating a reference current.

[0065] Further, the startup circuit module includes a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a PMOS tube M5; the gate of the PMOS tube M1 is connected to the drain and then connected to the gate of the NMOS tube M2, the gate of the NMOS tube M2 is also connected to the drain of the NMOS tube M3, the source of the NMOS tube M2 is grounded, and the drain of the NMOS tube M2 is connected to the bandgap reference circuit module; the gate of the NMOS tube M3 is connected to the gate of the NMOS tube M4 and the drain of the NMOS tube M4, the source of the NMOS tube M3 is connected to the source of the NMOS tube M4 and then grounded; the drain of the NMOS tube M4 is connected to the drain of the PMOS tube M5, the source of the PMOS tube M5 is connected to the source of the PMOS tube M1 and then connected to the current input end, and the gate of the PMOS tube M5 is connected to the bandgap reference circuit module.

[0066] Specifically, when the power starts to rise from 0, the current passes through the PMOS tube M1 to turn on the NMOS tube M2, so that the bandgap reference circuit module starts to work. When the current flows from the PMOS tube M5 to the NMOS tube M4, the NMOS tube M3 is turned on, so that the gate voltage of the NMOS tube M2 is reduced, and the NMOS tube M2 is turned off to turn off the bandgap reference circuit module, thereby turning on or off the bandgap reference circuit module.

[0067] Further, the bandgap reference circuit module includes PMOS tube M6, PMOS tube M7, NMOS tube M8, NMOS tube M9, NMOS tube M10, NMOS tube M11, NMOS tube M12, PMOS tube M13, NMOS tube M14, NMOS tube M15, PMOS tube M16, NMOS tube M17, NMOS tube M18, PMOS tube M19, NMOS tube M20, NMOS tube M21, PMOS tube M22 and NMOS tube M23.

[0068] The gate of the PMOS transistor M6 , the gate of the PMOS transistor M7 , the gate of the PMOS transistor M13 , the gate of the PMOS transistor M16 , the gate of the PMOS transistor M19 and the gate of the PMOS transistor M22 are connected to each other.

[0069] The source of the PMOS tube M6, the source of the PMOS tube M7, the source of the PMOS tube M13, the source of the PMOS tube M16, the source of the PMOS tube M19 and the source of the PMOS tube M22 are connected to each other and then connected to the current input terminal;

[0070] The gate of the PMOS tube M6 is also connected to the gate of the PMOS tube M5 and the drain of the PMOS tube M7 respectively. The drain of the PMOS tube M6 is connected to the drain of the NMOS tube M8 respectively. The drain of the PMOS tube M7 is connected to the drain of the NMOS tube M2.

[0071] The drain of the NMOS tube M8 is connected to the gate of the NMOS tube M8 and then to the gate of the NMOS tube M9. The source of the NMOS tube M8 is connected to the drain of the NMOS tube M10. The drain of the NMOS tube M9 is connected to the drain of the PMOS tube M7. The source of the NMOS tube M9 is connected to the drain of the NMOS tube M11.

[0072] The drain of the NMOS tube M10 is connected to the gate of the NMOS tube M10 and then connected to the gate of the NMOS tube M11. The source of the NMOS tube M10 is grounded. The source of the NMOS tube M11 is connected to the drain of the NMOS tube M12. The source of the NMOS tube M12 is grounded. The gate of the NMOS tube M12 is connected to the voltage-to-current circuit module.

[0073] The drain of the PMOS tube M13 is connected to the drain of the NMOS tube M14, the gate of the NMOS tube M14 is connected to the drain of the NMOS tube M14 and the gate of the NMOS tube M15 respectively, the source of the NMOS tube M14 is connected to the drain of the NMOS tube M15 and then connected to the source of the NMOS tube M18, and the source of the NMOS tube M15 is grounded.

[0074] The drain of the PMOS tube M16 is connected to the drain of the NMOS tube M17, the gate of the NMOS tube M17 is connected to the drain of the NMOS tube M17 and the gate of the NMOS tube M18 respectively, the source of the NMOS tube M17 is connected to the drain of the NMOS tube M18 and then to the source of the NMOS tube M21.

[0075] The drain of the PMOS tube M19 is connected to the drain of the NMOS tube M20, the gate of the NMOS tube M20 is connected to the drain of the NMOS tube M20 and the gate of the NMOS tube M21 respectively, the source of the NMOS tube M20 is connected to the drain of the NMOS tube M21 and then connected to the source of the NMOS tube M23.

[0076] The drain of the PMOS tube M22 is connected to the drain of the NMOS tube M23 and then connected to the voltage-to-current circuit module, and the gate of the NMOS tube M23 is connected to the drain of the NMOS tube M23.

[0077] Specifically, NMOS transistor M10, NMOS transistor M11, NMOS transistor M14, NMOS transistor M15, NMOS transistor M17, NMOS transistor M18, NMOS transistor M20, NMOS transistor M21, and NMOS transistor M23 all operate in the subthreshold region. At this time, the IV characteristics of the transistors operating in the subthreshold region are:

[0078]

[0079] Among them, I D is the current flowing into the drain of the NMOS tube, W is the width of the NMOS tube, L is the channel length of the NMOS tube, V GS is the gate-source voltage difference, V TH is the threshold voltage, where V T is the thermal voltage, μ is the channel electron mobility, C OX is the capacitance per unit area of ​​gate oxide, and η is the subthreshold region slope factor.

[0080] Therefore, the gate-source voltage difference of the NMOS tube M23 is:

[0081]

[0082] The gate-source voltage difference of NMOS tube M20 is:

[0083]

[0084] The gate-source voltage difference of NMOS tube M21 is:

[0085]

[0086] The drain-source voltage difference of NMOS tube M21 is:

[0087]

[0088] Similarly, the drain-source voltage difference of NMOS tube M18 is:

[0089]

[0090] The drain-source voltage difference of NMOS tube M15 is:

[0091]

[0092] Since the NMOS tube M12 works in the linear region, the NMOS tube M12 can be equivalent to a resistor with a resistance of

[0093]

[0094] so

[0095]

[0096] Among them, V T = kT / q, k is the Boltzmann constant, q is the elementary charge, V TH =V TH0 -nT, n is the temperature coefficient of the threshold voltage, V TH0 The threshold voltage is 0K.

[0097] V ref The first derivative with respect to temperature is:

[0098]

[0099] Among them, When Vref=V TH0 According to the above relationship, the proportional relationship between the NMOS tubes can be obtained, and the bandgap reference voltage can be obtained in turn.

[0100] Furthermore, the voltage-to-current circuit module includes a first-stage amplifier unit, a second-stage amplifier unit, a buffer unit, a source follower unit and a current mirror unit; the first-stage amplifier unit is connected to the second-stage amplifier unit, the second-stage amplifier unit is connected to the buffer unit, the buffer unit is connected to the source follower unit, and the source follower unit is connected to the current mirror unit to output the generated reference current.

[0101] Furthermore, the voltage-to-current circuit module also includes a capacitor, which is connected between the first-stage amplification unit and the buffer unit and is used to perform phase compensation.

[0102] Furthermore, the voltage-to-current circuit module further includes a first resistor R3, which is connected between the source follower unit and the buffer unit and is used as a source follower load.

[0103] Further, the first-stage amplification unit includes a PMOS tube M24, a PMOS tube M25, a PMOS tube M26, an NMOS tube M27, and an NMOS tube M28; the source of the PMOS tube M24 is connected to the current input end, the gate of the PMOS tube M24 is connected to the gate of the PMOS tube M22, the drain of the PMOS tube M24 is respectively connected to the source of the PMOS tube M25 and the source of the PMOS tube M26, the gate of the PMOS tube M25 is connected to the bandgap reference circuit module, and the gate of the PMOS tube M26 is connected to the source follower unit; the drain of the PMOS tube M25 is respectively connected to the first end of the capacitor and the drain of the NMOS tube M27, and the source of the NMOS tube M27 is grounded; the gate of the NMOS tube M28 is connected to the drain of the NMOS tube M28 and then connected to the gate of the NMOS tube M27, the drain of the NMOS tube M28 is also connected to the drain of the PMOS tube M26, and the source of the NMOS tube M28 is grounded.

[0104] Furthermore, the second-stage amplification unit includes a PMOS tube M29 and an NMOS tube M30; the gate of the PMOS tube M29 is connected to the gate of the PMOS tube M24, the source of the PMOS tube M29 is connected to the current input end, the drain of the PMOS tube M29 is respectively connected to the drain of the NMOS tube M30 and the buffer unit, the gate of the NMOS tube M30 is connected to the first end of the capacitor, and the source of the NMOS tube M30 is grounded.

[0105] Furthermore, the buffer unit includes an NMOS tube M31 and an NMOS tube M32; the gate of the NMOS tube M31 is respectively connected to the drain of the PMOS tube M29 and the drain of the NMOS tube M30, the drain of the NMOS tube M31 is connected to the current input end through the second resistor R4, and the source of the NMOS tube M31 is connected to the second end of the capacitor; the gate of the NMOS tube M32 is connected to the drain of the NMOS tube M32, and the source of the NMOS tube M32 is grounded.

[0106] Further, the source follower includes an NMOS tube M33, a gate of the NMOS tube M33 is connected to the gate of the NMOS tube M31, a drain of the NMOS tube M33 is connected to the current mirror unit, and a source of the NMOS tube M33 is grounded through a first resistor R3.

[0107] Furthermore, the current mirror unit includes a PMOS tube M34 and a PMOS tube M35, wherein the drain of the PMOS tube M34 is respectively connected to the drain of the NMOS tube M33 and the gate of the PMOS tube M34, the drain of the PMOS tube M35 is an output terminal to output the generated reference current, and the source of the PMOS tube M34 and the source of the PMOS tube M35 are connected to each other and to the current input terminal.

[0108] Specifically, the output of the first-stage amplification unit and the output of the second-stage amplification unit are high-impedance nodes, which produce two poles, resulting in insufficient phase margin and causing the circuit to oscillate. Capacitor C1 is used for phase compensation. One end of capacitor C1 is connected to the output end of the first-stage amplification unit, and the other end is connected to the output end of the buffer unit to avoid generating a zero point in the right half plane. At this time, the gain of the entire circuit is:

[0109] A v =gm1*ro1*gm2*ro2;

[0110] The gain-bandwidth product of the circuit is:

[0111]

[0112] The secondary point of the circuit is:

[0113]

[0114] Among them, ro1 and ro2 are the node output impedances of the first stage amplification unit and the second stage amplification unit, Co2 is the node capacitance of the second stage amplification, gm1, gm2, gm31, and gm32 are the transconductances of the PMOS tube M25, the NMOS tube M30, the NMOS tube M31, and the NMOS tube M32.

[0115] More specifically, R1 is a source follower load, which determines the magnitude of the current flowing through the PMOS tube M34:

[0116] I ref =V ref / R1.

[0117] The width-to-length ratio of the PMOS tube M35 may be K times that of the PMOS tube M34, so the magnitude of the output reference current is:

[0118] I out =K*I ref =K*V ref / R1.

[0119] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0120] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A reference current source circuit, characterized in that: It includes a startup circuit module, a bandgap reference circuit module and a voltage-to-current circuit module; The startup circuit module is connected to the bandgap reference circuit module, the bandgap reference circuit module is connected to the voltage-to-current circuit module, the bandgap reference circuit module is used to generate a temperature-independent voltage, and the voltage-to-current circuit module is used to generate a reference current according to the temperature-independent voltage; The startup circuit module includes a PMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4 and a PMOS tube M5; The gate and drain of the PMOS tube M1 are connected to the gate of the NMOS tube M2, the gate of the NMOS tube M2 is also connected to the drain of the NMOS tube M3, the source of the NMOS tube M2 is grounded, and the drain of the NMOS tube M2 is connected to the bandgap reference circuit module; The gate of the NMOS tube M3 is connected to the gate of the NMOS tube M4 and the drain of the NMOS tube M4, and the source of the NMOS tube M3 is connected to the source of the NMOS tube M4 and then grounded; The drain of the NMOS tube M4 is connected to the drain of the PMOS tube M5, the source of the PMOS tube M5 is connected to the source of the PMOS tube M1 and then connected to the current input terminal, and the gate of the PMOS tube M5 is connected to the bandgap reference circuit module; Among them, the bandgap reference circuit module includes multiple NMOS tubes working in the subthreshold region, the gate-source voltage difference of the NMOS tubes working in the subthreshold region presents a negative temperature characteristic, and the difference between the gate-source voltage differences of two adjacent NMOS tubes working in the subthreshold region presents a positive temperature characteristic.

2. The reference current source circuit according to claim 1, characterized in that: The bandgap reference circuit module includes a PMOS tube M6, a PMOS tube M7, an NMOS tube M8, an NMOS tube M9, an NMOS tube M10, an NMOS tube M11, an NMOS tube M12, a PMOS tube M13, an NMOS tube M14, an NMOS tube M15, a PMOS tube M16, an NMOS tube M17, an NMOS tube M18, a PMOS tube M19, an NMOS tube M20, an NMOS tube M21, a PMOS tube M22 and an NMOS tube M23; The gate of the PMOS tube M6, the gate of the PMOS tube M7, the gate of the PMOS tube M13, the gate of the PMOS tube M16, the gate of the PMOS tube M19 and the gate of the PMOS tube M22 are connected to each other; The source of the PMOS tube M6, the source of the PMOS tube M7, the source of the PMOS tube M13, the source of the PMOS tube M16, the source of the PMOS tube M19 and the source of the PMOS tube M22 are connected to each other and then connected to the current input end; The gate of the PMOS tube M6 is also connected to the gate of the PMOS tube M5 and the drain of the PMOS tube M7 respectively, the drain of the PMOS tube M6 is connected to the drain of the NMOS tube M8 respectively, and the drain of the PMOS tube M7 is connected to the drain of the NMOS tube M2; The drain of the NMOS tube M8 is connected to the gate of the NMOS tube M8 and then connected to the gate of the NMOS tube M9. The source of the NMOS tube M8 is connected to the drain of the NMOS tube M10. The drain of the NMOS tube M9 is connected to the drain of the PMOS tube M7. The source of the NMOS tube M9 is connected to the drain of the NMOS tube M11. The drain of the NMOS tube M10 is connected to the gate of the NMOS tube M10 and then connected to the gate of the NMOS tube M11. The source of the NMOS tube M10 is grounded. The source of the NMOS tube M11 is connected to the drain of the NMOS tube M12. The source of the NMOS tube M12 is grounded. The gate of the NMOS tube M12 is connected to the voltage-to-current circuit module. The drain of the PMOS tube M13 is connected to the drain of the NMOS tube M14, the gate of the NMOS tube M14 is connected to the drain of the NMOS tube M14 and the gate of the NMOS tube M15 respectively, the source of the NMOS tube M14 is connected to the drain of the NMOS tube M15 and then to the source of the NMOS tube M18, and the source of the NMOS tube M15 is grounded; The drain of the PMOS tube M16 is connected to the drain of the NMOS tube M17, the gate of the NMOS tube M17 is connected to the drain of the NMOS tube M17 and the gate of the NMOS tube M18 respectively, the source of the NMOS tube M17 is connected to the drain of the NMOS tube M18 and then connected to the source of the NMOS tube M21; The drain of the PMOS tube M19 is connected to the drain of the NMOS tube M20, the gate of the NMOS tube M20 is connected to the drain of the NMOS tube M20 and the gate of the NMOS tube M21 respectively, the source of the NMOS tube M20 is connected to the drain of the NMOS tube M21 and then connected to the source of the NMOS tube M23; The drain of the PMOS tube M22 is connected to the drain of the NMOS tube M23 and then connected to the voltage-to-current circuit module, and the gate of the NMOS tube M23 is connected to the drain of the NMOS tube M23.

3. The reference current source circuit according to claim 2, characterized in that: The voltage-to-current circuit module includes a first-stage amplification unit, a second-stage amplification unit, a buffer unit, a source follower unit, and a current mirror unit; The first-stage amplifying unit is connected to the second-stage amplifying unit, the second-stage amplifying unit is connected to the buffer unit, the buffer unit is connected to the source follower unit, and the source follower unit is connected to the current mirror unit to output the generated reference current.

4. The reference current source circuit according to claim 3, characterized in that: The voltage-to-current circuit module also includes a capacitor, which is connected between the first-stage amplifying unit and the buffer unit and is used for performing phase compensation.

5. The reference current source circuit according to claim 4, characterized in that: The voltage-to-current circuit module further includes a first resistor R3 , which is connected between the source follower unit and the buffer unit and is used as a source follower unit load.

6. The reference current source circuit according to claim 5, characterized in that: The first-stage amplifying unit includes a PMOS tube M24, a PMOS tube M25, a PMOS tube M26, an NMOS tube M27, and an NMOS tube M28; The source of the PMOS tube M24 is connected to the current input terminal, the gate of the PMOS tube M24 is connected to the gate of the PMOS tube M22, the drain of the PMOS tube M24 is respectively connected to the source of the PMOS tube M25 and the source of the PMOS tube M26, the gate of the PMOS tube M25 is respectively connected to the gate of the NMOS tube M12 in the bandgap reference circuit module, the drain of the PMOS tube M22, and the drain of the NMOS tube M23, and the gate of the PMOS tube M26 is connected to the source follower unit; The drain of the PMOS tube M25 is connected to the first end of the capacitor and the drain of the NMOS tube M27 respectively, and the source of the NMOS tube M27 is grounded; The gate of the NMOS tube M28 is connected to the drain of the NMOS tube M28 and then connected to the gate of the NMOS tube M27. The drain of the NMOS tube M28 is also connected to the drain of the PMOS tube M26. The source of the NMOS tube M28 is grounded.

7. The reference current source circuit according to claim 6, characterized in that: The second-stage amplification unit includes a PMOS tube M29 and an NMOS tube M30; The gate of the PMOS tube M29 is connected to the gate of the PMOS tube M24, the source of the PMOS tube M29 is connected to the current input end, the drain of the PMOS tube M29 is respectively connected to the drain of the NMOS tube M30 and the buffer unit, the gate of the NMOS tube M30 is connected to the first end of the capacitor, and the source of the NMOS tube M30 is grounded.

8. The reference current source circuit according to claim 7, characterized in that: The buffer unit includes an NMOS tube M31 and an NMOS tube M32; The gate of the NMOS tube M31 is connected to the drain of the PMOS tube M29 and the drain of the NMOS tube M30 respectively, the drain of the NMOS tube M31 is connected to the current input terminal through the second resistor R4, and the source of the NMOS tube M31 is connected to the second end of the capacitor; The gate of the NMOS tube M32 is connected to the drain of the NMOS tube M32 , the source of the NMOS tube M32 is grounded, and the drain of the NMOS tube M32 is respectively connected to the second end of the capacitor and the source of the NMOS tube M31 .

9. The reference current source circuit according to claim 8, characterized in that: The source follower unit includes an NMOS tube M33, a gate of the NMOS tube M33 is connected to the gate of the NMOS tube M31, a drain of the NMOS tube M33 is connected to the current mirror unit, and a source of the NMOS tube M33 is grounded through a first resistor R3.

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