A Verilog source code protection system and method based on code obfuscation technology
Through the Verilog source code protection system based on code obfuscation technology, the key information in the Verilog source code is hidden and obfuscated, and the problem of insufficient intellectual property protection in the existing technology is solved, and efficient Verilog source code protection is achieved.
Patent Information
- Application Number
- CN202410540554.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-30
- Publication Date
- 2025-04-15
- Estimated Expiration
- 2044-04-30
AI Technical Summary
The existing Verilog source code protection methods are difficult to effectively hide module names, input and output signals, registers and connections, resulting in insufficient intellectual property protection.
The Verilog source code protection system based on code obfuscation technology is adopted to process the Verilog source code through iterative arbitrators, lexical analyzers, arbitrators, random obfuscators and format processors to hide and obfuscate information such as module names, input and output signals, registers and connections.
It improves the difficulty of reverse analysis of Verilog source code, effectively protects intellectual property rights, and does not affect the expansion of the source code.
Smart Images
Figure CN118551373B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit design encryption, and in particular relates to a Verilog source code protection system and method based on code obfuscation technology. Background Art
[0002] With the development of integrated circuit technology, people are paying more and more attention to the intellectual property protection of Verilog code. One of the current mainstream means is to protect intellectual property by encrypting the source code. Code obfuscation technology can increase the difficulty of code reading and understanding without affecting the function and use of the program. It is one of the common encryption methods in the current source code encryption field. At present, common obfuscation methods include layout obfuscation, control flow obfuscation, data obfuscation and prevention obfuscation. Compared with other obfuscation methods, layout obfuscation has the lowest implementation complexity and obvious effect. Summary of the invention
[0003] The technology of the present invention solves the problem: overcomes the shortcomings of the prior art and provides a Verilog source code protection system and method based on code obfuscation technology, which can hide the module name, input and output signals, registers and connections of the Verilog source code, thereby protecting the intellectual property rights of the Verilog source code.
[0004] In order to solve the above technical problems, the present invention discloses a Verilog source code protection system based on code obfuscation technology, comprising:
[0005] An iterative arbitrator is used to receive input of Verilog source code and obfuscation pattern; input the Verilog source code line by line into the lexical analyzer; pass the obfuscation pattern down to the arbitrator as reference information for arbitration; and recursively process the macro definition body input by the lexical analyzer;
[0006] The lexical analyzer is used to analyze the code in the Verilog source code according to the naming rules of the Verilog language, and classify the code according to macro definition body, identifier and function / task; different processing methods are used for different classifications: the macro definition body is output to the iteration arbitrator for processing, the identifier is output to the arbitrator for processing, and the function / task is output to the format processor for processing;
[0007] An arbitrator is used to use the obfuscation mode as reference information to determine the reserved mode to which the input identifier belongs; if it belongs to the full reserved mode, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and belongs to the module range that needs to be reserved, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and does not belong to the module range that needs to be reserved, the identifier is input into the random obfuscator for processing; if it belongs to the non-reserved mode, the identifier is input into the random obfuscator for processing;
[0008] A random obfuscator, used to perform random obfuscation processing on the input identifier and output the identifier after random obfuscation processing;
[0009] The format processor is used to perform layout obfuscation on all input information to obtain obfuscated Verilog code;
[0010] Outputter, used to output obfuscated Verilog code.
[0011] In the above-mentioned Verilog source code protection system based on code obfuscation technology, identifiers include: module name, module instantiation, input signal name, output signal name, register name and connection name.
[0012] In the above-mentioned Verilog source code protection system based on code obfuscation technology, the full retention mode means: retaining all module names and input and output identifiers unchanged; the partial retention mode means: retaining the module name and corresponding input and output identifiers of the specified module unchanged; the no retention mode means: obfuscating all module names and input and output signals.
[0013] In the Verilog source code protection system based on code obfuscation technology, when the random obfuscator performs random obfuscation on the identifier without reserved pattern,
[0014] If the random obfuscation process is performed on the current identifier for the first time, after the random obfuscation process is performed on the current identifier for the first time, the mapping relationship before and after the random obfuscation process of the current identifier is saved in a historical obfuscation mapping relationship file;
[0015] If it is not the first time that random obfuscation processing is performed on the current identifier, before the random obfuscation processing, the historical obfuscation mapping relationship file is queried to see whether there is a random obfuscation rule that matches the current identifier; if so, the obfuscation rule that matches the current identifier is called from the historical obfuscation mapping relationship file to perform random obfuscation processing on the current identifier; if so, a new random obfuscation rule is used to perform random obfuscation processing on the current identifier, and after the random obfuscation processing, the mapping relationship corresponding to the new random obfuscation rule is saved to the end of the historical obfuscation mapping relationship file.
[0016] In the above Verilog source code protection system based on code obfuscation technology, the processing priorities of the three retention modes are: the full retention mode is higher than the partial retention mode, and the partial retention mode is higher than the no retention mode.
[0017] In the above Verilog source code protection system based on code obfuscation technology, for the partial reservation mode, at least one module name that needs to be reserved needs to be specified.
[0018] In the above-mentioned Verilog source code protection system based on code obfuscation technology, when the lexical analyzer analyzes the code in the Verilog source code according to the naming rules of the Verilog language, each time a new module name is matched, the module information corresponding to the current identifier is updated.
[0019] In the above Verilog source code protection system based on code obfuscation technology, when the random obfuscator performs random obfuscation processing on the identifier without reserved pattern, it ensures that the identifier after random obfuscation processing complies with the naming rules of the Verilog language in the following way:
[0020] Identifiers consist of letters, numbers, and underscores and begin with a letter or an underscore.
[0021] The length of the identifier shall not exceed 1024 characters;
[0022] Verilog keywords cannot be used as identifiers.
[0023] In the above-mentioned Verilog source code protection system based on code obfuscation technology, when the iterative arbitrator inputs the Verilog source code into the lexical analyzer line by line, it performs iterative arbitration on the Verilog source code to determine whether it has traversed to the last line of the Verilog source code. If not, the Verilog source code is input into the lexical analyzer line by line.
[0024] Correspondingly, the present invention also discloses a Verilog source code protection method based on code obfuscation technology, comprising:
[0025] Step 1, obtain the input Verilog source code and obfuscation pattern through the iterative arbitrator;
[0026] Step 2, iteratively arbitrate the Verilog source code through the iterative arbitrator, and input it into the lexical analyzer line by line; pass the obfuscation pattern down to the arbitrator as reference information for arbitration;
[0027] Step 3, using a lexical analyzer to analyze the code in the Verilog source code according to the naming rules of the Verilog language, and classifying the code according to macro definition body, identifier and function / task;
[0028] Step 4: different processing methods are used for different classifications: the macro definition body is returned to step 2 for recursive processing; the identifier is output to the arbitrator for processing, and the function / task is output to the format processor for processing;
[0029] Step 5, using the obfuscation mode as reference information, the arbitrator determines the reserved mode to which the input identifier belongs; if it belongs to the full reserved mode, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and belongs to the module range that needs to be reserved, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and does not belong to the module range that needs to be reserved, the identifier is input into the random obfuscator for processing; if it belongs to the non-reserved mode, the identifier is input into the random obfuscator for processing;
[0030] Step 6, performing random obfuscation processing on the input identifier through a random obfuscator, and outputting the identifier after random obfuscation processing;
[0031] Step 7, perform layout obfuscation processing on all input information through the format processor to obtain obfuscated Verilog code;
[0032] Step 8: Output the obfuscated Verilog code through the output device.
[0033] The present invention has the following advantages:
[0034] (1) The present invention discloses a Verilog source code protection solution based on code obfuscation technology, which can achieve efficient obfuscation of Verilog code, increase redundant information through identifier transformation to increase the difficulty of reverse analysis, and thus protect the intellectual property rights of users / enterprises from infringement.
[0035] (2) The present invention discloses a Verilog source code protection solution based on code obfuscation technology. Compared with other code obfuscation solutions, the present invention is positioned at the obfuscation implementation of Verilog source code. Combining the usage habits of engineers and the characteristics of Verilog code, the present invention also adds different degrees of Verilog source code interface retention functions to achieve obfuscation of Verilog source code without affecting the extensibility of Verilog source code. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] Figure 1 It is an implementation logic diagram of a Verilog source code protection system based on code obfuscation technology in an embodiment of the present invention. DETAILED DESCRIPTION
[0037] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments disclosed in the present invention will be further described in detail below with reference to the accompanying drawings.
[0038] One of the core ideas of the present invention is: through iterative processing, lexical analysis, arbitration, random obfuscation and format processing of Verilog source code, six identifiers of module name, module instantiation, input signal name, output signal name, register name and connection name in Verilog source code are obfuscated, so as to design and implement a Verilog source code protection scheme based on code obfuscation technology, which can effectively protect the rights and interests of Verilog source code authors from infringement.
[0039] Reference Figure 1 In this embodiment, the Verilog source code protection system based on code obfuscation technology includes: an iterative arbitrator, a lexical analyzer, an arbitrator, a random obfuscator, a format processor and an outputter.
[0040] Specific:
[0041] The iterative arbitrator is used to receive inputs of Verilog source code and obfuscation patterns; input the Verilog source code line by line into the lexical analyzer; pass the obfuscation pattern down to the arbitrator as reference information for arbitration; and recursively process the macro definition body input by the lexical analyzer.
[0042] In this embodiment, when the iterative arbitrator inputs the Verilog source code line by line into the lexical analyzer, iterative arbitration is performed on the Verilog source code to determine whether the last line of the Verilog source code has been traversed. If not, the Verilog source code is input into the lexical analyzer line by line.
[0043] The lexical analyzer is used to analyze the code in the Verilog source code according to the naming rules of the Verilog language, and classify the code according to the macro definition body, identifier (including module name, module instantiation, input signal name, output signal name, register name and connection name) and function / task; different processing methods are used for different classifications: the macro definition body is output to the iterative arbitrator for processing, the identifier is output to the arbitrator for processing, and the function / task is output to the format processor for processing.
[0044] In this embodiment, when the lexical analyzer analyzes the code in the Verilog source code according to the naming rules of the Verilog language, each time a new module name is matched, the module information corresponding to the current identifier needs to be updated.
[0045] The arbitrator is used to use the obfuscation mode as reference information to determine the reserved mode to which the input identifier belongs; if it belongs to the full reserved mode, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and belongs to the module range that needs to be reserved, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and does not belong to the module range that needs to be reserved, the identifier is input into the random obfuscator for processing; if it belongs to the non-reserved mode, the identifier is input into the random obfuscator for processing.
[0046] In this embodiment, the full retention mode means: retaining all module names and input and output identifiers unchanged; the partial retention mode means: retaining the module name and corresponding input and output identifiers of the specified module unchanged; the no retention mode means: obfuscating all module names and input and output signals. Among them, the processing priority of the three retention modes is: the full retention mode is higher than the partial retention mode, and the partial retention mode is higher than the no retention mode. For the partial retention mode, at least one module name that needs to be retained must be specified.
[0047] The random obfuscator is used to perform random obfuscation processing on the input identifier and output the identifier after random obfuscation processing.
[0048] In this embodiment, when the random obfuscator performs random obfuscation processing on an identifier without a reserved pattern: if it is the first time to perform random obfuscation processing on the current identifier, then after the first random obfuscation processing on the current identifier, the mapping relationship before and after the random obfuscation processing of the current identifier is saved in the historical obfuscation mapping relationship file. If it is not the first time to perform random obfuscation processing on the current identifier, then before the random obfuscation processing, the historical obfuscation mapping relationship file is queried to see whether there is a random obfuscation rule that matches the current identifier; if so, the obfuscation rule that matches the current identifier is called from the historical obfuscation mapping relationship file to perform random obfuscation processing on the current identifier; if so, a new random obfuscation rule is used to perform random obfuscation processing on the current identifier, and after the random obfuscation processing, the mapping relationship corresponding to the new random obfuscation rule is saved to the end of the historical obfuscation mapping relationship file.
[0049] Furthermore, when the random obfuscator performs random obfuscation processing on identifiers without reserved patterns, it can ensure that the identifiers after random obfuscation comply with the naming rules of the Verilog language in the following ways: 1) identifiers can only be composed of letters, numbers and underscores, and must start with letters and underscores; 2) the length of the identifier does not exceed 1024 characters; 3) Verilog keywords cannot be used as identifiers.
[0050] The format processor is used to perform layout obfuscation on all input information to obtain obfuscated Verilog code.
[0051] In this embodiment, when performing layout obfuscation processing, the format processor may replace line breaks, indentations, and consecutive spaces in the code with single spaces to further obfuscate the readability of the code.
[0052] Outputter, used to output obfuscated Verilog code.
[0053] In this embodiment, the implementation process of the Verilog source code protection system based on code obfuscation technology is as follows:
[0054] Step 1, obtain the input Verilog source code and obfuscation mode through the iterative arbitrator.
[0055] Step 2, iteratively arbitrate the Verilog source code through the iterative arbitrator and input it into the lexical analyzer line by line; pass the obfuscation pattern down to the arbitrator as reference information for arbitration.
[0056] Step 3, using a lexical analyzer to analyze the code in the Verilog source code according to the naming rules of the Verilog language, and classifying the code according to macro definition body, identifier and function / task.
[0057] Step 4, adopt different processing methods for different categories: return the macro definition body to step 2 for recursive processing; output the identifier to the arbitrator for processing, and output the function / task to the format processor for processing.
[0058] Step 5, using the obfuscation mode as reference information, the arbitrator determines the reserved mode to which the input identifier belongs; if there is no reserved mode, the identifier is input into the random obfuscator for processing; if it belongs to the full reserved mode, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and belongs to the module range that needs to be reserved, the identifier is input into the format processor for processing; if it belongs to the partial reserved mode and does not belong to the module range that needs to be reserved, the identifier is input into the random obfuscator for processing; if it belongs to step 6, the random obfuscator is used to perform random obfuscation processing on the input identifier, and the identifier after random obfuscation processing is output.
[0059] Step 7: Perform layout obfuscation processing on all input information through a format processor to obtain obfuscated Verilog code.
[0060] Step 8: Output the obfuscated Verilog code through the output device.
[0061] Based on the above embodiments, the present invention is further described in detail below using C++ language as an implementation method. Undoubtedly, the present invention is not limited to a specific programming language, but can be implemented using any programming language.
[0062] 1) Get the input Verilog source code and obfuscation mode.
[0063] 2) Perform iterative arbitration on the acquired Verilog source code, that is, determine whether the traversal has reached the last line. If not, input the code into the lexical analyzer line by line; at the same time, pass the obfuscation pattern downward to the arbitrator as reference information for arbitration.
[0064] 3) Perform lexical analysis on each line of code in the Verilog source code and classify it according to macro definition body, identifier and function / task.
[0065] 4) Perform different processing for different categories of source code. For the macro definition body, return to step 2) for recursive processing; for the identifier, perform subsequent arbitration obfuscation operations; for the function / task type, output it to the format processor.
[0066] 5) The arbitrator processes identifiers differently according to different obfuscation modes: in the no-reservation mode, all identifiers are input into the random obfuscator for obfuscation; in the partial-reservation mode, when obfuscating the module name, module instantiation, input signal and output signal identifiers, it is necessary to determine whether they belong to the module range that needs to be retained. If so, the identifier is directly input into the outputter, otherwise it is input into the random obfuscator; in the full-reservation mode, all interface signals in the code (including module name, module instantiation, input signal and output signal) are kept directly skipping the random obfuscator and input into the format processor to obfuscate other identifiers in the code.
[0067] 6) Combined with the historical obfuscation mapping relationship file, use a random obfuscator to obfuscate the identifier.
[0068] 7) Use a format processor to perform layout obfuscation on all input signals.
[0069] 8) The outputter outputs the obfuscated Verilog code.
[0070] In the above steps, there are:
[0071] In step 1), the Verilog source code is obtained by giving the path of the Verilog source code file, and the obfuscation mode is obtained by giving different parameters to the C++ code. For example, when the parameter "preserve_interface" is given, the full preservation mode is adopted; when the parameter "perserve_module aaa,bbb" is given, the partial preservation mode is adopted, that is, the module names and input and output signals of the module names aaa and bbb are preserved unchanged; when there is no module preservation information parameter, the no preservation mode is adopted, that is, the no preservation mode is used by default.
[0072] In step 2), an infinite loop for function is used to traverse the Verilog source code line by line, and the end of the file is judged at the beginning of the loop. When it is determined that the iteration has reached the end of the file, the loop is exited. When it has not yet iterated to the end of the file, the code inside the loop continues to run.
[0073] Step 3) is located inside the infinite loop of step 2, that is, after obtaining each line of code, it is lexically analyzed. To achieve this goal, the lexical analyzer in the Verilator library file can be used. The lexical analyzer is built by the Flex tool, which can decompose the input Verilog source code into a series of lexical units (tokens), each of which represents an atomic grammatical element in the source code.
[0074] In step 4), the Switch function in C++ is used to perform different processing on different atomic syntax elements analyzed from the lexical unit. For the tasks and functions in the Verilog source code, the identifiers are kept unchanged; for the macro definition part in the Verilog source code, step 2) is called again for recursive processing, that is, the source code in the macro definition is analyzed line by line; for other identifiers in the Verilog source code, the obfuscation processing function is called.
[0075] Step 5) and step 6) first need to use the if statement to determine whether there is a historical obfuscation mapping relationship file in json format. If not, create a new historical obfuscation mapping relationship file in json format. If it exists, continue to execute. Then, another if judgment statement is needed to determine whether the identifier is a module name. When the identifier is a module name, the global variable value corresponding to the module to which the current obfuscation belongs needs to be updated. If not, continue to execute the code. Finally, Switch needs to be used to perform obfuscation on different obfuscation modes. When the no-reservation mode is adopted, the obtained identifier is directly obfuscated; when the partial obfuscation mode is adopted, and the matched identifier is a module name, input or output signal, it is necessary to determine whether the value of the module variable corresponding to the identifier exists in the specified reserved module name. If it exists, the matched module name, input and output signals are retained unchanged. If not, the identifier is obfuscated; when the full retention mode is adopted, as long as the identifier belongs to the module name, input or output signal, the identifier is retained unchanged, and if it does not belong, it is obfuscated. In terms of the implementation of specific obfuscation, the identifier equal-length obfuscation mode is adopted, that is, the length of the obfuscated identifier is the same as that of the identifier before obfuscation. Before formal obfuscation, it is necessary to detect whether there is an obfuscation mapping relationship for the corresponding identifier in the historical obfuscation mapping relationship file. If not, generate a new obfuscation mapping relationship. If so, use the mapping relationship in the historical obfuscation mapping relationship file.
[0076] In step 6), the obfuscation process can be achieved by generating a pseudo-random number through the srand function in C++. Specifically: define two character arrays, the identifier's starting character array and the non-starting character array. The starting character array consists of 26 English letters and underscores, and the non-starting character array consists of 26 English letters, underscores, and numbers (0-9). Assuming that the character length of an identifier that needs to be obfuscated is N, a character is randomly selected from the starting character array through the pseudo-random number generated by srand, and combined with N-1 characters randomly selected from the non-starting character array to form the obfuscated string of the identifier. After the obfuscation is completed, if a new obfuscation mapping relationship is used, the mapping relationship information needs to be updated to the historical obfuscation mapping relationship file after the obfuscation is completed.
[0077] In step 7), the format processor obtains the function / task code from the random obfuscator, the arbitrator and the unchanged function / task code line by line. The continuous spaces, indentations and line breaks are matched through regular expressions. The format processor replaces the continuous spaces, indentations and line breaks with single spaces to obtain a Verilog source code string with gradually increasing code length. Whenever the number of the above string reaches the set threshold of 30, the first space after the 30th character is used to split the above string to obtain the two parts of the split string, and the first part of the string is input into the output device, and the value of the original string is updated.
[0078] In step 8), when the string is obtained for the first time, a Verilog source code output file needs to be created and the obtained Verilog source code is output to the file. When the Verilog source code is not obtained for the first time, the code can be directly appended to a new line of the output file.
[0079] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.
[0080] The contents not described in detail in the specification of the present invention belong to the common knowledge of the professionals in this field.
Claims
1. A Verilog source code protection system based on code obfuscation technology, characterized in that: include: An iterative arbitrator for receiving inputs of Verilog source code and obfuscation pattern; Input the Verilog source code line by line into the lexical analyzer; Pass the obfuscation pattern down to the arbitrator as reference information for arbitration; and, recursively processing the macro definition body input by the lexical analyzer; The lexical analyzer is used to analyze the code in the Verilog source code according to the naming rules of the Verilog language, and classify the code according to macro definition body, identifier and function / task; different processing methods are used for different classifications: the macro definition body is output to the iteration arbitrator for processing, the identifier is output to the arbitrator for processing, and the function / task is output to the format processor for processing; An arbitrator, used for determining the reserved mode to which the input identifier belongs, using the obfuscation mode as reference information; If it belongs to the all reserved mode, the identifier is input into the format processor for processing; If it belongs to the partial reservation mode and belongs to the module range that needs to be reserved, the identifier is input into the format processor for processing; If it belongs to the partial reservation mode and does not belong to the module range that needs to be reserved, the identifier is input into the random obfuscator for processing; If it belongs to the unreserved mode, the identifier is input into the random obfuscator for processing; A random obfuscator, used to perform random obfuscation processing on the input identifier and output the identifier after random obfuscation processing; The format processor is used to perform layout obfuscation on all input information to obtain obfuscated Verilog code; Outputter, used to output obfuscated Verilog code.
2. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: Identifiers include: module name, module instantiation, input signal name, output signal name, register name, and wire name.
3. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: The full retention mode means: all module names and input and output identifiers are kept unchanged; the partial retention mode means: the module name and corresponding input and output identifiers of the specified module are kept unchanged; the no retention mode means: all module names and input and output signals are obfuscated.
4. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: The random obfuscator performs random obfuscation on identifiers without preserving patterns. If the random obfuscation process is performed on the current identifier for the first time, after the random obfuscation process is performed on the current identifier for the first time, the mapping relationship before and after the random obfuscation process of the current identifier is saved in a historical obfuscation mapping relationship file; If it is not the first time that random obfuscation processing is performed on the current identifier, before the random obfuscation processing, the historical obfuscation mapping relationship file is queried to see whether there is a random obfuscation rule that matches the current identifier; if so, the obfuscation rule that matches the current identifier is called from the historical obfuscation mapping relationship file to perform random obfuscation processing on the current identifier; if not, a new random obfuscation rule is used to perform random obfuscation processing on the current identifier, and after the random obfuscation processing, the mapping relationship corresponding to the new random obfuscation rule is saved to the end of the historical obfuscation mapping relationship file.
5. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: The processing priority of the three retention modes is: full retention mode is higher than partial retention mode, and partial retention mode is higher than no retention mode.
6. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: For partial preservation mode, you need to specify at least one module name that needs to be preserved.
7. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: When the lexical analyzer analyzes the code in the Verilog source code according to the naming rules of the Verilog language, each time a new module name is matched, the module information corresponding to the current identifier is updated.
8. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: When the random obfuscator performs random obfuscation on identifiers without reserved patterns, it ensures that the identifiers after random obfuscation conform to the naming rules of the Verilog language in the following ways: Identifiers are composed of letters, numbers, and underscores, and begin with a letter or an underscore. The length of the identifier shall not exceed 1024 characters; Verilog keywords cannot be used as identifiers.
9. The Verilog source code protection system based on code obfuscation technology according to claim 1, characterized in that: When the iterative arbitrator inputs the Verilog source code line by line into the lexical analyzer, it iteratively arbitrates the Verilog source code to determine whether the last line of the Verilog source code has been traversed. If not, the Verilog source code is input into the lexical analyzer line by line.
10. A Verilog source code protection method based on code obfuscation technology, characterized in that: include: Step 1, obtain the input Verilog source code and obfuscation mode through the iterative arbitrator; Step 2, iteratively arbitrate the Verilog source code through the iterative arbitrator and input it into the lexical analyzer line by line; Pass the obfuscation pattern down to the arbitrator as reference information for arbitration; Step 3, using a lexical analyzer to analyze the code in the Verilog source code according to the naming rules of the Verilog language, and classifying the code according to macro definition body, identifier and function / task; Step 4: different processing methods are used for different classifications: the macro definition body is returned to step 2 for recursive processing; the identifier is output to the arbitrator for processing, and the function / task is output to the format processor for processing; Step 5, using the obfuscation pattern as reference information, the arbitrator determines the reserved pattern to which the input identifier belongs; If it belongs to the all reserved mode, the identifier is input into the format processor for processing; If it belongs to the partial reservation mode and belongs to the module range that needs to be reserved, the identifier is input into the format processor for processing; If it belongs to the partial reservation mode and does not belong to the module range that needs to be reserved, the identifier is input into the random obfuscator for processing; If it belongs to the unreserved mode, the identifier is input into the random obfuscator for processing; Step 6, performing random obfuscation processing on the input identifier through a random obfuscator, and outputting the identifier after random obfuscation processing; Step 7, perform layout obfuscation processing on all input information through the format processor to obtain obfuscated Verilog code; Step 8: Output the obfuscated Verilog code through the output device.
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