A level shifter and high voltage half bridge driver

Abstract

This application provides a level shifter and a high-voltage half-bridge driver, belonging to the field of high-voltage power integrated circuit technology. The level shifter includes a first capacitor driving module, an input logic edge detection module, a bootstrap capacitor module, an active control module, a first isolation capacitor module, a second capacitor driving module, a second isolation capacitor module, a first pulse sensing module, a second pulse sensing module, and a latch output module. The first capacitor driving module generates a first pulse signal; the first pulse sensing module generates a fourth pulse signal; the second pulse sensing module generates a seventh pulse signal; the latch output module generates a target pulse signal and sends a feedback signal when the voltages of the fourth and seventh pulse signals are both greater than the target high voltage, so that the voltages of the fourth and seventh pulse signals are both less than or equal to the target high voltage. This application can reduce the signal transmission delay and power consumption of the level shifter and improve reliability.

Description

Technical Field

[0001] This application relates to the field of high-voltage power integrated circuit technology, and in particular to a level shifter and a high-voltage half-bridge driver. Background Technology

[0002] High-voltage power integrated circuits are widely used in automotive electronics, motor drives, and high-voltage LED display drivers. Power drive circuits are a component of high-voltage power integrated circuits, and a high-voltage half-bridge driver is a type of power drive circuit that can drive high-voltage power devices to operate normally.

[0003] As a key module in a high-voltage half-bridge driver, the level shifter is responsible for converting logic control signals from the low-voltage side into signals from the high-voltage side. During the operation of the level shifter, the rapid alternation of switching on and off between the high-voltage and low-voltage sides generates transient voltage changes on the high-voltage side, resulting in common-mode noise. Large common-mode noise can cause the level shifter to generate incorrect logic control signals, thus affecting the normal operation of the high-voltage half-bridge driver and, in severe cases, even burning out the circuit.

[0004] With the development of LED display technology and new energy vehicles, high-voltage half-bridge drivers need to evolve towards lower transmission delay, lower power consumption, and higher reliability. However, level shifters affect these performance characteristics. Currently, common level shifters mainly include active-coupled and capacitive-coupled types. Active-coupled level shifters typically consist of high-voltage switches, achieving lower signal transmission delay but with higher power consumption. Capacitive-coupled level shifters typically consist of coupling capacitors, reducing circuit power consumption but are susceptible to noise.

[0005] In summary, current level shifters cannot simultaneously meet the requirements of low transmission delay, low power consumption, and high reliability. Therefore, how to reduce transmission delay, reduce power consumption, and improve reliability in level shifters has become an urgent technical problem to be solved. Summary of the Invention

[0006] The main objective of this application is to provide a level shifter and a high-voltage half-bridge driver, which aims to reduce the signal transmission delay and power consumption of the level shifter and improve its reliability.

[0007] To achieve the above objectives, a first aspect of this application provides a level shifter, which includes: a first capacitor driving module, an input logic edge detection module, a bootstrap capacitor module, an active control module, a first isolation capacitor module, a second capacitor driving module, a second isolation capacitor module, a first pulse sensing module, a second pulse sensing module, and a latch output module.

[0008] The first capacitor driving module receives the first initial pulse signal and shortens the rise time of the first initial pulse signal to obtain the first pulse signal, which has an initial low voltage and an initial high voltage.

[0009] The input logic edge detection module is electrically connected to the first capacitor driving module, and the input logic edge detection module is used to output a second pulse signal when the first pulse signal jumps from the initial low voltage to the initial high voltage;

[0010] The bootstrap capacitor module is electrically connected to the input logic edge detection module and the active control module, and the active control module generates a control signal based on the second pulse signal;

[0011] The first isolation capacitor module is electrically connected to the first capacitor driving module and the first pulse sensing module. The first isolation capacitor module is used to convert the first pulse signal into a third pulse signal.

[0012] The first pulse sensing module is electrically connected to the active control module. The first pulse sensing module enters a first working state in response to the control signal and generates a fourth pulse signal based on the third pulse signal. The fourth pulse signal has a target high voltage; wherein the target high voltage is greater than the initial high voltage.

[0013] The second capacitor driving module inverts the first pulse signal to obtain the fifth pulse signal;

[0014] The second isolation capacitor module is electrically connected to the second capacitor driving module and the second pulse sensing module. The second isolation capacitor module is used to convert the fifth pulse signal into a sixth pulse signal.

[0015] The second pulse sensing module is electrically connected to the active control module. The second pulse sensing module enters a second working state in response to the control signal and generates a seventh pulse signal according to the sixth pulse signal. The seventh pulse signal has the target high voltage.

[0016] The latch output module is electrically connected to the active control module, the first pulse sensing module, and the second pulse sensing module. The latch output module generates a target pulse signal based on the fourth pulse signal and the seventh pulse signal. When the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the latch output module sends a feedback signal to the active control module, the first pulse sensing module, and the second pulse sensing module. In response to the feedback signal, the active control module inverts the level of the control signal. In response to the feedback signal and the control signal, the first pulse sensing module enters a third working state, and the second pulse sensing module enters a fourth working state, so that the voltage of the fourth pulse signal and the seventh pulse signal are both less than or equal to the target high voltage.

[0017] In some embodiments, the latch output module includes: a switch latch submodule, a first noise isolation submodule, a second noise isolation submodule, a third noise isolation submodule, and a reverse latch submodule;

[0018] The switch latching submodule is electrically connected to the first pulse sensing module, the second pulse sensing module, and the first noise isolation submodule;

[0019] The second noise isolation submodule is electrically connected to the switch latch submodule, the active control module, the first pulse sensing module, and the second pulse sensing module;

[0020] The third noise isolation submodule is electrically connected to the switch latch submodule and the first noise isolation submodule. When the fourth pulse signal is the target high voltage and the seventh pulse signal is the target high voltage, the third noise isolation submodule outputs a shutdown signal. The first noise isolation submodule responds to the shutdown signal and switches to a shutdown state, thereby disconnecting the first noise isolation submodule from the reverse latch submodule.

[0021] The reverse latch submodule is used to clamp the voltages of the fourth pulse signal and the seventh pulse signal, and to reverse the fourth pulse signal and the seventh pulse signal to obtain the target pulse signal.

[0022] In some embodiments, the active control module includes a first MOSFET, a second MOSFET, and a first NOT gate, and the second noise isolation submodule has a feedback signal terminal;

[0023] The source of the first MOSFET is electrically connected to the source of the second MOSFET;

[0024] The drain of the first MOSFET is electrically connected to the input terminal of the first NOT gate and the drain of the second MOSFET, the gate of the first MOSFET is electrically connected to the feedback signal terminal, and the output terminal of the first NOT gate outputs the control signal.

[0025] When the feedback signal is at a first level, the first MOS transistor is turned on to change the control signal to a second level; wherein the first level is greater than the second level.

[0026] In some embodiments, the first pulse sensing module includes a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET; the fourth pulse signal also has a target low voltage.

[0027] The gate of the third MOS transistor is electrically connected to the output of the first NOT gate; when the control signal is at the second level, the third MOS transistor is turned off.

[0028] The gate of the fifth MOS transistor is electrically connected to the feedback signal terminal; when the feedback signal is at the first level, the fifth MOS transistor is turned on so that the voltage of the fourth pulse signal becomes the target low voltage;

[0029] The drains of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor are electrically connected to each other.

[0030] The drain of the sixth MOS transistor is electrically connected to the drain of the seventh MOS transistor.

[0031] In some embodiments, the second pulse sensing module includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, and a twelfth MOSFET; the seventh pulse signal also has the target low voltage;

[0032] The gate of the eighth MOS transistor is electrically connected to the output terminal of the first NOT gate; when the control signal is low, the eighth MOS transistor is turned off.

[0033] The gate of the tenth MOS transistor is electrically connected to the feedback signal terminal; when the feedback signal is high, the tenth MOS transistor is turned on so that the voltage of the seventh pulse signal becomes the target low voltage.

[0034] The drains of the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor are electrically connected to each other.

[0035] The drain of the eleventh MOS transistor is electrically connected to the drain of the twelfth MOS transistor.

[0036] In some embodiments, the switch latch submodule includes: a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, and a twentieth MOS transistor.

[0037] In some embodiments, the first noise isolation submodule includes a first transmission gate and a second transmission gate, the second noise isolation submodule includes a NAND gate and a first buffer, and the third noise isolation submodule includes an XNOR gate and a second NOT gate.

[0038] In some embodiments, the reverse latch submodule includes a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a seventh NOT gate;

[0039] The input terminals of the fourth NOT gate, the fifth NOT gate, and the sixth NOT gate are electrically connected to each other; the output terminal of the fifth NOT gate, the input terminal of the sixth NOT gate, and the input terminal of the seventh NOT gate are electrically connected to each other; wherein, the fifth NOT gate and the sixth NOT gate are used to clamp the voltages of the fourth pulse signal and the seventh pulse signal; the fourth NOT gate is used to invert the fourth pulse signal, and the seventh NOT gate is used to invert the seventh pulse signal to obtain the target pulse signal.

[0040] To achieve the above objectives, a second aspect of this application provides a high-voltage half-bridge driver, including the level shifter, dead-time generation module, first voltage buffer module, second voltage buffer module, first high-voltage switch module, second high-voltage switch module, and driver bootstrap module described in the first aspect.

[0041] The dead zone generation module is electrically connected to the level shifter and the second voltage buffer module. The level shifter is electrically connected to the first voltage buffer module. The first voltage buffer module is electrically connected to the driver bootstrap module and the first high voltage switch module. The second voltage buffer module is electrically connected to the second high voltage switch module. The first high voltage switch module is electrically connected to the second high voltage switch module.

[0042] The dead-time generation module is used to generate the first initial pulse signal and the second initial pulse signal according to the clock pulse signal; wherein the time difference between the first initial pulse signal and the second initial pulse signal is a preset dead-time.

[0043] The first high-voltage switch module enters a closed or open state in response to the target pulse signal, and the second high-voltage switch module enters a closed or open state in response to the second initial pulse signal.

[0044] In some embodiments, the driver bootstrap module includes a bootstrap driving diode and a bootstrap driving capacitor, wherein the bootstrap driving diode is electrically connected to the bootstrap driving capacitor, and the bootstrap driving capacitor is electrically connected to the first high-voltage switching module and the second high-voltage switching module.

[0045] This application proposes a level shifter and a high-voltage half-bridge driver. The level shifter converts a first initial pulse signal in the low-voltage region into a target pulse signal in the high-voltage region, thus realizing the level conversion function. A first capacitor driving module receives the first initial pulse signal and shortens its rise time to obtain the first pulse signal, thereby improving the signal level conversion speed and reducing the signal transmission delay of the level shifter. Through a bootstrap capacitor module, a first isolation capacitor module, and a second isolation capacitor module, the characteristic of high-voltage capacitors to isolate the DC component of the circuit is utilized to isolate the low-voltage region and the high-voltage region of the level shifter. This ensures that current exists only in the high-voltage region and the low-voltage region, avoiding current flow between the low-voltage and high-voltage regions and reducing circuit power consumption. When the voltages of the fourth and seventh pulse signals are both greater than the target high voltage, the latch output module sends a feedback signal to the active control module, the first pulse sensing module, and the second pulse sensing module. Since the first pulse sensing module generates the fourth pulse signal and the second pulse sensing module generates the seventh pulse signal, the circuit states of the first and second pulse sensing modules can be changed through the feedback signal. Specifically, the active control module inverts the level of the control signal in response to the feedback signal, the first pulse sensing module enters a third operating state in response to the feedback signal and the control signal, and the second pulse sensing module enters a fourth operating state in response to the feedback signal and the control signal, so that the voltages of the fourth pulse signal and the seventh pulse signal are both less than or equal to the target high voltage. It is evident that the embodiments of this application can quickly perform level switching, reduce voltage when transient voltage changes occur in the circuit to avoid circuit damage, and use capacitors to isolate the high-voltage region and the low-voltage region to reduce power consumption. In summary, the level shifter of this application can reduce signal transmission delay, reduce power consumption, and improve reliability. Attached Figure Description

[0046] Figure 1 This is a block diagram of a level shifter provided in an embodiment of this application;

[0047] Figure 2 yes Figure 1 Block diagram of the latch output module in the image;

[0048] Figures 3A to 3C This is a circuit schematic diagram of a level shifter provided in one embodiment of this application;

[0049] Figure 4This is a block diagram of the high-voltage half-bridge driver provided in the embodiments of this application.

[0050] Figure 5 This is a circuit schematic diagram of the module block diagram provided in the embodiments of this application. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0052] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0054] The level shifter and high-voltage half-bridge driver provided in this application are specifically described through the following embodiments. First, the level shifter in this application embodiment is described.

[0055] Figure 1 This is an optional module block diagram of a level shifter provided in an embodiment of this application. The level shifter 1 includes: a first capacitor driving module 11, an input logic edge detection module 12, a bootstrap capacitor module 13, an active control module 14, a first isolation capacitor module 15, a second capacitor driving module 16, a second isolation capacitor module 17, a first pulse sensing module 18, a second pulse sensing module 19, and a latch output module 110;

[0056] The first capacitor driving module 11 receives the first initial pulse signal and shortens the rise time of the first initial pulse signal to obtain the first pulse signal, which has an initial low voltage and an initial high voltage.

[0057] The input logic edge detection module 12 is electrically connected to the first capacitor driving module 11. The input logic edge detection module 12 is used to output a second pulse signal when the first pulse signal jumps from the initial low voltage to the initial high voltage.

[0058] The bootstrap capacitor module 13 is electrically connected to the input logic edge detection module 12 and the active control module 14. The active control module 14 generates a control signal based on the second pulse signal.

[0059] The first isolation capacitor module 15 is electrically connected to the first capacitor driving module 11 and the first pulse sensing module 18. The first isolation capacitor module 15 is used to convert the first pulse signal into a third pulse signal.

[0060] The first pulse sensing module 18 is electrically connected to the active control module 14. The first pulse sensing module 18 enters a first working state in response to the control signal and generates a fourth pulse signal based on the third pulse signal. The fourth pulse signal has a target high voltage; wherein the target high voltage is greater than the initial high voltage.

[0061] The second capacitor driving module 16 inverts the first pulse signal to obtain the fifth pulse signal;

[0062] The second isolation capacitor module 17 is electrically connected to the second capacitor drive module 16 and the second pulse sensing module 19. The second isolation capacitor module 17 is used to convert the fifth pulse signal into the sixth pulse signal.

[0063] The second pulse sensing module 19 is electrically connected to the active control module 14. The second pulse sensing module 19 enters the second working state in response to the control signal and generates a seventh pulse signal according to the sixth pulse signal. The seventh pulse signal has a target high voltage.

[0064] The latch output module 110 is electrically connected to the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19. The latch output module 110 generates a target pulse signal based on the fourth pulse signal and the seventh pulse signal. When the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the latch output module 110 sends a feedback signal to the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19. The active control module 14 reverses the level of the control signal in response to the feedback signal. The first pulse sensing module 18 enters the third working state in response to the feedback signal and the control signal. The second pulse sensing module 19 enters the fourth working state in response to the feedback signal and the control signal, so that the voltage of the fourth pulse signal and the seventh pulse signal are both less than or equal to the target high voltage.

[0065] The beneficial effects of this application embodiment include, but are not limited to: the first capacitor driving module 11 receives the first initial pulse signal and shortens the rise time of the first initial pulse signal to obtain the first pulse signal, thereby improving the signal level conversion speed and reducing the signal transmission delay of the level shifter. Through the bootstrap capacitor module 13, the first isolation capacitor module 15, and the second isolation capacitor module 17, the characteristic of high-voltage capacitors to isolate the DC component of the circuit is utilized to isolate the low-voltage region and the high-voltage region of the level shifter, thereby ensuring that current exists only in the high-voltage region and the low-voltage region, avoiding current between the low-voltage region and the high-voltage region of the level shifter, and reducing circuit power consumption. When the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the latch output module 110 sends a feedback signal to the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19. Since the first pulse sensing module 18 generates the fourth pulse signal and the second pulse sensing module 19 generates the seventh pulse signal, the circuit states of the first pulse sensing module 18 and the second pulse sensing module 19 can be changed through the feedback signal. Specifically, the active control module 14 inverts the level of the control signal in response to the feedback signal, the first pulse sensing module 18 enters the third operating state in response to the feedback signal and the control signal, and the second pulse sensing module 19 enters the fourth operating state in response to the feedback signal and the control signal, so that the voltages of the fourth pulse signal and the seventh pulse signal are both less than or equal to the target high voltage. It is evident that the embodiments of this application can quickly perform level switching, reduce voltage when transient voltage changes occur in the circuit to avoid circuit damage, and use capacitors to isolate the high-voltage region and the low-voltage region to reduce power consumption. In summary, the level shifter of this application can reduce signal transmission delay, reduce power consumption, and improve reliability.

[0066] It should be noted that the level shifter converts the initial pulse signal in the low-voltage region into the target pulse signal in the high-voltage region. The first capacitor drive module 11, the input logic edge detection module 12, and the second capacitor drive module 16 operate in the low-voltage region, while the active control module 14, the first pulse sensing module 18, the second pulse sensing module 19, and the latch output module 110 operate in the high-voltage region. The bootstrap capacitor module 13, the first isolation capacitor module 15, and the second isolation capacitor module 17 isolate the low-voltage region and the high-voltage region of the level shifter 1, thereby avoiding direct coupling between the low-voltage region and the high-voltage region, reducing circuit power consumption, and improving the conversion efficiency of the level shifter.

[0067] It should be noted that the first capacitor driving module 11 shortens the rise time of the first initial pulse signal, thereby increasing the speed of pulse signal level change, avoiding the situation where the input logic edge detection submodule cannot detect the pulse signal, and reducing the transmission delay of the level shifter. The rise time of the first initial pulse signal refers to the interval between two instants when the instantaneous value of the first initial pulse signal reaches a specified upper limit from a specified lower limit. The specified lower limit and the specified upper limit are set to 10% and 90% of the peak amplitude (i.e., the initial high voltage) of the first initial pulse signal, respectively.

[0068] It should be noted that, in some embodiments, the first pulse signal and the first initial pulse signal have the same waveform phase, and the first pulse signal has a single rising edge. Specifically, the rising edge refers to the moment when the pulse signal transitions from a low level to a high level.

[0069] It should be noted that in some embodiments, the waveform of the seventh pulse signal is the same as that of the fourth pulse signal, but the phases are opposite.

[0070] Please see Figure 1 and Figure 2 In some embodiments, the latch output module 110 includes: a switch latch submodule 1101, a first noise isolation submodule 1102, a second noise isolation submodule 1103, a third noise isolation submodule 1104, and a reverse latch submodule 1105;

[0071] The switch latching submodule 1101 is electrically connected to the first pulse sensing module 18, the second pulse sensing module 19 and the first noise isolation submodule 1102;

[0072] The second noise isolation submodule 1103 is electrically connected to the switch latching submodule 1101, the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19;

[0073] The third noise isolation submodule 1104 is electrically connected to the switch latch submodule 1101 and the first noise isolation submodule 1102. When the fourth pulse signal is the target high voltage and the seventh pulse signal is the target high voltage, the third noise isolation submodule 1104 outputs a shutdown signal. The first noise isolation submodule 1102 responds to the shutdown signal and switches to the shutdown state, so that the first noise isolation submodule 1102 is disconnected from the reverse latch submodule 1105.

[0074] The reverse latch submodule 1105 is used to clamp the voltages of the fourth pulse signal and the seventh pulse signal, and to reverse the fourth pulse signal and the seventh pulse signal to obtain the target pulse signal.

[0075] The advantage of this embodiment is that it improves the reliability and stability of the level shifter. Specifically, if the switch rapidly switches between on and off states, transient voltage changes often occur in the high-voltage region of the level shifter, resulting in common-mode noise and potentially causing circuit overvoltage. In this embodiment, the second noise isolation submodule 1103 sends feedback signals to the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19 when both the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are greater than the target high voltage. The active control module 14 inverts the level of the control signal in response to the feedback signal, the first pulse sensing module 18 enters a third operating state in response to the feedback signal and the control signal, and the second pulse sensing module 19 enters a fourth operating state in response to the feedback signal and the control signal, so that the voltages of the fourth and seventh pulse signals are both less than or equal to the target high voltage. Furthermore, the reverse latch submodule 1105 clamps the voltages of the fourth and seventh pulse signals. Therefore, this embodiment can reduce the voltage when a transient high voltage occurs in the high-voltage region of the level shifter, thereby preventing circuit damage. Furthermore, the third noise isolation submodule 1104 outputs a shutdown signal when both the fourth and seventh pulse signals are at the target high voltage. The first noise isolation submodule 1102 responds to the shutdown signal and switches to a shutdown state, thus disconnecting from the reverse latch submodule 1105, thereby isolating common-mode noise and preventing the reverse latch submodule 1105 from outputting a target pulse signal interfered with by common-mode noise. In summary, the embodiments of this application can prevent the level shifter from generating erroneous logic control signals due to common-mode noise and avoid circuit damage caused by excessive voltage, thereby improving the reliability and stability of the level shifter.

[0076] It should be noted that when the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the second noise isolation submodule 1103 sends a feedback signal to the active control module 14, the first pulse sensing module 18 and the second pulse sensing module 19.

[0077] It should be noted that the reverse latch submodule 1105 clamps the voltages of the fourth and seventh pulse signals, thereby limiting the voltage to a preset safe voltage value. For example, the preset safe voltage value can be the operating voltage of the circuit elements in the reverse latch submodule 1105.

[0078] Please see Figure 1 , Figure 2 , Figure 3A , 3B In some embodiments, the active control module 14 includes a first MOS transistor M1, a second MOS transistor M2 and a first NOT gate, and the second noise isolation submodule 1103 has a feedback signal terminal.

[0079] The source of the first MOSFET M1 is electrically connected to the source of the second MOSFET M2;

[0080] The drain of the first MOSFET M1 is electrically connected to the input terminal of the first NOT gate NOT1 and the drain of the second MOSFET M2. The gate of the first MOSFET M1 is electrically connected to the feedback signal terminal. The output terminal of the first NOT gate NOT1 outputs the control signal.

[0081] When the feedback signal is at the first level, the first MOSFET M1 is turned on to change the control signal to the second level; wherein, the first level is greater than the second level.

[0082] The advantage of this embodiment is that the active control module 14 generates a control signal based on the second pulse signal generated by the input logic edge detection module 12, thereby adjusting the pulse width of the control signal and influencing the pulse widths of the fourth and seventh pulse signals input to the latch output module through the control signal. Furthermore, when the voltages of the fourth and seventh pulse signals are both greater than the target high voltage, the latch output module 110 sends feedback signals to the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19, respectively. In response to the feedback signal, the active control module 14 inverts the level of the control signal; the first pulse sensing module 18 enters a third operating state in response to the feedback signal and the control signal; and the second pulse sensing module 19 enters a fourth operating state in response to the feedback signal and the control signal, so that the voltages of the fourth and seventh pulse signals are both less than or equal to the target high voltage. In summary, the active control module 14, influenced by the feedback signal, changes the control signal to stabilize the voltages of the fourth and seventh pulse signals at the target high voltage, preventing circuit damage due to excessive voltage and improving the reliability and stability of the level shifter. Furthermore, the active control module 14 can also influence the pulse width of the fourth and seventh pulse signals, thereby further reducing circuit power consumption.

[0083] It should be noted that in some embodiments, the source voltage of the first MOSFET M1 is the target low voltage. If common-mode noise exists in the circuit, the feedback signal is high, and the first MOSFET M1 turns on in response to the feedback signal, so that the first MOSFET M1 and the first NOT gate NOT1 form a path, thereby changing the voltage of the control signal output by the first NOT gate NOT1 to the target low voltage.

[0084] Specifically, the first level refers to a high level, and the second level refers to a low level.

[0085] It should be noted that, Figure 3A , Figure 3B and Figure 3CIn this diagram, Vin refers to the first pulse signal. Vsense refers to the feedback signal output from the feedback signal terminal; the ports identified by the feedback signals are interconnected. Vctr l refers to the control signal; the ports identified by the control signals are interconnected. Furthermore, Vboot is the voltage provided by one port of the external power supply (not shown in the diagram), and Vsw is the voltage provided by the other port of the external power supply. Here, Vsw represents the target low voltage, and Vboot represents the target high voltage.

[0086] Please see Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C In some embodiments, the first pulse sensing module 18 includes a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, and a seventh MOSFET M7; the fourth pulse signal also has a target low voltage.

[0087] The gate of the third MOSFET M3 is electrically connected to the output of the first NOT gate; when the control signal is at the second level, the third MOSFET M3 is turned off.

[0088] The gate of the fifth MOSFET M5 is electrically connected to the feedback signal terminal; when the feedback signal is at the first level, the fifth MOSFET M5 is turned on so that the voltage of the fourth pulse signal becomes the target low voltage;

[0089] The drains of the third MOSFET M3, the drains of the fourth MOSFET M4, the drains of the fifth MOSFET M5, the gates of the sixth MOSFET M6 and the gates of the seventh MOSFET M7 are electrically connected to each other.

[0090] The drain of the sixth MOSFET M6 is electrically connected to the drain of the seventh MOSFET M7.

[0091] The advantage of this embodiment is that the first pulse sensing module 18 enters the first working state in response to the control signal and generates a fourth pulse signal according to the third pulse signal. The fourth pulse signal has a target high voltage, thereby converting the first pulse signal in the low-voltage region into the fourth pulse signal in the high-voltage region. Furthermore, when the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the latch output module 110 sends a feedback signal to the active control module 14, the first pulse sensing module 18, and the second pulse sensing module 19. The first pulse sensing module 18 enters the third working state in response to the feedback signal and the control signal, so that the voltage of the fourth pulse signal is less than or equal to the target high voltage, thereby avoiding circuit damage caused by excessive voltage and improving the reliability and stability of the level shifter.

[0092] It should be noted that, in Figure 3A , Figure 3B and Figure 3C In a circuit, there are multiple circuit nodes, including: first connection point A, second connection point B, third connection point C, fourth connection point D, fifth connection point E, sixth connection point F, seventh connection point G, eighth connection point H, ninth connection point J, and tenth connection point K. Specifically, a circuit node is a connection point in a circuit; the point where three or more branches converge is called a node. A high-impedance node indicates that a particular circuit node has a relatively higher impedance than other circuit points.

[0093] It should be noted that the drains of the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the gate of the sixth MOSFET M6, and the gate of the seventh MOSFET M7 are electrically connected to each other to form the first connection point A. The drain of the sixth MOSFET M6 is electrically connected to the drain of the seventh MOSFET M7 to form the second connection point B.

[0094] It should be noted that in some embodiments, the control signal is low, and the third MOSFET M3 turns off in response to the control signal, resulting in a high-impedance node at the first connection point A. Simultaneously, the first isolation capacitor module 15 charges, causing the voltage at the first connection point A to rise. The sixth MOSFET M6 turns on, and the third pulse signal passes through the first connection point A and the sixth MOSFET M6 to generate the fourth pulse signal. The sixth MOSFET M6 and the seventh MOSFET M7 form a push-pull circuit, and the sixth MOSFET M6 is used to shape the pulse signal to make its waveform more stable.

[0095] It should be noted that, in some embodiments, the first pulse sensing module 18 entering the first operating state means that the third MOSFET M3, the fourth MOSFET M4, and the fifth MOSFET M5 are turned off. The first pulse sensing module 18 entering the third operating state means that the third MOSFET M3, the fourth MOSFET M4, and the fifth MOSFET M5 are turned on.

[0096] Please see Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C In some embodiments, the second pulse sensing module 19 includes an eighth MOSFET M8, a ninth MOSFET M9, a tenth MOSFET M10, an eleventh MOSFET M11, and a twelfth MOSFET M12; the seventh pulse signal also has a target low voltage;

[0097] The gate of the eighth MOSFET M8 is electrically connected to the output of the first NOT gate; when the control signal is low, the eighth MOSFET M8 is turned off.

[0098] The gate of the tenth MOSFET M10 is electrically connected to the feedback signal terminal; when the feedback signal is high, the tenth MOSFET M10 is turned on so that the voltage of the seventh pulse signal becomes the target low voltage.

[0099] The drain of the eighth MOSFET M8, the drain of the ninth MOSFET M9, the drain of the tenth MOSFET M10, the gate of the eleventh MOSFET M11, and the gate of the twelfth MOSFET M12 are electrically connected to each other.

[0100] The drain of the eleventh MOSFET M11 is electrically connected to the drain of the twelfth MOSFET M12.

[0101] The advantage of this embodiment is that the second pulse sensing module 19 enters the second working state in response to the control signal and generates a seventh pulse signal based on the sixth pulse signal, the seventh pulse signal having a target high voltage; when the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the latch output module 110 sends a feedback signal to the active control module 14, the first pulse sensing module 18 and the second pulse sensing module 19; wherein, the second pulse sensing module 19 enters the fourth working state in response to the feedback signal and the control signal, so that the voltage of the seventh pulse signal is less than or equal to the target high voltage.

[0102] It should be noted that the drains of the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the gate of the eleventh MOSFET M11, and the gate of the twelfth MOSFET M12 are electrically connected to each other to form the fifth connection point E. The drain of the eleventh MOSFET M11 is electrically connected to the drain of the twelfth MOSFET M12 to form the sixth connection point F.

[0103] It should be noted that in some embodiments, the control signal is low, and the eighth MOSFET M8 turns off in response to the control signal, resulting in a high-impedance node at the fifth connection point E. Simultaneously, the second isolation capacitor module 17 charges, causing the voltage at the fifth connection point E to rise. The eleventh MOSFET M11 turns on, and the sixth pulse signal passes through the fifth connection point E and the eleventh MOSFET M11 to generate the seventh pulse signal. The eleventh MOSFET M11 and the twelfth MOSFET M12 form a push-pull circuit, and the eleventh MOSFET M11 is used to shape the pulse signal to make its waveform more stable.

[0104] It should be noted that, in some embodiments, the second pulse sensing module 19 entering the second operating state means that the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are turned off. The second pulse sensing module 19 entering the fourth operating state means that the eighth MOSFET M8, the ninth MOSFET M9, and the tenth MOSFET M10 are turned on.

[0105] Please see Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C In some embodiments, the switch latch submodule 1101 includes: a thirteenth MOSFET M13, a fourteenth MOSFET M14, a fifteenth MOSFET M15, a sixteenth MOSFET M16, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a nineteenth MOSFET M19, and a twentieth MOSFET M20.

[0106] Specifically, the switch latch submodule 1101 is a current mirror circuit composed of the aforementioned MOS transistors. The advantage of this embodiment is that the switch latch submodule 1101 is used to suppress current fluctuations, stabilize the current in the circuit, and improve the reliability and stability of the level shifter.

[0107] It should be noted that the gates of the thirteenth MOSFET M13 and the fourteenth MOSFET M14 are electrically connected to each other and connected to the second connection point B. The gates of the fifteenth MOSFET M15 and the sixteenth MOSFET M16 are electrically connected to each other and connected to the sixth connection point F. The drains of the thirteenth MOSFET M13, the drains of the seventeenth MOSFET M17, the gates of the seventeenth MOSFET M17 and the gates of the eighteenth MOSFET M18 are electrically connected to each other to form the third connection point C. The drain of the fifteenth MOSFET M15 is electrically connected to the drain of the eighteenth MOSFET M18 to form the fourth connection point D. The drains of the sixteenth MOSFET M16, the gates of the nineteenth MOSFET M19, the gates of the twentieth MOSFET M20 and the drain of the twentieth MOSFET M20 are electrically connected to each other to form the seventh connection point G. The drain of the fourteenth MOSFET M14 is electrically connected to the drain of the nineteenth MOSFET M19 to form the eighth connection point H.

[0108] Please see Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C In some embodiments, the first noise isolation submodule 1102 includes a first transmission gate TG1 and a second transmission gate TG2, the second noise isolation submodule 1103 includes a NAND gate NAND1 and a first buffer BUF1, and the third noise isolation submodule 1104 includes an XNOR gate XNOR1 and a second NOT gate NOT2.

[0109] The advantage of this embodiment is that the third noise isolation submodule 1104 outputs a shutdown signal when both the fourth and seventh pulse signals are at the target high voltage. The first noise isolation submodule 1102 responds to the shutdown signal and switches to a shutdown state, thereby disconnecting the first noise isolation submodule 1102 from the reverse latch submodule 1105, thus isolating common-mode noise and preventing the reverse latch submodule 1105 from outputting a target pulse signal that is interfered with by common-mode noise.

[0110] It should be noted that the output of the first buffer BUF1 is electrically connected to the input of the second buffer BUF2 and the first input of the XOR gate XOR1, and the output of the second buffer BUF2 is electrically connected to the second input of the XOR gate XOR1. The input of the first transmission gate TG1 is electrically connected to the fourth connection point D, and the output of the first transmission gate TG1 is electrically connected to the ninth connection point J. The input of the second transmission gate TG2 is electrically connected to the eighth connection point H, and the output of the second transmission gate TG2 is electrically connected to the tenth connection point K. The first input of the NAND gate NAND1 is electrically connected to the second connection point B, the second input of the NAND gate NAND1 is electrically connected to the sixth connection point F, and the output of the NAND gate NAND1 is electrically connected to the input of the third buffer BUF3. The input of the third buffer BUF3 outputs a feedback signal. The first input of the XNOR gate XNOR1 is electrically connected to the second connection point B, and the second input is electrically connected to the sixth connection point F. The output of the XNOR gate XNOR1 is electrically connected to the input of the third NOT gate NOT3, the inverting control terminal of the first transmission gate TG1, and the inverting control terminal of the second transmission gate TG2. The output of the seventh NOT gate NOT7 is electrically connected to the positive control terminal of the first transmission gate TG1 and the positive control terminal of the second transmission gate TG2. The positive control terminals of the first and second transmission gates TG1 and TG2 refer to the ports for obtaining Vgn, and the inverting control terminals of the first and second transmission gates TG2 refer to the ports for obtaining Vgp.

[0111] It should be noted that the shutdown signal includes a first shutdown signal and a second shutdown signal, with the first shutdown signal being the inverted version of the second shutdown signal. Figure 3A and Figure 3C In this context, Vgn refers to the first turn-off signal, and Vgp refers to the second turn-off signal. Specifically, Vgn (the lead voltage of the input signal, Voltage Gate Neutral, abbreviated as VGN) is also called the turn-on voltage or gate voltage.

[0112] It should be noted that the first capacitor driving module 11 is the second buffer BUF2, the second capacitor driving module 16 is the third NOT gate, and the input logic edge detection module 12 includes the third buffer BUF3 and the XOR gate XOR1.

[0113] Please see Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 3C In some embodiments, the reverse latch submodule 1105 includes a fourth NOT gate NOT4, a fifth NOT gate NOT5, a sixth NOT gate NOT6, and a seventh NOT gate NOT7;

[0114] The inputs of NOT4, NOT5, and NOT6 are electrically connected; the outputs of NOT5, NOT6, and NOT7 are electrically connected. NOT5 and NOT6 are used to clamp the voltages of the fourth and seventh pulse signals. NOT4 inverts the fourth pulse signal, and NOT7 inverts the seventh pulse signal to obtain the target pulse signal.

[0115] The advantage of this embodiment is that, in the inverted latch submodule 1105, the fifth NOT gate NOT5 and the sixth NOT gate NOT6 are used to clamp the voltages of the fourth pulse signal and the seventh pulse signal, the fourth NOT gate NOT4 is used to invert the fourth pulse signal, and the seventh NOT gate NOT7 is used to invert the seventh pulse signal, thereby obtaining the target pulse signal.

[0116] It should be noted that, in Figure 3A In this context, Vout+ and Vout- refer to the positive and negative terminals of the output of the reverse latch submodule 1105, respectively, both used to output the target pulse signal.

[0117] It should be noted that the inputs of the fourth NOT gate (NOT4), the fifth NOT gate (NOT5), and the sixth NOT gate (NOT6) are electrically connected to form the ninth connection point J. The output of the fifth NOT gate (NOT5), the input of the sixth NOT gate (NOT6), and the input of the seventh NOT gate (NOT7) are electrically connected to form the tenth connection point K.

[0118] Please see Figure 4 This application embodiment also provides a high-voltage half-bridge driver, which includes the above-mentioned level shifter 1, dead-time generation module 2, first voltage buffer module 3, second voltage buffer module 4, first high-voltage switch module 5, second high-voltage switch module 6, and driver bootstrap module 7.

[0119] Dead zone generation module 2 is electrically connected to level shifter 1 and second voltage buffer module 4. Level shifter 1 is electrically connected to first voltage buffer module 3. First voltage buffer module 3 is electrically connected to driver bootstrap module 7 and first high voltage switch module 5. Second voltage buffer module 4 is electrically connected to second high voltage switch module 6. First high voltage switch module 5 is electrically connected to second high voltage switch module 6.

[0120] The dead-time generation module 2 is used to generate a first initial pulse signal and a second initial pulse signal based on the clock pulse signal; wherein the time difference between the first initial pulse signal and the second initial pulse signal is a preset dead-time.

[0121] The first high-voltage switch module 5 enters the off state or the on state in response to the target pulse signal, and the second high-voltage switch module 6 enters the off state or the on state in response to the second initial pulse signal.

[0122] The advantage of this embodiment is that the level shifter 1 performs level conversion based on the first initial pulse signal to generate the target pulse signal, and the first high-voltage switch module 5 responds to the target pulse signal switching state. The second high-voltage switch module 6 responds to the second initial pulse signal switching state. This embodiment of the application uses the above-described level shifter, which can reduce the signal transmission delay and power consumption of the high-voltage half-bridge driver and improve reliability.

[0123] It should be noted that the dead time can prevent the first high-voltage switch module 5 and the second high-voltage switch module 6 from being turned on at the same time, thereby avoiding the occurrence of current short circuit.

[0124] Specifically, a high-voltage switch refers to an integrated high-voltage LDMOS power device available in high-voltage, high-power BCD semiconductor processes (e.g., 0.18μm BCD process, 0.5μm BCD process, etc.). In some embodiments, the voltage range of the high-voltage switch can be 10V to 120V. It should be noted that BCD stands for Bipolar-CMOS-DMOS process technology, a technology that simultaneously integrates bipolar transistors, complementary metal-oxide-semiconductor (CMOS) and double-diffused metal-oxide-semiconductor (DMOS) transistors on a single chip. It should also be noted that LDMOS refers to Laterally Diffused Metal-Oxide Semiconductor (LDMOS). LDMOS is commonly used in the fabrication of radio frequency power amplifiers.

[0125] Please see Figure 4 and Figure 5In one embodiment, the driver bootstrap module 7 includes a bootstrap driving diode Db and a bootstrap driving capacitor Cb. The bootstrap driving diode Db is electrically connected to the bootstrap driving capacitor Cb, and the bootstrap driving capacitor Cb is electrically connected to the first high-voltage switching module 5 and the second high-voltage switching module 6.

[0126] It should be noted that CLK refers to the clock pulse signal. Vss l refers to the initial low voltage of the first pulse signal, and Vdd l refers to the initial high voltage of the first pulse signal. The first voltage buffer module 3 is the first voltage buffer Buffer_1, and the second voltage buffer module 4 is the second voltage buffer Buffer_2. The first high-voltage switch module 5 is the first high-voltage switch M_H, and the second high-voltage switch module 6 is the second high-voltage switch M_L.

[0127] Specifically, in some embodiments, when the level shifter performs level conversion, the bootstrap capacitor module 13, the first isolation capacitor module 15, and the second isolation capacitor module 17 are used to isolate the DC component in the circuit, so that the current exists only in the high-voltage region and the low-voltage region. That is, the current in the high-voltage region flows from Vboot to Vsw, and the current in the low-voltage region flows from Vddl to Vssl. Therefore, there is no current flowing directly from the high-voltage region to the low-voltage region in the level shifter, thereby reducing the power consumption of the level shifter and further reducing the power consumption of the high-voltage half-bridge driver.

[0128] The specific embodiment of the level shifter in this high-voltage half-bridge driver is basically the same as the specific embodiment of the level shifter described above, and will not be repeated here.

[0129] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0130] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0131] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0132] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0133] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0134] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, or indirect coupling or communication connection between the apparatus or units, and may be electrical, mechanical, or other forms.

[0135] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0136] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0137] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A level shifter, characterized in that, The level shifter includes: a first capacitor driving module, an input logic edge detection module, a bootstrap capacitor module, an active control module, a first isolation capacitor module, a second capacitor driving module, a second isolation capacitor module, a first pulse sensing module, a second pulse sensing module, and a latch output module; The first capacitor driving module receives the first initial pulse signal and shortens the rise time of the first initial pulse signal to obtain the first pulse signal, which has an initial low voltage and an initial high voltage. The input logic edge detection module is electrically connected to the first capacitor driving module, and the input logic edge detection module is used to output a second pulse signal when the first pulse signal jumps from the initial low voltage to the initial high voltage; The bootstrap capacitor module is electrically connected to the input logic edge detection module and the active control module, and the active control module generates a control signal based on the second pulse signal; The first isolation capacitor module is electrically connected to the first capacitor driving module and the first pulse sensing module. The first isolation capacitor module is used to convert the first pulse signal into a third pulse signal. The first pulse sensing module is electrically connected to the active control module. The first pulse sensing module enters a first working state in response to the control signal and generates a fourth pulse signal based on the third pulse signal. The fourth pulse signal has a target high voltage; wherein the target high voltage is greater than the initial high voltage. The second capacitor driving module inverts the first pulse signal to obtain the fifth pulse signal; The second isolation capacitor module is electrically connected to the second capacitor driving module and the second pulse sensing module. The second isolation capacitor module is used to convert the fifth pulse signal into a sixth pulse signal. The second pulse sensing module is electrically connected to the active control module. The second pulse sensing module enters a second working state in response to the control signal and generates a seventh pulse signal according to the sixth pulse signal. The seventh pulse signal has the target high voltage. The latch output module is electrically connected to the active control module, the first pulse sensing module, and the second pulse sensing module. The latch output module generates a target pulse signal based on the fourth pulse signal and the seventh pulse signal. When the voltage of the fourth pulse signal and the voltage of the seventh pulse signal are both greater than the target high voltage, the latch output module sends a feedback signal to the active control module, the first pulse sensing module, and the second pulse sensing module. In response to the feedback signal, the active control module inverts the level of the control signal. In response to the feedback signal and the control signal, the first pulse sensing module enters a third working state, and the second pulse sensing module enters a fourth working state, so that the voltage of the fourth pulse signal and the seventh pulse signal are both less than or equal to the target high voltage.

2. The level shifter according to claim 1, characterized in that, The latch output module includes: a switch latch submodule, a first noise isolation submodule, a second noise isolation submodule, a third noise isolation submodule, and a reverse latch submodule; The switch latching submodule is electrically connected to the first pulse sensing module, the second pulse sensing module, and the first noise isolation submodule; The second noise isolation submodule is electrically connected to the switch latch submodule, the active control module, the first pulse sensing module, and the second pulse sensing module; The third noise isolation submodule is electrically connected to the switch latch submodule and the first noise isolation submodule. When the fourth pulse signal is the target high voltage and the seventh pulse signal is the target high voltage, the third noise isolation submodule outputs a shutdown signal. The first noise isolation submodule responds to the shutdown signal and switches to a shutdown state, thereby disconnecting the first noise isolation submodule from the reverse latch submodule. The reverse latch submodule is used to clamp the voltages of the fourth pulse signal and the seventh pulse signal, and to reverse the fourth pulse signal and the seventh pulse signal to obtain the target pulse signal.

3. The level shifter according to claim 2, characterized in that, The active control module includes a first MOSFET, a second MOSFET, and a first NOT gate; the second noise isolation submodule has a feedback signal terminal. The source of the first MOSFET is electrically connected to the source of the second MOSFET; the gate of the second MOSFET is electrically connected to an external power supply. The drain of the first MOSFET is electrically connected to the input terminal of the first NOT gate and the drain of the second MOSFET, the gate of the first MOSFET is electrically connected to the feedback signal terminal, and the output terminal of the first NOT gate outputs the control signal. When the feedback signal is at a first level, the first MOS transistor is turned on to change the control signal to a second level; wherein the first level is greater than the second level.

4. The level shifter according to claim 3, characterized in that, The first pulse sensing module includes a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET; the fourth pulse signal also has a target low voltage. The gate of the third MOS transistor is electrically connected to the output of the first NOT gate; when the control signal is at the second level, the third MOS transistor is turned off. The gate of the fifth MOS transistor is electrically connected to the feedback signal terminal; when the feedback signal is at the first level, the fifth MOS transistor is turned on so that the voltage of the fourth pulse signal becomes the target low voltage; The drains of the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the gate of the sixth MOS transistor, and the gate of the seventh MOS transistor are electrically connected to each other. The drain of the sixth MOS transistor is electrically connected to the drain of the seventh MOS transistor; The gate and source of the fourth MOS transistor, and the source of the seventh MOS transistor, are electrically connected to a port of an external power supply. The source of the third MOS transistor, the source of the fifth MOS transistor, and the source of the sixth MOS transistor are electrically connected to another port of the external power supply.

5. The level shifter according to claim 4, characterized in that, The second pulse sensing module includes an eighth MOSFET, a ninth MOSFET, a tenth MOSFET, an eleventh MOSFET, and a twelfth MOSFET; the seventh pulse signal also has the target low voltage; The gate of the eighth MOS transistor is electrically connected to the output terminal of the first NOT gate; when the control signal is low, the eighth MOS transistor is turned off. The gate of the tenth MOS transistor is electrically connected to the feedback signal terminal; when the feedback signal is high, the tenth MOS transistor is turned on so that the voltage of the seventh pulse signal becomes the target low voltage. The drains of the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the gate of the eleventh MOS transistor, and the gate of the twelfth MOS transistor are electrically connected to each other. The drain of the eleventh MOS transistor is electrically connected to the drain of the twelfth MOS transistor; The gate and source of the ninth MOS transistor and the source of the twelfth MOS transistor are electrically connected to a port of an external power supply. The source of the eighth MOS transistor, the source of the tenth MOS transistor, and the source of the eleventh MOS transistor are electrically connected to another port of the external power supply.

6. The level shifter according to claim 5, characterized in that, The switch latch submodule includes: the thirteenth MOS transistor, the fourteenth MOS transistor, the fifteenth MOS transistor, the sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, and the twentieth MOS transistor.

7. The level shifter according to claim 6, characterized in that, The first noise isolation submodule includes a first transmission gate and a second transmission gate, the second noise isolation submodule includes a NAND gate and a first buffer, and the third noise isolation submodule includes an XOR gate and a second NOT gate.

8. The level shifter according to claim 7, characterized in that, The reverse latch submodule includes a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, and a seventh NOT gate; The input terminals of the fourth NOT gate, the fifth NOT gate, and the sixth NOT gate are electrically connected to each other; the output terminal of the fifth NOT gate, the input terminal of the sixth NOT gate, and the input terminal of the seventh NOT gate are electrically connected to each other; wherein, the fifth NOT gate and the sixth NOT gate are used to clamp the voltages of the fourth pulse signal and the seventh pulse signal; the fourth NOT gate is used to invert the fourth pulse signal, and the seventh NOT gate is used to invert the seventh pulse signal to obtain the target pulse signal.

9. A high-voltage half-bridge driver, characterized in that, The high-voltage half-bridge driver includes a level shifter as described in any one of claims 1 to 8, a dead-time generation module, a first voltage buffer module, a second voltage buffer module, a first high-voltage switch module, a second high-voltage switch module, and a driver bootstrap module; The dead zone generation module is electrically connected to the level shifter and the second voltage buffer module. The level shifter is electrically connected to the first voltage buffer module. The first voltage buffer module is electrically connected to the driver bootstrap module and the first high voltage switch module. The second voltage buffer module is electrically connected to the second high voltage switch module. The first high voltage switch module is electrically connected to the second high voltage switch module. The dead-time generation module is used to generate the first initial pulse signal and the second initial pulse signal according to the clock pulse signal; wherein the time difference between the first initial pulse signal and the second initial pulse signal is a preset dead-time. The first high-voltage switch module enters a closed or open state in response to the target pulse signal, and the second high-voltage switch module enters a closed or open state in response to the second initial pulse signal.

10. The high-voltage half-bridge driver according to claim 9, characterized in that, The driver bootstrap module includes a bootstrap driving diode and a bootstrap driving capacitor. The bootstrap driving diode is electrically connected to the bootstrap driving capacitor, and the bootstrap driving capacitor is electrically connected to the first high-voltage switching module and the second high-voltage switching module.

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