Enhancing bonding in microelectronic structures by capturing contaminants and stopping cracks during direct bonding processes

Abstract

Structures and techniques can provide bond enhancement in microelectronic structures by capturing contaminants and byproducts during the bonding process and stopping cracks. Example bonding surfaces are provided with recesses, depressions, wells, or cavities to capture small particles and gaseous byproducts of bonding that would create harmful voids between the micron-scale surfaces being joined. Such random voids would compromise the integrity of the bond and the electrical conductivity of the bonded interconnect. In example systems, pre-designed recess spaces or pre-designed recess patterns placed in the bonding interface capture particles and gases, reducing the formation of random voids, improving and protecting the bond as it is formed. The recess spaces or recess patterns can be placed at locations where particles collect on the bonding surface by example methods for determining the location of moving particles during the propagation of a bond wave. For example, the recesses can be repeated in a wafer-level stepped serpentine pattern or placed by an aligner or alignment process.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims priority to U.S. Non-Provisional Patent No. 16 / 553,879 filed August 28, 2019 and U.S. Non-Provisional Patent No. 16 / 553,535 filed August 28, 2019 and U.S. Provisional Patent No. 62 / 724,270 to Gao et al. filed August 29, 2018, the entire contents of which are incorporated herein by reference.

[0003] Divisional Description

[0004] This application is a divisional application of Chinese Invention Patent Application No. 201980064165.6, filed August 29, 2019, entitled “ENHANCING BONDING IN MICROELECTRONIC STRUCTURES BY CAPTURING CONTAMINANTS AND HALTING CRACKS DURING DIRECT BONDING PROCESSES.” BACKGROUND

[0005] Figure 1 Conventional defects that occur when forming a bond during direct bonding processes used in microelectronic fabrication and packaging are shown. Non-bonding regions, referred to as bond voids or simply “voids,” can occur in the bond interface between the two surfaces being bonded, and these voids weaken the direct bond formed.

[0006] Direct bonding processes occur between two non-metallic, inorganic dielectric surfaces, or can occur between two surfaces that also have metal pads to be bonded together, such as for electrical interconnection. When metal features are also present in the bond interface, the bonding process can be referred to as direct hybrid bonding.

[0007] Harmful voids can occur in the bond interface due to the lack of a buffer region in the interface to give space for stray particles and other undesirable byproducts of the direct bonding process. Stray particles have nowhere to go but to lodge between the surfaces being connected, causing random voids in the bond. Some stray particles, foreign matter, and other defects create relatively large voids between the surfaces being bonded. In direct bonding interconnects In hybrid bonding processes (available from Invensas Bonding Technologies, Inc. (formerly Ziptronix, Inc., Xperi Corporation), San Jose, CA), these concerns are amplified because undesired voids of only a few hundred nanometers or even tens of nanometers in width can occur on the electrical leads. Such ultra-fine electrical leads often require high performance. For example, high bandwidth memories such as HBM2 memories can require signal speeds of up to 2.4 Gbps per pin, or even higher, and SerDes signaling can need to pass through the bonding interface at rates of, for example, 112 Gbps.

[0008] In Figure 1 When an undesired void 10 occurs in a conventional direct bonding interface 20, the given void 10 can intrude into the footprint (cross-sectional bonding area) 30 of the electrical interconnect being bonded, and the particle itself 40 can also intrude. The void 10 effectively insulates a portion of the cross-sectional footprint 30 of the interconnect so that, if bonded, that portion will not carry the electrical current it is intended to carry. The void 10 thus results in a compromised input-output (IO) connection, and overall assembly yield and / or reliability of the resulting device is significantly reduced.

[0009] Such voids 10 have been observed in direct bonding of silicon wafers with only a thin native oxide layer. Because crystalline silicon does not have enough defect sites to trap gaseous contaminants during the anneal step, gaseous byproducts can form voids. Similarly, when one of the surfaces to be bonded is silicon nitride, the nitride layer is impermeable to water vapor, hydrogen, and other reaction byproducts that escape by diffusion, resulting in voids 10 being formed during the anneal step. Low-quality oxide surfaces that contain residual ingredients from the oxide deposition process can also cause outgassing and subsequent voids 10 to form at the bonding interface. In addition to the gases released during the anneal step, particles and other contaminants on the surfaces prior to bonding (not removed in the cleaning process or even deposited after the cleaning process) also cause voids 10 to form.

[0010] Additionally, the edges of the surfaces 20 being bonded can have flaking 50, microcracks 60, and debris that occurs from dicing or sawing along the edges. These likewise form bonding voids 10, even if they do not interfere with electrical conduction of the interconnect, they can weaken the bond between the surfaces being bonded.

[0011] In microelectronic fabrication processes, the tendency for small particles 40 to form voids 10 during bonding is exacerbated by making the bonding surface super flat, typically after a planarization process such as chemical mechanical planarization (CMP). Because the bonding surface is so flat, small particles 40 (e.g., 1 micron in diameter) can cause bonding voids 10 that are 10 microns or more in diameter. SUMMARY

[0012] Structures and techniques enhance bonding in microelectronic structures by capturing contaminants and byproducts during the bonding process and stopping crack propagation. Example surfaces for direct bonding are provided with pre-designed recesses, depressions, wells, trenches, or cavities (hereinafter referred to as (recesses)) to capture small particles and gaseous byproducts of bonding that would create harmful voids between the micrometer-scale surfaces being joined. The recesses can also prevent cracks and fissures from propagating along the surface or across layers. Such random voids are harmful and can compromise the bonding integrity and electrical conductivity of the bonded interconnects.

[0013] In example systems, pre-designed recess spaces or pre-designed recess patterns placed in the bonding interface capture particles and gases, reducing the formation of harmful random voids, improving and protecting the bond as it is formed. The recess spaces or recess patterns are placed in locations where particles collect on the bonding surface by example methods for determining where loose particles move during a bonding wave propagation. For example, the recesses can be repeated in a wafer-level stepped scribe line pattern or placed by an aligner or alignment process. The recesses can be less than 10 nm and can be non- operational so that the particles or contaminants do not come into contact with operational components or circuitry.

[0014] This summary is neither intended nor should it be construed to identify key or essential features of the claimed subject matter nor to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF DRAWINGS

[0015] Certain embodiments of the disclosure will now be described with reference to the drawings. Throughout the drawings, like reference numerals will be used for like elements unless context dictates otherwise. The drawings shown herein are not meant to be actual representations of the various implementations described herein, and are intended to be merely illustrative of the various technologies described herein.

[0016] Figure 1 is a diagram of a conventional bonding void and its harmful effects on the bonding integrity and electrical performance of a directly bonded interconnect.

[0017] Figure 2 is a diagram showing various bonding and annealing schemes, showing how contaminants affect direct bonding and example recesses for capturing the contaminants.

[0018] Figure 3FIG. 1 is a diagram illustrating an example technique for mitigating undesirable voids (not shown) and improving bond strength and integrity in the manufacture of microelectronic packages.

[0019] Figure 4 FIG. 2 is a diagram of an example pattern and array of recesses provided in a bond surface.

[0020] Figure 5 FIG. 3 is a diagram illustrating particle movement during bond wave propagation and the placement of pre-designed surface recesses in the area of maximum particle distribution.

[0021] Figure 6 FIG. 4 is a diagram of an example bond surface having large non-bonding areas or recesses for capturing contaminants.

[0022] Figure 7 FIG. 5 is a diagram of an example bond surface with recesses added to the surface to stop bond void propagation.

[0023] Figure 8 FIG. 6 is a diagram of an example bond surface having large area non-bonding areas or recesses on both sides of a die or wafer used to manufacture a stacked structure.

[0024] Figure 9 FIG. 7 is a diagram of an example bond surface having large non-bonding areas or recesses for capturing contaminants and ribbed bonding areas for improving bond propagation and increasing the overall bond contact area between the bonding surfaces.

[0025] Figure 10 FIG. 8 is a diagram illustrating conductive traces in a large area recess and the resulting electrical benefits.

[0026] Figure 11 FIG. 9 is a diagram of a surface for direct hybrid bonding where the pads are recessed or indented to capture contaminants and protect bond integrity.

[0027] Figure 12 FIG. 10 is a flow diagram of an example method of enhancing bonding in microelectronic devices.

[0028] Figure 13 FIG. 11 is a flow diagram of an example method of enhancing bonding in microelectronic devices by determining the location of contaminants and capturing the contaminants.

[0029] Figure 14 FIG. 12 is a flow diagram of an example method of enhancing bonding in microelectronic devices by placing recesses on the bond surface to stop stress.

[0030] Figure 15 FIG. 13 is a flow diagram of an example method of constructing a large area recess around a direct bonding area to capture contaminants around the direct bonding area in a microelectronic device.

[0031] Figure 16 is a flowchart of an example method to improve the electrical properties of conductive traces by routing traces in large-area recesses.

[0032] Figure 17 is a flowchart of an example method to place recessed or indented pads at the bonding surface to collect contaminants and enhance bonding in microelectronic devices.

[0033] Figure 18 is a diagram of a conventional rough sidewall on a die and build layer, the conventional rough sidewall having microcracks and causing damage to the dielectric bonding layer.

[0034] Figure 19 is a diagram of a conventional process for sawing or dicing a die from a wafer into small pieces, where the dielectric bonding layer flakes and is damaged.

[0035] Figure 20 is a diagram of an example process for forming a peripheral protection trench on a die to stop cracking and flaking of the die and dielectric bonding layer and to trap contaminants from interfering with a direct bonding process.

[0036] Figure 21 is a continuation of the example process of Figure 20

[0037] Figure 22 is a diagram of various example configurations of a peripheral protection trench to stop cracking and flaking of the die and dielectric bonding layer and to trap contaminants from interfering with a direct bonding process

[0038] Figure 23 is a diagram of different example configurations of a peripheral protection trench at the dielectric bonding interface between two directly bonded dies. DETAILED DESCRIPTION

[0039] SUMMARY

[0040] The present disclosure describes enhancing bonding in microelectronic structures by trapping contaminants and stopping cracks during a direct bonding process. Example surface structures and containment techniques provide enhanced bonding for the manufacture of microelectronic assemblies by trapping and isolating particles, contaminants, and gaseous byproducts in pre-designed recesses in the bonding surface during a direct bonding process, and by stopping the propagation of cracks. The direct bonding process can be an oxide-to-oxide bonding between non-metals, such as dielectrics, or a direct hybrid bonding, which also includes intermetallic bonding at the bonding interface.

[0041] ​In an example system, a bonding surface that has been planarized to a high flatness is provided with recesses, depressions, wells, or cavities at predetermined locations to capture small particles and gaseous byproducts of bonding that would otherwise form relatively large voids between the two surfaces being joined. Example recesses can be fabricated during manufacturing to the following locations in a die or wafer: where particles collect during direct bonding when the particles move during the propagation of the bonding wave. The recesses can also be generated in an array, pattern, or band at predetermined locations by etching the surface to be bonded. For example, the recesses can be repeated in a wafer-level step-and-stitch pattern, or can be placed by an aligner or alignment process.

[0042] Example systems and techniques

[0043] Figure 2 Various bonding and annealing scenarios are shown, showing how contaminants affect direct bonding. In a first example, silicon wafers with native oxide are processed and bonded in a room temperature direct bonding process. In scenario 200, after 15 minutes at an annealing temperature of 150°C, voids are indistinguishable, or nearly indistinguishable by techniques such as confocal scanning acoustic microscopy (CSAM). In scenario 202, after 2 hours at an annealing temperature of 250°C, many voids 10 are clearly visible on the CSAM image. The voids 10 can be a result of localized delamination caused by gaseous byproducts such as water and hydrogen molecules. Reaction byproducts and voids can form due to dielectrics on the silicon wafer, such as silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, etc. For example, low temperature oxides deposited via silane and TEOS processes can generate more reaction byproducts than silicon alone, which leads to voids being generated during the bonding process. These voids can further grow during annealing at higher temperatures. If the propagation of the voids is not prevented or inspected, delamination and layering can sometimes spread across the bonding surface.

[0044] Scenario 204 shows movement of contaminant particles during direct bonding. As shown in scenario 204, it has been found that certain direct bonding processes cause contaminant particles, such as particles on the bonding surface, to move during the propagation of the bonding wave. When pairs of wafers with a large number of small particles on the bonding surface are bonded together, the particles become mobile and move outward along the propagating bonding wave, and then deposit in rings, e.g., rings 208 and 210 and 212 on the wafer, by these forces, as the bonding begins at the wafer center 206. In scenario 214, when pairs of wafers with fewer particles are bonded together, the particles also move along the bonding wave and settle in one or more rings, but in fewer number. One or more example pre-designed recesses 216 can be placed at or near each ring of maximum particle concentration.

[0045] The example system determines the location of loose particle aggregation and then places one or more pre-designed recesses 216 as depressions or traps to collect and store particles near critical bonding areas to prevent the formation of bonding voids 10 in these critical areas.

[0046] Figure 3 Example techniques are shown for mitigating undesirable voids (not shown) and improving bonding strength and integrity in the manufacture of microelectronic packages.

[0047] In one implementation, a microelectronic assembly has a first bonding surface 300. A second bonding surface 302 is adapted for bonding with the first bonding surface 300. Both surfaces are typically superflat after CMP for direct bonding or direct hybrid bonding. For example, the two surfaces 300 and 302 can be surfaces of a first die and a second die in a D2D package configuration, or surfaces of a die and a wafer in a D2W package configuration, or can be wafer surfaces in a W2W process. In direct oxide-to-oxide bonding, the two surfaces 300 and 302 can be non-metallic, such as inorganic dielectric materials. In direct hybrid bonding, the two surfaces 300 and 302 can include both dielectric and metallic conductors 301 and 303, such as pads, pins, leads, and connectors to be joined across the bonding interface.

[0048] In one implementation, the first bonding surface 300 is provided with pre-designed recesses 304 and 304' to capture at least one species that is detrimental to the bonding between the first bonding surface 300 and the second bonding surface 302. The planar dimensions of the pre-designed recesses 304 can range from sub-microns to tens or hundreds of microns. The depth of each pre-designed recess 304 can range from a few nanometers for capturing gaseous contaminants to a few microns or more for capturing solid particles. For example, direct oxide-to-oxide bonding or other types of dielectric bonding can release water vapor and hydrogen gas. As shown in the scheme 202, the CVD oxide can also outgas during the annealing phase. Figure 2

[0049] ​Sometimes, if the bonded dielectric layer has sufficient intrinsic defects, the gaseous byproducts will naturally sink down and no harmful voids 10 can be randomly formed during the annealing step. The design of the bonding surfaces 300 and 302 can include providing the surfaces 300 and 302 with a material having intrinsic recesses with a size calculated to trap particulates or other contaminants of the direct bonding process. For example, various schemes can be used to create or provide the surfaces 300 and 302 with a calculated porosity. If the dielectric layer does not have sufficient intrinsic space or pores to trap at least the gases, the gas molecules tend to aggregate in random locations, forming harmful voids 10 during annealing. In contrast to randomly formed bonding voids 10 that negatively affect the electrical performance of the components, the pre-designed recessed areas 304 and 304' in designated locations do not adversely affect the electrical performance, but can improve the bonding. In some cases, the pre-designed recesses 304 and 304' can even enhance the electrical performance.

[0050] The spacing between the example recesses 304 and 304' can be configured in relation to the relative cleanliness of the bonding process, the type of materials being bonded, and the type of contaminants and bonding byproducts generated by the bonding step or annealing step. If there is little debris and the level of byproducts is low, the recesses 304 and 304' can be smaller and / or spaced farther apart. Figure 3 The recesses 304 shown in FIG. 3 are not drawn to scale. For example, the width of the conductive leads 301 and 303 to be bonded together can be only a few microns, and the recesses 304 imparted, for example, by etching, can be even smaller or larger.

[0051] The recesses 304 can be provided on only one surface 300. Alternatively, recesses 306 and 308 can also be provided on both surfaces 300 and 302, with the recesses 306 and 308 randomly aligned with respect to each other across the bonding interface.

[0052] The recesses 310 and 312 can be provided on both surfaces 300 and 302 and aligned with each other such that each recess 310 and 312 forms half or other fractional portion of the resulting final recess 314 at the bonding interface 316. Aligning the recesses 310 and 312 with each other minimizes the unbonded surface area between the first bonding surface 300 and the second bonding surface 302.

[0053] Although Figure 3The recesses 304 and 306 and 308 and 310 and 312 shown in FIG. 3 appear to have similar depths and widths, but they can have different depths, different widths, and different shapes. For example, the recesses 304 and 304' formed on the same surface 300 can have different shapes, depths, and / or widths. In another example, the recesses 306 and 308 formed on different surfaces 300 and 302 can have different shapes, depths, and / or widths. Also, a single recess can have multiple depths.

[0054] In Figure 4 different shapes, the pre-designed recesses 402 and 404 and 406 and 408 (not drawn to scale) can be wells, depressions, cavities, indentations, cupped or dish-shaped recessed surfaces that are used to trap contaminants. The pre-designed recesses 402 and 404 and 406 and 408 can be arranged or patterned to fit the particular direct bonding process used and the type of material being bonded. The pre-designed recesses 402 and 404 and 406 and 408 are placed so that the surrounding bonding area is more robust in the case of more consistent bonding. However, because the recesses 402 and 404 and 406 and 408 themselves occupy some bonding area, the minimum number of recesses 402 and 404 and 406 and 408 needed to protect the bonding area from contamination can be calculated in advance, or can be determined for a particular direct bonding process and material, before running the layout through experiments. The dimensions and spacing of the pre-determined recesses 402 and 404 and 406 and 408 can be customized to optimally trap one size of particulate contaminants, or another size or type of bonding reaction byproducts or byproducts of the annealing step. Alternatively, the dimensions and spacing of the pre-determined recesses 402 and 404 and 406 and 408 can be customized for all, or averaged considering all types of contaminants from all sources. In another example, recesses of arbitrary shape can also include surface texturing to create nanoholes or micropores on the surface of the recess. For example, porous silicon can use this approach.

[0055] In one implementation, a coating or deposit of palladium metal or other hydride forming metal can be added to the pre-designed recesses to absorb hydrogen byproduct. Palladium used in microelectronic structures can absorb up to 900 times its own volume of hydrogen. Also, in addition to depositing palladium or hydride forming metals, any other metal or dielectric that can absorb and / or block reaction byproduct gases, moisture, or contaminants can be deposited in one or more of the pre-designed recesses 402, 404, 406, 408. For example, one or more recesses can also be deposited with a getter material. Different getter materials can have different properties. For example, aluminum (Al) has a gettering capacity for oxygen (O2) of about 1 Pa-1 / mg. Barium (Ba) has a gettering capacity for carbon dioxide (CO2) of about 0.69 Pa-1 / mg, for hydrogen (H2) of about 11.5 Pa-1 / mg, and for (O2) of about 2 Pa-1 / mg. Titanium (Ti) has a gettering capacity for (O2) of about 4.4 Pa-1 / mg. Thus, in some embodiments, the deposited material can be selected based on the types of gases that can be present in the environment in which the bonded structure will be used.

[0056] In one implementation, the distributed pattern or array of recesses 402 and 404 and 406 and 408 can have first recesses 404 sized and spaced apart from each other for capturing fine particulate contaminants, and second recesses 406 sized and spaced apart from each other for capturing reaction byproducts (such as gases) from direct bonding or annealing steps. The recesses 408 can extend along the entire periphery of the die. The contaminants to be captured can be, for example, gaseous byproducts of an inter-oxide direct bonding process, gaseous byproducts of a hybrid direct bonding process, gaseous byproducts of a bonding process involving chemical vapor deposition (CVD) oxide, gaseous byproducts of a bonding process involving thermal oxide (TOX) silicon wafer or die, gaseous byproducts of a bonding process involving silicon nitride surface, or gaseous byproducts of an inter-silicon direct bonding process.

[0057] Figure 5 Various example bonding wave patterns that occur during direct bonding are shown, as well as pre-designed recesses in response to the bonding wave patterns. Various bonding waves have been found to loosen and sweep particles into a characteristic pattern or resting place on the bonding surface during direct bonding.

[0058] In one approach, at the example bonding interface 502, the propagation of the bonding wavefront proceeds from one side of the effective bonding area 504 to the other side, and sweeps contaminants from their original locations in the direction of the propagating bonding wavefront. The bonding interface 502 can be used in an example die-to-wafer (D2W) process that uses a porous bonding head with left edge first contact that creates lateral bonding wave propagation and moves dispersed particles to the right side location. Pre-designed traps such as lines of recessed areas 506 and 508 can be placed at right angles or near right angles to the direction of the bonding wave propagation to collect particles, for example, near the effective bonding area 504. The lines of recessed areas 506 and 508 can be placed such that a series of recesses in line 508 coincide with the openings of a series of recesses in line 506, such that contaminants not captured in line 506 of recesses are further moved in the direction of the bonding wave propagation and captured in line 508 of recesses. In an example D2W process, for example, one or more linear bands of recesses 506 and 508 can be placed at the location of the maximum particle distribution on the right side.

[0059] In one technique, recessed areas 506 and 508 can be assigned near the bonding initiation location to avoid contaminating the effective bonding area 504 from the start. As the effective bonding area 504 approaches the end of the bonding wave propagation, then large traps 506 and 508 can be placed in front of the effective bonding area 504 to collect contaminants swept from other areas. These layout techniques are useful in wafer-to-wafer (W2W) and die-to-die (D2D) direct bonding processes. Some layouts of recesses 506 and 508 are also useful for wafer-to-wafer (W2W) processes.

[0060] At the example bonding interface 509, the propagation of the bonding wavefront begins at the centerline and proceeds to both sides 510 and 512, sweeping the contaminants out of their original locations and in the direction of the propagating bonding wavefront. For example, the lines of recessed regions 516 / 518 and 514 / 520 are placed such that a series of recesses in line 514 / 520 are coincident with a series of recess openings in line 516 / 518, such that contaminants not captured in the recesses of line 516 / 518 are moved further in the direction of the bonding wave propagation and captured in the recesses of line 514 / 520. The bonding interface 509 can be used in an example D2W process that uses curved bond heads for centerline-first contact, moving to the top and bottom edges, and the moving particles are directed to the top side 510 and the bottom side 512. Pre-designed traps such as recessed lines 514 and 516 and 518 and 520 can be placed at right angles to the direction of the bonding wave propagation to collect particles, for example, near the active bonding area 522. One or more linear bands of recesses 514 and 516 and 518 and 520 can be placed at the top location 510 and the bottom location 512 where the maximum particle distribution occurs.

[0061] At the example bonding interface 524, the propagation of the bonding wavefront begins at the center point and proceeds outward to four sides 526 and 528 and 530 and 532, sweeping the contaminants out of their original locations and in the direction of the propagating bonding wave. Pre-designed traps such as recessed lines or arrays 534 and 536, 538 and 540, 542 and 544, and 546 and 548 can be placed at right angles to the direction of the bonding wave propagation to collect particles, for example, near the active bonding area 550. Concentric rings, lines, or bands of recesses can be placed, for example, near the periphery where the maximum particle distribution occurs.

[0062] In an example center-first W2W process, direct bonding can move particles to a specific ring (e.g., 216 in FIG. 2B), which can be located in the center or the periphery of the wafer. Recesses for capturing particle contaminants can be located in or concentrated in this annular region. Figure 2

[0063] Figure 5 The various pre-designed recesses in FIGS. 2A-2E can be etched grooves or pits created in the bonding surface to capture particle movement during direct bonding, protecting critical areas from contamination and harmful bonding voids. Although we have shown in FIG. 2A that all the recessed lines or arrays are outside the bonding area, they can also exist within the bonding area. This can be done to capture contaminants that can not be displaced by a propagating key wavefront for a longer distance. Figure 5

[0064] Figure 6 ​​An example bonding surface 600 is shown configured with a large-area recess 602 (also referred to as a non-bonding region 602) for particle capture to protect the bonding integrity of adjacent bonding regions 604 and 606. Bonding with another surface occurs in the bonding footprint 604, which can export contaminants, particles, and byproducts of the bonding reaction to the large-area recess 602, which then stores, binds, or isolates them there. Particles up to a certain size in the large-area recess 602 fit within the recess 602 and do not cause delamination in the bonding region 604.

[0065] In one implementation, the large-area recess 602 completely surrounds the bonding footprint 604. In one implementation, another peripheral bonding region 606 can surround the large-area recess 602 as part of the overall bonding region between two surfaces being bonded on either side of the bonding interface. The large-area recess 602 can also capture particles and contaminants from the bonding reaction and / or annealing steps of the peripheral bonding region 606.

[0066] Multiple instances of the bonding surface 600 of a die or wafer can be bonded together in a stack 608. When both sides of the bonding interface have aligned recesses 602, recesses 602 can be added for either bonding interface. Or, even when one of the bonding surfaces is flat, without any recesses, the recess 602 of one bonding surface can capture contaminants of both bonding surfaces.

[0067] Figure 7 An example bonding surface 700 is shown that uses narrower recesses 702 and 708 for collecting contaminants from around the bonding regions 704 and 706. This configuration can be particularly suitable for thin and flexible semiconductor dies. Given that the dies and wafers have ultra-planar surfaces by way of CMP planarization, an objectionable particle 40 can also be very planar according to the CMP process itself, but still create a large void between the bonded surfaces. Observational data suggests that a one-micron particle in the horizontal X-Y dimensions (with a vertical height of less than one micron) can create a ten-micron void or larger in the interface between the bonded surfaces 700.

[0068] In Figure 7 The purpose of the relatively narrower recess 702 is to provide a bonding interface with maximum bonding area for mechanical strength. The narrow recess 702 surrounding the bonding region 704 can stop delamination forces from propagating between the surfaces being bonded together, as well as capture contaminants that are harmful to direct bonding. The narrow recess 702 relieves stress that propagates delamination, whether or not that delamination is caused by a particle 40 within the bonding interface. Although in Figure 7The recess 702 shown in FIG. 6 fully surrounds the bonding area 704, but in another implementation the recess 702 can only partially surround the bonding area 704.

[0069] In one implementation, the narrow surrounding recess 702 forms a trench around the bonding area 704 that prevents void propagation or delamination processes from invading the bonding area 704 from outside the bonding area 704. Although only one surrounding recess 702 is shown in Figure 7 Although only one surrounding recess 702 is shown in FIG. 6, multiple recesses 702 can be used that partially or fully surround the bonding area 704, surround each other with bonding area strips in between, or surround each other in other configurations where multiple recesses 702 partially surround at least a central bonding area 704. Other patterns of recesses (not shown) can also be deployed in the large bonding area 706 to mitigate stresses that would cause the surfaces to delaminate from each other in the large bonding area 706. Periodic recesses arranged at intervals mitigate such stresses with an effect similar to drilling holes at the end of a crack in a material, thereby arresting the cracking process, or similar to placing a pile of granular aggregate rock into cement to form concrete, where the propagation of a crack in the concrete is internally arrested when the crack encounters the rock components of the concrete, thereby dissipating the crack energy.

[0070] Likewise, the peripheral recess 708 prevents delamination from starting at the edges of the bonding surface 700 where the die has been sawn or diced and where contaminant particles can have collected at the edges of the bonding surface 700. The ratio of the bonding surfaces 704 and 706 to the recessed non-bonding surface areas 702 and 708 can vary, and for example can be Figure 6 between any of the ratios shown and Figure 7 shown.

[0071] The recessed areas 702 in a stack 710 formed by two or more bonded dies or wafers can arrest stresses caused by particles 40 and resulting delamination 10. Such stresses can also be arrested and mitigated by the recessed areas 702 when the recessed areas 702 are present in only one of the two surfaces being bonded.

[0072] Figure 8 A die or wafer is shown with large area recesses 802 (non-bonding areas) for capturing contaminants on the front and back sides of the die or wafer. Figure 8 the example in FIG. 6 with Figure 6The difference between the examples in FIGS. 6 and 8 is that the illustrated die or wafer has example bonding regions 804 and 806 on both the top and bottom sides of the die or wafer. As shown, the recesses 802 on each side of the double-sided die or wafer can be large area recesses 802, but can also be recesses 802 with small or even microscopic horizontal spans. Bonding to the other surface on the other die or wafer occurs at the bonding footprint regions 804 and 804' and 806 and 806', which expel contaminants, particles, and byproducts in the bonding reaction into the large area recesses 802 and 802', which bind or sequester the contaminants there.

[0073] As shown in the stack 808, particles up to a certain size fit in the large area recesses 802 and 802', where they cannot further delaminate the bonding regions 804 and 804'. When the stacked large area recesses 802 and 802' abut each other, the large area recess 802 or 802' can accommodate particles that are Figure 6 twice as large as the contaminant particles 40 captured by the large area recess 602 in FIG. 6, thereby providing twice the vertical height of the large area recess as shown in Figure 6 FIG. 6. The respective large area recesses 802 and 802' completely surround each respective bonding footprint region 804 and 804'. In one implementation, the respective peripheral bonding regions 806 and 806' surround the respective large area recesses 802 and 802' and become part of the surface area of the overall bonding between the bonding surfaces 800. The same large area recesses 802 and 802' also capture particles and contaminants from the peripheral bonding regions 806 and 806'.

[0074] Figure 9 An example bonding surface 900 is shown, which is a variation of the bonding surface 600 shown in Figure 6 FIG. 6. In Figure 9 the strip or rib portions of the bonding regions (e.g., strip portions 902 and 904) are located between the central bonding region footprint 908 and the peripheral bonding regions 910, thereby connecting the two. The ribbed bonding region strip portions 902 and 904 improve bonding propagation and increase the overall bonding contact area between the surfaces 900 being bonded. The resulting large area recess 906, while larger than the large area recess 602 in FIG. 6, is still smaller than the large area recess 802 in FIG. 8. Figure 6The recess in the center is small, but can trap particles and reaction byproducts to protect the integrity of the bond. Bonding to the other surface occurs in the central bonding area footprint 908, the peripheral bonding area 910, and the various ribbed bonding areas 902 and 904, all of which can push contaminants, particles, and byproducts from the bonding reaction out to the large area recess 906 between them. Particles up to a certain size that fit into the large area recess 906 are removed so as not to cause or propagate further delamination in the bonding areas 908, 910, 902, and 904. Likewise, the large area recess 906 also traps particles and contaminants from the anneal step.

[0075] Although Figure 6 to Figure 9 The center rectangular bonding area, characteristics for DRAM HBM applications, are shown, but the layout of a given bonding surface can include multiple effective bonding areas, and these areas can be separated by recessed areas for trapping contaminants. The effective bonding areas can also be connected together, with the isolated recessed areas having random shapes pre-designed into the layout. In a given implementation, one or more of the effective bonding areas can be any shape, such as square, rectangular, circular, polygonal, star-shaped, etc.

[0076] Figure 10 A stack structure 1002 is shown, such as a stack die 1004 bonded into the stack 1002 by joining the bonding surfaces of the example die 1004 at bonding interfaces 1006 and 1008. The large area recess 1010 provides electrical benefits for conductive traces 1012 placed to crosscut the recess 1010, resulting in lower dielectric loss and lower capacitive loss for signals running in the traces 1012 in the recess 1010 compared to embedded or laminated traces 1012 between a semiconductor material such as silicon. The dielectric loss and capacitive loss can be controlled, for example, by the geometry of the air gap configured in a given recess 1010. The benefits of signal transmission can be significant when the conductive traces 1012 crosscut the relatively large area recess 1010.

[0077] Figure 11A first bonding surface 1100 and a second bonding surface 1102 are shown, with conductive pads 1104 and 1106 used to engage electrical interconnects from the respective surfaces 1100 and 1102 when the surfaces are bonded. The bonding surfaces 1100 and 1102 can be surfaces that undergo D2W bonding or W2W bonding. The bonding technique can be a direct dielectric bonding or a direct hybrid bonding process. Relatively large pads 1108, which can be non-functional dummy pads that are not connected to circuitry, are distributed between the conductive pads 1104 and 1106. These larger pads 1108 undergo a degree of dishing 1110 during one or more chemical mechanical planarization steps (CMP), resulting in a deeper recess 1110 in the pad 1108 than a conventional recess having a narrower width in the pad 1104 or 1106. In one implementation, the deeper recess can be placed to capture loose particles and bonding reaction byproducts. A significant recess for capturing contaminants can occur or can be obtained to form the example recess 1110 when the width of the pad 1108 is 10 pm or greater or at least two times larger than the conductive pads 1104 and 1106, which can be, for example, DBI pads.

[0078] Alternatively, larger pads 1112 can be intentionally recessed from the bonding surface 1100 by design and fabrication. Such recessed pads 1112 can be wide or narrow depending on the amount of captured contaminants to protect the bond. When the bond is formed, as the gap between the surfaces 1100 and 1102 disappears, some particles and gaseous byproducts of the bonding reaction tend to move to any available space, resulting in contaminants and byproducts being captured in the recess 1114. The location of the accumulated particles can also be determined by calculation or observation. The larger pads 1112 with the pre-designed recess 1114 can be placed at the determined location of the accumulated particles.

[0079] CSAM or confocal scanning acoustic microscope images have shown that the pre-designed recess successfully isolated the particles and bonding reaction byproducts, resulting in very few bonding voids. The lack of voids provides a robust bond with high bonding integrity and full electrical connection of the bonding interconnects. Electrical testing of the bonding interconnects confirms the results of the CSAM images, with example pre-designed recesses resulting in a clear lack of undesirable bonding voids.

[0080] Example method

[0081] Figure 12 An example method 1200 for enhancing bonding in microelectronic devices is shown. Operations of the example method 1200 are shown in separate blocks.

[0082] At block 1202, a recess is provided in a bonding surface of a die or wafer.

[0083] At block 1204, the bonding surface is planarized to a flatness for direct bonding. The example method 1200 can be used with other general types of bonding operations. CMP or other measures can be used to obtain a surface flatness suitable for direct bonding and direct hybrid bonding processes. Some or all of the recesses can be formed during or after this step, rather than at block 1202.

[0084] At block 1206, the bonding surface is joined to another bonding surface in a direct bonding operation or a direct hybrid bonding operation, allowing the recesses to trap particles, contaminants, and bonding reaction byproducts.

[0085] Figure 13 Another example method 1300 for enhancing bonding in microelectronic devices is shown. Operations of the example method 1300 are shown in separate blocks.

[0086] At block 1302, a location where particles accumulate during a direct bonding process between a first bonding surface and a second bonding surface is determined, where propagation of a bonding wavefront during the direct bonding process loosens and moves the particles.

[0087] At block 1304, a recess is placed at the location in the first bonding surface or the second bonding surface to prevent the particles from interfering with the direct bonding process.

[0088] At block 1306, the first surface and the second surface are directly bonded together.

[0089] The recess can be placed at or near the location in both the first bonding surface and the second bonding surface.

[0090] A first recess in the first bonding surface can be vertically aligned with a second recess in the second bonding surface across a bonding interface between the first bonding surface and the second bonding surface to form an additional recess or a composite recess across the bonding interface.

[0091] In one implementation, a pre-designed recess can be created in a bonding surface by etching. The location where a higher concentration of particle accumulation occurs can be determined by calculating or observing propagation of a bonding wavefront from one side of an active bonding area to an opposite side of the active bonding area. Alternatively, the bonding wavefront can travel from a centerline of the active bonding area to two opposite sides of the active bonding area. Likewise, the bonding wavefront can travel from a center point of the active bonding area to four sides of the active bonding area (or can propagate in more directions to more sides).

[0092] A pattern of one or more rows of linear recesses or point recesses can be placed at a right angle to a direction of bonding wave propagation to collect particles.

[0093] The recess dimensions can vary depending on the application and depending on the possible contaminants. In one implementation, the horizontal width of the recess can be less than one micron, or even be on the order of nanometers, and the width can be up to hundreds of microns.

[0094] The depth dimension of an example recess can range from a few nanometers for capturing gaseous contaminants to a few microns for capturing particles. The depth of the recess(es) can be greater than the pad thickness used in direct-bonding (e.g., DBI) bonding processes. The recess(es) can be free of active element portions, MEMS devices, etc., in order to isolate contaminants from potentially sensitive areas of the microelectronic device. The recess(es) can also be confined in the x, y, and z directions in order to maximize the area for circuitry, MEMS, or other operational features.

[0095] In one implementation, the pre-designed recesses can also be implemented in some wafers, for example, by selecting or creating materials with a given porosity or other inherent pattern of recesses.

[0096] Figure 14 Another example method 1400 for enhancing bonding in microelectronic devices is shown. The operations of the example method 1400 are shown in individual blocks.

[0097] In block 1402, a location or direction in which stress can propagate is determined for a bonding interface of a direct bonding operation.

[0098] At block 1404, one or more recesses are placed at the location or in the direction in the bonding surface to stop the stress propagation. In one implementation, a pattern of periodic recesses or holes can provide "interrupts" for stresses acting in the horizontal plane of a micron-scale direct bonding interface.

[0099] At block 1406, the bonding surface with the one or more recesses is direct bonded to another surface.

[0100] Figure 15 Another example method 1500 for enhancing bonding in microelectronic devices is shown. The operations of the example method 1500 are shown in individual blocks.

[0101] At block 1502, a large-area recess is formed to completely surround an active bonding area for direct bonding, the active bonding area being within a horizontal plane of the bonding surface.

[0102] At block 1504, the bonding surface is direct bonded to another surface, with the large-area recess capturing contaminants in the active bonding area that are detrimental to the direct bonding.

[0103] Figure 16Another example method 1600 for enhancing bonding in microelectronic devices is shown. The operation of example method 1600 is shown in a separate box.

[0104] At frame 1602, a large-area recess is formed near the effective bonding region for direct bonding. The effective bonding region lies within the horizontal plane of the bonding surface.

[0105] At frame 1604, the conductive trace is routed through a large-area recess. The large-area recess reduces the dielectric loss and / or capacitance loss of the conductive trace.

[0106] At frame 1606, the bonding surface is directly bonded to another surface. Large-area recesses trap contaminants that would hinder direct bonding and appear in the effective bonding region.

[0107] Figure 17 Another example method 1700 for enhancing bonding in microelectronic devices is shown. The operation of example method 1700 is shown in a separate box.

[0108] At frame 1702, the pads placed on the bonding surface are recessed or recessed by a chemical mechanical planarization (CMP) process.

[0109] At frame 1704, the bonding surface is directly bonded to another surface, while recessed or recessed pads trap contaminants that are harmful to the direct bonding process.

[0110] Figure 18 A close-up view of the roughened sidewall edge 1802 of the die surface 1804 to be bonded is shown, including conventional spalling 50 caused by cutting or sawing the surface 1804 along the edge (also in...). Figure 1 (As shown in the diagram). Residue from sawing or cutting may also be present. Surface 1804 may be a microelectronic die, but may be other surfaces suitable for bonding. Roughness and spalling at the edge 50 may cause edge 1802 or microcracks 60 ( Figure 1 Further spalling or fragmentation in surface 1804 may propagate further across surface 1804 when pressure is applied for bonding or when surface 1804 thermally expands and contracts. Spalling 50 may occur at the edges of the die material (e.g., silicon) or the edges of the dielectric layer (polymer material). In a cross-sectional side view of the bonded structure 1806 between the two surfaces 1804, spalling 50 results in post-bonding defects 1808, such as gaps or voids, between the two bonded surfaces 1804.

[0111] Figure 19A conventional process and production environment is shown in which rough sidewall edges 1802 and peeling 50 of the die material and dielectric layer can occur and propagate. A substrate 1902 with a smooth bonding surface 1904 has a coating, such as a dielectric layer 1906. A resist layer 1908 is then applied and patterned. An etch 1910 is performed through a wiring layer (not shown) in the dielectric layer 1906 and into a portion of the substrate material 1902. Next, the die is sawn for singulation, resulting in a narrower sawn channel 1912 within the etched area 1910 of the substrate 1902. The resist layer 1908 is removed. As shown in the bottom close-up view, sawing of the channel 1912 during the singulation step can cause peeling 50 or cracking 60 in the dielectric layer 1906.

[0112] Figure 20 An example process is shown for making a protective cavity, recess, trench, channel, etc. near the edge of a die or dielectric bonding layer to stop the propagation of stresses, peeling, cracking, splitting, or fissures that can occur in sawing, dicing, singulation, or other processes, as well as rough, peeled, or damaged edges.

[0113] A substrate 2002 with a smooth bonding surface 2004 has a coating, such as a dielectric layer 2006. A resist layer 2008 is applied and patterned. For each of the underlying dies 2010, 2012, and 2014, the patterning of the resist layer 2008 creates an outer trench or channel 2016 and an inner trench or channel 2018 near the edge of each die, where the die is sawn or diced from the wafer. These channels 2016 and 2018 can be patterned along the periphery of a given die. For example, for the die 2012, the outer channel 2016 represents the channel in which the die 2012 will be sawn or diced, while the inner channel 2018 represents the location of the protective channel 2018 for stopping the propagation of peeling, cracking, and / or microcracking caused by the sawing or dicing process.

[0114] An etch process 2020 using the patterned resist layer 2008 as a template etches through the dielectric layer 2006, through the wiring layer (not shown) within the dielectric layer 2006, and into the substrate material 2002 of the dies 2010 and 2012 and 2014 a distance or predetermined depth. Next, a narrower saw 2022 singulating the dies relative to each die 2010, 2012, and 2014 can be made in the outer channel 2016.

[0115] In Figure 21 , the substrate 2002 is etched through the dielectric layer 2006 and into the substrate material 2002 a distance or predetermined depth. Next, a narrower saw 2022 singulating the dies relative to each die 2010, 2012, and 2014 can be made in the outer channel 2016. Figure 20The process continues with resist strip 2102 and die clean. Each die 2012 resulting from this process now has a smooth dielectric bonding layer for direct bonding or direct hybrid bonding to another die or wafer, and has a die protection trench 2018 located near the edge of the dielectric layer 2006 that has been sawn. These die protection trenches or recesses 2018 prevent the propagation of any flaking, cracking, fissuring, or breaking near the edge of the dielectric bonding layer 2006, thereby increasing the yield of good dies 2012 and of good die stacks or microelectronic packages made from the dies 2012.

[0116] Figure 22 Different example patterns for implementing the protection trench 2018 in the semiconductor material of the die 2012 or in the dielectric bonding layer 2006 of the die 2012, or in both, are shown.

[0117] In addition to stopping the propagation of stresses, flaking, cracking, fracturing, fissuring, and chipping at the edge of the die 2012 or dielectric layer 2006, the protection trench 2018 can also serve as a recess for holding residue from the cutting or sawing operation itself that would interfere with direct bonding at the smooth dielectric bonding layer 2006, or the protection trench 2018 can act as a getter space for capturing byproducts of the direct bonding operation or other environmental contaminants that would interfere with the direct bonding process or cause voids 10 in the direct bonding interface. The protection trench 2018 serving as a recess for capturing contaminants is also shown as a recess 404 in Figure 4

[0118] Figure 22 Different example implementations of the protection trench 2018 of Figure 21 are shown. In configuration 2202, the top view of the die 2012 has the protection trench 2018 as a peripheral cavity or trench encircling the periphery of the die 2012, the protection trench 2018 going through the top dielectric bonding layer and into the semiconductor material of the die 2012, or into the substrate material if the surface being directly bonded is not the die 2012.

[0119] In configuration 2204, the top view of the die 2012 has the protection trench 2018 as a plurality of parallel peripheral cavities or trenches encircling the periphery of the die 2012, the protection trench 2018 going through the top dielectric bonding layer and into the semiconductor material of the die 2012, and into the substrate material if the surface being directly bonded is not the die 2012.

[0120] ​In configuration 2206, a top view of the die 2012 has a protective trench 2018 as a transverse peripheral cavity or trench encircling the periphery of the die 2012, the protective trench 2018 passing through the top dielectric bonding layer and into the semiconductor material of the die 2012, and into the substrate material if the surface being directly bonded is not the die 2012.

[0121] In configuration 2208, a top view of the die 2012 has a protective trench 2018 as a discontinuous peripheral cavity or trench or array of discontinuous cavities disposed parallel or non-parallel (relative to the edges of the die) encircling the periphery of the die 2012, the protective trench 2018 passing through the top dielectric bonding layer and into the semiconductor material of the die 2012, or into the substrate material if the surface being directly bonded is not the die 2012. In one embodiment, the top view of the trench 2018 can include one or more arrays of curvilinear lines or geometric features.

[0122] Figure 23 Two dies are shown directly bonded together at the interface of their respective dielectric bonding layers 2006. At configuration 2302, the peripheral protective trenches 2018 of each respective die are aligned vertically to provide a single protective trench 2018 that passes through both dielectric layers that are now bonded together. This configuration is expected to be useful for stopping certain types of microcracks from propagating across the direct bonding interface, as well as for collecting certain types of contaminants, thereby removing the contaminants without interfering with the direct bonding process.

[0123] At configuration 2304, the protective trenches 2018 are vertically staggered. The horizontal offset of the peripheral protective trenches 2018 can provide some structural advantages and can be useful for collecting certain types of contaminants that would interfere with the direct bonding process.

[0124] Example configuration 2306 shows vertically staggered protective trenches 2018, with one of the protective trenches 2018 stopping a local delamination process 2308.

[0125] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been chosen for the purposes of providing a thorough understanding of the disclosed embodiments. In some instances, certain terms or symbols can have been presented in order to provide for clarity in understanding the present disclosure. For example, any particular dimensions, numbers, types of materials, manufacturing steps, etc. can differ from those described above in alternative embodiments. The term "coupled" is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. The terms "example," "embodiment," and "implementation" are used to mean example, not a preference or requirement. Likewise, the terms "can" and "may" are used interchangeably to mean optional (permitted) subject matter. The absence of either term is not to be construed as a requirement of a given feature or technique.

[0126] Various modifications and changes can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, the features or aspects of any one embodiment can be used in combination with any other embodiment, or in place of the corresponding features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0127] While the disclosure has been disclosed with respect to a limited number of embodiments, those skilled in the art will appreciate that many modifications and variations can be made within the scope of the disclosure, given the benefit of this disclosure. It is intended that the appended claims cover all such modifications and variations as falling within the true spirit and scope of the disclosure.

Claims

1. An apparatus comprising: a first bonding surface of a microelectronic assembly; and a second bonding surface adapted for bonding with the first bonding surface; at least one recessed non-bonding region of the first bonding surface or the second bonding surface for capturing at least one species detrimental to a bonding interface between the first bonding surface and the second bonding surface, the at least one recessed non-bonding region being non-operative with respect to a circuit or operative element disposed on or in the microelectronic assembly, wherein at least one electrically conductive trace at the first bonding surface or the second bonding surface traverses the at least one recessed non-bonding region.

2. The apparatus of claim 1, further comprising a distributed pattern or distributed array of recesses in the first bonding surface or the second bonding surface, the distributed pattern or the distributed array being configured for capturing the at least one species.

3. The apparatus of claim 2, wherein the distributed pattern or distributed array of recesses comprises recesses sized and spaced apart from one another for capturing fine particulate contaminants.

4. The apparatus of claim 3, wherein the distributed pattern or the distributed array of recesses is configured for capturing or facilitating transfer of the fine particulate contaminants and byproducts of a subsequent anneal of the first bonding surface bonded to the second bonding surface.

5. The apparatus of claim 2, wherein recesses in the first bonding surface are aligned with recesses in the second bonding surface to minimize un-bonded surface area between the first bonding surface and the second bonding surface.

6. The apparatus of claim 1, further comprising a coating or deposit of an absorbent, adsorbent or occlusive material in the at least one recess to absorb, adsorb or occlude byproducts of bonding or annealing.

7. The apparatus of claim 2, wherein the recesses of the distributed pattern of recesses comprise etched micro-recesses on one or both of the first bonding surface and the second bonding surface; and wherein the micro-recesses comprise recesses of different sizes, shapes and / or depths at different locations on the first bonding surface or the second bonding surface.

8. The apparatus of claim 2, wherein recesses of the distributed pattern of recesses are arranged in a band at an interval to capture moving particles in a bonding wave motion, wherein the band is arranged at a location of maximum particle distribution perpendicular to a transverse bonding wave propagation direction.

9. The apparatus of claim 2, wherein recesses of the distributed pattern of recesses are arranged in concentric circles or annular intervals to capture moving particles at a location of maximum particle distribution in a bonding wave motion propagating radially outward from a center point of the first bonding surface and the second bonding surface.

10. The apparatus of claim 2, wherein the distributed pattern of recesses comprises a recessed region distributed at least partially around a bonding region between the first bonding surface and the second bonding surface.

11. The apparatus of claim 10, further comprising a second recess at least partially surrounding the recess region, wherein the recess portion of the recess region is offset from the recess portion of the second recess.

12. An apparatus comprising: a first bonding surface disposed at a surface of a microelectronic assembly; a first portion of a first conductor disposed at the first bonding surface, the first conductor positioned to form an electrical contact; a second bonding surface; a second conductor disposed at the second bonding surface, the second conductor positioned to make permanent electrical contact with a respective first portion of a first conductor disposed at the first bonding surface during a bonding process between the first bonding surface and the second bonding surface; a dished metal pad on the first bonding surface or the second bonding surface, the dished metal pad having a top contact surface and a side surface, and having a recessed region within the contact surface of the dished metal pad, the recessed region configured to capture contaminants or byproducts generated during or after bonding the first bonding surface to the second bonding surface; and a recessed non-bonding region disposed at a surface of the microelectronic assembly, wherein a second portion of the first conductor traverses the recessed non-bonding region.

13. The apparatus of claim 12, wherein the dished metal pad is configured to capture the contaminants of the bonding process or an anneal process, and dishing is imparted by chemical mechanical planarization (CMP) of the first bonding surface.

14. The apparatus of claim 13, wherein the second bonding surface has at least one dished metal pad to capture instances of contaminants of the bonding process or the anneal process.

15. The apparatus of claim 14, wherein the metal pads of the second bonding surface are electrically isolated from one another.

16. The apparatus of claim 14, wherein the metal pads of the first bonding surface partially or completely overlap the metal pads of the second bonding surface to form at least one gap across a bonding interface to capture contaminants.

17. A bonding structure for an assembly of microelectronic devices, comprising: a first bonding region of a wafer or die; a first recessed non-bonding region surrounding a majority or all of the first bonding region, the first recessed non-bonding region to collect byproducts of a bonding process from the first bonding region or to collect contaminants that are detrimental to a bonding interface; a second bonding region disposed outside of the first recessed non-bonding region and at least partially surrounding the first recessed non-bonding region, wherein conductive traces at the first bonding region or the second bonding region traverse the first recessed non-bonding region.

18. The bonding structure of claim 17, wherein the first recessed non-bonding region includes byproducts and contaminants collected from the second bonding region that are detrimental to the bonding process. ​ 19. The bonded structure of claim 17, further comprising another die or another wafer having instances of the first bonding region, the first recessed non-bonding region, the second bonding region, and the second recessed non-bonding region on at least one side of the other die or the other wafer for creating a stacked bonded structure.

20. The bonded structure of claim 17, further comprising a recess in the first bonding region and the second bonding region to prevent propagation of a delamination process or a layering process at the first bonding region or the second bonding region.

21. The bonded structure of claim 17, further comprising a rib between the first bonding region and the second bonding region to connect the first bonding region and the second bonding region as a single bonding region, the rib facilitating bonding propagation and increasing a total bonding region in a bonding process.

22. The bonded structure of claim 17, further comprising a conductive trace extending at least horizontally in the first recessed non-bonding region, the first recessed non-bonding region configured to impart reduced dielectric losses and reduced capacitive losses to a signal of the conductive trace.

23. An apparatus comprising: a first bonding region of a die or a wafer; a second bonding region of the die or the wafer separated from the first bonding region by a first recessed non-bonding region around the first bonding region; and a second recessed non-bonding region disposed along an entire peripheral edge of the die or the wafer around the second bonding region, the second recessed non-bonding region configured to trap at least one substance detrimental to a bonding interface between the first bonding region and the second bonding region, wherein a conductive trace at the first bonding region or the second bonding region traverses the first recessed non-bonding region or the second recessed non-bonding region.

24. The apparatus of claim 23, wherein the first bonding region or the second bonding region comprises a conductive layer.

25. An apparatus comprising: a first bonding surface of a microelectronic assembly, the first bonding surface comprising a first dielectric material; a second bonding surface directly bonded to the first bonding surface, the second bonding surface comprising a second dielectric material; at least one recessed non-bonding region not containing electrically operable elements, the at least one recessed non-bonding region disposed in and bounded by the first dielectric material of the first bonding surface or the second dielectric material of the second bonding surface, the at least one recessed non-bonding region comprising a first recess around a central portion of the first bonding surface, and the first bonding surface further comprising a peripheral portion of the first bonding surface.

26. The apparatus of claim 25, wherein a recess in the first bonding surface is aligned with a recess in the second bonding surface.

27. The apparatus of claim 25, further comprising a coating or deposit of an absorbent, adsorbent, or occlusive material in the at least one recessed non-bonding region to absorb, adsorb, or occlude bonding or annealing byproducts.

28. The apparatus of claim 25, wherein the at least one recessed non-bonding region further comprises a second recess around the perimeter portion of the first bonding surface.

29. The apparatus of claim 25, wherein the first bonding surface and the second bonding surface comprise metallic contacts, and the first bonding surface and the second bonding surface are directly hybrid bonded.

30. A directly hybrid bonded apparatus, comprising: a first bonding surface of a first microelectronic assembly; first conductors disposed at the first bonding surface, the first conductors positioned to form electrical contacts; a second bonding surface of a second microelectronic assembly directly bonded at a bonding interface to the first bonding surface; second conductors disposed at the second bonding surface, the second conductors directly bonded to respective ones of the first conductors disposed at the first bonding surface; a recessed metal pad beneath the first bonding surface, the recessed metal pad being a dummy pad unconnected to a circuit, the recessed metal pad being wider in a lateral direction than the first conductors, the recessed metal pad being sufficiently recessed relative to the first bonding surface to maintain a vertical gap between the recessed metal pad and the second bonding surface in the directly hybrid bonded apparatus.

31. The apparatus of claim 30, wherein the recessed metal pad has a dish-shaped surface feature of a chemical mechanical planarization (CMP) of the first bonding surface.

32. The apparatus of claim 30, further comprising a second recessed metal pad beneath the second bonding surface, the second recessed metal pad being wider in a lateral direction than the second conductors.

33. The apparatus of claim 32, wherein the recessed metal pad beneath the first bonding surface partially or completely overlaps the second recessed metal pad beneath the second bonding surface to form a merged vertical gap across the bonding interface.

34. The apparatus of claim 30, wherein the recessed metal pad is recessed relative to the first bonding surface by more than a thickness of the recessed metal pad.

35. A bonding structure for an assembly of microelectronic devices, comprising: a first bonding surface of a wafer or die, the first bonding surface comprising a first dielectric material; a first recessed non-bonding region around a majority or all of the first bonding surface, the first recessed non-bonding region comprising an etched recess in the first dielectric material and not containing metal connected to a circuit; and a second bonding surface of a wafer or die around a majority or all of the first recessed non-bonding region.

36. The bonding structure of claim 35, wherein the etched recess contains byproducts and contaminants that are detrimental to a bonding process. ​ 37. The bonded structure of claim 35, further comprising another wafer or another die having instances of the first bonding surface, the first recessed non-bonding region, the second bonding surface, and the second recessed non-bonding region located on at least one side of the other wafer or die for creating a stacked bonded structure.

38. The bonded structure of claim 35, further comprising additional recesses in the first bonding surface and the second bonding surface to stop propagation of a delamination process or a layering process in the first bonding surface or the second bonding surface.

39. The bonded structure of claim 35, further comprising a rib between the first bonding surface and the second bonding surface to connect the first bonding surface and the second bonding surface into a continuous bonding region, the rib facilitating bonding propagation and increasing the total bonding area during a bonding process.

40. The bonded structure of claim 35, further comprising a conductive trace at least horizontally across the first recessed non-bonding region, the etched recess configured to impart reduced dielectric loss and reduced capacitive loss to a signal of the conductive trace.

41. The bonded structure of claim 35, further comprising a metal contact in the first bonding surface, the first bonding surface being planarized and suitable for direct hybrid bonding.

42. An apparatus comprising: a first bonding region of a wafer or a die, the first bonding region configured for direct bonding and comprising a dielectric material; a second bonding region of the wafer or the die, the second bonding region surrounding the first bonding region, comprising the dielectric material, and configured for direct bonding; a first recessed non-bonding region at least substantially surrounding the first bonding region, the first recessed non-bonding region comprising at least one etched recess defined by the dielectric material and separating the first bonding region from the second bonding region; and a second recessed non-bonding region disposed along an entire outer periphery of the wafer or the die surrounding the second bonding region.

43. The apparatus of claim 42, further comprising a conductive trace traversing the first recessed non-bonding region and / or the second recessed non-bonding region.

44. The apparatus of claim 42, wherein the first bonding region and / or the second bonding region comprises a metal contact and is configured for direct hybrid bonding. ​

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