Ultra-low power self-biasing circuit and electronic terminal using the same

Abstract

The present application provides an ultra-low power self-bias circuit and an electronic terminal used therein, including: a startup circuit, a core circuit electrically connected to and controlled by the startup circuit; the core circuit includes: a first NMOS tube, a second NMOS tube, a resistor, and a current mirror circuit; the gate of the first NMOS tube is connected to the output end of the startup circuit and the drain of the second NMOS tube, and the source is connected to the first end of the resistor and the gate of the second NMOS tube; the second end of the resistor is grounded; the source of the second NMOS tube is connected to the second end of the resistor and grounded; wherein the drain of the first NMOS tube is connected to the current mirror circuit; the bias current output by the current mirror circuit is equivalent to the current flowing through the resistor. Compared with the traditional bandgap circuit, the self-bias circuit provided by the present application greatly simplifies the complexity of the circuit and saves the circuit layout area and power consumption, while also greatly reducing the chip cost.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to an ultra-low power self-biasing circuit and an electronic terminal used therein. Background Art

[0002] Bias circuits are an important component in electronic circuit design, used to provide a stable operating point for semiconductor devices such as transistors and field effect transistors (FETs). The main purpose of bias circuits is to ensure that semiconductor devices can operate stably under various operating conditions and avoid unstable performance caused by factors such as temperature changes and power supply voltage fluctuations.

[0003] At present, the bandgap bias circuit is a widely used circuit in integrated circuit design, which is mainly used to generate a stable reference voltage or current that is independent of or has little change with temperature. The bandgap bias circuit uses the bandgap characteristics of semiconductor materials, which are relatively stable at different temperatures, thereby providing a stable reference value. The structure of the current bandgap bias circuit is as follows Figure 1 As shown in FIG. 1 , the circuit uses bandgap technology to obtain the required bias current IBIAS. However, this circuit structure still has technical problems such as complex circuits, high circuit layout area and power consumption, and high chip cost. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an ultra-low power self-bias circuit and an electronic terminal used therein, so as to solve the technical problems of the existing bandgap bias circuit, such as complex circuit, high circuit layout area and power consumption, and high chip cost.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides an ultra-low power self-bias circuit, comprising: a startup circuit, a core circuit electrically connected to and controlled by the startup circuit; the core circuit comprises: a first NMOS tube, a second NMOS tube, a resistor, and a current mirror circuit; the gate of the first NMOS tube is connected to the output end of the startup circuit and the drain of the second NMOS tube, and the source is connected to the first end of the resistor and the gate of the second NMOS tube; the second end of the resistor is grounded; the source of the second NMOS tube is connected to the second end of the resistor and to the ground; wherein the drain of the first NMOS tube is connected to the current mirror circuit; the bias current output by the current mirror circuit is equal to the current flowing through the resistor.

[0006] In some embodiments of the first aspect of the present application, the current mirror circuit includes two PMOS tubes that are mirror-symmetrical to each other; the sizes of the two PMOS tubes, the voltage between the source and the drain, and the voltage between the gate and the source are all the same.

[0007] In some embodiments of the first aspect of the present application, the current mirror circuit includes: a first PMOS tube and a second PMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are connected and commonly connected to the drain of the first MMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are connected and commonly connected to the power supply end; the drain of the first PMOS tube is connected to the drain of the first NMOS tube; wherein, when the startup circuit is started, the first NMOS tube is turned on, the current flowing through the first PMOS tube is the same as the current flowing through the resistor, and the bias current output by the mirrored second PMOS tube is also equivalent to the current flowing through the resistor.

[0008] In some embodiments of the first aspect of the present application, the bias current is: I=V gs / R0; where I represents bias current; R0 represents resistance; V gs It represents the voltage across the resistor.

[0009] In some embodiments of the first aspect of the present application, the self-bias circuit also includes a third PMOS tube; the gate of the third PMOS tube is connected to the gate of the first PMOS tube and the drain of the first NMOS tube, the source is connected to the power supply terminal; the drain is connected to the drain of the second NMOS tube and the gate of the first NMOS tube.

[0010] In some embodiments of the first aspect of the present application, the startup circuit includes any one of the following circuits: a capacitor charging startup circuit, an RC delay startup circuit, a transistor startup circuit, a current source startup circuit, a voltage comparator startup circuit, an oscillator startup circuit, a watchdog circuit, and a bootstrap circuit.

[0011] To achieve the above-mentioned object and other related objects, a second aspect of the present application provides an electronic terminal, including the ultra-low power consumption self-bias circuit.

[0012] As described above, the ultra-low power self-bias circuit of the present application and the electronic terminal used therein have the following beneficial effects: compared with the traditional bandgap circuit, the self-bias circuit provided by the present application greatly simplifies the complexity of the circuit and saves the circuit layout area and power consumption, while also greatly reducing the chip cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the circuit structure of a bandgap bias circuit in the prior art.

[0014] Figure 2 Shown is a circuit structure schematic diagram of an ultra-low power self-bias circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0016] Before further describing the present invention in detail, the nouns and terms involved in the embodiments of the present invention are explained. The nouns and terms involved in the embodiments of the present invention are applicable to the following interpretations:

[0017] <1> Bandgap bias circuit: An integrated circuit that uses the bandgap characteristics of semiconductor materials to generate a stable voltage or current that is independent of or varies very little with temperature changes. Due to its high accuracy and stability.

[0018] <2> NMOS transistor: N-type metal oxide semiconductor transistor, which is manufactured on a P-type silicon substrate, and its source and drain are N-type doped regions. NMOS transistors mainly use electrons as their main carriers. When a voltage negative to the source voltage is applied to the gate, an N-type conductive channel is formed under the gate, allowing electrons to flow from the source to the drain. NMOS tubes can be used in digital logic circuits, loads of analog circuits, switches, etc.

[0019] <3> PMOS transistor: P-type metal oxide semiconductor transistor, which is manufactured on an N-type substrate, and its source (Source) and drain (Drain) are P-type doped regions. PMOS transistors mainly use holes as their main carriers. When a voltage higher than the source voltage is applied to the gate (Gate), a P-type conductive channel is formed under the gate, allowing holes to flow from the source to the drain. PMOS tubes can also be used in digital logic circuits, analog circuit loads, switches, etc.

[0020] <4> Current mirror circuit: An analog circuit technique used to copy a known current value to another branch or branches to generate the same current. This circuit is very important in integrated circuit design, especially in situations where a stable reference current is required, such as bandgap bias circuits, current regulators, analog amplifiers, etc.

[0021] The bandgap reference circuit of the embodiment of the present application has high precision and stability, as well as ultra-low power consumption and low cost, and can be applied to a variety of analog circuits that require high-precision reference signals, such as: analog-to-digital converters (ADCs), digital-to-analog converters (DACs), voltage regulators, sensors (such as temperature sensors, pressure sensors, and light sensors, etc.), precision amplifiers, power management, communication equipment, medical equipment (such as heart rate monitors, blood glucose meters, medical imaging equipment, etc.), industrial control systems, automotive electronics (such as engine management systems, safety systems, infotainment systems, etc.), consumer electronics (such as smart phones, tablet computers), test and measurement equipment, microcontrollers and processors, etc. It should be noted here that the bandgap characteristic refers to the energy gap between the valence band and the conduction band in semiconductor materials. This energy gap is called the bandgap, which is a very important parameter in the physical properties of semiconductors, which determines the electronic properties of the material.

[0022] like Figure 2 As shown, a schematic diagram of the structure of an ultra-low power self-bias circuit in an embodiment of the present invention is shown. The ultra-low power self-bias circuit in an embodiment of the present invention includes: a startup circuit, and a core circuit electrically connected to and controlled by the startup circuit. The core circuit includes: a first NMOS tube MN1, a second NMOS tube MN0, a resistor R0, and a current mirror circuit.

[0023] The gate G of the first NMOS transistor MN1 is connected to the output end of the startup circuit and the drain D of the second NMOS transistor MN0, the source S of the first NMOS transistor MN1 is connected to the first end 1 of the resistor R0 and the gate G of the second NMOS transistor MN0; the second end 2 of the resistor R0 is grounded; the source S of the second NMOS transistor MN0 is connected to the second end 2 of the resistor R0 and grounded. The drain D of the first NMOS transistor MN1 is connected to the current mirror circuit; the bias current IBIAS output by the current mirror circuit is equal to the current flowing through the resistor R0.

[0024] In the embodiment of the present application, the current mirror circuit includes two PMOS transistors that are mirror-symmetrical to each other, namely, a first PMOS transistor MP2 and a second PMOS transistor MP3. The first PMOS transistor MP2 and the second PMOS transistor MP3 have the same size, and the voltage V between the source and the drain is ds The same, the voltage between the gate and the source V gs Same.

[0025] Preferably, the specific structure of the current mirror circuit includes: a first PMOS tube MP2 and a second PMOS tube MP3; the gate G of the first PMOS tube MP2 and the gate G of the second PMOS tube MP3 are connected and connected to the drain D of the first MMOS tube MN1, the source S of the first PMOS tube MP2 and the source S of the second PMOS tube MP3 are connected and connected to the power supply terminal AVDD; the drain D of the first PMOS tube MP2 is connected to the drain D of the first NMOS tube MN1. When the startup circuit is started, the first NMOS tube MN1 is turned on, the current flowing through the first PMOS tube MP2 is the same as the current flowing through the resistor R0, and the bias current IBIAS output by the mirrored second PMOS tube MP3 is also equal to the current flowing through the resistor R0.

[0026] Further, the bias current IBIAS is expressed as:

[0027] I=V gs / R0; formula (1)

[0028] Where I represents bias current; R0 represents resistance; V gs represents the voltage applied across the resistor, ie, the gate-source voltage of the second NMOS transistor MN0.

[0029] It should be noted here that the current mirror circuit composed of PMOS tubes allows one transistor to copy the current of another transistor. In the current mirror circuit, there is usually a reference current (determined by the second NMOS tube MN0 and the resistor R0) to be copied to another transistor (such as the first PMOS tube MP2 and the second PMOS tube MP3). When the size (ratio of width to length) of the first PMOS tube MP2 and the second PMOS tube MP3 are the same, and the voltage V between their source and drain is ds Phase, gate and source voltage V gs are also the same, then the currents flowing through the two PMOS tubes are also the same.

[0030] In an embodiment of the present application, the ultra-low power self-bias circuit further includes a third PMOS transistor MP1; a gate G of the third PMOS transistor MP1 is connected to a gate G of the first PMOS transistor MP2 and a drain D of the first NMOS transistor MN1. A source S of the third PMOS transistor MP1 is connected to a power supply terminal AVDD. A drain D of the third PMOS transistor MP1 is connected to a drain D of the second NMOS transistor MN0 and a gate G of the first NMOS transistor MN1.

[0031] It is worth noting that, combined with Figure 1 and Figure 2 By comparison, it can be seen that the traditional bandgap bias circuit (such as Figure 1The traditional bandgap bias circuit (as shown in Figure 1) contains multiple components such as precise resistor networks, current mirrors, temperature compensation diodes, transistors, and operational amplifiers, which work together to generate a stable bias current. The complexity of the circuit comes from the need to accurately control and compensate for various influencing factors, such as temperature changes, power supply voltage fluctuations, etc. In addition, due to the inclusion of multiple components and complex connections, the traditional bandgap bias circuit occupies a large silicon wafer area, which directly affects the area of ​​the circuit layout. Complex circuit design means more current paths and components, which may lead to higher static power consumption, especially in applications that need to maintain a high-precision reference voltage or current. The complexity of the circuit, the larger layout area, and the higher power consumption will all lead to an increase in chip manufacturing costs.

[0032] In particular, the ultra-low power bias circuit provided by the present invention abandons the transistors Q1 and Q2 used in the traditional bias circuit. It should be understood by those skilled in the art that the transistor has obvious disadvantages in terms of power consumption and chip area compared with the transistor. In terms of dynamic power consumption, since the transistor is a current control device, the dynamic power consumption is higher than that of the MOS tube, and the switching speed of the MOS tube is fast and there is almost no power consumption in the cut-off state. In terms of static power consumption, although the base current of the transistor can be very small (low static power consumption) when used in analog applications or as a linear amplifier, the base current is large (high static power consumption) when the transistor works in the saturation region. In terms of power consumption efficiency, the MOS tube can be designed to have almost no leakage current in the off state, thereby reducing static power consumption. In terms of chip area, the transistor is composed of two PN junctions, while the MOS tube is composed of a PN junction and an insulating layer, so the chip area of ​​the transistor is larger under the same function.

[0033] In an embodiment of the present application, the startup circuit includes any of the following circuits: a capacitor charging startup circuit, an RC delay startup circuit, a transistor startup circuit, a current source startup circuit, a voltage comparator startup circuit, an oscillator startup circuit, a watchdog circuit, and a bootstrap circuit. Specifically, the capacitor charging startup circuit uses a small capacitor to charge when powered on, and gradually turns on the circuit (the core circuit in this embodiment) through the voltage on the capacitor until the circuit can work independently. The RC delay startup circuit combines a resistor and a capacitor to form a delay circuit to ensure that the circuit starts gradually over a period of time to avoid instantaneous current shocks when powered on. The transistor startup circuit uses one or more transistors to form a startup logic, such as using the threshold voltage of an NMOS or PMOS transistor to detect whether the power supply has reached a level sufficient to start the circuit. The current source startup circuit uses an auxiliary current source to provide an initial current when the circuit is powered on until the main circuit can generate its own operating current. The voltage comparator startup circuit uses a voltage comparator to detect the power supply voltage. Once the voltage exceeds a preset threshold, the comparator outputs a signal to enable the main circuit. The oscillator startup circuit uses an oscillator to generate a clock signal, which controls the startup process of the circuit until the circuit reaches a stable working state. A watchdog circuit can monitor the startup process of a circuit and reset the circuit if an abnormality is detected. A bootstrap circuit can generate a voltage higher than the power supply voltage at power-on to ensure that the circuit has enough voltage difference to start.

[0034] The present application also provides an electronic terminal, including the ultra-low power self-biasing circuit in the above embodiment. The electronic terminal in the embodiment of the present application can be an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a voltage regulator, a sensor (such as a temperature sensor, a pressure sensor, and a light sensor, etc.), a precision amplifier, a power management, a communication device, a medical device (such as a heart rate monitor, a blood glucose meter, a medical imaging device, etc.), an industrial control system, automotive electronics (such as an engine management system, a safety system, an infotainment system, etc.), consumer electronics (such as a smart phone, a tablet computer), a test and measurement device, a microcontroller, and a processor, etc.

[0035] In the embodiments of the present application, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first NMOS tube and the second NMOS tube are only used to distinguish different NMOS tubes, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0036] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0037] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0038] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0039] In summary, the present application provides an ultra-low power self-bias circuit and an electronic terminal used therein. Compared with the traditional bandgap circuit, the self-bias circuit provided by the present application greatly simplifies the complexity of the circuit and saves the circuit layout area and power consumption, while also greatly reducing the chip cost. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0040] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An ultra-low power self-biasing circuit, characterized in that: include: A start-up circuit and a core circuit electrically connected to and controlled by the start-up circuit; The core circuit includes: a first NMOS tube, a second NMOS tube, a resistor, and a current mirror circuit; The gate of the first NMOS tube is connected to the output end of the startup circuit and the drain of the second NMOS tube, and the source is connected to the first end of the resistor and the gate of the second NMOS tube; the second end of the resistor is grounded; the source of the second NMOS tube is connected to the second end of the resistor and grounded; wherein the drain of the first NMOS tube is connected to the current mirror circuit; the bias current output by the current mirror circuit is equal to the current flowing through the resistor; Wherein, the current mirror circuit includes two PMOS tubes that are mirror-symmetric to each other; the sizes, the voltages between the source and the drain, and the voltages between the gate and the source of the two PMOS tubes are the same; the current mirror circuit includes: a first PMOS tube and a second PMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are connected and commonly connected to the drain of the first MMOS tube, the source of the first PMOS tube and the source of the second PMOS tube are connected and commonly connected to the power supply terminal; the drain of the first PMOS tube is connected to the drain of the first NMOS tube; wherein, when the startup circuit is started, the first NMOS tube is turned on, the current flowing through the first PMOS tube is the same as the current flowing through the resistor, and the bias current output by the mirrored second PMOS tube is also equal to the current flowing through the resistor; The self-bias circuit also includes a third PMOS tube; the gate of the third PMOS tube is connected to the gate of the first PMOS tube and the drain of the first NMOS tube, the source is connected to the power supply terminal; the drain is connected to the drain of the second NMOS tube and the gate of the first NMOS tube.

2. The ultra-low power self-bias circuit according to claim 1, characterized in that: The bias current is: I=V gs / R0; Where I represents bias current; R0 represents resistance; V gs It represents the voltage across the resistor.

3. The ultra-low power self-bias circuit according to claim 1, characterized in that: The startup circuit includes any of the following circuits: a capacitor charging startup circuit, an RC delay startup circuit, a transistor startup circuit, a current source startup circuit, a voltage comparator startup circuit, an oscillator startup circuit, a watchdog circuit, and a bootstrap circuit.

4. An electronic terminal, characterized in that: The invention comprises the ultra-low power self-bias circuit as claimed in any one of claims 1 to 3.

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