Chip, chip testing method and electronic equipment

Abstract

The embodiments of the present application provide a chip, a chip testing method, and an electronic device, wherein the chip includes a plurality of core particles, the plurality of core particles including a first core particle and a second core particle interconnected; the first core particle includes a first on-chip memory, and a controller for controlling the first on-chip memory; the second core particle includes a second on-chip memory; wherein the control information output by the controller is transmitted to the first on-chip memory, and is transmitted to the second core particle through a first interconnection interface connecting the first core particle and the second core particle; when the second core particle chooses to use the control information to control the second on-chip memory, whether the controller obtains a response result of the second on-chip memory to the control information indicates whether the connection between the first interconnection interface of the first core particle and the second core particle is normal. The embodiments of the present application can enable chip testing to cover the connection between core particles, thereby improving the test coverage of the chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip technology, and specifically to a chip, a chip testing method, and an electronic device. Background Art

[0002] Packaging technology can interconnect multiple cores to form chips such as SOCs (System on Chips). Packaging technology can improve chip performance, functional density, and efficiency while reducing chip size and power consumption, making it widely used in chip manufacturing.

[0003] In order to ensure the performance of chips that use packaging technology, the chips need to be tested. Therefore, how to provide a technical solution to improve the test coverage of the chips has become a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a chip, a chip testing method, and an electronic device, so that the test can cover the connections between the chiplets in the chip, thereby improving the test coverage of the chip.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a chip, comprising a plurality of core particles, wherein the plurality of core particles include a first core particle and a second core particle that are interconnected;

[0007] The first chip includes a first on-chip memory and a controller for controlling the first on-chip memory; the second chip includes a second on-chip memory;

[0008] Among them, the control information output by the controller is transmitted to the first on-chip memory, and is transmitted to the second core particle through the first interconnection interface connecting the first core particle and the second core particle; when the second core particle chooses to use the control information to control the second on-chip memory, whether the controller obtains the response result of the second on-chip memory to the control information indicates whether the connection between the first interconnection interface of the first core particle and the second core particle is normal.

[0009] In a second aspect, an embodiment of the present application provides a chip testing method, wherein the chip includes a plurality of core particles, wherein the plurality of core particles include a first core particle and a second core particle that are interconnected. The testing method is applied to the first core particle. The testing method includes:

[0010] Determining control information output by the controller of the first chip;

[0011] transferring the control information to a first on-chip memory of the first chiplet, and transferring the control information to the second chiplet via a first interconnection interface connecting the first chiplet and the second chiplet; wherein the control information transferred to the second chiplet is used to control the second on-chip memory of the second chiplet;

[0012] Determining whether a response result of the second on-chip memory to the control information is obtained;

[0013] If not, confirming that the connection between the first interconnection interface of the first core particle and the second core particle is abnormal;

[0014] If so, it is confirmed that the connection between the first interconnection interface of the first core particle and the second core particle is normal.

[0015] In a third aspect, an embodiment of the present application provides an electronic device comprising the chip as described in the first aspect above.

[0016] The chip provided by the embodiment of the present application can use the controller of the first core to control the first on-chip memory of the first core and the second on-chip memory of the second core; thus, the control information output by the controller of the first core can be transmitted to the first on-chip memory, and can be transmitted to the second core through the first interconnection interface connecting the first core and the second core. Furthermore, when the second core chooses to use the control information output by the controller to control the second on-chip memory, whether the controller of the first core obtains the response result of the second on-chip memory to the control information can indicate whether the connection between the first interconnection interface of the first core and the second core is normal, so as to detect whether the connection between the first interconnection interface between the cores is normal and improve the test coverage of the chip. It can be seen that the embodiment of the present application can realize the control of on-chip memory across cores, thereby detecting whether there is an abnormality in the connection of the interconnection interface between the cores, confirming the interconnection interface that cannot communicate normally between the cores, so that the test can cover the connection of the interconnection interface between the cores, and improve the test coverage of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0018] Figure 1 This is an example diagram of a chip using 3D packaging technology.

[0019] Figure 2 Figure 1 is an example diagram of a chip with MBIST logic.

[0020] Figure 3This is an example diagram of the chip provided in the embodiment of the present application.

[0021] Figure 4A Another example diagram of the chip provided in an embodiment of the present application.

[0022] Figure 4B This is another example diagram of the chip provided in an embodiment of the present application.

[0023] Figure 5 An example diagram of a core particle with memory repair logic provided in an embodiment of the present application.

[0024] Figure 6 This is another example diagram of the chip provided in an embodiment of the present application.

[0025] Figure 7 This is another example diagram of a chip provided in an embodiment of the present application.

[0026] Figure 8A This is an example diagram of the implementation of the chip provided in the embodiment of the present application.

[0027] Figure 8B This is another example diagram of an implementation of the chip provided in an embodiment of the present application.

[0028] Figure 9 A flowchart of a chip testing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0030] Chip packaging technologies may include 2D, 2.5D, and 3D. 2D packaging places multiple chips on a single plane and connects them via wires. 2.5D packaging places multiple chips on a silicon interposer and connects them via the interposer. 3D packaging stacks multiple chips vertically and connects them via vertical interconnects.

[0031] Taking the chip using 3D packaging technology as an example, Figure 1 An example diagram of a chip using 3D packaging technology is shown as follows: Figure 1As shown, a chip using 3D packaging technology may include multiple cores stacked vertically. These cores may be divided into a bottom core 101 and at least one upper core 102 located above the bottom core 101. A core refers to a bare chip. Different cores have different functions or are manufactured using different processes. Multiple cores may be interconnected and packaged to form a chip. For example, multiple cores may be interconnected and packaged to form a chip such as a SOC through 3D packaging.

[0032] The bottom core particle 101 may be the bottom core particle in a 3D package. That is, based on the hierarchical positional relationship of the 3D package in the vertical stack, the bottom core particle is located at the bottom (bottom layer) of the vertical stack. The bottom core particle may be the main control core particle in the chip, such as the core core particle; the core core particle may integrate a processor core (such as a CPU core) and / or other system cores (such as a graphics processing core, an accelerator core, etc.).

[0033] The upper-layer core particle 102 is located above the bottom-layer core particle, that is, among the multiple core particles stacked in the vertical direction, except for the bottom-layer core particle at the bottom, the remaining core particles located above the bottom-layer core particles can be called upper-layer core particles. The number of upper-layer core particles can be at least one, that is, one or more (greater than one); when the number of upper-layer core particles is multiple, it can also support multiple upper-layer core particles to be stacked in different levels in the vertical direction, and one level can be provided with at least one upper-layer core particle. The upper-layer core particle can be a core particle that implements a specific function in the chip, such as a memory core particle (such as a cache core particle), a sensor core particle, or other integrated circuit core particles that implement a specific function.

[0034] Combine Figure 1 As shown, in the chip, the underlying core particles can be connected to the chip's packaging substrate 103 so as to communicate with the peripherals (external devices) through the peripheral interface 104 provided on the packaging substrate. In other words, the peripherals can communicate with the underlying core particles connected to the packaging substrate through the peripheral interface on the packaging substrate, so that the peripherals can interact with the chip and realize data transmission and control signal transmission between the chip and the peripherals. For example, the peripheral interfaces provided on the packaging substrate can be, for example, the chip's input and output interfaces, the chip's test and debug interfaces, etc.

[0035] In chips using 3D packaging technology, core particles at different levels can be connected through vertical interconnection technology. For example, the chip can stack multiple levels of core particles in the vertical direction, so that core particles at different levels can be connected through vertical interconnection technology.

[0036] Combine Figure 1As shown, the core particles can be provided with an interconnection interface 105 so that different core particles can be connected through the interconnection interface. For example, for each upper layer core particle, the lower layer core particle of the upper layer core particle can be connected to the upper layer core particle through the interconnection interface. For another example, the bottom layer core particle can be connected to the upper layer core particle of the upper layer of the bottom layer core particle through the interconnection interface. In addition, the bottom layer core particle and the packaging substrate can also support connection through the interconnection interface.

[0037] In one example, the vertical interconnection technology may be, for example, TSV (Through Silicon Via) technology, and the corresponding interconnection interface may be a TSV interface. It should be noted that the interconnection interface is used to connect between core particles. In chips using 2D packaging technology, 2.5D packaging technology, and 3D packaging technology, the connection between core particles can be achieved through the connection of the interconnection interface. Therefore, the TSV interface is only an example of an interconnection interface when the chip adopts 3D packaging technology.

[0038] It can be seen that a chip can include multiple cores. For example, a chip using 3D packaging technology can include multiple cores stacked vertically. Cores are the basic building blocks of a chip. However, if any core involved in the packaging has a defect or abnormality, it may cause the entire chip to have a defect or abnormality. In severe cases, the entire chip may even be discarded, resulting in an increase in chip manufacturing costs. Therefore, it is necessary to test the cores involved in the packaging. Among them, the defect or abnormality of the core may be caused by damage to the core during the production process of the core, or it may be caused by damage to the core during the packaging process.

[0039] For chiplets equipped with on-chip memory, a key task in testing whether the chiplet has defects or abnormalities is to test whether the chiplet's on-chip memory has defects or abnormalities. The chiplet's on-chip memory refers to the memory devices integrated within the chiplet, including but not limited to any of the following memory devices integrated within the chiplet: RAM (Random Access Memory), cache, etc.

[0040] One way to test the on-chip memory of the chip is to test the on-chip memory of the chip through MBIST (Memory Built-in Self-test) logic built into the chip to test whether the on-chip memory of the chip has defects or abnormalities.

[0041] It should be noted that the MBIST logic is a memory self-test logic built into the chip, which is used to test whether the chip's on-chip memory has defects or abnormalities, and to obtain test results. The test results can indicate whether there are abnormal storage units in the chip's on-chip memory, and when there are abnormal storage units in the chip's on-chip memory, provide the location information of the abnormal storage units (such as the address of the abnormal storage units and other information). It should be further explained that the storage unit is the basic component unit of the chip's on-chip memory, that is, the chip's on-chip memory can include multiple storage units; the abnormal storage unit refers to an abnormal storage unit in the on-chip memory, for example, a storage unit in the on-chip memory that cannot correctly store and / or restore data. The abnormality of the abnormal storage unit may be caused by defects in the manufacturing process, material defects, wear and tear caused by long-term use, power supply fluctuations, and the like.

[0042] For ease of understanding, Figure 2 An example diagram of a core particle with MBIST logic is shown as follows: Figure 2 As shown, the chiplet may include an on-chip memory 210 , a test controller 220 , and a test access port 230 .

[0043] The on-chip memory 210 may be an on-chip memory to be tested in a chip. The embodiment of the present application is not limited to the form of the on-chip memory, including but not limited to a cache and random access memory integrated in the chip.

[0044] The test controller 220 is a control circuit embedded in the chiplet for implementing MBIST logic and is used to test the on-chip memory of the chiplet. The test controller is, for example, an MBIST controller that supports MBIST logic.

[0045] Based on the chip's built-in MBIST logic, the test controller can be used to perform self-tests on the chip's on-chip memory. For example, the chip's test controller can generate test control information and pass it to the chip's on-chip memory. The on-chip memory can then respond to the test control information with corresponding operations. The test controller can then generate test results based on the on-chip memory's response results.

[0046] One way MBIST logic tests on-chip memory cells for defects and anomalies is by comparing the read and write data to determine if the cells are abnormal. For example, the MBIST logic can write data to the on-chip memory cells in a specific order and read the written data from the cells in a specific order. The logic then compares the read and written data to see if they are consistent. If they are consistent, the cell is considered normal; if not, the cell is marked as abnormal and the location of the abnormal cell is provided.

[0047] Based on this, the test control information generated by the test controller may include write test control information and read test control information, wherein the write test control information is used to write test data to the storage unit of the on-chip memory, and the read test control information is used to read test data from the storage unit of the on-chip memory. Thus, for any storage unit of the on-chip memory, the test controller can test whether the storage unit is abnormal by comparing the test data read by the read test control information with the test data written by the write test control information. That is, test data is written to the storage unit through the write test control information, and test data is read from the storage unit through the read test control information. If the test data read from the storage unit is consistent with the written test data, the storage unit is normal; if the test data read from the storage unit is inconsistent with the written test data, the storage unit is abnormal.

[0048] In one example, combining Figure 2 As shown, the test controller may include a test controller host 221 and a test controller slave 222; based on MBIST logic, the test controller host may be called an MBIST controller host, and the test controller slave may be called an MBIST controller slave. Wherein, the test controller host may generate a test vector and send it to the test controller slave; the test controller slave may convert the test vector into the test control information used by the on-chip memory for testing. For example, the test vector generated by the test controller host may include a write test vector for writing test data, and a read test vector for reading test data; accordingly, the test control information converted by the test controller slave based on the test vector may include write test control information corresponding to the write test vector, and read test control information corresponding to the read test vector.

[0049] exist Figure 2 As shown, the test access port 230 can be used to configure the test controller, for example, the test access port can configure test vectors for the test controller. In an optional implementation, the test access port can be connected to the test debug interface of the chip, and the test debug interface can be connected to peripherals such as a test debugger or a dedicated test machine, so that the test debugger or the peripherals such as a dedicated test machine can pass the configuration information of the test controller to the test access port of the core grain through the test debug interface, so as to configure the test controller of the core grain through the test access port of the core grain. The test debug interface can be regarded as a type of peripheral interface of the chip, which is used to connect peripherals such as a test debugger or a dedicated test machine. For example, the test debug interface can be a JTAG (Joint Test Action Group) interface, and accordingly, the test access port can be a TAP (Test Access Port) port that is connected to the JTAG interface, which is used to access the test functions inside the core grain.

[0050] The above-mentioned test method based on MBIST logic can perform self-test on the on-chip memory of the core grain, thereby testing whether the on-chip memory of the core grain has defect abnormality, for example, testing whether the on-chip memory of the core grain has abnormal storage unit. However, in addition to involving each core grain, the chip also involves the connection between the core grains, that is, the connection formed by the interconnection interface (such as TSV interface) between the core grains; the above-mentioned test method based on MBIST logic cannot cover the connection test between the core grains, that is, it cannot test whether the connection of the interconnection interface (such as TSV interface) between the core grains is normal, which causes the test coverage of the chip to be lacking. In other words, the above-mentioned test method based on MBIST logic is to test the on-chip memory of each core grain independently, and cannot meet the connection test requirements of the interconnection interface (such as TSV interface) between the core grains, resulting in a low test coverage of the chip.

[0051] Based on this, the embodiments of the present application provide an improved chip testing solution, which enables the test to cover the connections between the core particles in the chip, thereby improving the test coverage of the chip. For example, the test solution provided by the embodiments of the present application can cover the on-chip memory of the test core particles, and can also cover the connection of the interconnection interface between the test core particles, thereby meeting the test requirements within the core particles, and also meeting the connection test requirements between the core particles, thereby realizing the joint testing of multiple core particles of the chip and improving the test coverage of the chip.

[0052] As an optional implementation, Figure 3 The example diagram of the chip provided by the embodiment of the present application is exemplarily shown. The chip may include multiple core particles (for example, a chip using 3D packaging technology may include multiple core particles stacked in a vertical direction), combined with Figure 3 As shown, the plurality of core particles may include a first core particle 310 and a second core particle 320 that are interconnected; wherein the first core particle and the second core particle are any two core particles that are interconnected in the chip, and both the first core particle and the second core particle are provided with on-chip memory.

[0053] In one example, for a chip using 3D packaging technology, the first core particle and the second core particle can be any two core particles at different levels among multiple core particles stacked in a vertical direction of the chip, and both are provided with on-chip memory. In other words, the chip is stacked in multiple levels in a vertical direction, each level can be provided with at least one core particle, and the first core particle and the second core particle can be any two core particles at different levels in the vertical direction, and both are provided with on-chip memory.

[0054] For chips using 3D packaging technology, as an optional implementation, the hierarchical relationship between the first core particle and the second core particle can be: the level of the first core particle is lower than the level of the second core particle, or the level of the first core particle is higher than the level of the second core particle. It should be noted that the higher the level of the core particle, the higher the core particle is in the vertical direction. As an example, taking a chip using 3D packaging technology as an example, Figure 3 The example in which the level of the first core-particle is lower than the level of the second core-particle is used for demonstration. In other optional implementations, the embodiment of the present application may also support the level of the first core-particle being higher than the level of the second core-particle.

[0055] The first chiplet 310 may include a first on-chip memory 311 and a controller 312 for controlling the first on-chip memory. The on-chip memory integrated in the first chiplet may be referred to as the first on-chip memory, such as a first cache memory and a first random access memory integrated in the first chiplet.

[0056] The second chip 320 may include a second on-chip memory 321 ; the on-chip memory integrated in the second chip may be referred to as a second on-chip memory, such as a second cache and a second random access memory integrated in the second chip.

[0057] In the embodiment of the present application, the controller 312 of the first chiplet can control the first on-chip memory 311 of the first chiplet and can also control the second on-chip memory 321 of the second chiplet. Since the controller 312 is located in the first chiplet and the second on-chip memory 321 is located in the second chiplet, the controller 312 needs to utilize the connection between the first chiplet and the second chiplet to control the second on-chip memory 321. That is, the controller 312 of the first chiplet needs to utilize the connection between the first interconnection interface 301 of the first chiplet and the second chiplet to control the second on-chip memory 321 of the second chiplet.

[0058] In an optional implementation, the controller 312 of the first chiplet can output control information. In addition to being transmitted to the first on-chip memory 311 of the first chiplet via the internal connection circuit of the first chiplet, the control information output by the controller 312 can also be transmitted to the second chiplet via the first interconnection interface 301 connecting the first chiplet and the second chiplet (for example, a connection formed by the first interconnection interface of the first chiplet and the first interconnection interface of the second chiplet). The first interconnection interface can be an interconnection interface used for data communication and control between chiplets, which is a type of interconnection interface used for connecting between chiplets.

[0059] The second chip can choose to use the control information transmitted by the controller 312 to control the second on-chip memory 321. Therefore, when the controller 312 transmits control information to the second chip through the first interconnection interface between the first chip and the second chip, and the second chip chooses to use the control information transmitted by the controller 312 to control the second on-chip memory 321, whether the controller 312 of the first chip obtains the response result of the second on-chip memory 321 of the second chip to the control information can indicate whether the connection between the first interconnection interface of the first chip and the second chip is normal.

[0060] That is to say, when the connection between the first interconnection interface of the first chiplet and the second chiplet is normal, the first chiplet and the second chiplet can normally perform data communication and control, so that the control information output by the controller 312 of the first chiplet can be normally transmitted to the second chiplet through the first interconnection interface between the first chiplet and the second chiplet; when the second chiplet needs to choose to use the control information output by the controller to control the second on-chip memory, the second chiplet can control the second on-chip memory through the control information normally transmitted by the first interconnection interface; furthermore, the second on-chip memory can respond to the control information, perform response operations such as data reading and writing, and normally feed back the response results (such as data reading and writing results) to the controller of the first chiplet through the first interconnection interface, so that the controller of the first chiplet can obtain the response results of the second on-chip memory to the control information.

[0061] However, when the connection between the first interconnection interface of the first chip and the second chip is abnormal, since the first chip and the second chip cannot communicate and control data normally, the control information output by the controller of the first chip cannot be transmitted normally to the second chip. Therefore, when the second chip needs to choose to use the control information transmitted by the controller to control the second on-chip memory, the second chip cannot obtain the control information transmitted by the controller through the first interconnection interface normally. Therefore, the second chip cannot use the control information output by the controller to control the second on-chip memory, which also causes the second on-chip memory to be unable to generate a response result corresponding to the control information, causing the controller of the first chip to be unable to obtain the response result of the second on-chip memory to the control information after transmitting the control information.

[0062] It can be seen that when the controller of the first chip transmits control information to the first chip through the first interconnection interface between the first chip and the second chip, and the second chip chooses to use the control information output by the controller to control the second on-chip memory, if the controller of the first chip obtains the response result of the second on-chip memory to the control information, it indicates that the connection between the first interconnection interface of the first chip and the second chip is normal; if the controller of the first chip does not obtain the response result of the second on-chip memory to the control information, it indicates that the connection between the first interconnection interface of the first chip and the second chip is abnormal.

[0063] The chip provided by the embodiment of the present application can use the controller of the first core to control the first on-chip memory of the first core and the second on-chip memory of the second core; thus, the control information output by the controller of the first core can be transmitted to the first on-chip memory, and can be transmitted to the second core through the first interconnection interface connecting the first core and the second core. Furthermore, when the second core chooses to use the control information output by the controller to control the second on-chip memory, whether the controller of the first core obtains the response result of the second on-chip memory to the control information can indicate whether the connection between the first interconnection interface of the first core and the second core is normal, so as to detect whether the connection between the first interconnection interface between the cores is normal and improve the test coverage of the chip. It can be seen that the embodiment of the present application can realize the control of on-chip memory across cores, thereby detecting whether there is an abnormality in the connection of the interconnection interface between the cores, confirming the interconnection interface that cannot communicate normally between the cores, so that the test can cover the connection of the interconnection interface between the cores, and improve the test coverage of the chip.

[0064] In an optional implementation, the control information output by the controller of the first chip can be divided into access control information for accessing the on-chip memory in the normal working mode, and test control information for testing the on-chip memory in the test mode. Accordingly, the controller provided in the first chip can be divided into a memory controller for generating access control information, and a test controller for generating test control information. Based on the fact that the first chip can generate test control information through a built-in test controller with MBIST logic, Figure 4A Another example diagram of the chip provided in the embodiment of the present application is shown exemplarily. Figure 3 and Figure 4A As shown, in Figure 4A As shown, the controller 312 of the first chiplet 310 may include a memory controller 411 and a first test controller 412 provided in the first chiplet.

[0065] In an optional implementation, the storage controller 411 may be a control circuit in the first chip that performs access control on the first on-chip memory, and may generate access control information for the first on-chip memory. For example, in normal working mode, the storage controller 411 may generate access control information to perform access control on the first on-chip memory provided by the first chip. For example, in normal working mode, the chip may perform computing and control services, and in the process of performing computing and control services, the storage controller may perform read and write access control on the first on-chip memory provided by the first chip through access control information (including but not limited to read control information for controlling the on-chip memory to read data, write control information for controlling the on-chip memory to write data, etc.). The type of storage controller may depend on the type of memory controlled, such as a cache controller that controls the cache, etc., and the embodiments of the present application are not limited thereto.

[0066] The first test controller 412 is a test controller provided in the first core particle, and is used for performing a self-test on the first on-chip memory of the first core particle. The first test controller is, for example, a first MBIST controller supporting MBIST logic provided in the first core particle. In an optional implementation, the first test controller 412 can generate first test control information (including but not limited to first write test control information and first read test control information, etc.) to perform a self-test on the first on-chip memory of the first core particle. For example, in a test mode, the first test controller 412 can generate first test control information to test the first on-chip memory of the first core particle.

[0067] In an optional implementation, the first test controller may include a first test controller host (e.g., a first MBIST controller host) and a first test controller slave (e.g., a first MBIST controller slave); wherein the first test controller host (e.g., the first MBIST controller host) may generate a first test vector (including but not limited to a first write test vector and a first read test vector), and the first test controller slave (e.g., the first MBIST controller slave) may convert the first test vector into first test control information.

[0068] For ease of explanation, the embodiment of the present application refers to the test controller host in the first test controller as the first test controller host, and the test controller slave in the first test controller as the first test controller slave; the test control information generated by the first test controller is referred to as the first test control information, the write test control information corresponding to the first test control information is referred to as the first write test control information, and the read test control information corresponding to the first test control information is referred to as the first read test control information; accordingly, the write test vector corresponding to the first write test control information is referred to as the first write test vector, and the read test vector corresponding to the first read test control information is referred to as the first read test vector.

[0069] It should be noted that the normal working mode refers to the mode in which the chip performs normal operations and realizes its functions. In the normal working mode, the chip can perform calculations, control, and other services. The test mode refers to the mode in which the chip performs testing and inspection, such as the MBIST test mode.

[0070] As an optional implementation, in the first chiplet, the memory controller 411 and the first test controller 412 may share access to the first on-chip memory 311. For example, within the first chiplet 310, the first test controller 412 may be connected to the memory controller 411, and the memory controller 411 may be connected to the first on-chip memory 311. Thus, the first test control information generated by the first test controller 412 may be transmitted to the memory controller 411, and the memory controller 411 may select the control information to output from the access control information generated by itself and the first test control information generated by the first test controller 412.

[0071] The control information output by the memory controller 411 can be considered as the control information output by the controller 312 of the first chiplet 310. In addition to being transmitted to the first on-chip memory of the first chiplet to control the first on-chip memory, the control information output by the memory controller 411 is also transmitted to the second chiplet via the first interconnection interface 301 connecting the first and second chiplets.

[0072] The access control information generated by the storage controller 411 itself is used to control access to the on-chip memory in the normal operating mode, while the first test control information generated by the first test controller 412 is used to test the first on-chip memory in the test mode; therefore, the storage controller 411 can select the access control information generated by itself for output in the normal operating mode, and select the first test control information of the first test controller for output in the test mode.

[0073] In a further optional implementation, combined with Figure 4A As shown, the storage controller 411 can be provided with a first multiplexer 401. A multiplexer (MUX) is a digital switching device in an integrated circuit that can select one signal from a plurality of input signals for output, that is, the multiplexer can selectively pass one of the plurality of input signals to the output. In an embodiment of the present application, the first multiplexer can select the output control information from the access control information generated by the storage controller 411 and the first test control information generated by the first test controller 412. For example, the first multiplexer can select the access control information generated by the storage controller 411 for output in normal working mode, and select the first test control information of the first test controller 412 for output in test mode.

[0074] Furthermore, the first on-chip memory 311 may respond to the control information output by the memory controller 411 (e.g., the first multiplexer 401 in the memory controller 411) and feed back the response result to the memory controller 411. If the response result of the first on-chip memory 311 is in accordance with the access control information generated by the memory controller 411, the memory controller 411 may process the response result on its own; if the response result of the first on-chip memory 311 is in accordance with the first test control information generated by the first test controller 412, the memory controller 411 needs to further return the response result to the first test controller 412 so that the first test controller 412 can generate a test result for the first on-chip memory.

[0075] For example, when the response result of the first on-chip memory 311 corresponds to the first test control information generated by the first test controller 412, the response result of the first on-chip memory 311 can be returned to the first test controller 412 via the first multiplexer 401 of the memory controller 411, so that the first test controller 412 can generate a test result for the first on-chip memory. For example, the first test controller 412 can write test data to the memory cells of the first on-chip memory 311 using the first write test control information in the first test control information; and read test data from the memory cells of the first on-chip memory 311 using the first read test control information in the first test control information, thereby obtaining the read test data and valid flags fed back by the memory cells of the first on-chip memory 311. Furthermore, by comparing the test data read from the memory cells of the first on-chip memory 311 with the written test data to determine whether they are consistent, a test result is obtained to determine whether there are abnormal memory cells in the first on-chip memory 311. If an abnormal memory cell is present in the first on-chip memory, the test controller 412 can provide location information of the abnormal memory cell.

[0076] In the case where the controller 312 is divided into the memory controller 411 and the first test controller 412, and the control information output by the memory controller 411 serves as the control information output by the controller 312, the control information output by the controller 312 is not only transmitted to the first on-chip memory 311, but is also transmitted to the second chip via the first interconnect interface connecting the first chip and the second chip. Therefore, the control information output by the memory controller 411 can also be transmitted to the second chip via the first interconnect interface connecting the first chip and the second chip. In other words, the memory controller 411 can select the control information to output based on the access control information generated by itself and the first test control information generated by the first test controller 412. The selected control information is not only transmitted to the first on-chip memory 311, but is also transmitted to the second chip via the first interconnect interface connecting the first chip and the second chip.

[0077] For example, when the memory controller 411 (such as the first multiplexer 401 in the memory controller 411) is in normal operating mode, the access control information generated by the memory controller 411 is selected for output, and the control information transmitted to the first on-chip memory 311 is the access control information generated by the memory controller; correspondingly, through the first interconnection interface connecting the first chiplet and the second chiplet, the control information transmitted to the second chiplet is the access control information generated by the memory controller.

[0078] For another example, the memory controller 411 (such as the first multiplexer 401 in the memory controller 411) selects the first test control information of the first test controller 412 for output in the test mode, and the control information transmitted to the first on-chip memory 311 is the first test control information of the first test controller 412; correspondingly, through the first interconnection interface connecting the first chiplet and the second chiplet, the control information transmitted to the second chiplet is the first test control information of the first test controller 412.

[0079] That is to say, in an optional implementation, the control information transmitted by the controller of the first chip to the second chip through the first interconnection interface connecting the first chip and the second chip can be divided into: access control information generated by the storage controller of the first chip in normal working mode, and first test control information generated by the first test controller of the first chip in test mode.

[0080] Accordingly, if the second chiplet chooses to use the control information output by the controller of the first chiplet to control the second on-chip memory, and if the control information output by the controller is access control information of the memory controller, the second chiplet can control the second on-chip memory to perform read and write access control, etc., using the access control information of the memory controller of the first chiplet. For example, in normal operating mode, cross-chiplet access control such as read and write access control to the second on-chip memory is implemented.

[0081] If the second chiplet chooses to use the control information output by the controller of the first chiplet to control the second on-chip memory, then when the control information output by the controller is the first test control information of the first test controller, the second chiplet can control the second on-chip memory using the first test control information of the first test controller, thereby implementing cross-chiplet testing of the second on-chip memory. For example, in test mode, cross-chiplet testing of the second on-chip memory can be implemented to detect whether there are abnormal memory cells in the second on-chip memory and, if there are abnormal memory cells in the second on-chip memory, provide location information of the abnormal memory cells.

[0082] It should be noted that when the second chip chooses to use the control information output by the controller of the first chip to control the second on-chip memory, regardless of whether the control information output by the controller of the first chip is the access control information generated by the storage controller or the first test control information generated by the first test controller, whether the response result of the second on-chip memory to the control information can be fed back to the first chip can indicate whether the connection between the first interconnection interface of the first chip and the second chip is normal.

[0083] It can be seen that, during the chip testing phase, the embodiment of the present application supports the first chiplet to perform self-tests on the first on-chip memory, and supports the transmission of the first test control information generated by the first test controller in the first chiplet to the second chiplet via the first interconnection interface between the first chiplet and the second chiplet, so as to perform cross-chip testing on the second on-chip memory in the second chiplet. In addition, during the normal operation phase of the chip, the embodiment of the present application supports cross-chip access control on the second on-chip memory in the second chiplet, in addition to controlling access to the first on-chip memory in the first chiplet through the access control information generated by the storage controller. Thus, when the first chip implements self-testing and access control of the first on-chip memory, the first chip can detect whether the connection between the first interconnection interface of the first chip and the second chip is normal through the second on-chip memory in the second chip to determine whether the cross-chip test or access control has a corresponding response, so that the chip test can cover the test of the first on-chip memory inside the first chip, the test of the connection between the first chip and the second chip, and the test of the second on-chip memory inside the second chip (the above mainly tests the second on-chip memory across chips to cover the test of the second on-chip memory inside the second chip), thereby improving the coverage of the chip test.

[0084] In a further optional implementation, the embodiment of the present application may also support the second chip to perform self-test on the second on-chip memory through MBIST logic; thus, the second chip can select information for controlling the second on-chip memory at different stages from the test control information generated by the built-in MBIST logic and the control information transmitted by the controller of the first chip, so as to realize control of the second on-chip memory at different stages. As an optional implementation, Figure 4B Another example diagram of the chip provided in the embodiment of the present application is shown as an example. Figure 4A and Figure 4B As shown, in Figure 4B As shown, the second chip 320 may further include a second test controller 421 and a second multiplexer 422 .

[0085] The second test controller 421 can be the test controller provided in the second core grain, for the second on-chip memory of the second core grain is carried out self-test. The second test controller is for example the second mbist controller of the support mbist logic provided in the second core grain. In optional implementation, the second test controller 421 can produce the second test control information (including but not limited to the second write test control information and the second read test control information etc.), so that the second on-chip memory of the second core grain is carried out self-test.

[0086] For ease of explanation, the embodiment of the present application refers to the test control information generated by the second test controller as second test control information, the write test control information corresponding to the second test control information as second write test control information, and the read test control information corresponding to the second test control information as second read test control information.

[0087] In an embodiment of the present application, the second test control information generated by the second test controller 421 can be transmitted to the second multiplexer 422, and the control information output by the controller of the first chip is transmitted to the second multiplexer 422 of the second chip through the first interconnection interface connecting the first chip and the second chip; thereby, the second multiplexer can select information for controlling the second on-chip memory from the control information output by the controller of the first chip and the second test control information generated by the second test controller.

[0088] It should be noted that the second test controller and the second multiplexer can be connected via the internal connection circuit of the second chiplet, so that the second test control information generated by the second test controller can be transmitted to the second multiplexer via the internal connection circuit of the second chiplet. The control information output by the controller of the first chiplet needs to be transmitted to the second multiplexer of the second chiplet via the first interconnection interface connecting the first chiplet and the second chiplet.

[0089] In an optional implementation, the second chip can perform a self-test on the second on-chip memory during manufacturing but before packaging (e.g., before 3D packaging). In this case, the second multiplexer can choose to use the second test control information generated by the second test controller to control the second on-chip memory. After packaging (e.g., after 3D packaging), the second chip can be interconnected with the first chip through an interconnect interface to obtain information transmitted from the first chip. In this case, the second multiplexer can choose to use the control information output by the controller of the first chip to control the second on-chip memory, so as to enable the first chip to perform cross-chip testing or access control on the second on-chip memory of the second chip.

[0090] Based on this, for the second chip, the second multiplexer of the second chip can select the second test control information generated by the second test controller in the test stage before packaging (for example, the test stage before 3D packaging) to control the second on-chip memory; after packaging (for example, after 3D packaging), the second multiplexer can select the control information output by the controller of the first chip to control the second on-chip memory in the test stage after packaging (for example, the test stage after 3D packaging) and the normal operation stage of the chip.

[0091] In a further optional implementation, the test phase performed before packaging may include but is not limited to a wafer test phase, so that during the wafer test phase, the second chip can perform a self-test on the second on-chip memory. For example, during the wafer test phase, the second test controller of the second chip can generate second test control information and pass it to the second multiplexer of the second chip; thus, during the wafer test phase, the second multiplexer can select the second test control information of the second test controller to control the second on-chip memory. After packaging, the second chip (e.g., the second multiplexer of the second chip) can select the control information output by the controller of the first chip to control the second on-chip memory during the test phase after packaging and the normal working mode.

[0092] It should be noted that the first test controller in the first chip generates the first test control information in the test mode, and the test mode can be divided into multiple test phases, including but not limited to the test phase before packaging and the test phase after packaging. In other words, the test phase before packaging and the test phase after packaging are test phases in the test mode and can be regarded as the phases in which the first test controller in the first chip generates the first test control information; while the second test controller in the second chip generates the second test control information in the test phase before packaging.

[0093] In an optional implementation, for packaging technologies such as 3D packaging, there are test stages before packaging, such as the wafer test stage, and test stages after packaging, such as the final test stage and system startup self-test. The wafer test stage refers to the test stage before the wafer is cut and packaged, which is used to screen out wafers with production quality issues; the final test stage refers to the test stage after the wafer is cut and packaged, which is used to screen out packaged chips with production quality issues.

[0094] Furthermore, in an optional implementation, the controller of the first chip selects the access control information generated by the storage controller of the first chip for output in the normal working mode. Therefore, in the normal working mode, the control information transmitted by the controller of the first chip to the second chip is the access control information generated by the storage controller of the first chip; thus, in the normal working mode, the second multiplexer of the second chip selects the information for controlling the second on-chip memory as: the access control information generated by the storage controller of the first chip.

[0095] Furthermore, in an optional implementation, based on the controller of the first chip in test mode, the first test control information generated by the first test controller is selected for output. Therefore, in the test stage after packaging (for example, the final test stage, the system startup self-test stage), the control information transmitted by the controller of the first chip to the second chip is the first test control information generated by the first test controller; thus, in the test stage after packaging, the second multiplexer of the second chip selects the information for controlling the second on-chip memory as: the first test control information generated by the first test controller of the first chip.

[0096] It can be seen that in an optional implementation, the information selected by the second chiplet (for example, the second multiplexer of the second chiplet) for controlling the second on-chip memory can be divided into the following cases:

[0097] In the first case, in a test phase before packaging (eg, a wafer test phase), the second test control information generated by the second test controller of the second chip performs a self-test on the second on-chip memory in the second chip.

[0098] Accordingly, the response result of the second on-chip memory to the second test control information can be returned to the second test controller through the second multiplexer, so that the second test controller generates the test result of the second on-chip memory. For example, the second test controller can write test data to the storage unit of the second on-chip memory through the second write test control information in the second test control information; and read test data from the storage unit of the second on-chip memory through the second read test control information in the second test control information, thereby obtaining the read test data and valid flag fed back by the storage unit of the second on-chip memory; and then compare the test data read from the storage unit of the second on-chip memory with the written test data to determine whether they are consistent, so as to obtain the test result of the second on-chip memory. The test result of the second on-chip memory can provide information on whether there is an abnormal storage unit in the second on-chip memory, and provide location information of the abnormal storage unit when there is an abnormal storage unit in the second on-chip memory.

[0099] Case 2: In a normal operating mode, the access control information generated by the memory controller of the first chiplet performs cross-chiplet access control on the second on-chip memory in the second chiplet.

[0100] Accordingly, if the connection between the first interconnection interface of the first chiplet and the second chiplet is normal, the second on-chip memory's response result to the storage controller's access control information can be returned to the storage controller of the first chiplet, so that the storage controller can process the response result normally and confirm that the connection between the first interconnection interface of the first chiplet and the second chiplet is normal. If the connection between the first interconnection interface of the first chiplet and the second chiplet is abnormal, the second on-chip memory cannot obtain the second on-chip memory's response result to the access control information, thereby confirming that the connection between the first interconnection interface of the first chiplet and the second chiplet is abnormal.

[0101] Case 3: In the test phase after packaging (eg, the final test phase, the system startup self-test phase), the first test control information generated by the first test controller of the first chiplet performs a cross-chiplet test on the second on-chip memory in the second chiplet.

[0102] Correspondingly, when the first interconnection interface between the first chip and the second chip is connected normally, the response result of the second on-chip memory to the first test control information of the first test controller can be returned to the first test controller; for example, the response result of the second on-chip memory to the first test control information can be fed back to the memory controller of the first chip (for example, the first multiplexer in the memory controller of the first chip) through the first interconnection interface between the first chip and the second chip, and further fed back to the first test controller by the memory controller (for example, the first multiplexer in the memory controller).

[0103] In an optional implementation, based on the response result of the second on-chip memory to the first test control information, the first test controller can generate a test result of the second on-chip memory. For example, the first test controller can write test data to the storage unit of the second on-chip memory through the first write test control information in the first test control information; and read test data from the storage unit of the second on-chip memory through the first read test control information in the first test control information, thereby obtaining the read test data and valid flag fed back by the storage unit of the second on-chip memory; and then compare the test data read from the storage unit of the second on-chip memory with the written test data to determine whether they are consistent, so as to obtain a test result of whether there is an abnormal storage unit in the second on-chip memory, and when there is an abnormal storage unit in the second on-chip memory, provide the location information of the abnormal storage unit, etc.

[0104] Accordingly, if the connection between the first interconnection interface of the first chiplet and the second chiplet is abnormal, the first test controller cannot obtain the response result of the second on-chip memory to the first test control information, thereby confirming that the connection between the first interconnection interface of the first chiplet and the second chiplet is abnormal.

[0105] It can be seen that the embodiments of the present application support self-testing of the built-in on-chip memory by each chip before packaging; after packaging, the embodiments of the present application support self-testing (such as self-testing in the final test stage) and access control (such as access control in normal working mode) of the first on-chip memory of the first chip, and support cross-chip testing (such as cross-chip testing in the final test stage) and access control (such as cross-chip access control in normal working mode) of the second on-chip memory in the second chip by the first chip through the interconnection interface between the first chip and the second chip, thereby improving the coverage of chip testing.

[0106] In a further optional implementation, when an embodiment of the present application detects that an on-chip memory of a core particle has a defective abnormality, the embodiment of the present application supports repairing the on-chip memory with a defective abnormality through memory repair logic. The memory repair logic refers to reserving redundant storage units (such as redundant rows and redundant columns) in the on-chip memory, so that when an abnormal storage unit is detected in the on-chip memory, the redundant storage unit is used to replace the abnormal storage unit, thereby repairing the on-chip memory. For example, the use of redundant storage units to replace abnormal storage units can replace abnormal rows and abnormal columns of abnormal storage units with redundant rows and redundant columns.

[0107] To facilitate understanding of the memory repair logic, in an optional implementation, Figure 5 An exemplary diagram of a core particle with memory repair logic provided by an embodiment of the present application is shown, combined with Figure 2 and Figure 5 As shown, in Figure 5 In the shown chiplet, the chiplet may further include a repair configuration register 511 , a non-volatile controller 512 , and a non-volatile memory 513 .

[0108] The repair configuration register 511 is a register for storing the repair configuration information of the on-chip memory, and can temporarily store the repair configuration information of the on-chip memory. The repair configuration register is, for example, a BISR (Built In Self Repair) register.

[0109] In an optional implementation, the repair configuration information stored in the repair configuration register may originate from a test controller. For example, after the test controller tests the on-chip memory and obtains the test results, it may generate repair configuration information for the on-chip memory based on the test results of the on-chip memory, and store the repair configuration information in the repair configuration register. Optionally, the repair configuration information may include information about the abnormal storage unit of the on-chip memory (such as location information), and information about the redundant storage unit used to replace the abnormal storage unit (such as location information of the redundant storage unit used to replace the abnormal storage unit, etc.). For the relevant content of the test controller testing the on-chip memory and obtaining the test results, please refer to the relevant description in the corresponding part of the previous text, which will not be repeated here.

[0110] In an optional implementation, combined with Figure 5 Shown, the test controller in the test controller can generate the test result of on-chip memory from machine (for example mbist controller from machine), and based on the test result of on-chip memory, generates the repair configuration information of on-chip memory.And then the repair configuration information that the test controller generates from machine can be passed to the test controller main frame (for example mbist controller main frame), will repair configuration information and be saved in the repair configuration register by the test controller main frame; Perhaps, also can be saved in the repair configuration register by the test controller slave with the repair configuration information that generates.

[0111] In a further optional implementation, the repair configuration register can be connected to the repair configuration port of the on-chip memory, so that based on the repair configuration information stored in the repair configuration register, the repair configuration register can control the on-chip memory to use redundant storage units to replace abnormal storage units through the repair configuration port of the on-chip memory to achieve the purpose of repairing the on-chip memory.

[0112] In a further optional implementation, combined with Figure 5 As shown, the repair configuration information can also be burned into the non-volatile memory 513 through the non-volatile controller 512, so that after the computer system loaded with the chip is restarted and reset, the repair configuration information burned in the non-volatile memory can be reloaded into the repair configuration register through the non-volatile controller, thereby repairing the on-chip memory after the computer system is restarted and reset without retesting the on-chip memory.

[0113] A non-volatile memory is a non-volatile storage device that permanently stores information, maintaining the stored information even during a power outage. For example, an eFUSE (electronic fuse) array is an example of a non-volatile memory. A non-volatile controller is a controller corresponding to the non-volatile memory, such as an eFUSE controller corresponding to an eFUSE array.

[0114] In an optional implementation, burning the repair configuration information into a non-volatile memory (such as an eFUSE array) can be achieved by controlling a non-volatile controller (such as an eFUSE controller) through a test access port. For example, a debugger (such as a JTAG debugger) or a test machine can read the repair configuration information stored in the repair configuration register through a test access port, and then burn the repair configuration information into the non-volatile memory through the non-volatile controller to achieve the preservation of the repair configuration information in the non-volatile memory. Alternatively, after the test controller host obtains the repair configuration information transmitted by the test controller slave, the test controller host can forward the repair configuration information to the non-volatile controller, which saves the repair configuration information to its own memory and burns it into the non-volatile memory.

[0115] In an optional implementation, based on memory repair logic, Figure 6 Another example diagram of the chip provided in the embodiment of the present application is shown as an example. Figure 4B and Figure 6 As shown, in Figure 6 As shown, the first chiplet may further include: a first repair configuration register 611 , a first non-volatile controller 612 , and a first non-volatile memory 613 .

[0116] For ease of explanation, the repair configuration register set in the first chip is called the first repair configuration register, and the first repair configuration register is, for example, the first BISR register; the non-volatile controller set in the first chip is called the first non-volatile controller, and the first non-volatile controller is, for example, the first eFUSE controller; the non-volatile memory set in the first chip is called the first volatile memory, and the first volatile memory is, for example, the first eFUSE array.

[0117] As an optional implementation, in an embodiment of the present application, the first test controller in the first chip can generate first repair configuration information of the first on-chip memory. For ease of explanation, the repair configuration information of the first on-chip memory can be referred to as the first repair configuration information.

[0118] In an optional implementation, the first repair configuration information generated by the first test controller is obtained based on the response of the first on-chip memory to the first test control information. For example, in test mode, the first multiplexer selects the first test control information of the first test controller for output, so that the response result of the first on-chip memory is corresponding to the first test control information generated by the first test controller; further, the first test controller can generate a test result of the first on-chip memory based on the response result of the first on-chip memory to the first test control information, and generate the first repair configuration information of the first on-chip memory based on the test result of the first on-chip memory. For example, a first test controller slave (e.g., a first MBIST controller slave) in the first test controller can generate a test result of the first on-chip memory based on the response result of the first on-chip memory to the first test control information; and the first test controller slave can generate the first repair configuration information of the first on-chip memory based on the test result of the first on-chip memory. The relevant content of the test controller generating the repair configuration information of the on-chip memory can be referred to the description of the corresponding part above and will not be elaborated here.

[0119] As an optional implementation, on the one hand, the first repair configuration information generated by the first test controller can be saved to the first repair configuration register 611; for example, the first test controller slave in the first test controller can save the generated first repair configuration information to the first repair configuration register; for another example, the first test controller host in the first test controller can obtain the first repair configuration information generated by the first test controller slave, and the first test controller host saves the first repair configuration information to the first repair configuration register 611.

[0120] On the other hand, the first repair configuration information generated by the first test controller can be saved to the first non-volatile memory 613 via the first non-volatile controller 612. For example, the first test controller host can obtain the first repair configuration information generated by the first test controller slave, so that the first test controller host can forward the first repair configuration information to the first non-volatile memory; further, the first non-volatile memory can save the first repair configuration information to its own memory and burn it into the first non-volatile memory.

[0121] Based on the first repair configuration information stored in the first non-volatile memory, when the system restarts, the first non-volatile controller can read the first repair configuration information stored in the first non-volatile memory and write the first repair configuration information into the first repair configuration register. For example, when the system restarts, the first non-volatile controller can read the first repair configuration information from the first non-volatile memory, load it into its own memory, and write the first repair configuration information into the first repair configuration register. Based on the first repair configuration information written by the first non-volatile controller to the first repair configuration register when the system restarts, the embodiments of the present application can repair the first on-chip memory after the system restarts without retesting the first on-chip memory.

[0122] It can be seen that the first repair configuration information stored in the first repair configuration register comes from the first repair configuration information written by the first test controller after testing the first on-chip memory, and the first repair configuration information reprinted from the first non-volatile memory by the first non-volatile controller when the system is restarted.

[0123] Furthermore, the first repair configuration register can repair the first on-chip memory based on the saved first repair configuration information. For example, after the first test controller tests the first on-chip memory, the first repair configuration register can repair the first on-chip memory based on the first repair configuration information written by the first test controller; when the system is restarted, the first repair configuration register can repair the first on-chip memory based on the first repair configuration information written by the first non-volatile controller.

[0124] In an optional implementation, based on the first repair configuration information stored in the first repair configuration register, the first repair configuration register can control the first on-chip memory to use redundant storage units to replace abnormal storage units through the repair configuration port of the first on-chip memory, so as to achieve the purpose of repairing the first on-chip memory.

[0125] In a further optional implementation, the embodiment of the present application can support re-testing (for example, re-performing a BIST test) when the system is restarted, and the re-test is based on the repair of the on-chip memory using the repair configuration information stored in the non-volatile memory. For example, when the system is restarted, the embodiment of the present application can write the repair configuration information stored in the non-volatile memory back to the repair configuration register through the non-volatile controller, so that the on-chip memory is repaired based on the written repair configuration information by the repair configuration register; then, the test is re-performed (for example, re-performing a BIST test). Of course, in addition to using the repair configuration information stored in the non-volatile memory to repair the on-chip memory, the embodiment of the present application can also support regenerating the repair configuration information based on the newly discovered defect anomaly of the on-chip memory when the system is restarted to repair the on-chip memory.

[0126] In the above optional implementation, the embodiment of the present application supports repairing the on-chip memory when the system is restarted (it may be repaired based on the repair configuration information stored in the non-volatile memory, or it may be repaired based on the newly discovered defect anomaly of the on-chip memory to regenerate the repair configuration information and perform the repair), and then retesting, so that the system can be successfully started only when it is confirmed through the retest that the on-chip memory has been successfully repaired.

[0127] It should be noted that the embodiment of the present application provides a function of repairing on-chip memory based on the repair configuration information stored in the non-volatile memory because: the defect anomaly of the memory is related to the working environment factors such as the operating voltage and the operating temperature. The defect anomaly of the memory tested during the mass production test may not necessarily appear every time the system is restarted; for example, the defect anomaly of the memory tested during the mass production test may not be detected when the system is restarted; however, after the chip has been working for a period of time, due to changes in the operating temperature and the operating voltage, the defect anomaly of the memory tested during the mass production test may appear again. Therefore, during the mass production test, the embodiment of the present application can perform tests (such as BIST tests) under a variety of working voltage and temperature conditions to save the repair configuration information corresponding to the possible memory anomaly found in the non-volatile memory.

[0128] That is to say, the defect anomaly in the memory may not always exist, but may be affected by working environment factors (such as working voltage and temperature), causing the defect anomaly of the memory to appear or disappear under different working environment factors. Therefore, in the mass production test phase, using BIST technology to test the memory under a variety of working environment factors can help discover defect anomalies that may appear in actual use. The repair configuration information corresponding to the memory anomaly discovered in the mass production test phase is saved in the non-volatile memory. No matter when the system is restarted, the embodiment of the present application can read the repair configuration information pre-saved in the non-volatile memory, thereby dynamically responding to the memory defect anomaly that may reappear due to changes in working environment factors, ensuring the reliability and stability of the memory.

[0129] In a further optional implementation, combined with Figure 6 As shown, the first chip may further include: a third multiplexer 614. The first repair configuration information generated by the first test controller and required to be saved to the first repair configuration register may be passed to the third multiplexer, so that the third multiplexer selects to save it to the first repair configuration register; in an optional implementation, the embodiment of the present application supports the first test controller slave in the first test controller, or the first test controller master, to pass the first repair configuration information to the third multiplexer. In addition, the first repair configuration information read from the first non-volatile memory by the first non-volatile controller may be passed to the third multiplexer, so that the third multiplexer selects to save it to the first repair configuration register.

[0130] It can be seen that the input of the third multiplexer can be the first repair configuration information generated by the first test controller, or the first repair configuration information read by the first non-volatile controller from the first non-volatile memory; thus, the third multiplexer can select the input first repair configuration information when any input has information, and save it to the first repair configuration register. For example, if the first test controller performs a test on the first on-chip memory, the first test controller can generate the corresponding first repair configuration information and pass it to the third multiplexer. At this time, the third multiplexer can select the first repair configuration information generated by the first test controller and save it to the first repair configuration register. For another example, when the system restarts, the first non-volatile controller can load the first repair configuration information from the first non-volatile memory and pass it to the third multiplexer. At this time, the third multiplexer can select the first repair configuration information passed by the first non-volatile controller and save it to the first repair configuration register.

[0131] It should be noted that the multiplexer selects one output from multiple inputs through hardware logic, which can reduce the chip's demand for control lines. Therefore, using a third multiplexer to select and save the first repair configuration register generated by the first test controller to the first repair configuration register, and to select and save the first repair configuration information loaded by the first non-volatile controller to the first repair configuration register, can simplify the hardware design.

[0132] In other possible implementations, the first repair configuration register can be set in the first test controller, so that the first test controller can write the generated first repair configuration information into the built-in first repair configuration register, and output the repair configuration information to the first on-chip memory through the built-in first repair configuration register, thereby realizing a direct repair channel between the first test controller and the first on-chip memory. In the case where the first repair configuration register is built into the first test controller, in an optional implementation, the embodiment of the present application can also support a direct path between the first non-volatile controller and the first repair configuration register, so that when the system is restarted, the first non-volatile controller can write the first repair configuration information loaded from the first non-volatile memory into the first repair configuration register through a direct path without passing through a third multiplexer.

[0133] In a further optional implementation, combined with Figure 6 As shown, the second chiplet may further include: a second repair configuration register 621 , a fourth multiplexer 622 , a second non-volatile controller 623 , a second non-volatile memory 624 , and a fifth multiplexer 625 .

[0134] For ease of explanation, the repair configuration register set in the second chip is called the second repair configuration register, and the second repair configuration register is, for example, the second BISR register; the non-volatile controller set in the second chip is called the second non-volatile controller, and the second non-volatile controller is, for example, the second eFUSE controller; the non-volatile memory set in the second chip is called the second non-volatile memory, and the second non-volatile memory is, for example, the second eFUSE array.

[0135] As an optional implementation, in an embodiment of the present application, the first test controller in the first chip can generate second repair configuration information for the second on-chip memory. For ease of explanation, the repair configuration information of the second on-chip memory can be referred to as the second repair configuration information. In this optional implementation, the second repair configuration information generated by the first test controller is obtained based on the response of the second on-chip memory to the first test control information.

[0136] For example, in the test phase after packaging (such as the final test phase, the system startup self-test phase), the first test control information generated by the first test controller can be transmitted to the second chip to perform cross-chip testing on the second on-chip memory in the second chip; thereby, the second on-chip memory can generate a response result for the first test control information and pass it back to the first test controller. For example, the response result of the second on-chip memory to the first test control information can be fed back to the memory controller of the first chip through the first interconnection interface between the first chip and the second chip, and further fed back to the first test controller by the memory controller; further, the first test controller can generate a test result of the second on-chip memory based on the response result of the second on-chip memory to the first test control information, and generate second repair configuration information of the second on-chip memory based on the test result of the second on-chip memory.

[0137] Example, the first test controller in the first test controller can generate the test result of the second on-chip memory based on the response result of the second on-chip memory for the first test control information from the machine (for example the first mbist controller from the machine); And the first test controller can generate the second repair configuration information of the second on-chip memory based on the test result of the second on-chip memory from the machine. The relevant content of the repair configuration information that the test controller generates the on-chip memory can be referred to the description of the corresponding part above, and will not be expanded here.

[0138] In an optional implementation, combined with Figure 6 As shown, the second repair configuration information generated by the first test controller can be transmitted to the fourth multiplexer 622 of the second chiplet via the second interconnection interface 601 connecting the first chiplet and the second chiplet, so that the fourth multiplexer selects and saves the information into the second repair configuration register 621. The second interconnection interface 601 can be regarded as an interconnection interface between chiplets for configuring the repair configuration register (e.g., an interconnection interface between chiplets for transmitting repair configuration information), and is a type of interconnection interface for connecting between chiplets.

[0139] As an example, the first test controller slave in the first test controller can generate second repair configuration information and pass it to the first test controller host in the first test controller, so that the first test controller host can pass the second repair configuration information to the fourth multiplexer through the second interconnection interface connecting the first core particle and the second core particle.

[0140] As an optional implementation, in an embodiment of the present application, a second test controller in the second chip can generate second repair configuration information for the second on-chip memory. In the optional implementation, the second repair configuration information generated by the second test controller is obtained based on a response of the second on-chip memory to the second test control information.

[0141] For example, in the test stage before packaging (such as the wafer test stage), the second test control information generated by the second test controller can perform self-testing on the second on-chip memory; thereby, the second on-chip memory can generate a response result for the second test control information and pass it back to the second test controller; further, the second test controller can generate a test result of the second on-chip memory based on the response result of the second on-chip memory to the second test control information, and generate second repair configuration information of the second on-chip memory based on the test result of the second on-chip memory.

[0142] Example, the second test controller in the second test controller can generate the test result of the second on-chip memory based on the response result of the second test control information from the machine (for example the second mbist controller is from the machine); And the second test controller can generate the second repair configuration information of the second on-chip memory based on the test result of the second on-chip memory from the machine.The relevant content that test controller generates the repair configuration information of on-chip memory can refer to the description of preceding corresponding part, and no longer expands here.

[0143] In an optional implementation, combined with Figure 6 As shown, the second repair configuration information generated by the second test controller can be passed to the fourth multiplexer 622 so that the fourth multiplexer selects to be saved in the second repair configuration register. For example, the second test controller can pass the generated second repair configuration information to the fourth multiplexer through the internal connection line of the second core particle. As an example, the second test controller slave in the second test controller can generate the second repair configuration information, and the second test controller slave passes the generated second repair configuration information to the fourth multiplexer. Of course, the embodiment of the present application can also support the second test controller master in the second test controller to pass the second repair configuration information to the fourth multiplexer.

[0144] As an optional implementation, the fourth multiplexer may select the second repair configuration information from the second repair configuration information generated by the first test controller and the second repair configuration information generated by the second test controller, and save the selected second repair configuration information into the second repair configuration register.

[0145] For example, the fourth multiplexer can select the second repair configuration information generated by the second test controller in the test stage before packaging (such as the wafer test stage) and save it to the second repair configuration register; in the test stage after packaging (such as the final test stage, the system startup self-test stage, etc.), select the second repair configuration information generated by the first test controller and save it to the second repair configuration register.

[0146] In an optional implementation, based on the second repair configuration information stored in the second repair configuration register, the second repair configuration register can repair the second on-chip memory. For example, based on the second repair configuration information stored in the second repair configuration register, the second repair configuration register can control the second on-chip memory to replace the abnormal memory cell with a redundant memory cell through the repair configuration port of the second on-chip memory, thereby achieving the purpose of repairing the second on-chip memory.

[0147] In a further optional implementation, the second repair configuration information generated by the first test controller can also be passed to the fifth multiplexer 625 of the second core particle through the second interconnection interface 601 connecting the first core particle and the second core particle. For example, the first test controller host in the first test controller can pass the second repair configuration information to the fifth multiplexer 625 through the second interconnection interface connecting the first core particle and the second core particle. In addition, the second repair configuration information generated by the second test controller can be passed to the fifth multiplexer 625 (for example, the second test controller can pass the generated second repair configuration information to the fifth multiplexer through the internal connection line of the second core particle). For example, the second test controller host of the second test controller can pass the second repair configuration information to the fifth multiplexer 625.

[0148] Furthermore, the fifth multiplexer 625 may select the second repair configuration information from the second repair configuration information generated by the first test controller and the second repair configuration information generated by the second test controller, and output the selected second repair configuration information to the second non-volatile controller 623 .

[0149] For example, the fifth multiplexer 625 can select the second repair configuration information generated by the second test controller to be output to the second non-volatile controller 623 in the test stage before packaging (such as the wafer test stage); and select the second repair configuration information generated by the first test controller to be output to the second non-volatile controller 623 in the test stage after packaging (such as the final test stage, the system startup self-test stage, etc.).

[0150] Based on the second repair configuration information output by the fifth multiplexer 625 to the second non-volatile controller 623, the second non-volatile controller 623 may save the second repair configuration information output by the fifth multiplexer to the second non-volatile memory 624. For example, after obtaining the second repair configuration information output by the fifth multiplexer, the second non-volatile controller 623 may save the second repair configuration information to its own memory and burn it into the second non-volatile memory 624 it controls.

[0151] Based on the second repair configuration information stored in the second non-volatile memory, when the system restarts, the second non-volatile controller can read the second repair configuration information stored in the second non-volatile memory and write it to the second repair configuration register. For example, when the system restarts, the second non-volatile controller can read the second repair configuration information from the second non-volatile memory, then load it into its own memory, and write it to the second repair configuration register. Based on the second repair configuration information written by the second non-volatile controller to the second repair configuration register when the system restarts, the embodiment of the present application can repair the second on-chip memory after the system restarts without retesting the second on-chip memory.

[0152] In an optional implementation, combined with Figure 6 As shown, when the system restarts, the second non-volatile controller can read the second repair configuration information from the second non-volatile memory and write the second repair configuration information into the second repair configuration register through the fourth multiplexer 622. For example, when the system restarts, the second repair configuration information read from the second non-volatile memory by the second non-volatile controller can be passed to the fourth multiplexer, so that the fourth multiplexer selects to write the second repair configuration information passed by the second non-volatile controller into the second repair configuration register.

[0153] In a further optional implementation, the embodiment of the present application supports each chip to be connected to the peripheral device through the test access port to realize the configuration of the test controller and the configuration of the non-volatile controller. As an optional implementation, Figure 7 Another example diagram of the chip provided in the embodiment of the present application is shown as an example. Figure 6 and Figure 7 As shown, the first chiplet may include a first test access port 711, and the second chiplet may include a second test access port 712. For ease of explanation, the test access port provided in the first chiplet may be referred to as the first test access port, and the test access port provided in the second chiplet may be referred to as the second test access port. The first test access port 711 of the first chiplet and the second test access port 712 of the second chiplet may communicate via a third interconnection interface 701 connecting the first chiplet and the second chiplet. The third interconnection interface may be considered an interconnection interface for test configuration between chiplets (e.g., an interconnection interface for test configuration such as JTAG between chiplets), and is a type of interconnection interface for connecting between chiplets.

[0154] As an optional implementation, the first test access port can be used to configure the first test controller in the first chip, and / or the first non-volatile controller. The second test access port can be used to configure the second test controller in the second chip, and / or the second non-volatile controller. The information used for configuration by the first test access port and the second test access port can come from a peripheral device, and the peripheral device is connected to the peripheral interface of the chip. For example, the peripheral device can be a JTAG debugger, and the JTAG debugger can pass the information used for configuration (such as information for configuring the test controller, and / or information for configuring the non-volatile controller) to the first test access port and the second test access port through the JTAG interface, so that the first test access port configures the first test controller and / or the first non-volatile controller, and the second test access port configures the second test controller and / or the second non-volatile controller.

[0155] In the optional implementation example, Figure 8A The following is an exemplary diagram showing an implementation example of the chip provided in the embodiment of the present application, combined with Figure 7 and Figure 8A As shown, in Figure 8A In this example, the first core-grain can be a core core-grain, i.e., a core slice, and is located at the bottom layer of the chip (i.e., the first core-grain can be a bottom-layer core-grain and a core slice); the second core-grain can be a cache core-grain, i.e., a cache slice, and the cache slice is at a higher level than the core slice. In this embodiment of the present application, the core slice can perform cross-core testing and access control on the on-chip memory in the cache slice.

[0156] exist Figure 8A In the example, the core chip can be connected to the chip packaging substrate 103 and communicate with the peripherals through the peripheral interface 104 provided on the packaging substrate to obtain configuration information transmitted by the peripherals such as the JTAG debugger through the JTAG interface or other peripheral interfaces; furthermore, the first test access port in the core chip can configure the first test controller and / or the first non-volatile controller in the core chip. The first test access port in the core chip can also transmit the configuration information to the second test access port in the cache chip through the third interconnection interface 701 connecting the core chip and the cache chip, so that the second test access port in the cache chip can configure the second test controller and / or the second non-volatile controller in the cache chip.

[0157] Figure 8A Parts in the example that are similar in structure to those described above can be referenced to each other and will not be expanded here.

[0158] It should be noted that the above example is described based on the example that the level of the first core particle is lower than the level of the second core particle. The embodiment of the present application can also support the level of the first core particle being higher than the level of the second core particle. For example, the first core particle can be a core core particle (i.e., a core slice), and the second core particle can be a cache core particle (i.e., a cache slice), and the level of the core slice is higher than the cache slice. Taking the cache slice as an example where the cache slice is located at the bottom layer of the chip (i.e., the cache core particle is the bottom layer of the chip), in one example, Figure 8B Another implementation example diagram of the chip provided in the embodiment of the present application is shown as an example. Figure 8B In the example, the first chiplet is a core slice, the second chiplet is a cache slice, and the cache slice is at a lower level than the core slice. The core slice can perform cross-chiplet testing and access control on the on-chip memory in the cache slice.

[0159] exist Figure 8B In the example, the cache slice can be connected to the chip's packaging substrate 103 and communicate with the peripherals through the peripheral interface 104 provided on the packaging substrate to obtain configuration information transmitted by the peripherals such as the JTAG debugger through the JTAG interface or other peripheral interfaces; furthermore, the second test access port in the cache slice can configure the second test controller and / or the second non-volatile controller in the cache slice. The second test access port in the cache slice can also transmit the configuration information to the first test access port in the core slice via the third interconnection interface 701 connecting the cache slice and the core slice, so that the first test access port in the core slice can configure the first test controller and / or the first non-volatile controller in the core slice.

[0160] It should be noted that, in a 3D packaging scenario, the embodiment of the present application does not limit the number of layers of core particles stacked in the chip, and can support any number of layers of core particles stacked together. In addition, the embodiment of the present application does not limit the specific hierarchical differences between the first core particle and the second core particle. In the case where the hierarchies of the first core particle and the second core particle are different, the embodiment of the present application can enable the controller (storage controller, first test controller, etc.) in the first core particle to perform cross-core testing and access control on the second on-chip memory in the second core particle, thereby covering the connection of the interconnection interface between the first core particle and the second core particle.

[0161] It should be further explained that although some of the examples provided above are described using 3D packaging technology as an example for chips, 3D packaging is only one packaging technology that can be used for the chips provided in the embodiments of the present application. Through the solution provided in the embodiments of the present application, the embodiments of the present application can also support non-3D packaged chips, implement cross-chip testing and access control of on-chip memory, thereby covering the connection of the interconnection interface between the test core particles and meeting the testing and repair requirements of the on-chip memory inside the core particles. For example, the solution provided in the embodiments of the present application can also be applied to 2D packaged chips, 2.5D packaged chips, etc.

[0162] The solution provided by the embodiments of the present application can implement cross-chip testing and access control of on-chip memory, thereby covering the connection between test chiplets and improving the coverage of chip testing. In addition, during the process of the chiplet performing on-chip memory self-test and cross-chip testing of on-chip memory, if the on-chip memory is tested to have a defect or abnormality, it can support the repair of the defective on-chip memory, thereby meeting the on-chip memory testing and repair needs of the chiplet in different test scenarios such as wafer testing, final testing, and system startup self-test.

[0163] In a further optional implementation, based on the chip provided in the embodiment of the present application, the embodiment of the present application also provides a chip testing method. In an optional implementation, Figure 9 An optional flow chart of a chip testing method provided in an embodiment of the present application is exemplarily shown, wherein the chip may include multiple core particles, the multiple core particles including interconnected first core particles and second core particles. In an optional implementation, Figure 9 The test method shown can be applied to the first core particle, refer to Figure 9 , the method may include the following steps.

[0164] In step S910 , control information output by the controller of the first chip is determined.

[0165] In an optional implementation, the controller of the first chip may include a memory controller and a first test controller arranged in the first chip; the memory controller generates access control information for controlling the first on-chip memory of the first chip, and the first test controller generates first test control information for testing the first on-chip memory; thereby, the first test control information generated by the first test controller is transmitted to the memory controller; the memory controller is used to select output control information from the access control information and the first test control information; and further, the control information output by the memory controller is used as the control information output by the controller.

[0166] In step S911, control information is transferred to the first on-chip memory of the first chiplet, and is transferred to the second chiplet via the first interconnection interface connecting the first chiplet and the second chiplet; wherein the control information transferred to the second chiplet is used to control the second on-chip memory of the second chiplet.

[0167] In step S912, it is determined whether a response result of the second on-chip memory to the control information is obtained. If not, step S913 is executed; if so, step S914 is executed.

[0168] In step S913 , it is confirmed that the connection between the first interconnection interface of the first chiplet and the second chiplet is abnormal.

[0169] In step S914 , it is confirmed that the connection between the first interconnection interface of the first chiplet and the second chiplet is normal.

[0170] It should be noted that the optional implementation and extended implementation content corresponding to the chip testing method provided in the embodiment of the present application can be combined with the description of the corresponding parts of the previous text and refer to each other, and will not be expanded here.

[0171] In a further optional implementation, an embodiment of the present application further provides an electronic device, such as a server device or a terminal device, which may include the chip provided by the embodiment of the present application.

[0172] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0173] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A chip, characterized in that: comprising a plurality of core particles, wherein the plurality of core particles include a first core particle and a second core particle that are interconnected; The first chip includes a first on-chip memory and a controller for controlling the first on-chip memory; the second chip includes a second on-chip memory; The control information output by the controller is transmitted to the first on-chip memory and is transmitted to the second core particle through the first interconnection interface connecting the first core particle and the second core particle. When the second core particle chooses to use the control information to control the second on-chip memory, whether the controller obtains a response result of the second on-chip memory to the control information indicates whether the connection between the first interconnection interface of the first core particle and the second core particle is normal. The controller includes a memory controller and a first test controller provided in the first chip; the memory controller generates access control information for controlling the first on-chip memory, and the first test controller generates first test control information for testing the first on-chip memory; Among them, the first test control information generated by the first test controller is transmitted to the storage controller; the storage controller is used to select output control information from the access control information and the first test control information; the control information output by the storage controller is used as the control information output by the controller.

2. The chip according to claim 1, characterized in that The storage controller generates the access control information in a normal working mode; the first test controller generates the first test control information in a test mode; The control information selected by the storage controller for output from the access control information and the first test control information includes: In normal working mode, selecting the access control information for output; In the test mode, the first test control information is selected for output.

3. The chip according to claim 2, characterized in that The storage controller is provided with a first multiplexer; The first multiplexer is configured to select the access control information for output in a normal working mode; and select the first test control information for output in a test mode.

4. The chip according to any one of claims 1 to 3, characterized in that The second core particle further includes: a second test controller and a second multiplexer; the second test controller generates second test control information for testing the second on-chip memory; The second test control information is transmitted to the second multiplexer, and the control information output by the controller is transmitted to the second multiplexer via a first interconnection interface connecting the first core particle and the second core particle; The second multiplexer is used to select information for controlling the second on-chip memory from the control information output by the controller and the second test control information generated by the second test controller.

5. The chip according to claim 4, characterized in that The second multiplexer is configured to select information for controlling the second on-chip memory from the control information output by the controller and the second test control information generated by the second test controller, including: In the test phase before packaging, the second test control information generated by the second test controller is selected to control the second on-chip memory; in the test phase after packaging and the normal working mode, the control information output by the controller is selected to control the second on-chip memory.

6. The chip according to claim 5, characterized in that In the test phase after packaging, the control information output by the controller includes the first test control information generated by the first test controller; in the normal working mode, the control information output by the controller includes the access control information generated by the storage controller.

7. The chip according to claim 6, characterized in that The test stage before packaging includes the wafer test stage; the test stage after packaging includes any one of the following: the final test stage, the system startup self-test stage; wherein, the test stage before packaging and the test stage after packaging belong to the test stage in the test mode.

8. The chip according to any one of claims 1 to 3, characterized in that: The first chip further includes: a first repair configuration register, a first non-volatile controller and a first non-volatile memory; The first test controller generates first repair configuration information of the first on-chip memory, and the first repair configuration information generated by the first test controller is obtained based on a response of the first on-chip memory to the first test control information; The first repair configuration information generated by the first test controller is saved in the first repair configuration register, and the first repair configuration information generated by the first test controller is saved in the first non-volatile memory through the first non-volatile controller; When the system is restarted, the first non-volatile controller reads the first repair configuration information stored in the first non-volatile memory and writes the first repair configuration information into the first repair configuration register; The first repair configuration register repairs the first on-chip memory based on the stored first repair configuration information.

9. The chip according to claim 8, characterized in that The first chip further includes: a third multiplexer; wherein the first repair configuration information generated by the first test controller is transmitted to the third multiplexer and is selected and saved in the first repair configuration register by the third multiplexer; the first repair configuration information read from the first non-volatile memory by the first non-volatile controller is transmitted to the third multiplexer and is selected and saved in the first repair configuration register by the third multiplexer.

10. The chip according to any one of claims 6 to 7, characterized in that: The second core particle further includes: a second repair configuration register and a fourth multiplexer; wherein the first test controller generates second repair configuration information for the second on-chip memory, the second repair configuration information generated by the first test controller being obtained based on a response of the second on-chip memory to the first test control information; and the second repair configuration information generated by the first test controller is transmitted to a fourth multiplexer of the second chiplet via a second interconnection interface connecting the first chiplet and the second chiplet; The second test controller generates second repair configuration information for the second on-chip memory, wherein the second repair configuration information generated by the second test controller is obtained based on a response of the second on-chip memory to the second test control information; and the second repair configuration information generated by the second test controller is transmitted to the fourth multiplexer; The fourth multiplexer is configured to select the second repair configuration information from the second repair configuration information generated by the first test controller and the second repair configuration information generated by the second test controller, and save the selected second repair configuration information into the second repair configuration register; The second repair configuration register repairs the second on-chip memory based on the stored second repair configuration information.

11. The chip according to claim 10, characterized in that The fourth multiplexer is configured to select the second repair configuration information from the second repair configuration information generated by the first test controller and the second repair configuration information generated by the second test controller and save the second repair configuration information to the second repair configuration register, comprising: In the test phase before packaging, the second repair configuration information generated by the second test controller is selected and saved to the second repair configuration register; in the test phase after packaging, the second repair configuration information generated by the first test controller is selected and saved to the second repair configuration register.

12. The chip according to claim 10, characterized in that The second chip further includes: a second non-volatile controller, a second non-volatile memory, and a fifth multiplexer; The second repair configuration information generated by the first test controller is further transmitted to the fifth multiplexer of the second core particle through the second interconnection interface connecting the first core particle and the second core particle; the second repair configuration information generated by the second test controller is further transmitted to the fifth multiplexer; The fifth multiplexer is configured to select the second repair configuration information generated by the first test controller and the second repair configuration information generated by the second test controller, and output the second repair configuration information to the second non-volatile controller; The second non-volatile controller is configured to save the second repair configuration information output by the fifth multiplexer to the second non-volatile memory.

13. The chip according to claim 12, characterized in that The second non-volatile controller is further configured to read the second repair configuration information stored in the second non-volatile memory when the system is restarted, and write the second repair configuration information into the second repair configuration register through the fourth multiplexer so that the second repair configuration register repairs the second on-chip memory.

14. The chip according to claim 12 or 13, characterized in that: The first core further includes a first test access port; the second core further includes a second test access port; the first test access port and the second test access port communicate via a third interconnection interface connecting the first core and the second core; The first test access port is used to configure the first test controller and / or the first non-volatile controller in the first chip; The second test access port is used to configure a second test controller and / or a second non-volatile controller in the second chip; The information used to configure the first test access port and the second test access port comes from a peripheral device, and the peripheral device is connected to the peripheral interface of the chip.

15. A chip testing method, characterized in that: The chip includes a plurality of core particles, and the plurality of core particles include a first core particle and a second core particle that are interconnected. The testing method is applied to the first core particle. The testing method includes: Determine control information output by a controller of a first chip; wherein the controller includes a memory controller and a first test controller provided in the first chip; the memory controller generates access control information for controlling a first on-chip memory, and the first test controller generates first test control information for testing the first on-chip memory; the first test control information generated by the first test controller is transmitted to the memory controller; the memory controller is configured to select output control information from the access control information and the first test control information; the control information output by the memory controller serves as the control information output by the controller; transferring the control information to a first on-chip memory of the first chiplet, and transferring the control information to the second chiplet via a first interconnection interface connecting the first chiplet and the second chiplet; wherein the control information transferred to the second chiplet is used to control the second on-chip memory of the second chiplet; Determining whether a response result of the second on-chip memory to the control information is obtained; If not, confirming that the connection between the first interconnection interface of the first core particle and the second core particle is abnormal; If so, it is confirmed that the connection between the first interconnection interface of the first core particle and the second core particle is normal.

16. An electronic device, characterized in that: Comprising the chip according to any one of claims 1 to 14.

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