Block addressing method, device, storage control chip and storage medium

Abstract

The present application discloses a block addressing method, device, storage control chip and storage medium. The method includes: reading and loading a pre-stored block address table; using the block sequence number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table; calculating the block address according to the addressing algorithm based on the parameter data matched by the information area to which the current binding block belongs; and completing the writing or reading of the Flash according to the block address corresponding to the current binding block. By using the block sequence number of the binding block as an index factor to quickly locate the information area to which the binding block belongs in the block address table, and according to the parameter data of the information area matched by the binding block, the block address is obtained according to the addressing algorithm, so that the block address of the binding block can be quickly obtained, the addressing efficiency is improved, and the reading and writing acceleration is realized.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a block addressing method, device and storage control chip. Background Art

[0002] As one of the mainstream storage media, NAND Flash is widely used in various types of storage products, such as USB flash drives, SD cards, etc. The architecture of NAND Flash is divided into Bank, Plane,

[0003] Block and Page, where Block is the smallest erase unit of NAND Flash, and Page is the smallest read and write unit of NAND Flash.

[0004] Multi-Plane is an operation to improve the read and write performance of NAND Flash. This operation requires that blocks from different planes be bound to form bound blocks according to the configured binding rules in advance. When performing data reading and writing,

[0005] When data is read and written from the bound block, the transmission time between the Cache Register and Page Register inside the NAND Flash is reduced, achieving read and write acceleration.

[0006] The binding block is composed of blocks from different Planes. The binding block contains multiple block addresses. These block addresses will generate a block address table for unified management in the mass production stage.

[0007] When the storage control chip is operating, it needs to load the entire block address table to perform addressing to realize data reading and writing. However, since the entire block address table needs to be loaded for each reading and writing, the addressing efficiency of the bound block is low, which has a great impact on the storage

[0008] The random read and write performance of the product will be affected. Summary of the invention

[0009] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a block addressing method, device, storage control chip and storage medium, which can improve addressing efficiency and accelerate read and write performance.

[0010] A first aspect of the present application provides a block addressing method, comprising:

[0011] Read and load a pre-stored block address table;

[0012] Using the block number of the current binding block as an index factor, locating the information area to which the current binding block belongs in the block address table;

[0013] Based on the parameter data matched by the information area to which the current binding block belongs, a block address is calculated according to an addressing algorithm;

[0014] The writing or reading of the Flash is completed according to the block address corresponding to the current binding block.

[0015] Further, in one of the embodiments, the block address is calculated according to an addressing algorithm based on the parameter data matched by the information area to which the current binding block belongs, including:

[0016] Parsing out the flash memory blocks contained in the current binding block;

[0017] Read the parameter data of the information area to which each flash memory block belongs, wherein the parameter data includes: the CE to which the current flash memory block belongs, the Bank to which the current flash memory block belongs, the current flash memory block

[0018] The total number of blocks in the Plane, the total number of Planes in the Bank to which the current flash block belongs, the position number of the block template bit corresponding to the current flash block, and the Plane to which the current flash block belongs;

[0019] The block address of the current binding block is calculated according to the parameter data.

[0020] Furthermore, in one of the embodiments, after parsing out the block template corresponding to each Plane in the Flash, the method further includes:

[0021] If the block templates corresponding to the Planes are the same, one copy of the block template is saved as the block template corresponding to the Planes.

[0022] Further, in one of the embodiments, the pre-stored block address table is generated as follows:

[0023] Parse the block template corresponding to each Plane in Flash;

[0024] Classify each block template into different information areas according to a preset division rule, and add an index mark to each information area to generate a block address table, wherein the preset division rule includes: division based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship;

[0025] The block address table is stored.

[0026] A second aspect of the present application provides a block addressing device, comprising:

[0027] A loading module, used for reading and loading a pre-stored block address table;

[0028] An index module, used to use the block number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table;

[0029] An addressing module, configured to calculate a block address according to an addressing algorithm based on information data matched by the information area to which the current binding block belongs;

[0030] The read / write module is used to complete writing or reading to the Flash according to the block address corresponding to the current binding block.

[0031] Furthermore, in one embodiment, the addressing module includes:

[0032] A parsing unit, used for parsing out the flash memory blocks contained in the current binding block;

[0033] A reading unit, used for reading parameter data of the information area to which each flash memory block belongs, wherein the parameter data includes: the CE to which the current flash memory block belongs, the Bank to which the current flash memory block belongs, the total number of blocks of the Plane to which the current flash memory block belongs, the total number of Planes of the Bank to which the current flash memory block belongs, the position sequence number of the block template bit corresponding to the current flash memory block, and the Plane to which the current flash memory block belongs;

[0034] An address calculation unit is used to calculate the block address of the current binding block according to the parameter data.

[0035] Furthermore, in one of the embodiments, the addressing module further includes:

[0036] The compression unit is used for saving one of the block templates as the block template corresponding to each Plane if the block templates corresponding to each Plane are the same.

[0037] Further, in one of the embodiments, the pre-stored block address table is generated as follows:

[0038] Parse the block template corresponding to each Plane in Flash;

[0039] Classify each block template into different information areas according to a preset division rule, and add an index mark to each information area to generate a block address table, wherein the preset division rule includes: division based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship;

[0040] The block address table is stored.

[0041] A third aspect of the present application provides a storage control chip, comprising the block addressing device described above.

[0042] A fourth aspect of the present application provides a computer-readable storage medium storing executable code, which, when executed by a processor of an electronic device, enables the processor to execute the block addressing method as described above.

[0043] The technical solution of the present application includes: reading and loading a pre-stored block address table; using the block sequence number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table; calculating the block address according to the addressing algorithm based on the parameter data matching the information area to which the current binding block belongs; and completing the writing or reading of the Flash according to the block address corresponding to the current binding block. By using the block sequence number of the binding block as an index factor to quickly locate the information area to which the binding block belongs in the block address table, and according to the parameter data of the binding block matching information area, the block address is obtained according to the addressing algorithm, so that the block address of the binding block can be quickly obtained, the addressing efficiency is improved, and the reading and writing acceleration is realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 It is a flowchart of a block addressing method shown in an embodiment of the present application;

[0046] Figure 2 FIG. 1 is a schematic diagram of the structure of a block addressing device in an embodiment of the present application;

[0047] Figure 3 Shown is a schematic diagram of the structure of a storage product in an embodiment of the present application;

[0048] Figure 4 FIG. 1 is a schematic diagram of the structure of a storage control chip in an embodiment of the present application;

[0049] Figure 5 Shown is a schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0050] Figure 6 FIG. 1 is a schematic diagram showing the corresponding relationship between the flash memory blocks and the binding blocks in an embodiment of the present application. DETAILED DESCRIPTION

[0051] In order to facilitate the understanding of the present invention, the present invention will be described more fully with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.

[0052] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0054] In the related art, when performing read and write operations, the storage control chip needs to load the entire block address table for addressing to realize data reading and writing. However, since the entire block address table needs to be loaded for each read and write, the addressing efficiency of the bound block is low, which will affect the random read and write performance of the storage product.

[0055] Therefore, in order to solve the above technical problems, the present application provides a block addressing method, which can improve addressing efficiency and accelerate reading and writing performance.

[0056] The technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0057] See also Figure 1 , a block addressing method, comprising the following steps:

[0058] Step S110: read and load a pre-stored block address table.

[0059] As data for managing NAND Flash, the block address table is very important management data, and is used to record the block address management table of each block in NAND Flash. Since the number of blocks contained in NAND Flash is huge, and each block address generally requires 2 bytes of space to be allocated for storage, a certain amount of storage space is required to store the block address table according to the technical means in the prior art. In this embodiment, considering the above situation, the generation method of the block address table in the prior art is optimized to compress the length of the block address table as much as possible.

[0060] The block address table in this embodiment can be generated in the following manner: parse out the block template corresponding to each Plane in the Flash; classify each block template into different information areas according to the preset division rules, and add an index identifier to each information area to generate a block address table, wherein the preset division rules include: division based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship; store the block address table.

[0061] Block template: It is a binary sequence used to express which blocks are good blocks and which blocks are bad blocks in the current plane. This template is the basic data obtained when performing a full disk scan on the NAND Flash in the mass production stage.

[0062] In addition, a series of basic data used to describe NAND Flash will be scanned out during the mass production phase. These data include the relationship between Bank and CE (channel), the relationship between Bank and Plane, the binding relationship between Plane and Plane, the number of good and bad blocks contained in Plane, etc.

[0063] According to the NAND Flash basic data obtained in the mass production stage, in this embodiment, each block template can be classified into different information areas according to the preset division rules, and an index identifier is added to each information area, which is concretized into a block address table and stored. The specific preset division rules include: division based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship.

[0064] In order to better understand the technical solution of this embodiment, a specific example is used for explanation below.

[0065] like Figure 3The structure diagram of the storage product 30 in this embodiment is shown. The storage product 30 includes a storage control chip 310 and a storage particle 320. The storage control chip 310 selects NAND Flash 321 or NAND Flash 322 through the chip select port CE0. Each NAND Flash includes two Planes, where NAND Flash 321 corresponds to A1 and A2, and NAND Flash 322 corresponds to B1 and B2. In addition, each Plane includes five blocks, namely A11~A15, A21~A25, B11~B15 and B21~B25.

[0066] After mass production scanning, the block template shown in Table 1 is obtained:

[0067]

[0068] Among them, "0" means that the block is a bad block and data cannot be read or written, and "1" means that the block is a good block and data can be read or written. In addition, Plane A1 and Plane A2 have a binding relationship, and Plane B1 and Plane B2 have a binding relationship.

[0069] Further, as a preferred implementation, if the block templates corresponding to each Plane are the same, one of the block templates is saved as the block template corresponding to each Plane. It should be noted that when the block templates corresponding to each Plane are the same, that is, the block templates A1, A2, B1 and B2 are the same, only one block template can be saved as the block template corresponding to other Planes. The purpose of this is to further compress the length of the block address table and complete multiple reuse of the same block template.

[0070] Since block templates A1 and A2 are located under Bank0, and Plane A1 and Plane A2 have a binding relationship; block templates B1 and B2 are located under Bank1, and Plane B1 and Plane B2 have a binding relationship; Bank0 and Bank1 are located under CE0. Therefore, the data in Table 1 is divided according to the preset division rule, and index identifiers are added to generate the block address information table shown in Table 2.

[0071]

[0072] The "information area" is the area for storing block templates, which is divided based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship between Planes. "wStartBlkIndex" is one of the index identifiers, representing the starting block number of the binding block in the information area. "wBlkcnt" is another index identifier, representing the number of binding blocks in the information area.

[0073] In this embodiment, A1 and A2 can perform binding. Through the block template, it can be seen that after A1 and A2 are bound, 3 binding blocks can be obtained. The binding block numbers correspond to 0, 1 and 2. Therefore, the index identifier wStartBlkIndex=0 of INFO_0; wBlkcnt=3. B1 and B2 can also perform binding. Through the block template, it can be seen that after B1 and B2 are bound, 2 binding blocks can be obtained. The binding block numbers correspond to 3 and 4. Therefore, the index identifier wStartBlkIndex=3; wBlkcnt=2 of INFO_1. A total of 5 binding blocks are obtained, of which the basic information of binding blocks 0~2 can be found in INFO_0, and the basic information of binding blocks 3~4 can be found in INFO_1. In the above manner, the block address table generation is completed.

[0074] It should be noted that the generation of the block address table belongs to the pre-process, and is a block address table that must be created before step S110. After the block address table is created and generated, it will be stored in the NAND Flash. When the storage control chip 310 needs to write or read data, the read and write operations of each block in the NAND Flash can be realized by loading the block address table. Since the block template of this embodiment is a sequence expressed in binary concrete form, even if the NAND Flash contains many blocks, it will not occupy too much storage space of the NAND Flash. Distinguishing the "partition information" and "index identifier" added to different information areas will also not occupy too much storage space of the NAND Flash.

[0075] Assuming that each Plane in NAND Flash includes 2000 blocks, according to the technical solution of this embodiment, the 4 block templates are 2000*4=8000 bits in total, that is, 1000 bytes, and each item of "partition information" and "index identifier" is configured with a maximum of 2 bytes for storage, and the 2 information areas consume a total of = 1k+8*4=1032 bytes. Compared with the method in the related art that each block address requires 2 bytes for management, the block address table = 2000*4*4=16000 bytes. It can be seen that the present application can compress the storage space occupied by the block address table of NAND Flash as much as possible. At the same time, when the storage control chip 310 performs read and write operations on NAND Flash, it can greatly speed up the loading speed of the block address table in the RAM of the storage control chip, and greatly improve the random read and write performance of NAND Flash.

[0076] Step S120: Use the block number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table.

[0077] After the block address table is created, generated and stored, when the storage control chip needs to write a piece of data to NAND Flash, it needs to quickly locate the address of the bound block to complete the writing. In the mass production stage, it has been determined that A1 and A2 in NAND Flash 210 have a binding relationship, and B1 and B2 in NAND Flash 220 have a binding relationship. At the management level, the bound Plane will use a unified partition to manage it, that is, in this embodiment, A1, A2, B1 and B2 will have a dedicated Partition0 for management.

[0078] From this, it can be concluded that Figure 6 The correspondence between flash blocks and bonding blocks is shown (assuming sequential bonding).

[0079] Partition0 is used to manage the two planes A1 and A2. It has three binding blocks (S0~S2) inside, where:

[0080] The block address of binding block S0 = the block address of flash block A12 + the block address of flash block A21;

[0081] The block address of the binding block S1 = the block address of the flash block A13 + the block address of the flash block A24;

[0082] The block address of the binding block S2 = the block address of the flash memory block A15 + the block address of the flash memory block A25.

[0083] Partition0 is used to manage the two planes B1 and B2. It has two binding blocks (S3~S4) inside, where:

[0084] The block address of the binding block S3 = the block address of the flash block B11 + the block address of the flash block B21;

[0085] The block address of the binding block S4 = the block address of the flash block B12 + the block address of the flash block B24.

[0086] The above correspondence corresponds to the "index identifier" column in Table 1.

[0087] Furthermore, as a preferred embodiment, for Plane B1 and Plane B2, the number of binding blocks formed by the binding is 2, which is implemented in a sequential binding manner. The sequential binding means that the blocks in the current Plane are bound with the blocks of other Planes according to the arrangement order of the blocks, that is, the flash memory block B11 is bound with the flash memory block B21 to form a binding block S3, and the flash memory block B12 is bound with the flash memory block B24 to form a binding block S4.

[0088] However, in actual applications, in order to better exert the read and write performance of the bound block, it is necessary to preferentially select the flash memory blocks with good quality and bind them to form a bound block. Flash memory blocks with good quality can be analyzed by judging the size of the ECC. The smaller the ECC, the better the quality of the current flash memory block, and the larger the ECC, the worse the quality of the current flash memory block. Since the flash memory block contains several pages, each page corresponds to an ECC. All the ECCs of these pages are read, and the ECC of the current flash memory block is calculated by the average calculation method. For example, the current flash memory block contains 10 pages, and the ECC of each page is 50, 60, 40, 30, 20, 60, 50, and 40 respectively. Therefore, the ECC of the current flash memory block = (50+60+40+30+20+60+50+40) / 8≈44, so the ECC of the current flash memory block is

[0089] The ECC is equal to 44. If it is determined that the quality of the flash block B12 is not as good as that of the flash block B13, the flash block B13 will be preferentially bound with the flash block B24 to form a bound block S3.

[0090] Now the storage control chip 310 is ready to write a new data to the storage particle 320, which needs to be written into the binding block S1. The RAM of the storage control chip 310 loads the block address table, quickly locates it in the block address table according to the index "wBlkIndex" of the binding block S1, and calculates the block address of the binding block S1.

[0091] In this embodiment, since the information area has been classified for each binding block according to the "division information" and "index identifier", let wBlkIndex=1, wBlkIndex≥wStartBlkIndex and <wStartBlkIndex+wBlkcnt, it is determined that the binding block S1 is located in the information area INFO_0, and the binding block S1 is quickly located.

[0092] Step S130: Based on the parameter data matched by the information area to which the current binding block belongs, a block address is calculated according to an addressing algorithm.

[0093] In this embodiment, when the binding block S1 is located in the information area INFO_0, the parameter data matched by the information area INFO_0 is read, and the block address is calculated according to the addressing algorithm. The addressing algorithm can be implemented as follows:

[0094] Parse the flash memory blocks contained in the current binding block; read the parameter data of the information area to which each flash memory block belongs, wherein the parameter data includes: the Bank to which the current flash memory block belongs, the total number of blocks of the Plane to which the current flash memory block belongs, the total number of Planes of the Bank to which the current flash memory block belongs, the position number of the block template bit corresponding to the current flash memory block, and the Plane to which the current flash memory block belongs; calculate the block address of the current binding block based on the parameter data.

[0095] It should be noted that since the block address of the binding block S1 is composed of the block address of the flash block A13 and the block address of the flash block A24, the block address of the binding block S1 can be obtained by calculating the block addresses of the flash block A13 and the flash block A24 respectively.

[0096] In Bank0 to which flash block A13 belongs, the total number of flash blocks in Plane A1 to which flash block A13 belongs is 5, the total number of Planes in Bank0 to which flash block A13 belongs is 2, the bit of flash block A13 based on the block template "01101" is "1", and the sequence number of Plane A1 to which flash block A13 belongs is 0. Therefore, according to the above parameter data, the block address of flash block A13 is calculated by formula 1).

[0097] Block address=INFO[i].Bank[j]*wBlkPerBank+Planecnt*x+Plane[k] 1)

[0098] in:

[0099] "Block address" represents the address of the current flash memory block;

[0100] "INFO[i]" represents the information area to which the current flash memory block belongs;

[0101] "Bank[j]" represents the bank to which the current flash block belongs;

[0102] "wBlkPerBank" represents the total number of blocks in the Bank to which the current flash block belongs;

[0103] "Planecnt" represents the total number of Planes under the Bank to which the current flash block belongs;

[0104] "x" represents the position number of the block template bit corresponding to the current flash block;

[0105] "Plane[k]" indicates in which plane the current flash block is located under the bank.

[0106] In this embodiment, let INFO[i].Bank[j]=0; wBlkPerBank=5; Planecnt=2; x=1;

[0107] Plane[k]=0, the address of flash block A13 can be calculated:

[0108] The address of flash block A13 = 0*5+2*2+0=4.

[0109] Similarly, the block address of flash memory block A24 is calculated according to formula 1):

[0110] The address of flash block A24 = 0*5+2*3+1=7.

[0111] According to the above steps, the address of the binding block S1 can be obtained. It should be noted that the address of the binding block S1 is composed of the addresses of the flash memory block A13 and the flash memory block A24.

[0112] Step S140: Complete writing or reading to the Flash according to the block address corresponding to the current binding block.

[0113] Through the above steps, the block address of the binding block can be obtained, and the storage control chip 310 can implement the write operation to the Flash according to the block address of the binding block S1. It should be noted that the calculation principle of the block address of the binding block is the same regardless of writing or reading, so in the case presentation, only writing is used as an example for explanation.

[0114] The technical solution implemented in this embodiment uses the block number of the binding block as an index factor to quickly locate the information area to which the binding block belongs in the block address table, and obtains the block address according to the addressing algorithm based on the parameter data of the binding block matching information area. It can quickly obtain the block address of the binding block, improve the addressing efficiency, and achieve read and write acceleration.

[0115] Corresponding to the aforementioned method embodiments, the present application also provides a block addressing device and corresponding embodiments.

[0116] Figure 2 Shown is a schematic structural diagram of a block addressing device shown in an embodiment of the present application.

[0117] See also Figure 2 , a block addressing device 200, comprising: a loading module 210, an indexing module 220, an addressing module 230 and a reading and writing module 240. Wherein:

[0118] The loading module 210 is used to read and load a pre-stored block address table.

[0119] It should be noted that the pre-stored block address table can be generated and parsed to obtain the block templates corresponding to each Plane in the Flash in the following manner: each block template is classified into different information areas according to the preset division rules, and an index identifier is added to each information to generate a block address table, wherein the preset division rules include: division based on the Bank to which the current Plane belongs and the binding relationship; and storage of the block address table.

[0120] The index module 220 is used to use the block number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table.

[0121] The addressing module 230 is used to calculate the block address according to the addressing algorithm based on the parameter data matched by the information area to which the current binding block belongs.

[0122] The read / write module 240 is used to complete writing or reading to the Flash according to the block address corresponding to the current binding block.

[0123] Further, in one embodiment, the addressing module 230 includes: a parsing unit 231, a compression unit 232, a reading unit 233 and an address calculation unit 234. Among them:

[0124] The parsing unit 231 is used to parse out the flash memory blocks included in the current binding block.

[0125] The compression unit 232 is used for saving one of the block templates as the block template corresponding to each Plane if the block templates corresponding to each Plane are the same.

[0126] The reading unit 233 is used to read the parameter data of the information area to which each flash memory block belongs, wherein the parameter data includes: the Bank to which the current flash memory block belongs, the total number of blocks of the Plane to which the current flash memory block belongs, the total number of Planes of the Bank to which the current flash memory block belongs, the position number of the block template bit corresponding to the current flash memory block, and the Plane to which the current flash memory block belongs.

[0127] The address calculation unit 234 is used to calculate the block address of the current binding block according to the parameter data.

[0128] It should be noted that the block addressing method implemented by the block addressing device disclosed in this embodiment is the same as the above embodiment, so it will not be described in detail here. Optionally, each module in this embodiment and the above other operations or functions are respectively for implementing the methods in the above embodiments.

[0129] Figure 4 Shown is a schematic diagram of the structure of a storage control chip shown in an embodiment of the present application.

[0130] See also Figure 4, a storage control chip 310 includes the above-mentioned block addressing device 200.

[0131] It should be noted that the storage control chip 310 of this embodiment uses the block number of the binding block as an index factor to quickly locate the information area to which the binding block belongs in the block address table, and obtains the block address according to the addressing algorithm based on the parameter data of the binding block matching information area. It can quickly obtain the block address of the binding block, improve the addressing efficiency, and achieve read and write acceleration.

[0132] See also Figure 5 Another embodiment of the present application shows a computing electronic device 500 including: a processor 510 and a memory 520.

[0133] The processor 510 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0134] A general purpose processor may be a microprocessor or the processor may be any conventional processor 510 may include various types of memory units such as system memory, read-only memory (ROM), and permanent storage.

[0135] Among them, ROM can store static data or instructions required by processor 510 or other modules of the computer. The permanent storage device can be a readable and writable storage device. The permanent storage device can be a non-volatile storage device that does not lose the stored instructions and data even if the computer is powered off. In some embodiments, the permanent storage device uses a large-capacity storage device (such as a magnetic or optical disk, flash memory) as a permanent storage device.

[0136] In some other embodiments, the permanent storage device may be a removable storage device (e.g., a floppy disk, an optical drive). The system memory may be a read-write storage device or a volatile read-write storage device, such as a dynamic random access memory. The system memory may store some or all of the instructions and data required by the processor at run time.

[0137] In addition, the memory 520 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (eg, DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic disks and / or optical disks.

[0138] In some embodiments, the memory 520 may include a removable storage device that can be read and / or written, such as a laser disc (CD), a read-only digital versatile disc (such as a DVD-ROM, a double-layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (such as an SD card, a mini SD card, and a Micro-SD card, etc.), a magnetic floppy disk, etc. The computer-readable storage medium does not include a carrier wave and an instantaneous electronic signal transmitted wirelessly or by wire. The memory 520 stores executable code, and when the executable code is processed by the processor 510, the processor 510 can execute part or all of the methods described above.

[0139] In addition, the method according to the present application may also be implemented as a computer program or a computer program product, which includes computer program code instructions for executing some or all of the steps in the above method of the present application.

[0140] Alternatively, the present application can also be implemented as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) on which executable code (or computer program or computer instruction code) is stored. When the executable code (or computer program or computer instruction code) is executed by a processor of an electronic device (or server, etc.), the processor executes part or all of the steps of the above-mentioned method according to the present application.

[0141] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A block addressing method, characterized in that: include: Read and load a pre-stored block address table; Using the block number of the current binding block as an index factor, locating the information area to which the current binding block belongs in the block address table, wherein the current binding block is composed of flash memory blocks from different Planes; Parse the flash memory blocks included in the current binding block, read the parameter data of the information area to which each flash memory block belongs, wherein the parameter data includes: the CE to which the current flash memory block belongs, the Bank to which the current flash memory block belongs, the total number of blocks of the Plane to which the current flash memory block belongs, the total number of Planes of the Bank to which the current flash memory block belongs, the position number of the block template bit corresponding to the current flash memory block, and the Plane to which the current flash memory block belongs, and calculate the block address of the current binding block according to the parameter data, the block address of the current binding block is equal to the sum of the block addresses of the flash memory blocks included in the current binding block; Block address= INFO[i].Bank[j]*wBlkPerBank+Planecnt*x+Plane[k], where: "Block address" represents the address of the current flash memory block; "INFO[i]" represents the information area to which the current flash memory block belongs; "Bank[j]" represents the Bank to which the current flash memory block belongs; "wBlkPerBank" represents the total number of blocks in the Bank to which the current flash block belongs; "Planecnt" represents the total number of Planes under the Bank to which the current flash block belongs; "x" represents the position number of the block template bit corresponding to the current flash memory block; "Plane[k]" indicates in which Plane the current flash block is located under the Bank; The writing or reading of the Flash is completed according to the block address corresponding to the current binding block.

2. The block addressing method according to claim 1, characterized in that: The pre-stored block address table is generated as follows: Parse the block template corresponding to each Plane in Flash; According to the preset division rules, each block template is classified into different information areas, and each block template is The information area is added with an index mark to generate a block address table, wherein the preset division rule includes: division based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship; The block address table is stored.

3. The block addressing method according to claim 2, characterized in that: After parsing out the block templates corresponding to each Plane in the Flash, the process further includes: If the block templates corresponding to the Planes are the same, one copy of the block template is saved as the block template corresponding to the Planes.

4. A block addressing device, characterized in that: include: A loading module, used for reading and loading a pre-stored block address table; An index module, used for taking the block serial number of the current binding block as an index factor to locate the information area to which the current binding block belongs in the block address table, wherein the current binding block is composed of flash memory blocks from different Planes; An addressing module is used to parse out the flash memory blocks included in the current binding block, and read parameter data of the information area to which each flash memory block belongs, wherein the parameter data includes: the CE to which the current flash memory block belongs, the Bank to which the current flash memory block belongs, the total number of blocks of the Plane to which the current flash memory block belongs, the total number of Planes of the Bank to which the current flash memory block belongs, the position serial number of the block template bit corresponding to the current flash memory block, and the Plane to which the current flash memory block belongs, and the block address of the current binding block is calculated according to the parameter data, and the block address of the current binding block is equal to the sum of the block addresses of the flash memory blocks included in the current binding block; Block address= INFO[i].Bank[j]*wBlkPerBank+Planecnt*x+Plane[k], where: "Block address" represents the address of the current flash memory block; "INFO[i]" represents the information area to which the current flash memory block belongs; "Bank[j]" represents the Bank to which the current flash memory block belongs; "wBlkPerBank" represents the total number of blocks in the Bank to which the current flash block belongs; "Planecnt" represents the total number of Planes under the Bank to which the current flash block belongs; "x" represents the position number of the block template bit corresponding to the current flash memory block; "Plane[k]" indicates in which Plane the current flash block is located under the Bank; The read / write module is used to complete writing or reading to the Flash according to the block address corresponding to the current binding block.

5. The block addressing device according to claim 4, characterized in that: The pre-stored block address table is generated as follows: Parse the block template corresponding to each Plane in Flash; Classify each block template into different information areas according to a preset division rule, and add an index mark to each information area to generate a block address table, wherein the preset division rule includes: division based on the CE to which the current Bank belongs, the Bank to which the current Plane belongs, and the binding relationship; The block address table is stored.

6. The block addressing device according to claim 4, characterized in that: The addressing module further includes: The compression unit is used for saving one of the block templates as the block template corresponding to each Plane if the block templates corresponding to each Plane are the same.

7. A storage control chip, characterized in that: It comprises a block addressing device as described in any one of claims 4 to 6.

8. A computer-readable storage medium, characterized in that: An executable code is stored, and when the executable code is executed by a processor of an electronic device, the processor is caused to execute the block addressing method as described in any one of claims 1 to 3.

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