Artificial intelligence apparatus, method of operating the same, and machine readable storage medium

Abstract

An artificial intelligence (AI) device and an operating method thereof are provided. The AI device includes a switch chip and a plurality of AI chips. The plurality of AI chips are to collectively perform a computation task. One of the plurality of AI chips is a request initiation chip based on a communication operator of the computation task. The request initiation chip issues a reduce type request with a multicast address to the switch chip based on the communication operator. The switch chip multicasts the reduce type request to the plurality of AI chips that collectively perform the computation task. Any of the plurality of AI chips converts the multicast address to an internal memory physical address in response to the reduce type request to return target data corresponding to the internal memory physical address to the switch chip. The switch chip performs a reduce operation on the target data returned by the plurality of AI chips to generate reduced data. The switch chip returns the reduced data to the request initiation chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of artificial intelligence, and in particular, to an artificial intelligence device, an operation method thereof, a machine readable storage medium, and a computer program product. BACKGROUND

[0002] In a large model training process, a large number of artificial intelligence chips are needed to perform parallel operations to jointly execute a computing task. In order to jointly execute the computing task, the operation data of different artificial intelligence chips need to communicate with each other. How to implement the communication operator between different artificial intelligence chips is one of the technical problems in the field. SUMMARY

[0003] The present application relates to the technical field of artificial intelligence, and in particular, to an artificial intelligence device, an operation method thereof, a machine readable storage medium, and a computer program product.

[0004] In an embodiment according to the present application, the artificial intelligence device includes a switch chip and a plurality of artificial intelligence chips. The plurality of artificial intelligence chips are used to jointly execute a computing task, wherein the plurality of artificial intelligence chips are coupled to the switch chip. One of the plurality of artificial intelligence chips is a request initiation chip based on a communication operator of the computing task. The request initiation chip sends a protocol type request with a multicast address to the switch chip based on the communication operator. The switch chip multicasts the protocol type request to the plurality of artificial intelligence chips that jointly execute the computing task. Any one of the plurality of artificial intelligence chips converts the multicast address into an internal memory physical address in response to the protocol type request to return target data corresponding to the internal memory physical address to the switch chip.

[0005] In an embodiment according to the present application, the operation method includes: jointly executing a computing task by a plurality of artificial intelligence chips of an artificial intelligence device, wherein the plurality of artificial intelligence chips are coupled to a switch chip of the artificial intelligence device; being a request initiation chip by one of the plurality of artificial intelligence chips based on a communication operator of the computing task; sending a protocol type request with a multicast address to the switch chip by the request initiation chip based on the communication operator; multicasting the protocol type request to the plurality of artificial intelligence chips that jointly execute the computing task by the switch chip; and converting the multicast address into an internal memory physical address by any one of the plurality of artificial intelligence chips in response to the protocol type request to return target data corresponding to the internal memory physical address to the switch chip.

[0006] In an embodiment according to the present application, the machine readable storage medium is used to store non-transitory machine readable instructions. When the non-transitory machine readable instructions are executed by a computer, the operation method can be implemented.

[0007] In an embodiment according to the present application, the computer program product comprises a computer program. When the computer program is executed by a processor, the operation method can be implemented.

[0008] Based on the above, the artificial intelligence chip converts the multicast address carried by the load instruction from the switch chip into an internal memory physical address for the internal memory. Therefore, although the switch chip cannot address the internal memory of the artificial intelligence chip, the artificial intelligence chip can feed back the corresponding target data of the multicast address to the switch chip according to the multicast address carried by the load instruction of the switch chip, thereby realizing the communication operator between different artificial intelligence chips. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a circuit block schematic diagram of an artificial intelligence (AI) device according to an embodiment.

[0010] Figure 2 is a circuit block schematic diagram of an AI chip according to an embodiment.

[0011] Figure 3 is a flowchart of an operation method of an AI chip according to an embodiment of the present application.

[0012] Figure 4 is a schematic diagram of different AI chips performing a communication operator according to an embodiment of the present application.

[0013] Figure 5 is a circuit block schematic diagram of an AI chip according to an embodiment of the present application.

[0014] Figure 6 is a circuit block schematic diagram of an interface circuit according to an embodiment of the present application.

[0015] REFERENCE SIGNS

[0016] 100: artificial intelligence (AI) device

[0017] 110, 210, 510: switch chip

[0018] 120_1, 120_2, 120_3, 120_4, 120_n, 220_1, 220_n, 520_1, 520_n: AI chip

[0019] 221, 521_1, 521_n: interface circuit

[0020] 222, 522_1, 522_n: network on chip

[0021] 223, 523_1, 523_n: internal memory

[0022] 224, 524_1, 524_n: computing core

[0023] A1, A2, A3, A4, B1, B2, B3, B4, C1, C2, C3, C4, D1, D2, D3, D4: target data

[0024] S310-S350: steps DETAILED DESCRIPTION

[0025] Reference will now be made to exemplary embodiments of the present application, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0026] The term "coupled" or "connected" used in the full description of the specification, including claims, can refer to either a direct or indirect connection. For example, if a first device is coupled or connected to a second device, it can be directly connected to the second device, or it can be indirectly connected to the second device through one or more other devices or some connection means. The terms "first", "second", and the like used in the full description of the specification, including claims, are used to name components (elements) or to distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, the same reference numerals are used in the drawings and embodiments to represent the same or similar parts. Components / elements / steps using the same reference numerals or using the same terms in different embodiments can be referred to each other for relevant description.

[0027] Figure 1 is a circuit block diagram of an artificial intelligence (AI) device 100 according to an embodiment. Figure 1The illustrated AI device 100 includes a switch chip 110 and a plurality of AI chips 120_1, …, 120_n. By way of example (but not by way of limitation), any one or more (or all) of the AI chips 120_1-120_n can include a graphics processing unit (GPU), a General-purpose computing on graphics processing units (GPGPU), or other processing circuitry. The specific number n of AI chips 120_1-120_n in the AI device 100 can be determined in accordance with actual design. Large model training requires a large number of AI chips for parallel operation. The AI chips 120_1-120_n are coupled to the switch chip 110 through a bus. Different AI chips 120_1-120_n can communicate with each other through the switch chip 110.

[0028] Figure 2 is illustrated in accordance with an embodiment, a circuit block diagram of an AI chip 220_1. Figure 2 The illustrated switch chip 210 and AI chips 220_1, …, 220_n can be used as Figure 1 The illustrated switch chip 110 and AI chips 120_1-120_n are one of many embodiments. That is, Figure 2 The illustrated switch chip 210 and AI chips 220_1-220_n can refer to Figure 1 The illustrated switch chip 110 and AI chips 120_1-120_n can refer to the related description and analogy. In Figure 2 In the illustrated embodiment, the AI chip 220_1 includes an interface circuit 221, an internal memory 223, and a plurality of compute units (CUs) 224. The compute units 224 take data from the internal memory 223 through an on-chip network 222 to perform various computing tasks, and store the results of the computing tasks in the internal memory space of the internal memory 223 through the on-chip network 222. The internal memory space of the internal memory 223 is dedicated to the AI chip 220_1. Other chips (such as the switch chip 210) cannot address the internal memory space of the internal memory 223 of the AI chip 220_1. Figure 2 The illustrated other AI chips (such as the AI chip 220_n) can refer to the related description and analogy of the AI chip 220_1, and therefore are not described here.

[0029] To enable other chips (e.g., switch chip 210) to access target data of internal memory 223 of AI chip 220_1, a public storage space is set in internal memory 223. The physical address space of the public storage space of internal memory 223 is well-known, so that switch chip 210 or other chips can address the public storage space of AI chip 220_1. Target data that needs to be communicated is first copied from the internal storage space of internal memory 223 to the public storage space of internal memory 223. When other chips (e.g., switch chip 210) issue an access instruction with an intermediate physical address (e.g., a multicast address) to AI chip 220_1, interface circuit 221 fetches target data from the public storage space of internal memory 223 through on-chip network 222 and feeds the target data back to other chips (e.g., switch chip 210). In this way, although other chips cannot address the internal storage space of internal memory 223 of AI chip 220_1, other chips (e.g., switch chip 210) can still obtain target data (of internal memory 223) from the public storage space of AI chip 220_1. Figure 2 A disadvantage of the illustrated embodiment is that redundant public storage space is added to store the copied data, thereby increasing a large amount of overhead.

[0030] Figure 3 is a flowchart of an operation method of an AI chip according to an embodiment of the present application. Each step in the flowchart or a combination of steps in the flowchart can be implemented by various means, such as hardware, one or more computer-readable media storing computer programs or computer program products. In some embodiments, Figure 3 The illustrated operation method can be implemented in firmware or software (i.e., a program). For example, Figure 3 The related operations of the illustrated operation method can be implemented as non-transitory machine-readable instructions (code or programs), and the non-transitory machine-readable instructions can be stored in a "non-transitory machine-readable storage medium". When the non-transitory machine-readable instructions are executed by a computer, the illustrated operation method can be implemented. Figure 3 The illustrated operation method can be implemented in firmware or software (i.e., a program). For example, Figure 3 The illustrated operation method can be implemented in hardware, for example, in Figure 5The illustrated AI devices (to be described later). In yet other embodiments, one or more steps in the flowchart diagram can be embodied by a computer program of a computer program product. The computer program product can be stored by one or more memory devices in the computing devices and executed by processors in the computing devices. The computer program product can be implemented on a computer or other programmable apparatus to generate a machine, such that the computer program product generates functions specified in the steps of the flowchart diagram. The computer program product can include one or more computer readable memories (on which computer program instructions can be stored), or the computer program instructions of one or more computer program products can also be loaded onto a computer or other programmable apparatus.

[0031] Please refer to Figure 1 and Figure 3 In step S310, the AI chips 120_1-120_n jointly perform a computing task. In step S320, one of the AI chips 120_1-120_n initiates a chip as a request based on a communication operator of the computing task. The communication operator can include a switch sharp communication operator or other communication operators based on actual application scenarios, where the switch sharp communication operator is a collective communication optimization technology used in high-performance computing (HPC) and large-scale data center environments to optimize and accelerate cluster communication in high-performance computing and large-scale data center environments. In step S330, the request initiating chip sends a reduction type request with a multicast address to the switch chip 110 based on the communication operator. For example, based on the communication operator of the computing task, the AI chip 120_1 can send a first reduction type request with a first multicast address to the switch chip 110 as a first request initiating chip, and so on. The AI chip 120_n can send an nth reduction type request with an nth multicast address to the switch chip 110 as an nth request initiating chip.

[0032] In step S340, the switch chip 110 multicasts the reduction type request to the AI chips (the AI chips corresponding to the communication operator, such as the AI chips 120_1-120_n) jointly performing the computing task. The specific implementation of the reduction type request can be set according to actual application scenarios. For example, in some embodiments, the reduction type request has a multicast group identifier. The switch chip 110 determines the multicast object of the reduction type request based on the multicast group identifier.

[0033] In some embodiments, the contract type request carries identification information in addition to the multicast address. For example, when AI chip 120_1 performs a communication operator (e.g., a switch sharp communication operator) into a computation task, AI chip 120_1 sets the base address of the target data into a lookup table of AI chip 120_1. Other AI chips (e.g., AI chip 120_n) can refer to the relevant description of AI chip 120_1 and draw analogies, and thus are not described again. AI chip 120_1 extracts the base address of the target data from the lookup table based on the identification information from the contract type request of the switch chip 110. Depending on the actual application scenario, the identification information can include a multicast group identification number, a tensor identification number, or other identification information. After extracting the base address of the target data from the lookup table, AI chip 120_1 converts the multicast address into an internal memory physical address. For example, any one of AI chips 120_1-120_n generates a virtual address by adding the base address to the multicast address of the contract type request, and then converts the virtual address into the internal memory physical address. Depending on the actual application scenario, the multicast address can be an offset value, and the virtual address can be the base address extracted from the lookup table of AI chip 120_1 plus the offset value (multicast address).

[0034] In step S350, any of the AI chips that receives the protocol type request converts the multicast address to an internal memory physical address in response to the protocol type request to return the target data corresponding to the internal memory physical address to the switch chip 110. For example, assume that the AI chip corresponding to the communication operator is 120_1-120_n. When the AI chip 120_1 executes the switch sharp communication operator, the AI chip 120_1 issues a protocol type request to the switch chip 110 as a request initiation chip. The switch chip 110 multicasts the protocol type request of the AI chip 120_1 to the AI chips 120_1-120_n that collectively execute the computing task. Any of the AI chips 120_1-120_n that receives the protocol type request converts the multicast address to an internal memory physical address in response to the protocol type request to return the target data corresponding to the internal memory physical address to the switch chip 110. For example, the AI chip 120_1 converts the multicast address to an internal memory physical address of the AI chip 120_1 in response to the protocol type request from the switch chip 110, and then returns the target data corresponding to the internal memory physical address to the switch chip 110. By analogy, the AI chip 120_n converts the multicast address to an internal memory physical address of the AI chip 120_n in response to the protocol type request from the switch chip 110, and then returns the target data corresponding to the internal memory physical address to the switch chip 110.

[0035] In step S360, the switch chip 110 performs reduction operation on the target data returned by the different AI chips 120_1~120_n to generate reduced data. In step S370, the switch chip 110 returns the reduced data to the request initiating chips. For example, based on the communication operator of the computing task, the AI chip 120_1 can send a first reduction type request with a first multicast address to the switch chip 110 as a first request initiating chip, and so on, the AI chip 120_n can send a nth reduction type request with a nth multicast address to the switch chip 110 as a nth request initiating chip. The switch chip 110 obtains different first target data from the different AI chips 120_1~120_n in response to the first reduction type request of the first request initiating chip, and then the switch chip 110 performs reduction operation on the first target data to generate first reduced data, and then the switch chip 110 returns the first reduced data to the first request initiating chip (the AI chip 120_1). Similarly, the switch chip 110 obtains different nth target data from the different AI chips 120_1~120_n in response to the nth reduction type request of the nth request initiating chip, and then the switch chip 110 performs reduction operation on the nth target data to generate nth reduced data, and then the switch chip 110 returns the nth reduced data to the nth request initiating chip (the AI chip 120_n).

[0036] Figure 4 is shown according to an embodiment of the present application, and is a schematic diagram of different AI chips 120_1~120_4 performing a communication operator. It is assumed that the AI chip corresponding to the communication operator is Figure 4The AI chips 120_1, 120_2, 120_3 and 120_4 are shown. When the AI chip 120_1 executes the switch sharp communication operator, the AI chip 120_1 sends a reduce type request with a multicast address to the switch chip 110 as a request initiating chip. The switch chip 110 multicasts the reduce type request of the AI chip 120_1 to the AI chips 120_1-120_4 that jointly perform a computing task. The AI chip 120_1 converts the multicast address to an internal memory physical address in response to the reduce type request from the switch chip 110, and returns the target data Al corresponding to the internal memory physical address to the switch chip 110. By analogy, the AI chips 120_2, 120_3 and 120_4 return the target data A2, A3 and A4 to the switch chip 110 in response to the reduce type request from the switch chip 110. The switch chip 110 performs a reduce operation on the target data Al-A4 returned by the AI chips 120_1-120_4 to generate reduced data "Al + A2 + A3 + A4". The switch chip 110 returns the reduced data "Al + A2 + A3 + A4" to the request initiating chip 120_1. The request initiating chip 120_1 stores the reduced data "Al + A2 + A3 + A4" in the internal memory (such as the internal memory 122_1 shown in FIG. 1). Figure 4

[0037] ​Similarly, when the AI chip 120_2 executes the switch sharp communication operator, the AI chip 120_2 issues a reduce type request with a multicast address to the switch chip 110 as a request initiation chip. The switch chip 110 multicasts the reduce type request of the AI chip 120_2 to the AI chips 120_1 ~ 120_4 that collectively perform a computing task, and the AI chips 120_1 ~ 120_4 return target data B1, B2, B3, and B4 to the switch chip 110 in response to the reduce type request from the switch chip 110. The switch chip 110 performs a reduction operation on the target data B1 ~ B4 returned from the AI chips 120_1 ~ 120_4, and returns the reduced data "B1 + B2 + B3 + B4" to the request initiation chip 120_2. The AI chip 120_3 issues a reduce type request with a multicast address to the switch chip 110 as a request initiation chip, the switch chip 110 multicasts the reduce type request of the AI chip 120_3 to the AI chips 120_1 ~ 120_4 that collectively perform a computing task, and the AI chips 120_1 ~ 120_4 return target data C1, C2, C3, and C4 to the switch chip 110 in response to the reduce type request from the switch chip 110. The switch chip 110 performs a reduction operation on the target data C1 ~ C4 returned from the AI chips 120_1 ~ 120_4, and returns the reduced data "C1 + C2 + C3 + C4" to the request initiation chip 120_3. The AI chip 120_4 issues a reduce type request with a multicast address to the switch chip 110 as a request initiation chip, the switch chip 110 multicasts the reduce type request of the AI chip 120_4 to the AI chips 120_1 ~ 120_4 that collectively perform a computing task, and the AI chips 120_1 ~ 120_4 return target data D1, D2, D3, and D4 to the switch chip 110 in response to the reduce type request from the switch chip 110. The switch chip 110 performs a reduction operation on the target data D1 ~ D4 returned from the AI chips 120_1 ~ 120_4, and returns the reduced data "D1 + D2 + D3 + D4" to the request initiation chip 120_4.

[0038] Based on the above, the AI chips 120_1-120_4 convert the multicast address carried by the protocol type request from the switch chip 110 into a local internal memory physical address of the AI chips 120_1-120_4. Although the switch chip 110 cannot address the internal memory of the AI chips 120_1-120_4, the AI chips 120_1-120_4 can feed back the corresponding target data of the multicast address to the switch chip 110 according to the multicast address carried by the protocol type request from the switch chip 110. Therefore, the AI device 100 can implement a communication operator between different AI chips 120_1-120_n.

[0039] Figure 5 FIG. 5 is a circuit block schematic diagram of an AI chip 520_1-520_n according to an embodiment of the present application. Figure 5 The AI device shown includes a switch chip 510 and AI chips 520_1, …, 520_n. The AI chips 520_1-520_n are coupled to the switch chip 510. Figure 5 The switch chip 510 and the AI chips 520_1-520_n shown can be used as Figure 1 The switch chip 110 and the AI chips 120_1-120_n shown are one of many embodiments of the switch chip 110 and the AI chips 120_1-120_n. That is, Figure 5 The switch chip 510 and the AI chips 520_1-520_n shown can refer to Figure 1 The switch chip 110 and the AI chips 120_1-120_n shown are related to the description of the switch chip 110 and the AI chips 120_1-120_n and can be analogized. Figure 5 The AI chips 520_1-520_n shown can be exempted from Figure 2 The copy operation shown. In response to an access instruction with a multicast address issued by other chips (for example, the switch chip 510) to the AI chips 520_1-520_n, the AI chips 520_1-520_n convert the multicast address into an internal memory physical address of the internal storage space of the AI chips 520_1-520_n. The present embodiment does not limit the address conversion method of the AI chips 520_1-520_n. For example (but not limited to), the AI chips 520_1-520_n can run Figure 3 The operation method shown to convert the multicast address into an internal memory physical address. The AI chips 520_1-520_n access their internal memory according to the converted internal memory physical address to execute the access instruction of other chips (for example, the switch chip 510).

[0040] In Figure 5In the illustrated embodiment, AI chip 520_1 includes interface circuit 521_1, on-chip network 522_1, internal memory 523_1, and computing core 524_1. Similarly, AI chip 520_n includes interface circuit 521_n, on-chip network 522_n, internal memory 523_n, and computing core 524_n. AI chip 520_n can be understood by referring to the relevant description of AI chip 520_1 and by analogy. Different from... Figure 2 The AI ​​chip 220_1 shown here has the following characteristics: Figure 5 The AI ​​chip 520_1 shown does not have this feature. Figure 2 The copy operation is shown. Figure 5 The internal memory 523_1 and computing core 524_1 shown can be referenced. Figure 2 The related descriptions of the internal memory 223 and computing core 224 shown are similar and will not be repeated here. Internal memory 523_1 is dedicated to AI chip 520_1. Switch chip 510 or other chips cannot address the internal memory 523_1 of AI chip 520_1.

[0041] Interface circuit 521_1 is used to establish a communication interface with switch chip 510. Internal memory 523_1 is coupled to interface circuit 521_1 via on-chip network 522_1. Computation core 524_1 is coupled to interface circuit 521_1 and internal memory 523_1 via on-chip network 522_1. Interface circuit 521_1 obtains a multicast address from switch chip 510 requesting a protocol type. Interface circuit 521_1 translates the multicast address into an internal memory physical address and assigns it to internal memory 523_1 to retrieve the target data. For example (but not limited to), interface circuit 521_1 can operate... Figure 3 The illustrated operation method converts a multicast address into an internal memory physical address. Internal memory 523_1 is accessed according to the internal memory physical address to output the target data corresponding to the internal memory physical address to interface circuit 521_1. Interface circuit 521_1 then feeds the target data back to switch chip 510.

[0042] Figure 6 This is a circuit block diagram of an interface circuit 610 according to an embodiment of the present invention. Figure 6 The interface circuit 610 shown can be used as Figure 5 The interface circuit 521_1 shown is one of many implementation examples and can also be used as... Figure 5 This is one of many implementation examples of the interface circuit 521_n shown. That is, Figure 6 The switch chip 510, interface circuit 610, on-chip network 620, internal memory 630, and computing core 640 shown can be referenced. Figure 1The relevant descriptions of the switch chip 510, the interface circuit 521_1, the network-on-chip 522_1, the internal memory 523_1, and the computing core 524_1 are similar and can be referred to Figure 1 The relevant descriptions of the switch chip 510, the interface circuit 521_n, the network-on-chip 522_n, the internal memory 523_n, and the computing core 524_n are similar and can be referred to.

[0043] Figure 6 The interface circuit 610 includes a base address memory 611, an address calculation circuit 612, and a memory management circuit 613. The address calculation circuit 612 is coupled to the base address memory 611. The address calculation circuit 612 obtains a multicast address from a protocol type request of the switch chip 510. The address calculation circuit 612 queries a base address of target data from the base address memory 611 (a lookup table) based on the protocol type request. The address calculation circuit 612 generates a virtual address by adding the base address to the multicast address (an offset value). The memory management circuit 613 is coupled to the address calculation circuit 612 to receive the virtual address. The memory management circuit 613 is coupled to the internal memory 630 through the network-on-chip 620. The memory management circuit 613 converts the virtual address to an internal memory physical address to the internal memory 630 to obtain the target data. The memory management circuit 613 feeds back the target data to the switch chip 510.

[0044] Based on the above, the interface circuit 610 converts the multicast address from the protocol type request of the switch chip 510 to an internal memory physical address to the internal memory 630. Therefore, although the switch chip 510 cannot address the internal memory 630 of the AI chip, the interface circuit 610 of the AI chip can feed back corresponding target data of the multicast address to the switch chip 510 according to the multicast address from the protocol type request of the switch chip 510, thereby realizing the communication operator between different AI chips 520_1-520_n.

[0045] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An artificial intelligence device, characterized by, The artificial intelligence device includes: Switch chips; and Multiple AI chips are used to work together to perform computing tasks. in, The plurality of artificial intelligence chips are coupled to the switch chip. During the joint execution of the computing task, one of the plurality of AI chips acts as a request initiating chip based on the communication operator of the computing task. It sends a protocol type request with a built-in multicast address for generating a virtual address to the switch chip, causing the switch chip to multicast the protocol type request to all the AI ​​chips jointly executing the computing task. In response to a protocol type request from a switch chip, any one of the plurality of AI chips converts the multicast address into an internal memory physical address and returns the target data corresponding to the internal memory physical address to the switch chip, causing the switch chip to perform a protocol operation to remove the copy operation used to copy the requested target data from the internal memory to its common storage space. in, The multicast address represents the access address of the target data when the switch chip accesses the internal memory of the artificial intelligence chip. The virtual address is used to convert the access address into the physical address of the internal memory of the artificial intelligence chip. 2.The artificial intelligence apparatus of claim 1, wherein, The switch chip performs a reduction operation on the target data returned by the plurality of artificial intelligence chips to generate reduced data, and the switch chip returns the reduced data to the artificial intelligence chip that is the request initiating chip. 3.The artificial intelligence apparatus of claim 1, wherein, The communication operator includes the switch sharp communication operator for network computation. 4.The artificial intelligence apparatus of claim 1, wherein, The protocol type request also includes a multicast group identifier, and the switch chip uses the multicast group identifier to determine the multicast object of the protocol type request.

5. The artificial intelligence device according to claim 1, characterized in that, The protocol type request also includes identification information, and any one of the plurality of artificial intelligence chips uses the identification information to retrieve the base address of the target data from the lookup table to convert the multicast address into the internal memory physical address.

6. The artificial intelligence device according to claim 5, characterized in that, Any one of the plurality of AI chips generates a virtual address by adding the base address to the multicast address, and any one of the plurality of AI chips converts the virtual address into the physical address of the internal memory.

7. The artificial intelligence device according to claim 5, characterized in that, When the communication operator in the computation task is executed, each of the plurality of artificial intelligence chips sets the base address of the target data into the lookup table.

8. The artificial intelligence device according to claim 1, characterized in that, Any one of the plurality of artificial intelligence chips includes: Interface circuitry, used to establish a communication interface with the switch chip; Internal memory, coupled to the interface circuitry via an on-chip network; and The computing core is coupled to the interface circuitry and the internal memory via the on-chip network. in, The interface circuit obtains the multicast address of the protocol type request from the switch chip, the interface circuit converts the multicast address into the internal memory physical address and gives it to the internal memory to obtain the target data, and the interface circuit returns the target data to the switch chip.

9. The artificial intelligence device according to claim 8, characterized in that, The interface circuit includes: Base address memory; An address calculation circuit, coupled to the base address memory, wherein the address calculation circuit obtains the multicast address of the protocol type request from the switch chip, the address calculation circuit queries the base address memory to obtain the base address of the target data based on the protocol type request, and the address calculation circuit adds the multicast address to the base address to generate a virtual address; and A memory management circuit is coupled to the address calculation circuit and coupled to the internal memory via the on-chip network, wherein the memory management circuit translates the virtual address into a physical address for the internal memory to obtain the target data, and the memory management circuit feeds the target data back to the switch chip.

10. A method for operating an artificial intelligence device, characterized in that, The operation method includes: The computational task is jointly performed by multiple artificial intelligence chips in the artificial intelligence device, wherein the multiple artificial intelligence chips are coupled to the switch chip of the artificial intelligence device; During the joint execution of the computing task, one of the plurality of artificial intelligence chips acts as the request initiating chip based on the communication operator of the computing task; The AI ​​chip, which acts as the request initiating chip, sends a protocol type request with its own multicast address for generating virtual addresses to the switch chip based on the communication operator; The switch chip multicasts the protocol type request to the multiple AI chips that jointly perform the computation task; and In response to a protocol type request from a switch chip, any one of the plurality of AI chips converts the multicast address into an internal memory physical address and returns the target data corresponding to the internal memory physical address to the switch chip, causing the switch chip to perform a protocol reduction operation to remove the copy operation used to copy the requested target data from the internal memory to its common storage space. in, The multicast address represents the access address of the target data when the switch chip accesses the internal memory of the artificial intelligence chip. The virtual address is used to convert the access address into the physical address of the internal memory of the artificial intelligence chip.

11. The operating method according to claim 10, characterized in that, The operation method further includes: The switch chip performs a reduction operation on the target data returned by the plurality of artificial intelligence chips to generate reduced data; and The switch chip returns the regulated data to the artificial intelligence chip, which is the request initiating chip.

12. The operating method according to claim 10, characterized in that, The communication operators include the switch sharp communication operator.

13. The operating method according to claim 10, characterized in that, The protocol type request also includes a multicast group identifier, and the operation method further includes: The switch chip determines the multicast object of the protocol type request based on the multicast group identifier.

14. The operating method according to claim 10, characterized in that, The specification type request also includes identification information, and the operation method further includes: Any one of the plurality of artificial intelligence chips retrieves the base address of the target data from the lookup table based on the identification information, so as to convert the multicast address into the internal memory physical address.

15. The operating method according to claim 14, characterized in that, The operation method further includes: A virtual address is generated by adding the multicast address to the base address by any of the plurality of artificial intelligence chips; and The virtual address is translated into the physical address of the internal memory by any one of the plurality of artificial intelligence chips.

16. The operating method according to claim 14, characterized in that, The operation method further includes: When the communication operator in the computation task is executed, each of the plurality of artificial intelligence chips sets the base address of the target data into the lookup table.

17. A machine-readable storage medium for storing non-transitory machine-readable instructions, characterized in that, The operation method of any one of claims 10-16 can be implemented when the non-transitory machine-readable instructions are executed by a computer.

18. A computer program product, comprising a computer program, characterized in that, When executed by a processor, the computer program implements the operating method as described in any one of claims 10-16.

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