DRAM memory cell testing methods, systems, equipment, and storage media

Abstract

This invention provides a method, system, device, and storage medium for testing DRAM memory cells. The method includes: writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length; creating an access array, accessing the memory cell groups, and obtaining the row and column addresses of the memory cell groups; reading the current test data of the corresponding memory cell group according to the row and column addresses, and comparing it with the preset test data of the memory cell group; if the comparison results are consistent, the memory cell group is determined to have been accessed; obtaining the four adjacent row and column addresses on the diagonal according to the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed according to the adjacent row and column addresses; if all adjacent memory cell groups have been accessed, the test is determined to have passed. This invention can cover test blind spots and detect chip defects that are difficult to find, improve fault coverage, and enhance product quality.

Description

Technical Field

[0001] This invention relates to the field of DRAM chip testing technology, and specifically to a method, system, device, and storage medium for testing DRAM memory cells. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory and an indispensable component of modern computer systems. Its primary operating principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM platforms include Double Data Rate (DDR) modules used in personal computers or servers, and Low Power Double Data Rate (LPDDR) chips used in embedded ARM architectures. The basic storage unit of LPDDR is a cell. Computers and embedded systems store and read data by writing high or low voltage levels into cells. Cells are arranged in rows and columns, forming a row called a bank. Each LPDDR chip has multiple banks.

[0003] Current DRAMs employ burst read / write operations for high access speeds. This means read / write operations within a memory array are performed in units of burst length (BL), reading or writing multiple bits (e.g., 8-bit, 16-bit, or 32-bit) of column addresses at a time, accessing data consisting of 0s and 1s within each burst length. To ensure DRAM chip reliability, testing is typically required. Different testing methods can affect the state of memory cells. Generally, sequential testing is used, testing the memory cells within the DRAM in ascending order, i.e., continuous access within a specific bank. While this testing method traverses all addresses in the DRAM, in practical use, it's impossible to strictly read and write each memory cell row-by-row and column-by-column in ascending order. Therefore, blind spots appear, making it difficult to detect hard-to-find chip defects, resulting in low fault coverage when testing DRAM. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a method, system, device and storage medium for testing DRAM memory cells, which effectively solves the problem of test blind spots when testing DRAM, making it difficult to detect chip defects that are hard to find, resulting in low fault coverage.

[0005] In a first aspect, the present invention provides a method for testing DRAM memory cells, the method comprising:

[0006] Preset test data is written into all memory cells of the DRAM to be tested, and the memory cells are grouped into memory cell groups according to a preset burst length.

[0007] Create an access array, access the storage unit group, and obtain the row and column addresses of the storage unit group;

[0008] The current test data corresponding to the storage unit group is read according to the row and column address and compared with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed.

[0009] Obtain the four adjacent row and column addresses on the diagonal based on the row and column addresses, and determine whether the corresponding adjacent storage cell group has been accessed based on the adjacent row and column addresses. If all the adjacent storage cell groups have been accessed, the test is considered to have passed.

[0010] Furthermore, the content of the preset test data is set according to the preset burst length, and the preset test data includes a first preset test data and a second preset test data, wherein the second preset test data is the inverse of the first preset test data.

[0011] Furthermore, the step of writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length, including:

[0012] Write the first preset test data into the first memory cell group of the first row of the memory array of the DRAM to be tested;

[0013] The remaining columns of the first row of the storage array are randomly written with either the first preset test data or the second preset test data;

[0014] The data of the remaining columns other than the first storage cell group of the i-th row of the storage array are written sequentially from the first cell of the (i+1)-th row of the storage array, and the data of the first storage cell group of the i-th row of the storage array is written to the last storage cell group of the (i+1)-th row of the storage array, until all storage cells of the DRAM to be tested are written with the preset test data, where i = 1, 2, 3, ..., k-1, and k is the maximum number of rows of the storage array.

[0015] Furthermore, the step of creating an access array, accessing the storage cell group, and obtaining the row and column addresses of the storage cell group includes:

[0016] Create an access array with all initial values ​​of 0. Each value of the access array represents whether the corresponding storage unit group has been accessed, where 0 represents not accessed and 1 represents accessed.

[0017] Starting from the storage cell group corresponding to the initial row and column address of the storage cell group array, the current row and column address A(X,Y) of the currently accessed storage cell group is obtained, where X represents the row number of the currently accessed storage cell group in the storage cell group array, and Y represents the column number of the currently accessed storage cell group in the storage cell group array.

[0018] Furthermore, the step of reading the current test data corresponding to the storage unit group based on the row and column address, and comparing it with the preset test data of the storage unit group, and determining that the storage unit group has been accessed if the comparison result is consistent, includes:

[0019] Determine whether the out-of-bounds condition is met based on the current row and column address A(X,Y). If the out-of-bounds condition is met, read the current test data of the corresponding storage unit group.

[0020] Compare the current test data of the storage unit group with the preset test data. If the comparison result is consistent, modify the value at the corresponding position of the current row and column address A(X,Y) in the access array to 1.

[0021] If the comparison results are inconsistent, the test result is returned as a failure;

[0022] The out-of-bounds conditions are: 0≤X≤H, 0≤X≤L, and the value at (X,Y) of the access array is 0, where H is the maximum number of rows in the access array and L is the maximum number of columns in the access array.

[0023] Furthermore, the step of obtaining the four adjacent row and column addresses on the diagonal based on the row and column addresses, and determining whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses, and determining that the test passes if all the adjacent memory cell groups have been accessed, includes:

[0024] Based on the current row and column address A(X,Y), obtain the four adjacent row and column addresses on the diagonal. The adjacent row and column addresses include: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), A4(X+N,YN), where N is a positive integer determined by the maximum number of rows and the maximum number of columns of the access array.

[0025] Determine whether the out-of-bounds condition is met based on the adjacent row and column addresses. If the out-of-bounds condition is met, then read the current test data of the corresponding storage unit group in sequence.

[0026] The current test data of the storage unit group is compared with the preset test data. If the comparison result is consistent, the value of the corresponding position of the adjacent row and column address in the access array is modified to 1. If the comparison result is inconsistent, the test is determined to be unsuccessful.

[0027] If the values ​​at the corresponding positions of the four adjacent row and column addresses in the access array are all 1, the current row and column address A(X,Y) is modified to Previous A, and the previous A is re-evaluated to see if it meets the out-of-bounds condition. The previous A are, in order: A4(X+N,YN), A3(XN,YN), A2(XN,Y+N), A1(X+N,Y+N).

[0028] The test is considered passed when all the values ​​at the corresponding positions of the adjacent row and column addresses in the access array are 1.

[0029] Furthermore, after determining whether the out-of-bounds condition is met based on the adjacent row and column addresses, the method further includes:

[0030] If the adjacent row and column address does not meet the out-of-bounds condition, then the current row and column address A(X,Y) is modified to Next A, and the out-of-bounds condition is re-evaluated, wherein:

[0031] The Next A are, in order: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), A4(X+N,YN).

[0032] Secondly, the present invention provides a DRAM memory cell testing system, the system comprising:

[0033] An initialization module is used to write preset test data into all storage cells of the DRAM to be tested, wherein the storage cells are grouped into storage cell groups according to a preset burst length.

[0034] The processing module is used to create an access array, access the storage unit group, and obtain the row and column addresses of the storage unit group;

[0035] The comparison module is used to read the current test data corresponding to the storage unit group according to the row and column address, and compare it with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed.

[0036] The determination module is used to obtain the addresses of four adjacent rows and columns on the diagonal based on the row and column addresses, and to determine whether the corresponding adjacent storage unit groups have been accessed based on the adjacent row and column addresses. If all the adjacent storage unit groups have been accessed, the test is determined to be passed.

[0037] Thirdly, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the DRAM memory cell testing method as described in the first aspect of the present invention.

[0038] Fourthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the DRAM memory cell testing method as described in the first aspect of the present invention.

[0039] This invention provides a method, system, device, and storage medium for testing DRAM memory cells. It pre-defines preset test data, eliminating the need for additional data generation algorithms and saving computing resources on the testing machine during the initialization and data comparison phases. Furthermore, the DRAM initialization data can be marked as 0 and 1 on the testing machine's storage, further conserving storage resources. The DRAM access rule prioritizes accessing adjacent data cells at the lower right corner, continuing recursively. This rule allows for rapid access to the diagonal of the memory array, covering all memory cells in the array in the order of lower triangle first, then upper triangle. This new access rule can cover test blind spots and detect difficult-to-find chip defects, improving fault coverage and product quality. It also effectively reduces time and space complexity, making it suitable for mass production testing. Based on DDR and LPDDR memory principles, it is applicable to all generations of DDR and LPDDR products. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart of the DRAM memory cell testing method in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of preset test data in an embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of a DRAM storage array to be tested, in which preset test data is written in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram comparing the storage array and access array of the DRAM to be tested in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of four adjacent row and column addresses on the diagonal of the current row and column address in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of the structure of the DRAM memory cell testing system in an embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0048] Explanation of key component symbols:

[0049] 600. DRAM memory cell test system; 610. Initialization module; 620. Processing module; 630. Comparison module; 640. Decision module; 700. Electronic device; 710. Processor; 720. Communication interface; 730. Memory; 740. Communication bus. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be further described clearly and completely below with reference to the accompanying drawings of the embodiments of this invention. It should be noted that the described embodiments are merely some embodiments of this invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0053] Current DRAM uses burst read / write for high access speeds. This means read / write operations are performed in units of burst length (BL) within a memory array. Each operation reads or writes multiple bits (e.g., 8-bit, 16-bit, or 32-bit) of column addresses, accessing data consisting of 0s and 1s within each burst length. For example, if the target address is row 0 and the burst length is 8 bits, then 1 bit of data is written to each bit in the space from row 0, column 0 to row 0, column 7, for a total of 8 bits. The second burst length is from row 0, column 8 to column 15, and so on. When all the memory locations in a row are written, the memory controller (MC) locates the address of the next row and continues the same operation.

[0054] To ensure the reliability of DRAM chips, they typically require testing. Different testing methods can affect the state of the memory cells. Generally, testing is performed sequentially, checking the memory cells within the DRAM in ascending order, i.e., continuously accessing them within a specific bank. While this testing method traverses all addresses in the DRAM, in actual use, it's impossible to strictly read and write to each memory cell row by row and column by column in ascending order. This results in test blind spots, making it difficult to detect hard-to-find chip defects, leading to low fault coverage when testing DRAM.

[0055] Example 1

[0056] To address the aforementioned shortcomings of existing technologies, this invention provides a method for testing DRAM memory cells, effectively solving the problem of test blind spots during DRAM testing, making it difficult to detect hard-to-find chip defects and resulting in low fault coverage. Figure 1 This is a flowchart of the DRAM memory cell testing method in an embodiment of the present invention, as shown below. Figure 1 As shown, the method includes the following steps:

[0057] S100: Write the preset test data into all memory cells of the DRAM to be tested. The memory cells are grouped into memory cell groups according to the preset burst length.

[0058] The content of the preset test data is set according to the preset burst length. Figure 2 This is a schematic diagram of preset test data in an embodiment of the present invention, such as... Figure 2As shown, in this embodiment of the invention, the preset burst length is BL = 8 bits. The preset test data includes a first preset test data and a second preset test data, and the second preset test data is the inverse of the first preset test data. The data content written or read from the first preset test data and the second preset test data are D and / D, respectively, where: D = 01010101, then / D = 10101010. Setting adjacent bits to opposite data can maximize the pressure on the DRAM's storage and read / write functions. For different preset burst lengths, the corresponding preset test data D and / D can be set according to this logic.

[0059] First, the background data is initialized, which involves sequentially writing the storage array to D or / D. Figure 3 This is a schematic diagram of the DRAM under test in an embodiment of the present invention, in which preset test data is written. It is assumed that the storage array size is 64×64 bits, with 8 storage cells forming a storage cell group, as shown below. Figure 3 As shown in (a), the first preset test data D is written to the first group of storage cells in the storage array, i.e., columns 1-7 of the first row. Figure 3 As shown in (b), the remaining columns of the first row of the storage array are randomly written in groups of 8 bits, using either the first preset test data D or the second preset test data / D. Figure 3 As shown in (c), a preset test data write operation is performed on the second row of the storage array. Relative to the first row, the preset test data shifts the last seven storage cell groups forward by eight columns (i.e., the distance of one storage cell group). The position of the last empty storage cell group is then filled with the preset test data from the first storage cell group of the first row. For example... Figure 3 As shown in (d), the remaining rows are filled according to the above process to complete the initialization and obtain the result as shown in (d). Figure 3 The array of storage cells shown in (e) is an example.

[0060] S200: Create an access array, access the memory cell group, and obtain the row and column addresses of the memory cell group;

[0061] Create an 8×8 access array, denoted as Access_array, with all initial values ​​set to 0. Each value in the access array represents whether the corresponding memory cell group in the memory cell group array has been accessed, where 0 represents unaccessed and 1 represents accessed.

[0062] The address of a memory cell group is represented by its row and column numbers in the memory cell group array, denoted as (X,Y), where X represents the row number and Y represents the column number. Access begins from the first memory cell group (1,1) in the first row, and the row and column address of the currently accessed memory cell group is denoted as A(X,Y).

[0063] S300: Read the current test data of the corresponding storage unit group according to the row and column address, and compare it with the preset test data of the storage unit group. If the comparison results are consistent, the storage unit group is determined to have been accessed.

[0064] The system checks if the current row and column address A(X,Y) meets the out-of-bounds condition. If it does, it reads the current test data from the corresponding memory location. The out-of-bounds conditions are: 0≤X≤H, 0≤X≤L, and the value at (X,Y) in the accessed array is 0. Here, H is the maximum number of rows in the accessed array, and L is the maximum number of columns. The system compares the current test data in the memory location with the preset test data. If the comparison is consistent, the value at the corresponding position in the accessed array at the current row and column address A(X,Y) is set to 1. If the comparison is inconsistent, the system returns a test failure result.

[0065] Specifically, Figure 4 This is a schematic diagram showing the comparison between the memory array and the access array of the DRAM to be tested in an embodiment of the present invention, as shown below. Figure 4 As shown, depending on whether the current row and column address A(3,2) meets the out-of-bounds condition, in an 8×8 access array with all initial values ​​of 0, the current row and column address A(3,2) meets the following out-of-bounds condition: 0≤X≤8, 0≤X≤8, and the value at (3,2) in the corresponding access array is 0. Therefore, the current row and column address A(3,2) can be accessed. The current test data of the corresponding memory unit group is read and compared with the preset test data. If the comparison result is consistent, the value at the corresponding position of the current row and column address A(3,2) in the access array is modified to 1. If the comparison result is inconsistent, the test result is returned as failure.

[0066] If the out-of-bounds condition is not met, the current row and column address A(X,Y) is modified to Next A, and the out-of-bounds condition is re-evaluated. Next A is successively: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), A4(X+N,YN), where N is a positive integer determined by the maximum number of rows and columns of the accessed array.

[0067] S400: Obtain the four adjacent row and column addresses on the diagonal based on the row and column addresses, and determine whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses. If all adjacent memory cell groups have been accessed, the test is considered to have passed.

[0068] Given the current row and column address A(X,Y), obtain the addresses of the four adjacent rows and columns on the diagonal. The adjacent row and column addresses are: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), and A4(X+N,YN), where N is a positive integer determined by the maximum number of rows and columns of the array being accessed.

[0069] Specifically, Figure 5 This is a schematic diagram of four adjacent row and column addresses on the diagonal of the current row and column address in an embodiment of the present invention, as shown below. Figure 5 As shown, with N=2 as the default, the four adjacent row and column addresses on the diagonal based on the current row and column address A(X,Y) are: A1(X+2,Y+2), A2(X-2,Y+2), A3(X-2,Y-2), and A4(X+2,Y-2).

[0070] The system determines whether the above out-of-bounds conditions are met based on the adjacent row and column addresses. If the out-of-bounds conditions are met, the system reads the current test data of the corresponding storage unit group in sequence and compares the current test data of the storage unit group with the preset test data. If the comparison results are consistent, the system modifies the value at the corresponding position of the adjacent row and column address in the access array to 1. If the comparison results are inconsistent, the system determines that the test has failed.

[0071] If the above out-of-bounds condition is not met, the current row and column address A(X,Y) is modified to Next A, and NextA is re-evaluated to see if it meets the out-of-bounds condition. Next A is in the following order: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), A4(X+N,YN).

[0072] If the values ​​at the corresponding positions of four adjacent row and column addresses in the array are all 1, the current row and column address A(X,Y) is modified to Previous A, and Previous A is re-evaluated to see if it meets the out-of-bounds condition. The previous A values ​​are: A4(X+N,YN), A3(XN,YN), A2(XN,Y+N), and A1(X+N,Y+N).

[0073] The test is considered passed when the values ​​at all corresponding positions of adjacent row and column addresses in the access array are all 1. Each comparison operation in the combination operation compares the current test data of the read memory cell group with the preset test data, that is, comparing the read value with the data written during initialization (D or / D) bit by bit. If data inconsistency occurs, the test is considered to have failed; if all memory cell group data comparisons are correct, the test is considered to have passed.

[0074] The DRAM memory cell testing method provided in this invention predefines preset test data, eliminating the need to call additional data generation algorithms. This saves computing resources on the testing machine during the initialization and data comparison phases. Furthermore, the DRAM initialization data can be marked as 0 and 1 on the testing machine's storage, further conserving storage resources. The DRAM access rule prioritizes accessing adjacent data cells at the lower right corner, continuing recursively. This rule allows for rapid access to the diagonal of the memory array, covering all memory cells in the array in the order of lower triangle first, then upper triangle. This new access rule can cover previous test blind spots and detect chip defects that were previously difficult to find, improving fault coverage and enhancing product quality.

[0075] Example 2

[0076] Based on the same technical concept as the method embodiment in Embodiment 1 above, this embodiment of the invention also provides a DRAM memory cell testing system. Figure 6 This is a schematic diagram of the DRAM memory cell testing system in an embodiment of the present invention, as shown below. Figure 6 As shown, the DRAM memory cell test system 600 includes:

[0077] The initialization module 610 is used to write preset test data into all memory cells of the DRAM to be tested. The memory cells are grouped into memory cell groups according to the preset burst length.

[0078] Processing module 620 is used to create an access array, access the storage unit group, and obtain the row and column addresses of the storage unit group;

[0079] The comparison module 630 is used to read the current test data of the corresponding storage unit group according to the row and column address, and compare it with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed.

[0080] The determination module 640 is used to obtain the addresses of four adjacent rows and columns on the diagonal based on the row and column addresses, and to determine whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses. If all adjacent memory cell groups have been accessed, the test is considered to have passed.

[0081] The DRAM memory cell testing system provided in this embodiment of the invention effectively reduces time and space complexity, is suitable for mass production testing, and is applicable to all generations of DDR and LPDDR products based on DDR and LPDDR memory principles.

[0082] It is understood that the implementation method of the multimodal visitor information registration method described in Embodiment 1 above is also applicable to the embodiments of the present invention and can achieve the same technical effect, so it will not be described again here.

[0083] Example 3

[0084] Based on the same concept, embodiments of the present invention also provide an electronic device. Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention, such as... Figure 7 As shown, the electronic device 700 may include: a processor 710, a communication interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communication interface 720, and the memory 730 communicate with each other through the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute the steps of the DRAM memory cell testing method as described in the above embodiments. For example, this includes:

[0085] S100: Write the preset test data into all memory cells of the DRAM to be tested. The memory cells are grouped into memory cell groups according to the preset burst length.

[0086] S200: Create an access array, access the memory cell group, and obtain the row and column addresses of the memory cell group;

[0087] S300: Read the current test data of the corresponding storage unit group according to the row and column address, and compare it with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed.

[0088] S400: Obtain the four adjacent row and column addresses on the diagonal based on the row and column addresses, and determine whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses. If all adjacent memory cell groups have been accessed, the test is considered to have passed.

[0089] The processor 710 can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof.

[0090] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] The memory 730 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0092] Example 4

[0093] Based on the same concept, embodiments of the present invention also provide a computer-readable storage medium storing a computer program containing at least one piece of code executable by a master control device to control the master control device to implement the steps of the DRAM memory cell testing method as described in the above embodiments. For example, it includes:

[0094] S100: Write the preset test data into all memory cells of the DRAM to be tested. The memory cells are grouped into memory cell groups according to the preset burst length.

[0095] S200: Create an access array, access the memory cell group, and obtain the row and column addresses of the memory cell group;

[0096] S300: Read the current test data of the corresponding storage unit group according to the row and column address, and compare it with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed.

[0097] S400: Obtain the four adjacent row and column addresses on the diagonal based on the row and column addresses, and determine whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses. If all adjacent memory cell groups have been accessed, the test is considered to have passed.

[0098] Based on the same technical concept, this embodiment of the invention also provides a computer program, which, when executed by a master control device, is used to implement the above-described method embodiments.

[0099] The computer program may be stored, in whole or in part, on a computer-readable storage medium packaged with the processor, or in part or in whole on a memory not packaged with the processor.

[0100] Based on the same technical concept, embodiments of the present invention also provide a processor for implementing the above-described method embodiments. The processor may be a chip.

[0101] In summary, the present invention provides a DRAM memory cell testing method, system, device, and storage medium. It predefines preset test data, eliminating the need for additional data generation algorithms and saving computing resources on the testing machine during the initialization and data comparison phases. Furthermore, the DRAM initialization data can be marked as 0 and 1 on the testing machine's storage, further conserving storage resources. The DRAM access rule prioritizes accessing adjacent data cells at the lower right corner, continuing recursively. This rule allows for rapid access to the diagonal of the memory array, covering all memory cells in the array in the order of lower triangle first, then upper triangle. This new access rule can cover previous test blind spots and detect previously difficult-to-find chip defects, improving fault coverage and product quality. It also effectively reduces time and space complexity, making it suitable for mass production testing. Based on DDR and LPDDR memory principles, it is applicable to all generations of DDR and LPDDR products.

[0102] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0103] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for testing DRAM memory cells, characterized in that, The method includes: Preset test data is written into all memory cells of the DRAM to be tested, and the memory cells are grouped into memory cell groups according to a preset burst length. Create an access array, access the storage unit group, and obtain the row and column addresses of the storage unit group; The current test data corresponding to the storage unit group is read according to the row and column address and compared with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed. Based on the row and column addresses, obtain the addresses of the four adjacent rows and columns on the diagonal, and determine whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses. If all the adjacent memory cell groups have been accessed, the test is considered passed, including: Based on the current row and column address A(X,Y) of the currently accessed storage cell group, obtain the four adjacent row and column addresses on the diagonal. The adjacent row and column addresses include: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), and A4(X+N,YN), where X represents the row number of the currently accessed storage cell group in the storage cell group array, Y represents the column number of the currently accessed storage cell group in the storage cell group array, and N is a positive integer determined by the maximum number of rows and the maximum number of columns of the access array. Determine whether the out-of-bounds condition is met based on the adjacent row and column addresses. If the out-of-bounds condition is met, read the current test data of the corresponding storage unit group in sequence. The out-of-bounds condition is: 0≤X≤H, 0≤X≤L, and the value at (X,Y) of the access array is 0. H is the maximum number of rows in the access array, and L is the maximum number of columns in the access array. The current test data of the storage unit group is compared with the preset test data. If the comparison result is consistent, the value of the corresponding position of the adjacent row and column address in the access array is modified to 1. If the comparison result is inconsistent, the test is determined to be unsuccessful. If the values ​​at the corresponding positions of the four adjacent row and column addresses in the access array are all 1, the current row and column address A(X,Y) is modified to Previous A, and the previous A is re-evaluated to see if it meets the out-of-bounds condition. The previous A are, in order: A4(X+N,YN), A3(XN,YN), A2(XN,Y+N), A1(X+N,Y+N). The test is considered passed when all the values ​​at the corresponding positions of the adjacent row and column addresses in the access array are 1.

2. The DRAM memory cell testing method according to claim 1, characterized in that, The content of the preset test data is set according to the preset burst length. The preset test data includes a first preset test data and a second preset test data, where the second preset test data is the inverse of the first preset test data.

3. The DRAM memory cell testing method according to claim 2, characterized in that, The process of writing preset test data into all memory cells of the DRAM to be tested, wherein the memory cells are grouped into memory cell groups according to a preset burst length, includes: Write the first preset test data into the first memory cell group of the first row of the memory array of the DRAM to be tested; The remaining columns of the first row of the storage array are randomly written with either the first preset test data or the second preset test data; The data of the remaining columns other than the first storage cell group of the i-th row of the storage array are written sequentially from the first cell of the (i+1)-th row of the storage array, and the data of the first storage cell group of the i-th row of the storage array is written to the last storage cell group of the (i+1)-th row of the storage array, until all storage cells of the DRAM to be tested are written with the preset test data, where i=1,2,3,…,k-1, and k is the maximum number of rows of the storage array.

4. The DRAM memory cell testing method according to claim 1, characterized in that, The step of creating an access array, accessing the storage unit group, and obtaining the row and column addresses of the storage unit group includes: Create an access array with all initial values ​​of 0. Each value of the access array represents whether the corresponding storage unit group has been accessed, where 0 represents not accessed and 1 represents accessed. Starting from the storage cell group corresponding to the initial row and column address of the storage cell group array, the current row and column address A(X,Y) of the currently accessed storage cell group is obtained.

5. The DRAM memory cell testing method according to claim 4, characterized in that, The step of reading the current test data corresponding to the storage unit group according to the row and column address, and comparing it with the preset test data of the storage unit group, and determining that the storage unit group has been accessed if the comparison result is consistent, includes: Determine whether the out-of-bounds condition is met based on the current row and column address A(X,Y). If the out-of-bounds condition is met, read the current test data of the corresponding storage unit group. Compare the current test data of the storage unit group with the preset test data. If the comparison result is consistent, modify the value at the corresponding position of the current row and column address A(X,Y) in the access array to 1. If the comparison results are inconsistent, the test result is returned as a failure.

6. The DRAM memory cell testing method according to claim 1, characterized in that, After determining whether the out-of-bounds condition is met based on the adjacent row and column addresses, the method further includes: If the adjacent row and column address does not meet the out-of-bounds condition, then the current row and column address A(X,Y) is modified to NextA, and the out-of-bounds condition is re-evaluated, wherein: The Next A are, in order: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), A4(X+N,YN).

7. A DRAM memory cell testing system, characterized in that, The system includes: An initialization module is used to write preset test data into all storage cells of the DRAM to be tested, wherein the storage cells are grouped into storage cell groups according to a preset burst length. The processing module is used to create an access array, access the storage unit group, and obtain the row and column addresses of the storage unit group; The comparison module is used to read the current test data corresponding to the storage unit group according to the row and column address, and compare it with the preset test data of the storage unit group. If the comparison result is consistent, the storage unit group is determined to have been accessed. The determination module is used to obtain the addresses of four adjacent rows and columns on the diagonal based on the row and column addresses, and to determine whether the corresponding adjacent memory cell groups have been accessed based on the adjacent row and column addresses. If all the adjacent memory cell groups have been accessed, the test is considered to have passed, including: Based on the current row and column address A(X,Y) of the currently accessed storage cell group, obtain the four adjacent row and column addresses on the diagonal. The adjacent row and column addresses include: A1(X+N,Y+N), A2(XN,Y+N), A3(XN,YN), and A4(X+N,YN), where X represents the row number of the currently accessed storage cell group in the storage cell group array, Y represents the column number of the currently accessed storage cell group in the storage cell group array, and N is a positive integer determined by the maximum number of rows and the maximum number of columns of the access array. Determine whether the out-of-bounds condition is met based on the adjacent row and column addresses. If the out-of-bounds condition is met, read the current test data of the corresponding storage unit group in sequence. The out-of-bounds condition is: 0≤X≤H, 0≤X≤L, and the value at (X,Y) of the access array is 0. H is the maximum number of rows in the access array, and L is the maximum number of columns in the access array. The current test data of the storage unit group is compared with the preset test data. If the comparison result is consistent, the value of the corresponding position of the adjacent row and column address in the access array is modified to 1. If the comparison result is inconsistent, the test is determined to be unsuccessful. If the values ​​at the corresponding positions of the four adjacent row and column addresses in the access array are all 1, the current row and column address A(X,Y) is modified to Previous A, and the previous A is re-evaluated to see if it meets the out-of-bounds condition. The previous A are, in order: A4(X+N,YN), A3(XN,YN), A2(XN,Y+N), A1(X+N,Y+N). The test is considered passed when all the values ​​at the corresponding positions of the adjacent row and column addresses in the access array are 1.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the DRAM memory cell testing method as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the DRAM memory cell testing method as described in any one of claims 1 to 6.

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