Semiconductor device, semiconductor module, and manufacturing method

Abstract

In one embodiment, a semiconductor device (1) comprises: • a semiconductor chip configured for a voltage of at least 0.6 kV, the semiconductor chip comprising a top contact area at a top side of the chip, • a first electric wiring layer in electrical contact with the top contact area, the first electric wiring layer having first contact areas electrically assigned to the top contact area, • a second electric wiring layer on a side of the first electric wiring layer remote from the top contact area and having second contact areas electrically assigned to the top contact area, the second contact areas being configured as external contact areas, wherein at least one of the second contact areas is shaped differently from the one assigned in the top contact area.

Description

Technical Field

[0001] A semiconductor device and a semiconductor module including such a semiconductor device are provided. A method for manufacturing such a semiconductor device is also provided. Background Technology

[0002] Document EP 2 988 328 A1 mentions a power semiconductor module.

[0003] Document DE 10 2014 218 240 A1 discloses a power device integrated in a printed circuit board.

[0004] The electrical components are mentioned in documents DE 10 2015 115999A1, US2010 / 0078789 A1, US 8 975 732 B2, DE 202011110547U1 and EP 3 534 394 A1. Summary of the Invention

[0005] The problem to be solved is to provide a semiconductor device that can be used at relatively high voltages.

[0006] This objective is achieved, in particular, by semiconductor devices, semiconductor modules, and methods as defined in the independent patent claims. Exemplary further developments constitute the subject matter of the dependent claims.

[0007] For example, a semiconductor device includes at least one intermediate electrical wiring layer located in an insulating body, the at least one intermediate electrical wiring layer being located between a chip top contact region of the semiconductor chip and a second contact region for external contact of the semiconductor device.

[0008] By utilizing at least one intermediate wiring layer, the shape of the second contact region can be designed independently of the shape of the top contact region of the chip. Furthermore, the distance between the top contact region of the chip and the outside of the semiconductor device can be increased. Therefore, the semiconductor device can be provided with a high voltage, and the second contact region can be designed in a manifold manner for electrical connection to the semiconductor device.

[0009] In at least one embodiment, the semiconductor device includes:

[0010] - A semiconductor chip configured for a voltage of at least 0.6 kV, the semiconductor chip including a top contact region located on the top side of the chip.

[0011] - A first electrical wiring layer that is in electrical contact with the top contact area, the first electrical wiring layer having a first contact area that is electrically distributed to the top contact area.

[0012] - A second electrical wiring layer, located on the side of the first electrical wiring layer away from the top contact area, and having a second contact area electrically assigned to the top contact area, the second contact area being configured as an external contact area.

[0013] In the top view of the chip, at least one of the second contact areas is shaped in a different manner than that assigned to the top contact area.

[0014] For example, at least one semiconductor chip is selected from the group consisting of: metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), insulated-gate bipolar transistors (IGBTs), bipolar junction transistors (BJTs), thyristors, gate turn-off thyristors (GTOs), gate commutated thyristors (GCTs), junction-gate field-effect transistors (JFETs), and diodes. If multiple semiconductor chips are present, all semiconductor chips can be of the same type, or different types of semiconductor chips can be present.

[0015] Semiconductor devices, such as power devices, convert direct current from a battery into alternating current for an electric motor, for example in vehicles (e.g., hybrid vehicles or plug-in electric vehicles) or in trains (e.g., commuter trains).

[0016] For example, the semiconductor chip and thus the semiconductor device are configured for a maximum voltage of at least 0.6 kV, at least 1.2 kV, or at least 1.6 kV. Alternatively or additionally, the semiconductor chip and thus the semiconductor device are configured for a maximum current of at least 1 A, at least 20 A, or at least 50 A; the maximum current may be up to 1000 A or up to 200 A.

[0017] For example, the first electrical wiring layer is an electrical wiring layer immediately adjacent to the top side of the chip. Between the top side of the chip and the first electrical wiring layer, there are one or more electrically insulating layers. Through the insulating layer, an electrically conductive contact makes the top contact region of the semiconductor chip contact the first contact region. The first contact region may be a structured metallization layer applied to at least one electrically insulating layer.

[0018] Similarly, at least one electrically insulating layer exists between the first and second electrical wiring layers, wherein the electrically conductive contact extends through at least one electrically insulating layer. The second electrical wiring layer is the topmost electrical wiring layer applied to the outside of the semiconductor device. For example, the second electrical wiring layer is another structured metallization layer applied on top of the topmost electrically insulating layer. Therefore, the second electrical wiring layer is the electrical wiring layer furthest from the top side of the chip. With the aid of the second contact region, the semiconductor device can be externally contacted, for example, a circuit board.

[0019] For example, as seen in a top view of the chip, at least one, some, or all of the second contact regions are shaped in a different manner than those allocated to the top contact regions. It is also possible that at least one, some, or all of the second contact regions are shaped in a different manner than those allocated to the first contact regions.

[0020] According to at least one embodiment, the semiconductor device further includes one or more third electrical wiring layers. At least one third electrical wiring layer is located between the first electrical wiring layer and the second electrical wiring layer. Furthermore, at least one third electrical wiring layer is electrically connected to both the first and second electrical wiring layers, particularly by means of electrically through-contact portions extending through adjacent additional insulating layers. At least one third electrical wiring layer includes third contact regions, which are formed, for example, by at least one additional structured metallization layer.

[0021] According to at least one embodiment, the following sequence exists: starting from the top side of the chip, the top contact area of ​​the semiconductor chip – an insulating layer with electrically conductive contacts – a first contact area of ​​a first electrical wiring layer – an insulating layer with electrically conductive contacts – a second contact area of ​​a second electrical wiring layer. If there are N third electrical wiring layers, the following sequence exists: the top contact area of ​​the semiconductor chip – an insulating layer with electrically conductive contacts – a first contact area of ​​a first electrical wiring layer – N times (an insulating layer with electrically conductive contacts – a third contact area of ​​a third electrical wiring layer) – an insulating layer with electrically conductive contacts – a second contact area of ​​a second electrical wiring layer, where N is a natural number equal to or greater than one. In particular, N = 1, N = 2, or N = 3. For example, the following applies: 1 ≤ N ≤ 20, 1 ≤ N ≤ 5, or 2 ≤ N ≤ 5.

[0022] For example, there is exactly one electrical insulation layer between each of the electrical wiring layers and between the top contact area and the first electrical wiring layer.

[0023] According to at least one embodiment, the shapes of the assigned contact areas, starting from the top contact area or starting from the first contact area and moving towards the second contact area, respectively, become more similar to the second contact area, for example, from the third electrical wiring layer to the third electrical wiring layer and finally towards the second contact area. Therefore, the shape of the intermediate electrical wiring layer can be progressively changed to approximate the second contact area.

[0024] According to at least one embodiment, the number of top contact areas is the same as the number of contact areas in each of the electrical wiring layers. In other words, the number of contact areas does not change from the chip to the second contact area. For example, a one-to-one allocation of contact areas may exist from the top contact area to the second contact area, from electrical wiring layer to electrical wiring layer. For example, in each case, the contact areas of a wiring layer are electrically connected to the contact areas of adjacent wiring layers by means of one or more electrically pass-through contacts. This also applies to the top contact areas and the first contact areas.

[0025] According to at least one embodiment, the thickness of the insulating layer between the wiring layers and between the top contact area and the first wiring layer is at most 200 μm or at most 120 μm in each case. Alternatively or additionally, the thickness is at least 10 μm, at least 50 μm, or at least 80 μm.

[0026] According to at least one embodiment, at least one or some or each of the wiring layers includes one, two or more contact areas.

[0027] It is possible that contact areas of different wiring layers are assigned to each other according to their size. For example, the largest top contact area is assigned to the largest first contact area, the largest second contact area, and (if any) the largest third contact area, and the smallest top contact area is assigned to the smallest first contact area, the smallest second contact area, and (if any) the smallest third contact area, and so on. The assignment can be a one-to-one assignment.

[0028] For example, the smallest top contact area and the smallest second contact area are the gate contact portions. 'Small' and 'large' refer, for example, to the area content of the corresponding contact regions, i.e., the size of the region on which the corresponding metallization is applied.

[0029] According to at least one embodiment, in a top view of the chip top side, at least one of the second contact regions overlaps with any one of the top contact regions by up to 20%, 10%, or 5% of the size of the corresponding second contact region. That is, in the top view, the corresponding second contact region and the assigned top contact region do not significantly overlap. This can be applied to exactly one second contact region, some second contact regions, or all second contact regions.

[0030] According to at least one embodiment, as seen in a top view of the chip top side, at least one of the second contact regions is completely outside the corresponding top contact region. That is, as seen in the top view, the corresponding second contact region and the assigned top contact region are separate and therefore do not overlap at all. This can be applied to exactly one second contact region, some second contact regions, or all second contact regions.

[0031] According to at least one embodiment, as seen in a top view of the chip top side, the first element in the second contact region extends partially or completely around the second element in the second contact region. Therefore, as seen in the top view, the second element in the second contact region can be completely surrounded by the first element in the second contact region.

[0032] According to at least one embodiment, the first contact region extends coaxially around the second contact region in the second contact region. Therefore, as seen in the top view, the corresponding second contact regions are arranged in a rotationally symmetric and / or point-symmetric manner. Using such a coaxial design, low parasitic inductance, as well as improved shielding and controlled stray capacitance, can be achieved.

[0033] The coaxial arrangement of the first and second elements in the second contact region means, for example, that the first and second elements in the top contact region have point-symmetric shapes and share the same center of symmetry. Alternatively or additionally, this might mean that, when viewed from above, the first and second elements in the second contact region have the same basic shape, such as a rectangle, square, hexagon, octagon, or circle, and these basic shapes are oriented in the same way, for example, having corresponding corners at the same straight line extending through the common center of symmetry. It is possible that the circumferences of the first and second elements in the second contact region can be mapped onto each other by means of homogeneous expansion.

[0034] For example, the first one in the second contact region is the frame surrounding the second one in the second contact region, and can be an external contact pad for the source or emitter. For example, the first one in the second contact region is the largest one in the second contact region. Therefore, the second one in the second contact region can be the smallest external contact pad, and can be a gate contact pad.

[0035] Therefore, by means of the first and second contacts in the second contact region, different external electrical contact regions of the semiconductor device can be realized.

[0036] According to at least one embodiment, as seen in a top view of the top side of the chip, the top contact area of ​​the second contact area assigned to the second contact area is located at the edge of the top side of the chip. Therefore, the top contact area is arranged in a non-point-symmetric manner, while the second contact area can be arranged in a point-symmetric manner.

[0037] According to at least one embodiment, as seen in a top view of the chip top side, the third party in the second contact area has an L-shape, and the fourth party in the second contact area has a rectangular shape and is located in the cutout of the third party in the second contact area, for example, in the corner of the second electrical wiring layer.

[0038] According to at least one embodiment, the top contact area of ​​the fourth party assigned to the second contact area is located at the central portion of the edge (e.g., the longitudinal edge) on the top side of the chip.

[0039] According to at least one embodiment, as seen in a top view of the top side of the chip, the fifth and sixth contacts in the second contact area have rectangular shapes that extend parallel to each other.

[0040] According to at least one embodiment, also seen in a top view of the chip top side, the top contact area of ​​the fifth person assigned to the second contact area has a U-shape and is positioned adjacent to all four edges of the chip top side, and the top contact area of ​​the sixth person assigned to the second contact area is located outside the sixth person in the second contact area.

[0041] According to at least one embodiment, the top contact area is arranged symmetrically. For example, as seen in a top view of the top side of the chip, there is one or two mirror axes of symmetry with respect to the top contact area. Alternatively, the top contact area can be arranged asymmetrically, i.e., specifically without any mirror or point symmetry.

[0042] According to at least one embodiment, the semiconductor device is a chip-sized package. This may mean that, as seen in a top view from the top side of the chip, the overall size of the semiconductor device is at most 130% or at most 120% of the size of the top side of the chip. Alternatively or additionally, this may mean that the semiconductor device comprises exactly one semiconductor chip.

[0043] According to at least one embodiment, the overall size of all the second contact areas together is greater than the overall size of the top contact area or the size of the top side of the chip. Therefore, by having at least one intermediate wiring layer, the top contact area can be fanned out and / or extended toward the second contact areas.

[0044] According to at least one embodiment, the thickness of the electrical wiring layer and / or the top contact region is at least 1 μm, at least 20 μm, or at least 40 μm in each case. Alternatively, the thickness is at most 200 μm or at most 100 μm. It is possible that the top contact region is thinner than the first and third contact regions, and the second contact region is thicker than the first and third contact regions.

[0045] According to at least one embodiment, the diameter of the electrical direct contact is between 20 μm and 200 μm in each case, including the end value. For example, the diameter is about 0.1 mm.

[0046] Additionally, a semiconductor module is provided. This semiconductor module includes at least one semiconductor device as indicated in the embodiments described above. Therefore, the features of the semiconductor module are also disclosed with respect to the semiconductor device, and vice versa.

[0047] In at least one embodiment, the semiconductor module includes one or more semiconductor devices and an electrical carrier. The second contact region is connected to at least one of the electrical contact surface or thermal contact surface of the electrical carrier.

[0048] Additionally, a method for manufacturing a semiconductor device is provided. By means of this method, a semiconductor device as indicated in at least one of the embodiments described above is produced. Therefore, the features of the semiconductor device are also disclosed with respect to this method, and vice versa.

[0049] In at least one embodiment, the method is used to manufacture a semiconductor device. The method includes the following steps, for example, in the order stated:

[0050] - Provides a semiconductor chip configured for a voltage of at least 0.6kV, the semiconductor chip including a top contact region located on the top side of the chip.

[0051] - Apply dielectric material for the first insulating layer to the top contact area.

[0052] - A first electrical through-contact portion is formed through the first insulating layer, and a first electrical wiring layer is formed on the first insulating layer, the first electrical wiring layer having a first contact area electrically distributed to the top contact area.

[0053] Optionally, at least one additional dielectric material for at least one third insulating layer is applied to the first electrical wiring layer, and a third electrical through-contact portion is formed through the at least one third insulating layer, and at least one third electrical wiring layer is formed on the third insulating layer, the at least one third electrical wiring layer having a third contact region electrically distributed to the first contact region.

[0054] - Apply dielectric material for the second insulating layer on the first wiring layer or (if present) on the topmost third wiring layer.

[0055] - A second electrically conductive contact portion is formed through the second insulating layer, and a second electrical wiring layer is formed on the second insulating layer. The second electrical wiring layer has a second contact region electrically assigned to the top contact region, and the second contact region is configured as an external contact region of the semiconductor device.

[0056] In the top view of the chip, at least one of the second contact areas is shaped in a different manner than that assigned to the top contact area.

[0057] In at least one embodiment, the method is used to manufacture a semiconductor device. The method includes the following steps, for example, in the order stated:

[0058] - Provides a semiconductor chip configured for a voltage of at least 0.6kV, the semiconductor chip including a top contact region located on the top side of the chip.

[0059] - Apply an insulating layer, a first electrical wiring layer, a second electrical wiring layer, and at least one third electrical wiring layer onto a semiconductor chip.

[0060] in,

[0061] - A first wiring layer is in electrical contact with a top contact area, the first wiring layer having a first contact area that is electrically distributed to the top contact area.

[0062] - The second wiring layer is located on the side of the first wiring layer away from the top contact area and has a second contact area electrically distributed to the top contact area, the second contact area being configured as an external contact area.

[0063] - At least one third wiring layer is located between and electrically connected to the first and second wiring layers, and has a third contact area.

[0064] - Semiconductor chips are either power metal-insulator field-effect transistors (MISFETs) or power insulated-gate bipolar transistors (IGBTs).

[0065] The first, second, and third wiring layers are separated from each other by one of the insulating layers, each made of a dielectric material.

[0066] - As seen in the top view of the chip, at least one of the second contact areas is shaped in a different manner than that assigned to the top contact area.

[0067] -As seen in the top view of the chip, the first second contact region in the second contact region, which is shaped in a different manner from that in the top contact region, extends completely around the second second contact region in the second contact region, which is shaped in a different manner from that in the top contact region.

[0068] For the semiconductor devices and modules described herein, the shape of the top contact region does not need to correspond to the shape of the external electrical contact region (e.g., the second contact region). Therefore, it is possible to design the top contact region to achieve optimized semiconductor chip properties, while the second contact region and intermediate contact regions can be designed fairly independently based on the specific requirements of the application scenario (e.g., available physical space). Thus, geometric considerations, electrical considerations (regarding, for example, voltage, current, and insulation), and thermal considerations (e.g., thermal conduction and thermal interfaces) can be taken into account simultaneously. For example, using a coaxial design for the second contact region, low parasitic inductance, improved shielding, control over increased stray capacitance, and / or reduced stray inductance can be achieved. Therefore, by having at least one of the second contact regions have a different shape compared to the one assigned in the top contact region, multifaceted optimizations can be achieved that would be impossible without an intermediate first electrical wiring layer and possibly a third electrical wiring layer. Attached Figure Description

[0069] The semiconductor devices, semiconductor modules, and methods described herein are explained in more detail below with reference to the accompanying drawings and exemplary embodiments. Identical elements in the various figures are indicated by the same reference numerals. However, the relationships between elements are not shown to scale, but rather the elements may be shown exaggerated to aid understanding.

[0070] In the attached diagram:

[0071] Figure 1 This is a schematic top view of a modified semiconductor device.

[0072] Figure 2 yes Figure 1 A schematic cross-sectional view of a semiconductor device.

[0073] Figure 3 This is a schematic cross-sectional view of an exemplary embodiment of the semiconductor device described herein.

[0074] Figure 4 Is with Figure 3 A schematic top view of a semiconductor device from the vertical direction.

[0075] Figures 5 to 9 This is a schematic top view of an exemplary embodiment of the semiconductor device described herein.

[0076] Figures 10 to 12 This is a schematic cross-sectional view of an exemplary embodiment of the semiconductor device described herein.

[0077] Figures 13 to 16 These are different schematic cross-sectional views of exemplary embodiments of the semiconductor devices described herein.

[0078] Figure 17 This is a schematic side view of an exemplary embodiment of a semiconductor module including the semiconductor devices described herein, and

[0079] Figure 18 This is a schematic block diagram of an exemplary embodiment of a method for manufacturing the semiconductor device described herein. Detailed Implementation

[0080] exist Figure 1 and Figure 2 The modified semiconductor device 9 is illustrated in the figure. The modified semiconductor device 9 includes a semiconductor chip 2 embedded in an insulating body 6. At the top side 20 of the chip, the semiconductor chip 2 includes a top contact region 21. In the lateral direction (i.e., in the direction parallel to the top side 20 of the chip), the semiconductor chip 2 is embedded in the insulating embedding portion 60 of the insulating body 6.

[0081] Starting from the top contact region 21, a first electrical through contact 71 extends through the first insulating layer 61 of the insulating body 6. By means of the through contact 71, the top contact region 21 is electrically connected to the first contact region 31 of the first electrical wiring layer 3 located at the top side 66 of the insulating body 6. Alternatively, a semiconductor chip 2 is applied to a substrate 8, the side surface of which can contact the insulating body 6.

[0082] Chip-scale packaging (CSP) originated from conventional printed circuit board (PCB) manufacturing and was initially envisioned for the integration of miniaturized and heterogeneous microelectronic / optical components, also known as system-in-package (SiP), primarily used in consumer electronics. However, as... Figure 1 The type of package illustrated is not compatible with high voltages, such as 0.6 kV.

[0083] Chip-scale packaging offers numerous advantages over TO-like, QFN, and other surface-mount packages (e.g., improved thermal extraction, leadless bonding, lower parasitic effects) and provides an alternative route for power module assembly (e.g., cleanroom-free assembly). Another key advantage of such embedded solutions is the design freedom to fan out contact areas (also known as bonding pads) and integrate multilayer signal routing of any shape and complexity as needed. This allows for low-inductance interconnects, integration of sensors and controllers with a large number of I / O channels, and ultra-compact packaging without the need for lead bonding, resulting in flat layouts and geometries that also benefit from dual-sided cooling designs. Finally, the development of such technologies could impact the semiconductor power module value chain: chip manufacturers could adopt the technology and break through current technological barriers in the design and assembly of power modules.

[0084] A significant advantage of CSP is that it allows the chip pad contacts to be fanned out. However, in single-metal pre-packaged systems, such as... Figure 1 As shown, the fan-out layout is constrained by the layout of the chip contact pads (i.e., the top contact area 21). For example, the top metallization of the CSP must overlap with the chip contact pads. Therefore, the layout of the top metallization of the CSP cannot be arbitrary, whereas arbitrary layout is desirable when designing power modules to provide complete flexibility in the arrangement of CSP components. Furthermore, for example, enlarging the gate contact pads typically comes at the cost of reducing the drain / emitter contact area, and thus reducing the current capability of the semiconductor chip.

[0085] To overcome these limitations, the semiconductor device 1 described herein includes at least one intermediate wiring layer located between the top contact region 21 and the topmost second electrical wiring layer 4 (compare). Figure 3 and Figure 4 Therefore, multilayer pre-packaging is used to produce CSP components with arbitrary top metallization layouts. This can be accomplished through multiple embedding and lamination steps. Such solutions achieve the desired fan-out without reducing the active area of ​​semiconductor chip 2, and therefore without reducing its current capability.

[0086] For high-voltage applications, the package thickness and, in the case of a multilayer structure, each insulating layer should be properly designed to withstand blocking voltages. These requirements can be relaxed if the inner and top metal pads do not extend across the chip's termination region and the component is further packaged.

[0087] Therefore, a semiconductor device 1 is provided, comprising a semiconductor chip 2 configured for a voltage of at least 0.6 kV, the semiconductor chip 2 having a top contact region 21 located on a chip top side 20, and a plurality of electrically conductive contacts 71, 72, 73 electrically connected to the top contact region 21. The semiconductor chip 2 and the electrically conductive contacts 71, 72, 73 are embedded in an electrically insulating body 6, wherein the electrically conductive contacts 71, 72, 73 extend through the insulating body 6 in a direction away from the chip top side 20. At least one intermediate wiring 3, 5 is present on the side of the top contact region 21 away from the semiconductor chip 2 and is in electrical contact with the electrically conductive contacts 71, 72, 73.

[0088] Wiring layers 3, 4, and 5 are designed to prevent short circuits between any circuits in the top contact areas (also known as chip terminations, such as gate-source-drain).

[0089] according to Figure 3 and Figure 4A first insulating layer 61 is present on top of the top contact area 21, and a first electrical wiring layer 3 is applied on this first insulating layer. Following the first electrical wiring layer 3 is a second insulating layer 62, on which a second electrical wiring layer 4 having a second electrical contact area 42 is applied. Possibly, the second contact area 42 of the second electrical wiring layer 4 is the only contact area exposed from the insulating body 6 at the top side 66 of the body. However, as an option, the semiconductor chip 2 may be electrically contacted with the substrate 8, which may be, for example, a copper-based lead frame. Therefore, only the substrate 8 and the second contact area 42 may be exposed from the insulating body 6.

[0090] Figure 3 The diagram illustrates along Figure 4 A cross-sectional view with dashed lines in the middle. According to... Figure 3 and Figure 4 The smaller of the rectangular second contact areas 42 are connected to multiple smaller ones of the top contact areas 21, but do not overlap with the top contact areas 21 as seen in the top view. This is achieved by means of a first electrical wiring layer 3 located within the insulating body 6, which provides a current path parallel to the top side 20 of the chip. Therefore, the shape of the second contact areas 42 is largely independent of the shape of the top contact areas 21.

[0091] For example, semiconductor chip 2 is a power MOSFET or a power IGBT, configured for a current of at least 10A and / or at most 100A. Alternatively or additionally, semiconductor chip 2 and thus semiconductor device 1 are configured for a voltage of at least 1.2kV or at least 1.5kV.

[0092] Alternatively, as seen in the top view, the larger of the top contact areas 21 is shaped like a └┘ or a U. The smaller of the top contact areas 21 is located between the legs of the └┘ or U. For example, the arrangement of the top contact areas 21 can have at least one axis of mirror symmetry. Figure 4 In the diagram, the top contact area 21 is symbolized as a shaded area, and the semiconductor chip 2 is also schematically illustrated to enhance understanding; however, in Figure 4 The middle wiring layer 3 is not shown in the diagram.

[0093] For example, the size of the top side 20 of the chip is at least 5 mm x 5 mm and / or at most 15 mm x 15 mm. Alternatively or additionally, the thickness of the semiconductor chip 2 perpendicular to the top side 20 of the chip is at least 100 μm and / or at most 1 mm, for example, between 300 μm and 500 μm.

[0094] For example, the electrical through contacts 71, 72, and 73 can be metallized vias or metal blocks. Each contact region 21, 31, 42, and 53 may have only one or more electrical through contacts 71, 72, and 73, depending particularly on the size of the respective contact region 21, 31, 42, and 53 and the current it is configured for. If the through contacts 71, 72, and 73 are metallized vias, their diameters are, for example, between 50 μm and 200 μm; if the through contacts 71, 72, and 73 are metal blocks, they can have a larger lateral width. Such metal blocks can be bonded (e.g., sintered or welded) to the corresponding contact regions 21, 31, 42, and 53.

[0095] The heights of the through contacts 71, 72, and 73 may correspond to the heights of the associated insulating layers 61, 62, 63, and 65. For example, the through contacts 71, 72, and 73 may be made of copper or a copper alloy.

[0096] although Figure 3 and Figure 4 The semiconductor device includes two top contact regions 21 and therefore two contact regions 31, 42 in each of the electrical wiring layers 3, 4. Alternatively, there may be only one top contact region 21 and therefore only one contact region 31, 42 in each of the electrical wiring layers 3, 4, or there may be at least three top contact regions 21 and therefore at least three contact regions 31, 42 in each of the electrical wiring layers 3, 4. Furthermore, it is not strictly required that the number of top contact regions 21 be the same as the number of contact regions 31, 42 in each of the electrical wiring layers 3, 4, although this is preferred. In addition to the electrical contact regions 21, 31, 42, as an option, thermal contact regions (not shown) may also be present to improve cooling; these thermal contact regions do not need to have any electrical function. In all other embodiments, these aspects may also be applied in any combination.

[0097] Other aspects, regarding Figure 1 and Figure 2 The same applies to the situation. Figure 3 and Figure 4 And vice versa.

[0098] exist Figure 5 The diagram illustrates another embodiment of semiconductor device 1, similar to... Figure 4 .according to Figure 5The second contact region 42 is arranged coaxially. Therefore, as seen in the top view of the chip top side 20, the first of the second contact regions 42 extends completely around the second of the second contact regions 42. Thus, both the first and second of the second contact regions 42 belong to the second electrical wiring layer 4 and can be arranged as external electrical contact pads in a common plane. In addition to those shown, there may be other second contact regions 42 of the second electrical wiring layer 4 serving as external electrical contact pads.

[0099] For example, the top contact area 21 of the second contact area 42 is located at the edge of the chip top side 20, and the contact areas 21, 42 may overlap only marginally. Again, as seen in the top view of the chip top side 20, the top contact area 21 of the first contact area 42 may have a └┘ or U shape.

[0100] As seen in the top view, the shape of the second contact region 42 may have two or four mirror-symmetric axes. For example, the outer, first track width of the second contact region 42 may correspond to at least 10% and / or at most 40% of the maximum edge length of the chip top side 20. The inner, second edge length of the second contact region 42 is, for example, at least 20% and / or at most 60% of the maximum edge length of the chip top side 20.

[0101] Other aspects, regarding Figures 1 to 4 The same applies to the situation. Figure 5 And vice versa.

[0102] according to Figure 6 As seen in the top view of the chip top side 20, the larger third contact area 42 has an L-shape, and the smaller fourth contact area 42 has a rectangular or square shape and is located within the cutout of the third contact area 42. For example, the fourth contact area 42 is located in a corner of the second electrical wiring layer 4.

[0103] For example, the top contact area 21 is shaped like... Figure 4 and Figure 5 As in the middle. Therefore, the smaller, fourth one in the second contact area 42 may not overlap with the smaller one assigned in the top contact area 21. Besides Figure 6 In addition to what is shown, it is also possible that the smaller one of the top contact areas 21 is partially or completely covered by a third party in the second contact area 42.

[0104] Other aspects, regarding Figures 1 to 5 The same applies to the situation. Figure 6 And vice versa.

[0105] according to Figure 7 As seen in the top view of the chip top side 20, the fifth and sixth of the second contact areas 42 have rectangular shapes and can extend parallel to each other. The second contact areas 42 can have different sizes. For example, the top contact area 21 is shaped like... Figures 4 to 6 Like in China.

[0106] Therefore, as seen in the top view of the chip top side 20, the larger top contact area 21 assigned to the fifth in the second contact area 42 may have a └┘ or U shape and may be positioned adjacent to all four edges of the chip top side 20, and the top contact area 21 assigned to the sixth in the second contact area 42 is located outside the sixth in the second contact area 42. Thus, the sixth in the second contact area 42 and the assigned top contact area 21 do not overlap or overlap only slightly.

[0107] As in all other embodiments, the overall size of all the second contact areas 42 together may be larger than the size of the top side 20 of the chip.

[0108] Other aspects, regarding Figures 1 to 6 The same applies to the situation. Figure 7 And vice versa.

[0109] exist Figure 8 The diagram shows the central, second contact region 42, which is the largest of the second contact regions 42. This second contact region 42 is, for example, an emitter pad or a source pad, and correspondingly, the circumferential first contact region 42 has a smaller overall area and may be a gate contact pad. For example, the outer, first contact region 42 may correspond to at least 2% and / or at most 15% of the maximum edge length of the top edge 20 of the chip. The inner, second contact region 42 may have an edge length that is, for example, at least 60% and / or at most 95% of the maximum edge length of the top edge 20 of the chip.

[0110] For example, the top contact area 21 is shaped like... Figures 4 to 8 As seen in the top view, the second contact area 42 may have a square shape.

[0111] Other aspects, regarding Figures 1 to 7 The same applies to the situation. Figure 8 And vice versa.

[0112] according to Figure 9As seen in the top view, the inner, second contact region 42 is relatively small, and for example, occupies at most 10% or 5% of the overall size of the semiconductor device 1. Therefore, the circumferential first contact region 42 can cover almost the entire top side 66 of the body. For example, the inner, second contact region 42 is a gate contact pad. In this coaxial design, by placing the gate contact pad in the middle, the outer contact region 42 (which is, for example, an emitter or source contact pad) can be maximized to achieve low parasitic inductance. The same applies to all intermediate wiring layers 3, 5.

[0113] It is possible that, as seen in the top view, the second of the second contact areas 42 does not overlap with the assigned top contact area 21.

[0114] Other aspects, regarding Figure 8 The same applies to the situation. Figure 9 And vice versa.

[0115] exist Figure 10 In the embodiment, all the first contact areas 31 of the first wiring layer 3 are illustrated to be located in a common plane on top of the first insulating layer 61. Further, as an option, an additional insulating layer 65 surrounds the first contact areas 31 in the lateral direction. Therefore, the additional insulating layer 65 is located between the first insulating layer 61 and the second insulating layer 62.

[0116] according to Figure 10 The substrate 8 is not embedded in the insulating body 6; instead, the side surfaces of the substrate 8 are detached from the insulating body 6. The substrate 8 is connected to the semiconductor chip by means of a connecting device 81 (e.g., solder). The substrate 8 is, for example, a heat sink or a lead frame. Such a configuration can also exist in all other embodiments. Note that, for the sake of simplicity, in... Figure 10 Only one of the contact areas 31 and 42 is clearly illustrated in the diagram.

[0117] and Figure 10 The situation shown is the opposite, according to Figure 11 The first contact areas 31, assigned to different top contact areas 21, are not located in a single plane, but are offset in a direction perpendicular to the top side 20 of the chip. Therefore, two additional insulating layers 65 may be present on top of each other, each assigned to one of the first contact areas 31. As an additional option, additional insulating layers 65 may also be present assigned to the connecting device 81.

[0118] Other aspects, regarding Figures 1 to 9 The same applies to the situation. Figure 10 and Figure 11 And vice versa.

[0119] exist Figure 12 The diagram illustrates a semiconductor device 1 comprising more than one intermediate layer, namely, in addition to a first electrical wiring layer 3, at least one third electrical wiring layer 5 located between the first electrical wiring layer 3 and the second electrical wiring layer 4. Figure 12 In the example, there are two third wiring layers 5 located on top of each other; however, it is also possible that there is only one third wiring layer 3, or at least three third wiring layers 5.

[0120] exist Figure 12 In the middle, the intermediate wiring layers 3 and 4 are configured for imaging. Figure 10 In this way, all contact areas 31 and 53 of specific wiring layers 3 and 4 are located in a common plane. However, according to Figure 11 It is also possible to configure the contact areas 31, 53 within one of the first wiring layer 3 and the third wiring layer 4 to be shifted in a direction perpendicular to the top side 20 of the chip.

[0121] In all other embodiments, at least one such third electrical wiring layer 5 may also be present.

[0122] Furthermore, as an option, the intermediate wiring layers 3 and 5 may have patterns of contact areas 31 and 53 that are different from each other. Thus, starting with the top contact area 21, the more the assigned contact areas 31 and 53 are shaped to resemble the assigned second contact area 42, the closer the assigned contact areas 31 and 53 are to the associated second contact area 42.

[0123] It is possible that the metallization of the intermediate wiring layers 3 and 5 is thinner than the metallization of the topmost second wiring layer 4. For example, the thickness of the first contact region 31 and / or the third contact region 53 is between 30 μm and 70 μm, while the thickness of the second contact region 42 is between 80 μm and 200 μm. The same is possible in all other embodiments.

[0124] Other aspects, regarding Figures 1 to 11 The same applies to the situation. Figure 12 And vice versa.

[0125] exist Figures 13 to 16 Another embodiment of the semiconductor device 1 is illustrated in the cross-sectional view. In this case, the semiconductor device 1 includes a third electrical wiring layer 5. Figure 12 Similar to the embodiments, the intermediate layers 3 and 5 have different shapes, which allows for a more gradual change in the shape of the top contact area 21 toward the shape of the second contact area 42.

[0126] Therefore, for example, the top contact area 21 (see Figure 13 It can be shaped into an image Figures 5 to 7Like that. Then, see Figure 14 The smaller one of the first contact areas 31 of the first electrical wiring layer 3 extends toward the center of the semiconductor device 1 (with... Figure 13 compared to).

[0127] Next, see Figure 15 The smaller one in the third contact area 53 is shifted to the center (with) Figure 14 (Compared), and the larger of the third contact areas 53 surrounds the smaller of the third contact areas 53. However, the smaller of the third contact areas 53 is still arranged eccentrically. Finally, see Figure 16 The smaller of the third contact areas 53 is symmetrically surrounded by the larger of the third contact areas 53.

[0128] Such a gradual change in the shape of the contact area toward the shape of the second contact area 42 may also exist in all other exemplary embodiments.

[0129] Other aspects, regarding Figures 1 to 12 The same applies to the situation. Figures 13 to 16 And vice versa.

[0130] exist Figure 17 The diagram illustrates a semiconductor module 10. The semiconductor module 10 includes one or more semiconductor devices 1, such as... Figures 1 to 16 As shown in any of them. The semiconductor module 10 further includes an electrical carrier 11 (e.g., a circuit board). The electrical carrier 11 has a contact surface 12, to which a second contact region 42 is attached, for example by means of soldering or sintering.

[0131] It is possible that, referring to the middle one of the semiconductor devices 1, the contact surface 12 and the assigned second contact area 42 have the same size, or it is possible that, referring to the left one and the right one of the semiconductor devices 1, the contact surface 12 is larger or smaller than the assigned second contact area 42, respectively.

[0132] As a further option, the semiconductor module 10 includes a cooler 13. The cooler 13 may be attached to the substrate 8 of at least one semiconductor device 1. Therefore, it is possible to provide heat sinks on both main sides of at least one semiconductor device 1 to improve cooling and allow for the handling of higher currents.

[0133] Finally, see Figure 18 The diagram schematically illustrates a method for manufacturing semiconductor devices.

[0134] In the first method step S1, a semiconductor chip 1 having a top contact region 42 is provided. In this step, for example, an optional insulating insert 60 is already present.

[0135] Then, in method step S2, a first insulating layer 31 is provided, and a first electrical direct contact 71 is created.

[0136] In method step S3, a first wiring layer 3 is formed, wherein the first contact area 31 can all be in the same plane (comparatively). Figure 10 Alternatively, the first contact areas 31 can be formed one after another by using an additional insulating layer 65 (compare). Figure 11 For example, the thickness of the additional insulating layer 65 corresponds to the thickness of the associated first contact region 31.

[0137] In method step S4, a second insulating layer 62 is provided, and a second electrically conductive contact 72 is formed. If an additional insulating layer 65 is present, the second electrically conductive contact 72 may also extend through the additional insulating layer 65.

[0138] Then, in method step S5, the second contact area 42 is formed, for example, by means of electroplating.

[0139] Optionally, method steps S6 and S7 can be performed between method steps S3 and S4. In method step S6, a third insulating layer 63 is formed and a third electrical pass-through contact 73 is provided to the third insulating layer. In method step S7, a third electrical wiring layer 5 is provided. Method steps S6 and S7 can be repeated a variety of times corresponding to the number of third electrical wiring layers 5.

[0140] Therefore, the CSP semiconductor device 1 is manufactured, for example, through a series of steps:

[0141] i) Bonding (e.g., sintering) the semiconductor chip onto a substrate 8 (e.g., a copper lead frame).

[0142] ii) Embedding the semiconductor chip 1 and optionally the substrate 8 by laminating with copper foil and / or prepreg and cutting the prepreg, or by performing epoxy compression molding as an alternative process.

[0143] iii) For example, through-hole drilling is used to form an electrically conductive contact;

[0144] iv) Perform copper electroplating and structuring to produce the corresponding electrical wiring layers.

[0145] The thickness of the prepreg foil will limit the maximum voltage that the CSP can withstand. Standard materials are FR4 and epoxy resin with a breakdown field of approximately 2 kV / 100 μm. Including safety margins, proper embedding of a 1.2 kV semiconductor device 1 typically requires a 100 μm thick insulating layer 61, 62, 63, 65 between the semiconductor chip 1 and the top-side layer at the source or gate potential. However, technological limitations (i.e., lamination and drilling of thick or multilayer insulating layers, and conformal plating for such deep via structures) hinder the scaling of CSPs to voltages above, for example, 0.6 kV. Higher voltages can be achieved, for example, by means of the multilayer structure of the semiconductor device 1 presented herein, due to increased insulating layer thickness.

[0146] Unless otherwise indicated, the components shown in the figures are preferably arranged in a specified order, one directly or indirectly on top of the other. Non-contacting layers in the figures are preferably spaced apart from each other. If lines are drawn parallel to each other, the corresponding surfaces are preferably oriented parallel to each other. Similarly, unless otherwise indicated, the positions of the drawn components relative to each other are correctly reproduced in the figures.

[0147] The invention described herein is not limited to the description based on embodiments. Rather, the invention covers any new features and any combination of features, particularly any combination of features in the patent claims, even if the feature or combination itself is not expressly specified in the patent claims or exemplary embodiments.

[0148] This patent application claims priority to European Patent Application 2215 2939.9, the disclosure of which is hereby incorporated by reference.

[0149] Figure Labels

[0150] 1. Semiconductor devices

[0151] 2 Semiconductor chips

[0152] 20 Chip Top Side

[0153] 21 Top contact area

[0154] 3 First wiring layer

[0155] 31 First contact area

[0156] 4 Second wiring layer

[0157] 42 Second contact area

[0158] 5 Third wiring layer

[0159] 53 Third Contact Area

[0160] 6. Insulation body

[0161] 60 Insulating Embedded Part

[0162] 61 First Insulation Layer

[0163] 62 Second Insulation Layer

[0164] 63 Third Insulation Layer

[0165] 65. Additional insulation layer

[0166] 66 Main body top side

[0167] 71 First Electrical Direct Contact

[0168] 72 Second Electrical Direct Contact

[0169] 73 Third Electrical Direct Contact Section

[0170] 8 Substrates

[0171] 81 Connecting Devices

[0172] 9 Modified semiconductor devices

[0173] 10 Semiconductor Modules

[0174] 11. Carrier

[0175] 12 Contact surfaces

[0176] 13 Cooler

[0177] S.. Method Steps

Claims

1. A semiconductor device (1), the semiconductor device comprising: - A semiconductor chip (2) configured for a voltage of at least 0.6 kV, the semiconductor chip including a top contact region (21) located on the top side (20) of the chip. - A first electrical wiring layer (3) is electrically contacted with the top contact area (21), the first electrical wiring layer having a first contact area (31) electrically distributed to the top contact area (21). - A second electrical wiring layer (4), located on the side of the first electrical wiring layer (3) away from the top contact area (21) and having a second contact area (42) electrically distributed to the top contact area (21), the second contact area (42) being configured as an external contact area, and - At least one third electrical wiring layer (5), the at least one third electrical wiring layer being located between the first electrical wiring layer (3) and the second electrical wiring layer (4) and electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4), and having a third contact area (53). in, - The semiconductor device (1) is a chip-sized package. - The semiconductor chip (2) is a power metal-insulator field-effect transistor (MISFET) or a power insulated-gate bipolar transistor (IGBT). - The first electrical wiring layer (3), the second electrical wiring layer (4) and the at least one third electrical wiring layer (5) are separated from each other by an insulating layer (61, 62, 63) made of dielectric material, and an electrical direct contact (71, 72, 73) is formed through the insulating layer (61, 62, 63). - A first one in the second contact area (42) with a shape different from that of the electrically assigned top contact area of ​​the top contact area extends coaxially around a second one in the second contact area (42) with a shape different from that of the electrically assigned top contact area of ​​the top contact area, as seen in a top view of the chip top side (20), such that the first and second ones in the second contact area (42) are set to be rotationally symmetric and / or point symmetric.

2. The semiconductor device (1) according to claim 1. Includes at least two third electrical wiring layers from the at least one third electrical wiring layer (5), the at least two third electrical wiring layers being located between the first electrical wiring layer (3) and the second electrical wiring layer (4) and electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4) respectively. in, Starting from the first contact area (31) and moving toward the second contact area (42), the shapes of the assigned third contact areas (53) become more similar to the second contact area (42) from one of the at least two third electrical wiring layers to the other of the at least two third electrical wiring layers.

3. The semiconductor device (1) according to claim 1. in, The thickness of the insulating layers (61, 62, 63) is at most 100 µm in each case.

4. The semiconductor device (1) according to claim 1. in, As seen in the top view of the chip top side (20), the overall size of the semiconductor device (1) is at most 130% of the size of the chip top side (20), and the semiconductor device (1) includes exactly one of the semiconductor chips (2), wherein the sum of the total size of all the second contact areas (42) is greater than the size of the chip top side (20).

5. The semiconductor device (1) according to any one of claims 1 to 4. - The thicknesses of the first electrical wiring layer (3), the second electrical wiring layer (4), and the at least one third electrical wiring layer (5) are in each case between 20 µm and 200 µm, including end values, and - The electrical direct contact (71, 72, 73) extends through each of the insulating layers (61, 62, 63), the electrical direct contact (71, 72, 73) electrically connects adjacent ones of the first electrical wiring layer (3), the second electrical wiring layer (4) and the at least one third electrical wiring layer (5), and the diameter of the electrical direct contact (71, 72, 73) is between 20 µm and 200 µm in each case and includes end values.

6. A semiconductor module (10), the semiconductor module comprising: - At least one semiconductor device (1) according to any one of claims 1 to 5, and - Electrical carrier (11). The second contact area (42) is connected to the electrical contact surface (12) of the electrical carrier (11).

7. A method for manufacturing a semiconductor device (1), the method comprising: - Provides a semiconductor chip (2) configured for a voltage of at least 0.6 kV, the semiconductor chip including a top contact region (21) located on the top side (20) of the chip. - An insulating layer (61, 62, 65) and a first electrical wiring layer (3), a second electrical wiring layer (4) and at least one third electrical wiring layer (5) are applied to the semiconductor chip (2). in - The semiconductor device (1) is a chip-sized package. - The first electrical wiring layer (3) is in electrical contact with the top contact area (21), and the first electrical wiring has a first contact area (31) that is electrically distributed to the top contact area (21). - The second electrical wiring layer (4) is located on the side of the first electrical wiring layer (3) away from the top contact area (21) and has a second contact area (42) electrically assigned to the top contact area (21), the second contact area (42) being configured as an external contact area. - The at least one third electrical wiring layer (5) is located between the first electrical wiring layer (3) and the second electrical wiring layer (4) and is electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4), and has a third contact area (53). - The semiconductor chip (2) is a power metal-insulator field-effect transistor (MISFET) or a power insulated-gate bipolar transistor (IGBT). - The first electrical wiring layer (3), the second electrical wiring layer (4) and the at least one third electrical wiring layer (5) are separated from each other by one of the insulating layers (61, 62, 63) each made of dielectric material, and form electrical direct contact portions (71, 72, 73) through the insulating layers (61, 62, 63). - The first one in the second contact area (42) with a shape different from that of the electrically assigned top contact area of ​​the top contact area extends completely around the second one in the second contact area (42) with a shape different from that of the electrically assigned top contact area of ​​the top contact area, as seen in the top view of the chip top side (20), such that the first one and the second one in the second contact area (42) are set to be rotationally symmetric and / or point symmetric.

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