Voltage regulation circuit, display panel and voltage regulation method

Abstract

The present application discloses a voltage regulation circuit, a display panel and a voltage regulation method. The voltage regulation circuit includes a detection circuit, a controller and a power supply circuit. The detection circuit is configured to detect the maximum voltage value and the minimum voltage value of the data voltage within a specific time period. The controller is configured to determine the regulation voltage based on the average voltage value of the maximum voltage value and the minimum voltage value. The power supply circuit is configured to adjust the voltage of the common electrode to the regulation voltage under the control of the controller. The voltage regulation circuit can automatically adjust the voltage of the common electrode according to the average voltage value of the maximum voltage value and the minimum voltage value, thereby avoiding flickering and afterimage problems caused by unstable voltage of the common electrode, and improving product reliability and user experience. In addition, the automatic regulation of the voltage of the common electrode by the voltage regulation circuit also reduces the need for manual adjustment, thereby reducing production costs and improving production efficiency.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and more specifically, to a voltage regulation circuit, a display panel, and a voltage regulation method. Background Art

[0002] In a display panel, data lines provide data voltages to pixel electrodes via TFTs. Pixel electrodes are connected to common electrodes via capacitors, and both gate and data lines are connected to pixel electrodes via capacitors. The gate voltages of the TFTs differ when they are on and off. The capacitors charge and discharge the pixel electrodes during these periods, resulting in differences in the pixel's ability to maintain positive and negative frame voltages. This can cause a shift in the Vcom voltage provided by the common voltage electrode. This shift in Vcom voltage can cause flicker and image retention in the display panel, impacting both display quality and user experience.

[0003] To address this issue, the traditional method involves manual testing of panels using test equipment such as the CA310 during production. The Vcom voltage is manually adjusted until the display panel exhibits no flicker. However, due to the uneven ΔVp (the difference between the positive and negative frame voltages) across each display panel, manual adjustment of the Vcom voltage is required for each panel, resulting in low efficiency. Summary of the Invention

[0004] Embodiments of the present application provide a voltage regulation circuit, a display panel, and a voltage regulation method.

[0005] The voltage regulation circuit provided in an embodiment of the present application is used for a display panel. The display panel includes a common electrode, a pixel electrode, a gate line, a data line, a control transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor is connected between the common electrode and the pixel electrode, the second capacitor is connected between the pixel electrode and the gate line, the third capacitor is connected between the pixel electrode and the data line, and the fourth capacitor is connected between the gate line and the data line. The control electrode of the control transistor is connected to the gate line, the first electrode of the control transistor is connected to the data line, and the second electrode of the control transistor is connected to the pixel electrode. The data line is configured to provide a data voltage. The voltage regulation circuit includes a detection circuit, a controller, and a power supply circuit. The detection circuit is configured to detect the maximum and minimum voltage values ​​of the data voltage within a specific time period. The controller is configured to determine a regulation voltage based on the average voltage value of the maximum and minimum voltage values. The power supply circuit is configured to regulate the voltage of the common electrode to the regulation voltage under the control of the controller.

[0006] It is understood that the voltage regulation circuit of the embodiments of the present application can automatically adjust the voltage of the common electrode based on the average voltage value of the maximum voltage value and the minimum voltage value, thereby avoiding flicker and afterimage problems caused by unstable common electrode voltage, ensuring that the display panel can provide optimal contrast and viewing angle in different environments and usage conditions, and improving product reliability and user experience. In addition, the voltage regulation circuit automatically adjusts the voltage of the common electrode, thereby reducing production costs and improving production efficiency.

[0007] In some embodiments, the specific time period includes a first time period and a second time period that are adjacent to each other. The detection circuit includes a peak detection circuit and a valley detection circuit. The peak detection circuit is configured to detect a maximum voltage value of the data voltage during the first time period. The valley detection circuit is configured to detect a minimum voltage value of the data voltage during the second time period.

[0008] In this way, the maximum voltage value and the minimum voltage value of the data voltage can be accurately detected by setting the peak detection circuit, the valley detection circuit, and the start time of the peak detection circuit and the start time of the valley detection circuit.

[0009] In some embodiments, the first time period includes the moment when the control transistor is switched from closed to open, and the second time period includes the moment when the control transistor is switched from closed to open.

[0010] In this way, the time when the maximum voltage value and the minimum voltage value of the data voltage appear can be determined according to the time when the control transistor is switched from closed to open.

[0011] In some embodiments, the peak detection circuit includes a first comparator and a first charging circuit. The first comparator includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is configured to receive the data voltage, the second input terminal is configured to receive a first reference voltage, and the first output terminal is configured to output a first control signal when the data voltage is greater than the first reference voltage. The first charging circuit is configured to charge the second input terminal according to the first control signal so that the voltage value of the first reference voltage is consistent with the maximum value of the data voltage.

[0012] In this way, the maximum voltage value of the data voltage can be determined according to the first reference voltage connected to the second input terminal of the first comparator.

[0013] In some embodiments, the first charging circuit includes a first voltage source, a first transistor and a first charging capacitor, the first electrode of the first transistor is connected to the first voltage source, the control electrode of the first transistor is connected to the first output end, the second electrode of the first transistor is grounded through the first charging capacitor, and the second electrode of the first transistor is connected to the second input end.

[0014] In this way, the first voltage source can charge the first charging capacitor, so that the first reference voltage is pulled up until the voltage value of the first reference voltage is consistent with the maximum voltage value of the data voltage, so that the maximum voltage value of the data voltage is determined according to the first reference voltage.

[0015] In some embodiments, the first voltage source is configured to provide a first voltage, wherein a voltage value of the first voltage is greater than a maximum voltage value of the data voltage.

[0016] In this way, by setting the magnitude of the first voltage, it is possible to ensure that the voltage value of the first reference voltage is pulled up to be consistent with the maximum voltage value of the data voltage.

[0017] In some embodiments, the peak detection circuit includes a first discharge circuit, the first charging capacitor is grounded through the first discharge circuit, and the controller is configured to control the first discharge circuit to be connected so as to discharge the first charging capacitor to the ground.

[0018] In this way, after the peak detection circuit detects the peak voltage, the first discharge circuit can reset the voltage of the first charging capacitor, thereby preventing the first charging capacitor from continuously maintaining a high voltage and affecting the circuit.

[0019] In some embodiments, the valley detection circuit includes a second voltage source, a first processing circuit, a second comparator, a second processing circuit, and a second charging circuit. The second voltage source is configured to provide a second voltage. The first processing circuit is configured to provide a first processing voltage based on the second voltage and the data voltage, where the first processing voltage is the difference between the second voltage and the data voltage. The second comparator includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is configured to receive the first processing voltage, the fourth input terminal is configured to receive a second reference voltage, and the second output terminal is configured to output a second control signal when the first processing voltage is greater than the second reference voltage. The second processing circuit is configured to provide a second processing voltage based on the second reference voltage and the second voltage, where the second processing voltage is the difference between the second voltage and the second reference voltage. The second charging circuit is configured to charge the fourth input terminal according to the second control signal to ensure that the voltage value of the second reference voltage is consistent with the maximum value of the first processing voltage, thereby ensuring that the voltage value of the second processing voltage is consistent with the minimum value of the data voltage.

[0020] In this way, the minimum voltage value of the data voltage can be determined according to the second processing voltage provided by the second processing circuit.

[0021] In some embodiments, the valley detection circuit includes a second discharge circuit, the second charging capacitor is grounded through the second discharge circuit, and the controller is configured to control the second discharge circuit to be connected so as to discharge the second charging capacitor to the ground.

[0022] In this way, after the valley detection circuit detects the peak voltage, the second discharge circuit can reset the voltage of the second charging capacitor, thereby preventing the second capacitor from continuously maintaining a high voltage and affecting the circuit.

[0023] In some embodiments, the controller is further configured to control the power supply circuit to supply power to the detection circuit when the display panel displays flickering, so that the detection circuit detects the maximum voltage value and the minimum voltage value of the data voltage within a specific time period.

[0024] In this way, the controller can control the power supply circuit to supply power to the detection circuit according to the condition of the display panel, so as to reduce the power consumption of the display panel.

[0025] An embodiment of the present application further provides a display panel, which includes the voltage regulating circuit of the above embodiment.

[0026] An embodiment of the present application also provides a voltage adjustment method, which includes: obtaining the maximum voltage value and the minimum voltage value of the data voltage within a specific time period; determining an adjustment voltage based on the average voltage value of the maximum voltage value and the minimum voltage value; and controlling the power supply circuit to adjust the voltage of the common electrode to the adjustment voltage.

[0027] In the voltage regulation circuit, display panel, and voltage regulation method provided in the embodiments of the present application, the voltage regulation circuit can automatically adjust the voltage of the common electrode based on the average voltage value of the maximum voltage value and the minimum voltage value detected by the detection circuit. This avoids flickering and afterimage problems caused by unstable common electrode voltage, ensures that the display panel can provide optimal contrast and viewing angle in different environments and usage conditions, and improves product reliability and user experience. In addition, the voltage regulation circuit's automatic adjustment of the common electrode voltage also reduces the need for manual adjustment, thereby reducing production costs and improving production efficiency.

[0028] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 is a schematic diagram of a voltage regulating circuit and a display panel according to an embodiment of the present application;

[0031] Figure 2 is a schematic diagram of the connection of pixel electrodes according to an embodiment of the present application;

[0032] Figure 3 is a timing diagram of the data voltage and the common voltage in an embodiment of the present application;

[0033] Figure 4 is a schematic diagram of a peak detection circuit according to an embodiment of the present application;

[0034] Figure 5 Schematic diagram of a valley detection circuit according to an embodiment of the present application.

[0035] Explanation of main component symbols: common electrode 100, pixel electrode 110, gate line 120, data line 130, control transistor 140, first capacitor 151, second capacitor 152, third capacitor 153, fourth capacitor 154, voltage regulation circuit 200, detection circuit 300, peak detection circuit 310, first comparator 311, first charging circuit 312, first voltage source 3121, first transistor 3122, first charging capacitor 3123, first discharge circuit 313, valley detection circuit 320, second voltage source 321, first processing circuit 322, second comparator 323, second processing circuit 324, second charging circuit 325, second transistor 3251, second charging capacitor 3252, second discharge circuit 326, controller 400, power supply circuit 500, display panel 1000. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below. The embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0037] In a display panel, data lines provide data voltages to pixel electrodes via TFTs. Pixel electrodes are connected to common electrodes via capacitors, and both gate and data lines are connected to pixel electrodes via capacitors. The gate voltages of the TFTs differ when they are on and off. The capacitors charge and discharge the pixel electrodes during the on and off phases of the TFTs, resulting in differences in the ability of the pixel voltage to maintain positive and negative frame voltages. This can cause a shift in the Vcom voltage provided by the common voltage electrode. This shift in Vcom voltage can cause flickering and image retention in the display panel, impacting the display quality and user experience.

[0038] To address this issue, the traditional method involves manual testing of panels using test equipment such as the CA310 during production. The Vcom voltage is manually adjusted until the display panel exhibits no flicker. However, due to the uneven ΔVp (the difference between the positive and negative frame voltages) across each display panel, manual adjustment of the Vcom voltage is required for each panel, resulting in low efficiency.

[0039] Reference Figure 1 as well as Figure 2In one embodiment of the present application, a display panel 1000 is provided. The display panel 1000 includes a common electrode 100, a pixel electrode 110, a gate line 120, a data line 130, a control transistor 140, a first capacitor 151, a second capacitor 152, a third capacitor 153, and a fourth capacitor 154. The first capacitor 151 is connected between the common electrode 100 and the pixel electrode 110, the second capacitor 152 is connected between the pixel electrode 110 and the gate line 120, the third capacitor 153 is connected between the pixel electrode 110 and the data line 130, and the fourth capacitor 154 is connected between the gate line 120 and the data line 130. The control electrode of the control transistor 140 is connected to the gate line 120, the first electrode of the control transistor 140 is connected to the data line 130, the second electrode of the control transistor 140 is connected to the pixel electrode 110, and the data line 130 is configured to provide a data voltage.

[0040] The display panel also includes a voltage regulation circuit 200, which includes a detection circuit 300, a controller 400, and a power supply circuit 500. The detection circuit 300 is configured to detect the maximum voltage value and the minimum voltage value of the data voltage within a specific time period. The controller 400 is configured to determine the regulated voltage based on the average voltage value of the maximum voltage value and the minimum voltage value. The power supply circuit 500 is configured to regulate the voltage of the common electrode 100 to the regulated voltage under the control of the controller 400.

[0041] The present invention provides a voltage regulation method, comprising: obtaining a maximum voltage value and a minimum voltage value of a data voltage within a specific time period; determining a regulation voltage based on an average of the maximum voltage value and the minimum voltage value; and controlling a power supply circuit 500 to regulate the voltage of a common electrode 100 to the regulation voltage. The voltage regulation method of the present invention can be implemented by the voltage regulation circuit 200 or the display panel 1000 provided in the present invention.

[0042] Specifically, refer to Figure 2 The common electrode 100 can be set as the electrode Com, the gate line 120 can be set as the signal line Gate, the data line 130 can be set as the signal line Data, and the control transistor 140 can be set as the transistor Qa. The control electrode of the transistor Qa is connected to the signal line Gate, the first electrode of the transistor Qa is connected to the signal line Data, and the second electrode of the transistor Qa is connected to the pixel electrode 110.

[0043] The first capacitor 151 can be set as a capacitor Cst, the second capacitor 152 can be set as a capacitor Cgs, the third capacitor 153 can be set as a capacitor Cdp1, and the fourth capacitor 154 can be set as a capacitor Cgc. Capacitor Cst is connected between the electrode Com and the pixel electrode 110, capacitor Cgs is connected between the signal line Gate and the pixel electrode 110, capacitor Cdp1 is connected between the signal line Data and the pixel electrode 110, and capacitor Cgc is connected between the signal line Gate and the signal line Data. The first capacitor 151 can also be set as a capacitor CIc, and the third capacitor 153 can also be set as a capacitor Cdp2. Capacitor CIc is connected between the electrode Com and the pixel electrode 110, and capacitor Cdp2 is connected between the signal line Data and the pixel electrode 110.

[0044] The voltage of the pixel electrode 110 can be set to voltage Vp. The voltage of the electrode Com can be set to voltage Vcom, the voltage provided by the signal line Data can be set to voltage Vd, and the voltage provided by the signal line Gate can be set to voltage Vg. When the voltage provided by the signal line Gate is Vgon, the transistor Qa is turned on, and when the voltage provided by the signal line Gate is Vgoff, the transistor Qa is turned off.

[0045] Since the total charge of capacitors Cst, CIc, Cdp1, Cdp2 and Cgc complies with the charge conservation principle, the voltage provided by the signal line Gate is inconsistent when the transistor Qa is turned on and off. The voltage Vp of the pixel electrode 110 will change, and the voltage change value of the pixel electrode 110 is The voltage change ΔVp of the pixel electrode 110 may cause the electrode Com to charge and discharge the capacitor Cst or the capacitor CIc, thereby causing a shift in Vcom.

[0046] The detection circuit 300 can be turned on during a specific time period. The maximum voltage value of the voltage Vd provided by the signal line Data during the specific time period can be set to voltage Vdmax. The minimum voltage value of the voltage Vd provided by the signal line Data during the specific time period can be set to voltage Vdmin. The detection circuit 300 can detect voltages Vdmax and Vdmin when turned on.

[0047] The voltage difference between voltage Vdmax and voltage Vcom can be set to x1, and the voltage difference between voltage Vcom and voltage Vdmin can be set to x2. When voltage Vcom is less than voltage Vd, the pixel voltage is maintained at a positive frame voltage. When voltage Vcom is greater than voltage Vd, the pixel voltage is maintained at a negative frame voltage. If x1 and x2 are inconsistent, the pixel's ability to maintain positive and negative frame voltages differs, and voltage Vcom deviates from its optimal position, potentially causing flicker and afterimages on display panel 1000.

[0048] The controller 400 may set the adjustment voltage to (Vdmax+Vdmin) / 2, and control the power supply circuit 500 to output the voltage (Vdmax+Vdmin) / 2 to the electrode Com, so that the voltage Vcom=(Vdmax+Vdmin) / 2.

[0049] In this way, the voltage regulator circuit 200 can automatically adjust the Vcom voltage, avoiding flicker and afterimage issues caused by unstable Vcom voltage. This ensures that the display panel 1000 provides optimal contrast and viewing angles in a variety of environments and usage conditions, improving product reliability and user experience. Furthermore, the automatic adjustment of the Vcom voltage by the voltage regulator circuit 200 reduces the need for manual adjustment, thereby reducing production costs and improving production efficiency.

[0050] The voltage regulation circuit 200 and regulation method provided in the embodiments of the present application can adapt to different types of displays and technologies and have good flexibility and scalability.

[0051] In some embodiments, the specific time period includes a first time period and a second time period that are adjacent to each other. The detection circuit 300 includes a peak detection circuit 310 and a valley detection circuit 320. The peak detection circuit 310 is configured to detect the maximum voltage value of the data voltage in the first time period. The valley detection circuit 320 is configured to detect the minimum voltage value of the data voltage in the second time period.

[0052] Specifically, refer to Figure 3 , the first time period can be set to the time period t0 to t2. In the time period t0 to t1, the transistor Qa is turned on, and the voltage Vd provided by the signal line Data is written to the pixel electrode 110. The voltage value of the voltage Vd provided by the signal line Data rises from a voltage value lower than Vcom to a voltage value higher than Vcom, and the pixel voltage switches from a negative frame voltage to a positive frame voltage. In the time period t1 to t2, the transistor Qa is turned off, and the pixel voltage maintains a positive frame voltage. The peak detection circuit 310 can be turned on in the time period t0 to t2, and detect Vdmax in the time period t0 to t2, that is, detect the ability of the pixel voltage to maintain the positive frame voltage.

[0053] The second time period can be set to the time period t2 to t4. In the time period t2 to t3, the transistor Qa is turned on, and the voltage Vd provided by the signal line Data is written to the pixel electrode 110. The voltage value of the voltage Vd provided by the signal line Data rises from a voltage value higher than Vcom to a voltage value lower than Vcom, and the pixel voltage switches from a positive frame voltage to a negative frame voltage. In the time period t3 to t4, the transistor Qa is turned off, and the pixel voltage maintains a negative frame voltage. The valley detection circuit 320 can be turned on in the time period t2 to t4, and detect Vdmin in the time period t2 to t4, that is, detect the pixel voltage's ability to maintain a negative frame voltage.

[0054] In this way, by setting the peak detection circuit 310 , the valley detection circuit 320 , and the on-time of the peak detection circuit 310 and the on-time of the valley detection circuit 320 , the maximum voltage value and the minimum voltage value of the data voltage can be accurately detected.

[0055] In some embodiments, the first time period includes the moment when the control transistor 140 is switched from closed to open, and the second time period includes the moment when the control transistor 140 is switched from closed to open.

[0056] Specifically, during the time period t0 to t1, the voltage Vd provided by the signal line Data gradually increases. During the time period t2, due to the decrease in the voltage Vg, the signal line Data charges the capacitor Cgd, causing the voltage Vd provided by the signal line Data to gradually decrease. Therefore, during the time period t0 to t2, the voltage Vd provided by the signal line Data reaches its maximum at time t1, which can be set to Vdmax.

[0057] During the time period t2 to t3, the voltage Vd provided by the Data signal line gradually decreases. At time t3, due to the increase in the voltage Vg, the Data signal line discharges the capacitor Cgd, causing the voltage Vd provided by the Data signal line to gradually increase. Therefore, during the time period t2 to t4, the voltage Vd provided by the Data signal line reaches its minimum at time t3 and can be set to Vdmin.

[0058] In this way, the time when the maximum voltage value and the minimum voltage value of the data voltage appear can be determined according to the time when the control transistor 140 is switched from on to off.

[0059] Reference Figure 4In some embodiments, the peak detection circuit 310 includes a first comparator 311 and a first charging circuit 312. The first comparator 311 includes a first input terminal, a second input terminal, and a first output terminal. The first input terminal is configured to receive a data voltage, the second input terminal is configured to receive a first reference voltage, and the first output terminal is configured to output a first control signal when the data voltage is greater than the first reference voltage. The first charging circuit 312 is configured to charge the second input terminal according to the first control signal so that the voltage value of the first reference voltage is consistent with the maximum value of the data voltage.

[0060] Specifically, the first comparator 311 can be set as the comparator U2, the first input terminal can be set as the positive input terminal of the comparator U2, the second input terminal can be set as the negative input terminal of the comparator U2, and the first output terminal can be set as the output terminal of the comparator U2.

[0061] The positive input of the comparator U2 is connected to the data voltage Vd, and the negative input of the comparator U2 is connected to the first reference voltage Vref1. When the data voltage Vd is greater than the first reference voltage Vref1, the comparator U2 can output a first control signal, causing the first charging circuit 312 to charge the negative input of the comparator U2, thereby increasing the first reference voltage Vref1. When the data voltage Vd is greater than the first reference voltage Vref1, the first reference voltage Vref1 is continuously increased until the data voltage Vd equals the first reference voltage Vref1.

[0062] During the time period t0 to t1, the data voltage Vd provided by the signal line Data gradually increases, and the first reference voltage Vref1 is pulled up until it matches the data voltage Vd. At time t1, the first reference voltage Vref1 reaches Vdmax. During the time period t1 to t2, the data voltage Vd gradually decreases, and the first reference voltage Vref1 remains at Vdmax. Vdmax is determined based on the value of the first reference voltage Vref1 during the time period t1 to t2.

[0063] In this way, the maximum voltage value of the data voltage can be determined according to the first reference voltage connected to the second input terminal of the first comparator 311 .

[0064] The peak detection circuit 310 further includes a comparator U1 and a comparator U3 . The comparator U1 and the comparator U3 can be set as positive-following comparators.

[0065] The voltage terminal Vin can be connected to the positive input terminal of the comparator U1 via a resistor R1, the negative input terminal of the comparator U1 is connected to the output terminal of the comparator U1, and the output terminal of the comparator U1 is connected to the positive input terminal of the comparator U2 via a resistor R2. The voltage terminal Vin can be connected to the data voltage Vd provided by the signal line Data. The voltage connected to the voltage terminal Vin is consistent with the output voltage of the output terminal of the comparator U1 and the voltage connected to the positive input terminal of the comparator U2, and is the data voltage Vd provided by the signal line Data.

[0066] The positive input of the comparator U3 is connected to the first charging circuit 312, the negative input of the comparator U3 is connected to the output of the comparator U3, and the output of the comparator U3 is connected to the negative input of the comparator U2 via the resistor R7. The voltage applied to the positive input of the comparator U3 is consistent with the voltage output by the output of the comparator U3 and the voltage applied to the negative input of the comparator U2, and is the first reference voltage Vref1.

[0067] The output of comparator U3 can be grounded via resistor R8 and capacitor C2, and signal terminal PEAK+ can be grounded via capacitor C2. The output of comparator U3 can output a first reference voltage Vref1 to charge capacitor C2, so that the voltage provided by signal terminal PEAK+ is the first reference voltage Vref1. Controller 400 can be connected to signal terminal PEAK+ and determine Vdmax based on the first reference voltage Vref1 provided by signal terminal PEAK+.

[0068] In some embodiments, the first charging circuit 312 includes a first voltage source 3121, a first transistor 3122 and a first charging capacitor 3123, the first electrode of the first transistor 3122 is connected to the first voltage source 3121, the control electrode of the first transistor 3122 is connected to the first output end, the second electrode of the first transistor 3122 is grounded through the first charging capacitor 3123, and the second electrode of the first transistor 3122 is connected to the second input end.

[0069] Specifically, the first voltage source 3121 can be set to the voltage source AVDD1, the first transistor 3122 can be set to the transistor Q1, and the first charging capacitor 3123 can be set to the capacitor C1.

[0070] The voltage source AVDD1 can be connected to the first electrode of the transistor Q1 through the resistor R4, the output end of the comparator U2 is connected to the control electrode of the transistor Q1, the second electrode of the transistor Q1 can be grounded through the resistor R5, the second electrode of the transistor Q1 can be connected to the positive input end of the comparator U3 through the resistor R3 and the diode D1, the second electrode of the transistor Q1 can be connected to one end of the capacitor C1 through the resistor R3 and the diode D1, and the other end of the capacitor C1 is grounded.

[0071] When the data voltage Vd is greater than the first reference voltage Vref1, the comparator U2 can output a first control signal to turn on the transistor Q1. When the transistor Q1 is turned on, the voltage source AVDD1 can charge the capacitor C1, so that the voltage connected to the positive input of the comparator U3 is pulled up, that is, the first reference voltage Vref1 is pulled up.

[0072] When the data voltage Vd is consistent with the first reference voltage Vref1, the comparator U2 stops outputting the first control signal, the transistor Q1 is disconnected, the connection between the voltage source AVDD1 and the capacitor C1 is disconnected, the voltage source AVDD1 stops charging the capacitor C1, and the voltage value of the first reference voltage Vref1 is maintained at the voltage value of the data voltage Vd.

[0073] In this way, the first voltage source 3121 can charge the first charging capacitor 3123, so that the first reference voltage is pulled up until the voltage value of the first reference voltage is consistent with the maximum voltage value of the data voltage, so that the maximum voltage value of the data voltage is determined according to the first reference voltage.

[0074] In some embodiments, the first voltage source 3121 is configured to provide a first voltage having a voltage value greater than a maximum voltage value of the data voltage.

[0075] Specifically, the voltage provided by the voltage source AVDD1 may be set to a voltage Vdd1 , and the voltage Vdd1 may be set to be greater than the voltage Vdmax.

[0076] During the time period from t0 to t1, the data voltage Vd provided by the signal line Data gradually increases. At time t1, the first reference voltage Vref1 reaches Vdmax. During the time period from t0 to t1, the comparator U2 continuously outputs the first control signal to close the transistor Qa, thereby connecting the voltage source AVDD1 to the capacitor C1.

[0077] When voltage source AVDD1 is connected to capacitor C1, if voltage Vdd1 is greater than first reference voltage Vref1, voltage source AVDD1 can charge capacitor C1 to increase first reference voltage Vref1. Because voltage Vdd1 is greater than voltage Vdmax, voltage Vdmax is greater than or equal to first reference voltage Vref1, and voltage Vdd is greater than first reference voltage Vref1, voltage source AVDD1 can charge capacitor C1 when comparator U2 outputs the first control signal, ensuring that first reference voltage Vref1 is consistent with voltage Vdmax.

[0078] In this way, by setting the magnitude of the first voltage, it is possible to ensure that the voltage value of the first reference voltage is pulled up to be consistent with the maximum voltage value of the data voltage.

[0079] In some embodiments, the peak detection circuit 310 includes a first discharge loop 313 , and the first charging capacitor 3123 is grounded through the first discharge loop 313 . The controller 400 is configured to control the first discharge loop 313 to be connected so that the first charging capacitor 3123 discharges to the ground.

[0080] Specifically, the first discharge circuit 313 may include a transistor M1, a resistor R6, a resistor R23, a diode D3, and a signal terminal Discharge1. One end of the capacitor C1 is grounded, and the other end of the capacitor C1 may be connected to the first electrode of the transistor M1 via the resistor R6. The signal terminal Discharge1 may be connected to the control electrode of the transistor M1 via the diode D3, and the second electrode of the transistor M1 is grounded. The signal terminal Discharge1 may also be grounded via the diode D3 and the resistor R23.

[0081] The controller 400 may be connected to the signal terminal Discharge 1. When the peak detection circuit 310 is working, for example, during the time period t0 to t2, the controller 400 may control the transistor M1 to be disconnected to prevent the first discharge loop 313 from affecting the voltage of the capacitor C1.

[0082] When the peak detection circuit 310 stops working, for example, after the controller 400 obtains the voltage Vdmax, the controller 400 can control the transistor M1 to close, so that the voltage of the capacitor C1 is discharged to the ground, thereby resetting the voltage of the capacitor C1 and preventing the capacitor C1 from continuously maintaining a high voltage and affecting the circuit.

[0083] In this way, after the peak detection circuit 310 detects the peak voltage, the first discharge circuit 313 can reset the voltage of the first charging capacitor 3123 to prevent the first charging capacitor 3123 from continuously maintaining a high voltage and affecting the circuit.

[0084] In some embodiments, the valley detection circuit 320 includes a second voltage source 321, a first processing circuit 322, a second comparator 323, a second processing circuit 324, and a second charging circuit 325. The second voltage source 321 is configured to provide a second voltage. The first processing circuit 322 is configured to provide a first processing voltage based on the second voltage and the data voltage, where the first processing voltage is the difference between the second voltage and the data voltage. The second comparator 323 includes a third input terminal, a fourth input terminal, and a second output terminal. The third input terminal is configured to receive the first processing voltage, the fourth input terminal is configured to receive a second reference voltage, and the second output terminal is configured to output a second control signal when the first processing voltage is greater than the second reference voltage. The second processing circuit 324 is configured to provide a second processing voltage based on the second reference voltage and the second voltage, where the second processing voltage is the difference between the second voltage and the second reference voltage. The second charging circuit 325 is configured to charge the fourth input terminal according to the second control signal to ensure that the voltage value of the second reference voltage is consistent with the maximum value of the first processing voltage, thereby ensuring that the voltage value of the second processing voltage is consistent with the minimum value of the data voltage.

[0085] Specifically, the second voltage source 321 may be set to the voltage source AVDD2 , and the first processing circuit 322 may include a comparator U7 , a resistor R14 , a resistor R17 , a resistor R18 , and a resistor R25 .

[0086] The signal terminal Vin2 can be connected to the negative input terminal of the comparator U7 via resistor R14, and the negative input terminal of the comparator U7 can be connected to the output terminal of the comparator U7 via resistor R17. The voltage source AVDD2 can be connected to the positive input terminal of the comparator U7 via resistor R18, and the positive input terminal of the comparator U7 can also be grounded via resistor R25. The signal terminal Vin2 can be connected to the voltage Vd provided by the signal line Data, and the voltage connected to the voltage source AVDD2 can be set to voltage Vdd2. By setting the resistance values ​​of resistors R14, R18, R25, and R17, the first processed voltage Vout1 output by the comparator U7 can be set to Vdd2-Vd.

[0087] The second comparator 323 can be set as the comparator U6, the third input terminal can be set as the positive input terminal of the comparator U6, the fourth input terminal can be set as the negative input terminal of the comparator U6, and the second output terminal can be set as the output terminal of the comparator U6.

[0088] The positive input of the comparator U6 is connected to the first processing voltage Vout1, and the negative input of the comparator U6 is connected to the second reference voltage Vref2. When the data voltage Vout1 is greater than the second reference voltage Vref2, the comparator U6 can output a second control signal, causing the second charging circuit 325 to charge the negative input of the comparator U6, thereby increasing the second reference voltage Vref2. When the first processing voltage Vout1 is greater than the second reference voltage Vref2, the second reference voltage Vref2 is continuously increased until the first processing voltage Vout1 equals the second reference voltage Vref2.

[0089] During the time period from t2 to t3, the data voltage Vd provided by the signal line Data gradually decreases, the first process voltage Vout1 gradually increases, and the second reference voltage Vref2 is pulled up until it matches the first process voltage Vout1. At time t3, the first process voltage Vout1 reaches its maximum value of Vdd2-Vdmin, and the second reference voltage Vref2 reaches its maximum value of Vdd2-Vdmin.

[0090] During the time period t3 to t4, the voltage value of the data voltage Vd gradually increases, the voltage value of the first processing voltage Vout1 gradually decreases, and the voltage value of the second reference voltage Vref2 can be maintained at Vdd2-Vdmin.

[0091] The second processing circuit 324 may include a comparator U8, resistors R19, R20, R22, and R26. The negative input of the comparator U8 may be connected to the second reference voltage Vref2 via resistor R20, and the negative input of the comparator U8 may be connected to the output of the comparator U8 via resistor R19. The positive input of the comparator U8 may be connected to the signal terminal AVDD2 via resistor R22, and the positive input of the comparator U8 may be grounded via resistor R26. By setting the resistance values ​​of resistors R19, R20, R22, and R16, the second processed voltage Vout2 output by the comparator U8 may be set to Vdd2 - Vref2.

[0092] During the time period t2 to t3, the voltage value of Vout1 gradually increases, the second reference voltage Vref2 is continuously pulled up until it matches the first process voltage Vout1, and the second process voltage Vout2 is continuously pulled down. At time t3, the voltage value of the first process voltage Vout1 can reach the maximum value Vdd2-Vdmin, the voltage value of the second reference voltage Vref2 can reach Vdd2-Vdmin, and the second process voltage Vout2 is pulled down to the minimum value Vdmin.

[0093] The output of comparator U8 can be grounded via resistor R21 and capacitor C5, and signal terminal PEAK- can be grounded via capacitor C5. The output of comparator U8 can output a second processed voltage Vout2 to charge capacitor C5, so that the voltage provided by signal terminal PEAK- is the second processed voltage Vout2. Controller 400 can be connected to signal terminal PEAK- and determine Vdmin based on the second processed voltage Vout2 provided by signal terminal PEAK-.

[0094] In this way, the minimum voltage value of the data voltage can be determined according to the second processing voltage provided by the second processing circuit 324 .

[0095] The valley detection circuit 320 further includes a comparator U5 , which can be set as a positive follower comparator.

[0096] The positive input of the comparator U5 is connected to the second charging circuit 325, the negative input of the comparator U5 is connected to the output of the comparator U5, and the output of the comparator U5 is connected to the negative input of the comparator U6 via the resistor R9. The voltage applied to the positive input of the comparator U5 is consistent with the voltage output by the output of the comparator U5 and the voltage applied to the negative input of the comparator U6, and is the second reference voltage Vref2.

[0097] In some embodiments, the second charging circuit 325 includes a second transistor 3251 and a second charging capacitor 3252, the first electrode of the second transistor 3251 is connected to the second voltage source 321, the control electrode of the second transistor 3251 is connected to the second output terminal, the second electrode of the second transistor 3251 is grounded through the second charging capacitor 3252, and the second electrode of the second transistor 3251 is connected to the fourth input terminal.

[0098] Specifically, the second transistor 3251 can be set to transistor Q2, and the second charging capacitor 3252 can be set to capacitor C4.

[0099] The voltage source AVDD2 can be connected to the first electrode of the transistor Q2 through the resistor R10, the output end of the comparator U6 is connected to the control electrode of the transistor Q2, the second electrode of the transistor Q2 can be grounded through the resistor R15, the second electrode of the transistor Q2 can be connected to the positive input end of the comparator U5 through the resistor R12 and the diode D2, the second electrode of the transistor Q1 can be connected to one end of the capacitor C4 through the resistor R12 and the diode D2, and the other end of the capacitor C4 is grounded.

[0100] When the data voltage Vout1 is greater than the second reference voltage Vref2, the comparator U6 can output a second control signal to control the transistor Q2 to turn on. When the transistor Q2 is turned on, the voltage source AVDD2 can charge the capacitor C4, so that the voltage connected to the positive input terminal of the comparator U5 is pulled up, that is, the second reference voltage Vref2 is pulled up.

[0101] When the first processing voltage Vout1 is consistent with the second reference voltage Vref2, the comparator U6 stops outputting the second control signal, the transistor Q2 is disconnected, the connection between the voltage source AVDD2 and the capacitor C4 is disconnected, the voltage source AVDD2 stops charging the capacitor C4, and the voltage value of the second reference voltage Vref2 is maintained at the voltage value of the first processing voltage Vout1, that is, the voltage value of the second reference voltage Vref2 can be maintained at Vdd2-Vdmin, thereby maintaining the second processing voltage Vout2 at Vdmin.

[0102] In this way, the second voltage source 321 can charge the second charging capacitor 3252, so that the second reference voltage is pulled up and the second processing voltage is pulled down until the second processing voltage is consistent with the minimum voltage value of the data voltage, so as to determine the minimum voltage value of the data voltage according to the second processing voltage.

[0103] In some embodiments, the valley detection circuit 320 includes a second discharge loop 326 , and the second charging capacitor 3252 is grounded via the second discharge loop 326 . The controller 400 is configured to control the second discharge loop 326 to be connected so as to discharge the second charging capacitor 3252 to the ground.

[0104] Specifically, the second discharge circuit 326 may include a transistor M2, a resistor R16, a resistor R24, a diode D2, and a signal terminal Discharge2. One end of the capacitor C4 is grounded, and the other end of the capacitor C4 may be connected to the first electrode of the transistor M2 via the resistor R16. The signal terminal Discharge2 may be connected to the control electrode of the transistor M2 via the diode D4, and the second electrode of the transistor M2 may be grounded. The signal terminal Discharge2 may also be grounded via the diode D4 and the resistor R24.

[0105] The controller 400 may be connected to the signal terminal Discharge2. When the valley detection circuit 320 is working, for example, during the time period t2 to t4, the controller 400 may control the transistor M2 to be turned off to prevent the second discharge loop 326 from affecting the voltage of the capacitor C2.

[0106] When the valley detection circuit 320 stops working, for example, after the controller 400 obtains the voltage Vdmin, the controller 400 can control the transistor M2 to close, so that the voltage of the capacitor C4 is discharged to the ground, thereby resetting the voltage of the capacitor C4 and preventing the capacitor C4 from continuously maintaining a high voltage and affecting the circuit.

[0107] In this way, after the valley detection circuit 320 detects the peak voltage, the second discharge circuit 326 can reset the voltage of the second charging capacitor 3252 to prevent the second capacitor 152 from continuously maintaining a high voltage and affecting the circuit.

[0108] In some embodiments, a maximum voltage value Vdmax of the voltage Vd provided by the signal line Data can be set to 12.2 V, a minimum voltage value Vdmin of the voltage Vd provided by the signal line Data can be set to 0.3 V, a voltage Vdd1 provided by the voltage source AVDD1 can be set to 13.3 V, and a voltage Vdd2 provided by the voltage source AVDD2 can be set to 13.3 V. The controller 400 determines that the regulated voltage is 6.25 V based on Vdmax and Vdmin, and regulates the voltage Vcom to 6.25 V.

[0109] In some embodiments, the controller 400 is further configured to control the power supply circuit 500 to supply power to the detection circuit 300 when the display panel 1000 displays flickering, so that the detection circuit 300 detects the maximum voltage value and the minimum voltage value of the data voltage within a specific time period.

[0110] Specifically, if the display panel 1000 displays flickering, the controller 400 can control the power supply circuit 500 to supply power to the detection circuit 300, so that the detection circuit 300 starts working. The controller 400 can adjust the voltage Vcom based on the Vdmax and Vdmin obtained by detection. If the display panel 1000 operates normally, the controller 400 can control the power supply circuit 500 to stop supplying power to the detection circuit 300 to reduce the power consumption of the display panel 1000.

[0111] In this way, the controller 400 can control the power supply circuit 500 to supply power to the detection circuit 300 according to the condition of the display panel 1000 , so as to reduce the power consumption of the display panel 1000 .

[0112] In the description of this specification, the reference terms "one embodiment," "some embodiments," "illustrative embodiments," "example," "specific example," or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the exemplary expressions of the above terms do not necessarily refer to the same embodiment or example. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification, as well as features of different embodiments or examples, unless they are mutually inconsistent.

[0113] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connection, detachable connection, or integral connection; it can include direct connection, indirect connection through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0114] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0115] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a specific logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0116] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A voltage regulating circuit for a display panel, characterized in that: The display panel includes a common electrode, a pixel electrode, a gate line, a data line, a control transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, wherein the first capacitor is connected between the common electrode and the pixel electrode, the second capacitor is connected between the pixel electrode and the gate line, the third capacitor is connected between the pixel electrode and the data line, and the fourth capacitor is connected between the gate line and the data line. The control electrode of the control transistor is connected to the gate line, the first electrode of the control transistor is connected to the data line, the second electrode of the control transistor is connected to the pixel electrode, and the data line is configured to provide a data voltage. The voltage regulating circuit comprises: a detection circuit configured to detect a maximum voltage value and a minimum voltage value of the data voltage within a specific time period; a controller configured to determine a regulation voltage according to an average voltage value of the maximum voltage value and the minimum voltage value; a power supply circuit, configured to adjust the voltage of the common electrode to the adjustment voltage under the control of the controller; The specific time period includes a first time period and a second time period that are adjacent to each other, and the detection circuit includes: a peak detection circuit configured to detect a maximum voltage value of the data voltage in the first time period; a valley detection circuit configured to detect a minimum voltage value of the data voltage in the second time period; The first time period includes the moment when the control transistor is switched from closed to open, and the second time period includes the moment when the control transistor is switched from closed to open.

2. The voltage regulating circuit according to claim 1, wherein: The peak detection circuit comprises: a first comparator comprising a first input terminal, a second input terminal, and a first output terminal, wherein the first input terminal is configured to receive the data voltage, the second input terminal is configured to receive a first reference voltage, and the first output terminal is configured to output a first control signal when the data voltage is greater than the first reference voltage; A first charging circuit is configured to charge the second input terminal according to the first control signal so that the voltage value of the first reference voltage is consistent with the maximum value of the data voltage.

3. The voltage regulating circuit according to claim 2, wherein: The first charging circuit includes a first voltage source, a first transistor and a first charging capacitor, the first electrode of the first transistor is connected to the first voltage source, the control electrode of the first transistor is connected to the first output end, the second electrode of the first transistor is grounded through the first charging capacitor, and the second electrode of the first transistor is connected to the second input end.

4. The voltage regulating circuit according to claim 3, wherein: The first voltage source is configured to provide a first voltage having a voltage value greater than a maximum voltage value of the data voltage.

5. The voltage regulating circuit according to claim 3, wherein: The peak detection circuit includes a first discharge circuit, the first charging capacitor is grounded through the first discharge circuit, and the controller is configured to control the first discharge circuit to be connected so as to discharge the first charging capacitor to the ground.

6. The voltage regulating circuit according to claim 1, wherein: The valley detection circuit comprises: a second voltage source configured to provide a second voltage; a first processing circuit configured to provide a first processing voltage according to the second voltage and the data voltage, wherein the first processing voltage is a difference between the second voltage and the data voltage; a second comparator comprising a third input terminal, a fourth input terminal, and a second output terminal, wherein the third input terminal is configured to receive the first process voltage, the fourth input terminal is configured to receive a second reference voltage, and the second output terminal is configured to output a second control signal when the first process voltage is greater than the second reference voltage; a second processing circuit configured to provide a second processing voltage according to the second reference voltage and the second voltage, wherein the second processing voltage is a difference between the second voltage and the second reference voltage; A second charging circuit, wherein the second charging circuit is configured to charge the fourth input terminal according to the second control signal so that the voltage value of the second reference voltage is consistent with the maximum value of the first processing voltage, and further the voltage value of the second processing voltage is consistent with the minimum value of the data voltage.

7. The voltage regulating circuit according to claim 6, wherein: The second charging circuit includes a second transistor and a second charging capacitor, the first electrode of the second transistor is connected to the second voltage source, the control electrode of the second transistor is connected to the second output end, the second electrode of the second transistor is grounded through the second charging capacitor, and the second electrode of the second transistor is connected to the fourth input end.

8. The voltage regulating circuit according to claim 7, wherein: The valley detection circuit includes a second discharge circuit, the second charging capacitor is grounded via the second discharge circuit, and the controller is configured to control the second discharge circuit to be connected so as to discharge the second charging capacitor to the ground.

9. The voltage regulating circuit according to claim 1, wherein: The controller is further configured to control the power supply circuit to supply power to the detection circuit when the display panel displays flickering, so that the detection circuit detects a maximum voltage value and a minimum voltage value of the data voltage within a specific time period.

10. A display panel, characterized in that: The display panel includes the voltage regulating circuit of the display panel according to any one of claims 1 to 9.

11. A method for adjusting voltage of a display panel, characterized in that: The display panel includes a common electrode, a pixel electrode, a gate line, a data line, a control transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor, wherein the first capacitor is connected between the common electrode and the pixel electrode, the second capacitor is connected between the pixel electrode and the gate line, the third capacitor is connected between the pixel electrode and the data line, and the fourth capacitor is connected between the gate line and the data line. The control electrode of the control transistor is connected to the gate line, the first electrode of the control transistor is connected to the data line, and the second electrode of the control transistor is connected to the pixel electrode. The data line is configured to provide a data voltage. The method includes: Obtaining a maximum voltage value and a minimum voltage value of the data voltage within a specific time period; determining a regulation voltage according to an average voltage value of the maximum voltage value and the minimum voltage value; controlling the power supply circuit to adjust the voltage of the common electrode to the adjustment voltage; The specific time period includes a first time period and a second time period that are adjacent to each other, and the step of obtaining the maximum voltage value and the minimum voltage value of the data voltage within the specific time period includes: The peak detection circuit is used to detect the maximum voltage value of the data voltage in the first time period; The valley detection circuit is used to detect the minimum voltage value of the data voltage in the second time period; The first time period includes the moment when the control transistor is switched from closed to open, and the second time period includes the moment when the control transistor is switched from closed to open.

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