Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, and relate to the display field, and are used for optimizing the performance of a pixel circuit. The display panel comprises a pixel circuit and a light emitting unit; wherein the pixel circuit has a first node and a second node, the first node is electrically connected with a first power supply line, and the second node is electrically connected with the light emitting unit; the pixel circuit comprises a first transistor, and the first transistor is coupled between the first node and the second node; wherein the first transistor comprises X first sub-transistors, the gates of the X first sub-transistors are connected, the first poles are connected, and the second poles are connected, and X is an integer and X is greater than or equal to 2.

Description

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device.

[0002] Light emitting diode (LED) display panel is widely used in various display devices due to its high brightness, good light emitting efficiency and low power consumption.

[0003] Display devices in different applications have different requirements for display screen brightness, which requires that in some display panels, the pixel circuit can output larger driving current to the LED. However, how to increase the upper limit of the driving current that can be output by the pixel circuit while ensuring good performance of the pixel circuit is a technical problem to be solved at present.

[0004] Therefore, the embodiments of the present application provide a display panel and a display device to optimize the performance of the pixel circuit.

[0005] In one aspect, the embodiments of the present application provide a display panel, comprising a pixel circuit and a light emitting unit.

[0006] The pixel circuit has a first node and a second node, the first node is electrically connected with a first power supply line, and the second node is electrically connected with the light emitting unit.

[0007] The pixel circuit comprises a first transistor, which is coupled between the first node and the second node; wherein the first transistor comprises X first sub-transistors, the gates of the X first sub-transistors are connected, the first poles are connected, and the second poles are connected, X≥2 and X is an integer.

[0008] In another aspect, the embodiments of the present application provide a display device comprising the above display panel.

[0009] One of the above technical solutions has the following beneficial effects:

[0010] In the embodiments of the present application, for the first transistor coupled in the current transmission path, the channel width is not directly increased, but at least two first sub-transistors are arranged in parallel. In this structure of the first transistor, the equivalent width-length ratio of the first transistor is equal to the width-length ratio of a single first sub-transistor multiplied by the number of first sub-transistors included in the first transistor, so that the equivalent width-length ratio of the first transistor is greatly increased, the current output capability of the first transistor is improved, and at the same time, the channel width of a single transistor structure in the pixel circuit is not too large, so that the transistor structure has a relatively optimal opening speed, and the performance of the pixel circuit is relatively optimal.​​​

[0011] Further can be understood that, the first transistor current output capability increases, the upper limit of the drive current that the pixel circuit can output will also be improved, the pixel circuit can output greater drive current to the light emitting unit, so that the display screen can have higher brightness, and further better meet the display requirements.

DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0013] Figure 1 A structural schematic diagram of the display panel provided by the embodiment of the present application;

[0014] Figure 2 A circuit structural schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0015] Figure 3 A film layer structural schematic diagram of at least part of the first sub-transistor in the first transistor provided by the embodiment of the present application;

[0016] Figure 4 Another film layer structural schematic diagram of at least part of the first sub-transistor in the first transistor provided by the embodiment of the present application;

[0017] Figure 5 A top view of the display panel provided by the embodiment of the present application;

[0018] Figure 6 A structural schematic diagram of the first display unit provided by the embodiment of the present application; Figure 5 A structural schematic diagram corresponding to the region A in the middle;

[0019] Figure 7 Another structural schematic diagram corresponding to the region A in the middle; Figure 5

[0020] Figure 8 A structural schematic diagram of the first display unit provided by the embodiment of the present application;

[0021] Figure 9 A size schematic diagram of the pixel circuit provided by the embodiment of the present application;

[0022] Figure 10 Another structural schematic diagram of the first display unit provided by the embodiment of the present application;

[0023] Figure 11 ​A connection diagram of a pixel circuit and a light emitting unit in a first display unit provided by an embodiment of the present application;

[0024] Figure 12 Another structure diagram of the first display unit provided by an embodiment of the present application;

[0025] Figure 13 A structure diagram corresponding to a middle region B; Figure 12

[0026] Figure 14 A structure diagram corresponding to a middle region C; Figure 12

[0027] Another structure diagram of the first display unit provided by an embodiment of the present application; Figure 15

[0028] Another film layer structure diagram of the display panel provided by an embodiment of the present application; Figure 16

[0029] Another film layer structure diagram of the display panel provided by an embodiment of the present application; Figure 17

[0030] A cross-sectional structure diagram of the display panel provided by an embodiment of the present application; Figure 18

[0031] A cross-sectional structure diagram corresponding to a middle region B; Figure 19 Figure 17 Another structure diagram of the second power supply line and the second output electrode provided by an embodiment of the present application;

[0032] Figure 20 Another structure diagram of the second power supply line and the second output electrode provided by an embodiment of the present application;

[0033] Figure 21 Another film layer structure diagram of the display panel provided by an embodiment of the present application;

[0034] Figure 22 A cross-sectional structure diagram corresponding to a middle region B;

[0035] Figure 23 Figure 22 A cross-sectional structure diagram corresponding to a middle region B;

[0036] Figure 24 Another film layer structure diagram of the display panel provided by an embodiment of the present application;

[0037] Figure 25 Another structure diagram of the first display unit provided by an embodiment of the present application; ​​​

[0038] Figure 26 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0039] Figure 27 This is another structural schematic diagram of the first display unit provided in an embodiment of the present invention;

[0040] Figure 28 This is a schematic diagram of a film structure for a pixel circuit provided in an embodiment of the present invention;

[0041] Figure 29 This is a schematic diagram of a driving transistor provided in an embodiment of the present invention;

[0042] Figure 30 This is a schematic diagram of a first light-emitting control transistor provided in an embodiment of the present invention;

[0043] Figure 31 This is a schematic diagram of a second light-emitting control transistor provided in an embodiment of the present invention;

[0044] Figure 32 for Figure 29 A schematic diagram of a structure of the first sub-transistor arranged along the first direction;

[0045] Figure 33 for Figure 29 A schematic diagram of a structure of the first sub-transistor arranged along the second direction;

[0046] Figure 34 for Figure 30 and Figure 31 A schematic diagram of a structure of the first sub-transistor arranged along the first direction;

[0047] Figure 35 for Figure 30 and Figure 31 A schematic diagram of a structure of the first sub-transistor arranged along the first direction;

[0048] Figure 36 This is a schematic diagram of the distribution of temperature sensors provided in an embodiment of the present invention;

[0049] Figure 37 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention;

[0050] Figure 38 for Figure 37 A sectional view along the C1-C2 direction;

[0051] Figure 39 for Figure 5 Another structural diagram corresponding to region A in the middle;

[0052] Figure 40 This is a schematic diagram of a second display unit provided in an embodiment of the present invention;

[0053] Figure 41 This is a schematic diagram of another structure of the first transistor provided in an embodiment of the present invention;

[0054] Figure 42 This is a schematic diagram of the dimensions of the first sub-transistor provided in an embodiment of the present invention;

[0055] Figure 43 This is a simplified structural diagram of a pixel circuit provided in an embodiment of the present invention;

[0056] Figure 44 This is a schematic diagram of another circuit structure of the pixel circuit provided in an embodiment of the present invention;

[0057] Figure 45 for Figure 43 A schematic diagram of a structure corresponding to region D in the middle;

[0058] Figure 46 for Figure 43 A schematic diagram of a structure corresponding to region E in the middle;

[0059] Figure 47 for Figure 43 A schematic diagram of a structure corresponding to region F in the middle;

[0060] Figure 48 This is another structural schematic diagram of the first light-emitting control signal line provided in an embodiment of the present invention;

[0061] Figure 49 This is another structural schematic diagram of the second light-emitting control signal line provided in an embodiment of the present invention;

[0062] Figure 50 for Figure 43 A schematic diagram of a structure corresponding to region G in the middle;

[0063] Figure 51 for Figure 43 A schematic diagram of a structure corresponding to region H in the middle;

[0064] Figure 52 for Figure 50 A corresponding enlarged schematic diagram;

[0065] Figure 53 for Figure 50 Another corresponding enlarged view;

[0066] Figure 54 This is a schematic diagram of a display device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.

[0068] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0069] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0070] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0071] The embodiments of the present application provide a display panel, such as Figure 1 as shown, Figure 1 is a structural schematic diagram of the display panel provided by the embodiments of the present application, which includes a pixel circuit 1 and a light emitting unit 2.

[0072] As shown in Figure 2 as shown, Figure 2 is a circuit structure schematic diagram of the pixel circuit 1 provided by the embodiments of the present application, the pixel circuit 1 has a first node O1 and a second node O2, the first node O1 is electrically connected with a first power supply line PVDD, and the second node O2 is electrically connected with the light emitting unit 2.

[0073] The pixel circuit 1 includes a first transistor 3, which is coupled between the first node O1 and the second node O2. Among them, the first transistor 3 includes X first sub-transistors 4, the gates of the X first sub-transistors 4 are connected together, the first poles of the X first sub-transistors 4 are connected together, and the second poles of the X first sub-transistors 4 are connected together, X≥2 and X is an integer.

[0074] Among them, "the gates of the X first sub-transistors 4 are connected together, the first poles of the X first sub-transistors 4 are connected together, and the second poles of the X first sub-transistors 4 are connected together" specifically means that the gates of the X first sub-transistors 4 are connected together, the first poles of the X first sub-transistors 4 are connected together, and the second poles of the X first sub-transistors 4 are connected together.

[0075] Or, also can be expressed as: X first sub-transistor 4 includes the first 1st sub-transistor 4-1~X first sub-transistor 4, for any two of the first x1st sub-transistor 4-x1 and the first x2nd sub-transistor 4-x2, the gate of the first x1st sub-transistor 4-x1 and the gate of the first x2nd sub-transistor 4-x2 are connected, the first pole of the first x1st sub-transistor 4-x1 and the first pole of the first x2nd sub-transistor 4-x2 are connected, the second pole of the first x1st sub-transistor 4-x1 and the second pole of the first x2nd sub-transistor 4-x2 are connected. Wherein, x1 and x2 are respectively in 1~X, and x1≠x2.

[0076] And based on the connection relationship of the X first sub-transistor 4, the X first sub-transistor 4 is in parallel, that is, the first transistor 3 includes X first sub-transistors 4 in parallel.

[0077] Wherein, the first sub-transistor 4 in the embodiment of the application can be understood as a smallest transistor structure, which can be divided according to the channel:

[0078] As shown in Figure 3 and Figure 4 , Figure 3 A film layer structure diagram of at least part of the first sub-transistor 4 in the first transistor 3 provided by the embodiment of the application, Figure 4 Another film layer structure diagram of at least part of the first sub-transistor 4 in the first transistor 3 provided by the embodiment of the application, the first sub-transistor 4 includes a gate g and an active layer al, and the active layer al includes a channel c, a first doped region dr1 and a second doped region dr2.

[0079] Wherein, the channel c is the part of the active layer al overlapping with the gate g, that is, in the direction perpendicular to the plane where the display panel is located, the channel c coincides with the gate g, wherein the channel length is marked as L, and the channel width is marked as W. The first doped region dr1 can be understood as the first pole of the first sub-transistor 4, and the first doped region dr1 is usually electrically connected to other structures through the first source-drain metal electrode 5. The second doped region dr2 can be understood as the second pole of the first sub-transistor 4, and the second doped region dr2 is usually electrically connected to other structures through the second source-drain metal electrode 6.

[0080] Referring to Figure 3 and Figure 4 , the first sub-transistor 4 can be divided according to the spacing of the channel c, that is, the channel c in a single first sub-transistor 4 is a whole block connected together, and the channels c in adjacent first sub-transistors 4 are spaced apart. Exemplarily, in Figure 3In the embodiment, the active layers al of the two adjacent first sub-transistors 4 are spaced from each other, and thus the channels c of the two first sub-transistors 4 are also spaced. Figure 4 In the embodiment, the active layers al of the two adjacent first sub-transistors 4 are connected, but the channels c of the two first sub-transistors 4 are spaced by the first doped region dr1 or the second doped region dr2, and thus the channels c of the two first sub-transistors 4 are also spaced.

[0081] It can be understood that the pixel circuit 1 is used to transmit a driving current to the light emitting unit 2 connected thereto to drive the light emitting unit 2 to emit light, and the greater the driving current transmitted by the pixel circuit 1, the higher the luminance of the light emitting unit 2, and correspondingly, the greater the luminance that the display screen can achieve. In the pixel circuit 1, the path between the first node O1 and the second node O2 is the transmission path of the driving current, and the current output capability of the transistors in series on the current transmission path will greatly affect the upper limit of the driving current that can be output by the pixel circuit 1.

[0082] According to the characteristics of the transistor, the greater the width-length ratio of the transistor, the greater the current output capability of the transistor, that is, the higher the upper limit of the current that can be output by the transistor. However, the inventors have further found that if the transistor on the current transmission path is directly set as a transistor structure with a very large channel width, the transfer characteristic curve of the transistor will be abnormal, affecting the opening speed of the transistor, and further affecting the performance of the pixel circuit 1.

[0083] In this regard, in the embodiment, for the first transistor 3 coupled on the current transmission path, the channel width of the first transistor 3 is not directly increased, but at least two first sub-transistors 4 are included and arranged in parallel. In the structure of the first transistor 3, the equivalent width-length ratio of the first transistor 3 is equal to the width-length ratio of a single first sub-transistor 4 multiplied by the number of the first sub-transistors 4 included in the first transistor 3, so as to greatly increase the equivalent width-length ratio of the first transistor 3 and improve the current output capability of the first transistor 3, while avoiding that the channel width of a single transistor structure in the pixel circuit is too large, so that the transistor structure has a relatively optimal opening speed, and further so that the performance of the pixel circuit 1 is relatively optimal.

[0084] It can be further understood that after the current output capability of the first transistor 3 is increased, the upper limit of the driving current that can be output by the pixel circuit 1 will also be improved, the pixel circuit 1 can output a greater driving current to the light emitting unit 2, so that the display screen can have a higher luminance, and further better meet the display requirements.

[0085] It should be noted that, referring to Figure 1The display panel involved in this embodiment of the invention can be applied to conventional display devices such as mobile phones and computers. These types of display devices do not have excessively high brightness requirements, therefore, the upper limit of the driving current that the pixel circuit 1 can output is not excessively high. In this type of display panel, the number of first sub-transistors 4 in the first transistor 3 can be slightly less; for example, the first transistor 3 may include only a few first sub-transistors 4.

[0086] Or, such as Figure 5 and Figure 6 As shown, Figure 5 This is a top view of a display panel provided in an embodiment of the present invention. Figure 6 for Figure 5 The diagram shows a structural schematic corresponding to region A. The display panel involved in this embodiment can also be applied to special display devices such as printer LED strips. This type of display panel is typically elongated horizontally and has a high horizontal resolution. These display devices have high brightness requirements; the operating current of a single LED may need to reach several hundred microamps. Therefore, this type of display panel places a high demand on the upper limit of the driving current output by the pixel circuit 1, requiring the pixel circuit 1 to be able to output a large driving current. In this type of display panel, the first transistor 3 includes a larger number of first sub-transistors 4; for example, the first transistor 3 may include dozens of first sub-transistors 4.

[0087] The display panel provided in this embodiment of the invention is more suitable for display devices with high brightness requirements. These display devices have very high brightness requirements, which correspondingly necessitates a high upper limit for the driving current output by the pixel circuit 1. By applying the technical solution provided in this embodiment of the invention, the upper limit of the driving current output by the pixel circuit 1 can be significantly increased by increasing the number of first sub-transistors 4 in the first transistor 3. Moreover, because the channel width of a single first sub-transistor 4 is small, the pixel circuit 1 can maintain superior performance.

[0088] In one feasible implementation, see again Figure 2 The pixel circuit 1 includes a driving transistor M0, a first light-emitting control transistor M1, and a second light-emitting control transistor M2. The first light-emitting control transistor M1 is coupled between the first node O1 and the driving transistor M0, and the second light-emitting control transistor M2 is coupled between the driving transistor M0 and the second node O2.

[0089] At least one of the first light emitting control transistor M1, the driving transistor M0 and the second light emitting control transistor M2 is the first transistor 3, so as to improve the current output capability of the first light emitting control transistor M1, the driving transistor M0 and / or the second light emitting control transistor M2, and enable a larger driving current to flow in the current transmission path.

[0090] It should be noted that, Figure 2 The first light emitting control transistor M1, the driving transistor M0 and the second light emitting control transistor M2 are all first transistors 3, which are only schematically shown by taking the pixel circuit 1 including three first transistors 3 as an example. Of course, in other alternative embodiments of the present application, any one or any two of the first light emitting control transistor M1, the driving transistor M0 and the second light emitting control transistor M2 can be the first transistor 3, and at this time, the pixel circuit 1 only includes one or two first transistors 3.

[0091] In a feasible embodiment, as shown in Figure 7 and Figure 8 , the first light emitting control transistor M1, the driving transistor M0 and the second light emitting control transistor M2 are all first transistors 3. Figure 7 Figure 5 The other structure diagram corresponding to the region A in Figure 8 is a structure diagram of the first display unit 7 provided by the embodiment of the present application. The display panel includes the first display unit 7, and the first display unit 7 includes a first light emitting unit group 8 and a first pixel circuit group 9.

[0092] The first light emitting unit group 8 includes M light emitting units 2 arranged along a first direction x, and the first pixel circuit group 9 includes N pixel circuits 1 arranged along a second direction y. The pixel circuit 1 in the first pixel circuit group 9 is electrically connected with at least one light emitting unit 2 in the first light emitting unit group 8. Wherein, M≥2, N≥2, and M and N are both integers. The drawings of the embodiment of the present application are schematically shown by taking M=8 and N=8 as an example. The first direction x and the second direction y intersect, and specifically, the first direction x is perpendicular to the second direction y.

[0093] Hereinafter, the first direction x is simply referred to as the horizontal direction, and the second direction y is simply referred to as the vertical direction.

[0094] It can be known from Figure 2 that the pixel circuit 1 needs to be electrically connected with the data line Data. Generally, a plurality of pixel circuits 1 arranged in the vertical direction are electrically connected with one data line Data. For the N pixel circuits 1 connected with the M light emitting units 2 arranged in the horizontal direction, when the N pixel circuits 1 adopt the arrangement mode shown in Figure 6 , the N pixel circuits 1 are arranged in the horizontal direction, and the N pixel circuits 1 need to be respectively electrically connected with N data lines Data. When the N pixel circuits 1 adopt the arrangement mode shown in Figure 8 ​In the shown arrangement, the N pixel circuits 1 are arranged in a longitudinal direction, and the N pixel circuits 1 only need to be electrically connected to one data line Data. For the entire display panel, the originally required N*m data lines are reduced to m data lines, greatly saving the number of data lines Data.

[0095] This arrangement is particularly suitable for the aforementioned printer lamp strip and other long strip-shaped display panels. Such display panels have a high horizontal resolution and small pixel pitch. After the above scheme is applied, the number of data lines Data can be greatly reduced. Correspondingly, the number of pins in the lower frame for providing signals to the data channel can also be greatly reduced, thereby helping to further optimize the narrow-frame design of the display panel.

[0096] It should be noted that this method only adjusts the arrangement of the pixel circuits 1 and does not change the horizontal distribution density of the light-emitting units 2, and thus does not affect the horizontal resolution of the display panel.

[0097] In addition, it should be noted that when the first transistor 3 includes X first sub-transistors 4 arranged in parallel, the longitudinal space occupied by the pixel circuit 1 can be relatively large. When the N pixel circuits 1 in the first display unit 7 are arranged in the above-described longitudinal arrangement, the embodiment of the present application can further adjust the arrangement of the X first sub-transistors 4 in the first transistor 3 to reduce the longitudinal length of a single pixel circuit 1, and thus reduce the total length of the N pixel circuits 1 in the second direction y. This part will be described in detail later.

[0098] Further, referring again to Figure 8 , M=N. At this time, one pixel circuit 1 is electrically connected to one light-emitting unit 2, and the pixel circuit 1 only needs to provide the driving current required by the light-emitting unit 2, and the brightness displayed by each light-emitting unit 2 is more accurate.

[0099] In a feasible implementation manner, referring again to Figure 8 , in the first display unit 7, the N pixel circuits 1 in the first pixel circuit group 9 are located on at least one side of the first light-emitting unit group 8 in the second direction y. At this time, the pixel circuit 1 longitudinally overlaps the first light-emitting unit group 8, and the pixel circuit 1 does not occupy space between two horizontally adjacent first light-emitting unit groups 8, and the horizontal distribution of the light-emitting units 2 is more uniform, and the display effect is better.

[0100] Further, as shown in Figure 9 , the first display unit 7 includes a first pixel circuit group 9 and a first light-emitting unit group 8. Figure 9This is a schematic diagram of the dimensions of a pixel circuit 1 provided in an embodiment of the present invention. The length of the pixel circuit 1 in the first direction x is D, (M-1)×(d1+d2)≤D≤M×(d1+d2), where d1 is the length of the light-emitting unit 2 in the first direction x, and d2 is the spacing between adjacent light-emitting units 2 in the first direction x.

[0101] Setting the length D of pixel circuit 1 in the first direction x to be greater than or equal to (M-1)×(d1+d2) allows for maximizing the horizontal widening and vertical narrowing of pixel circuit 1. This avoids the impact of excessive vertical space occupied by N pixel circuits 1 on the vertical length of the display panel when arranged vertically, and also reduces the connection distance between the light-emitting unit 2 and the pixel circuit 1. Furthermore, setting the length D of pixel circuit 1 in the first direction x to be less than or equal to M×(d1+d2) prevents the pixel circuit 1 from being too wide horizontally, thus avoiding the inability to properly arrange two horizontally adjacent first pixel circuit groups 9.

[0102] It should be noted that when the length D of the pixel circuit 1 in the first direction x is defined, the boundaries of the pixel circuit 1 on both sides in the first direction x can be defined by the boundaries of the active layer a1 of the outermost transistor structure on both sides of the pixel circuit 1.

[0103] For example, see Figure 28 In the first direction x, the pixel circuit 1 has two opposite sides, one of which has the outermost transistor structure of the first sub-transistor 4 in the driving transistor M0, and the other side has the outermost transistor structure of the data writing transistor M4. Therefore, the boundaries of the pixel circuit 1 on both sides in the first direction x can be defined by the edges of the active layers of the outermost first sub-transistor 4 in the driving transistor M0 and the active layers of the data writing transistor M4, respectively. Figure 28 The diagram illustrates the length D of pixel circuit 1 in the first direction x.

[0104] In one feasible implementation, such as Figure 10 As shown, Figure 10 This is another schematic diagram of the structure of the first display unit 7 provided in an embodiment of the present invention. The first pixel circuit group 9 includes a first sub-circuit group 10 and a second sub-circuit group 11. The first sub-circuit group 10 includes N1 pixel circuits 1, and the second sub-circuit group 11 includes N2 pixel circuits 1, where N1 + N2 = N, N1 ≥ 1, N2 ≥ 1, and N1 and N2 are both integers. The first light-emitting unit group 8 is located between the first sub-circuit group 10 and the second sub-circuit group 11.

[0105] Compared with the case that the N pixel circuits 1 are located on one side of the first light emitting unit group 8, the pixel circuits 1 are dispersed on the opposite sides of the first light emitting unit group 8, so that the connection distance between the outermost pixel circuit 1 (the pixel circuit 1 farthest from the first light emitting unit group 8) and the light emitting unit 2 is shortened, and the signal attenuation is reduced.

[0106] Further, as shown in Figure 11 , Figure 11 Fig. 1 is a schematic diagram of a connection between a pixel circuit 1 and a light emitting unit 2 in a first display unit 7 according to an embodiment of the present application, M = N, N1≥ 2, and N2≥ 2.

[0107] The first light emitting unit group 8 includes a first sub-unit group 12 and a second sub-unit group 13 arranged along a first direction x, the first sub-unit group 12 includes N1 light emitting units 2, and the second sub-unit group 13 includes N2 light emitting units 2.

[0108] The N1 pixel circuits 1 arranged in the first sub-circuit group 10 along a direction (indicated by an arrow y1) from the first sub-circuit group 10 to the second sub-circuit group 11 are sequentially electrically connected to the N1 light emitting units 2 arranged in the first sub-unit group 12 along a direction (indicated by an arrow x1) from the first sub-unit group 12 to the second sub-unit group 13. Figure 11 Figure 11 The N2 pixel circuits 1 arranged in the second sub-circuit group 11 along a direction from the first sub-circuit group 10 to the second sub-circuit group 11 are sequentially electrically connected to the N2 light emitting units 2 arranged in the second sub-unit group 13 along a direction from the first sub-unit group 12 to the second sub-unit group 13.

[0109] Based on the above connection mode, the wiring of the connection lines 14 between the pixel circuits 1 and the light emitting units 2 is regular and more convenient. Moreover, the pixel circuits 1 closer to the first light emitting unit group 8 are connected to the light emitting units 2 closer to the center of the first light emitting unit group 8, and the pixel circuits 1 farther from the first light emitting unit group 8 are connected to the light emitting units 2 farther from the center of the first light emitting unit group 8, so that the difference in the connection distance between different pixel circuits 1 and light emitting units 2 is reduced, and the difference in signal attenuation is reduced.

[0110] In a possible implementation, referring again to Figure 11 , N1 = N2, that is, the number of pixel circuits 1 on the opposite sides of the first light emitting unit group 8 is the same, and the outermost pixel circuits 1 on the opposite sides are not too far from the first light emitting unit group 8, so that the connection distance between the outermost pixel circuits 1 and the light emitting units 2 is reduced.

[0111] In a possible implementation, referring to Figure 2 ​The pixel circuit 1 comprises a first light-emitting control transistor M1, a driving transistor M0 and a second light-emitting control transistor M2, wherein the first light-emitting control transistor M1 is coupled between the first node O1 and the driving transistor M0, and the second light-emitting control transistor M2 is coupled between the driving transistor M0 and the second node O2. At least one of the first light-emitting control transistor M1, the driving transistor M0 and the second light-emitting control transistor M2 is the first transistor 3.

[0112] As shown in FIG. 1, Figures 12-14 , Figure 12 is another structural schematic diagram of the first display unit provided by the embodiment of the present application, Figure 13 is Figure 12 a structural schematic diagram corresponding to the region B in FIG. 1, Figure 14 is Figure 12 a structural schematic diagram corresponding to the region C in FIG. 1. In the pixel circuit 1 of the first sub-circuit group 10 and / or the second sub-circuit group 11, the distance between the second light-emitting control transistor M2 and the first light-emitting unit group 8 is less than the distance between the first light-emitting control transistor M1 and the first light-emitting unit group 8.

[0113] Since the second light-emitting control transistor M2 needs to be electrically connected with the light-emitting unit 2, in the pixel circuit 1 of the first sub-circuit group 10 and / or the second sub-circuit group 11, by making the second light-emitting control transistor M2 closer to the first light-emitting unit group 8, the connection distance between the second light-emitting control transistor M2 and the light-emitting unit 2 can be reduced. Further, the second light-emitting control transistor M2 can be the transistor closest to the first light-emitting unit group 8 in the pixel circuit 1.

[0114] Further, referring again to Figure 12 , the pixel circuit 1 of the first sub-circuit group 10 and the pixel circuit 1 of the second sub-circuit group 11 are in a mirror relationship along the first direction x.

[0115] That is, the pixel circuit 1 of the first sub-circuit group 10 and the pixel circuit 1 of the second sub-circuit group 11 are symmetrical along the first direction x. At this time, the pattern of the pixel circuit 1 on one side of the first light-emitting unit group 8 can be obtained by turning the pattern of the pixel circuit 1 on the other side of the first light-emitting unit group 8 by 180° along the first direction x as the axis, without the need for additional adjustment of the arrangement of the transistors inside the pixel circuit 1 on the other side.

[0116] In a possible implementation, as shown in FIG. 1, Figures 15-19 , Figure 15 is still another structural schematic diagram of the first display unit 7 provided by the embodiment of the present application, Figure 16 is another film layer structure schematic diagram of the display panel provided by the embodiment of the present application, Figure 17 is still another film layer structure schematic diagram of the display panel provided by the embodiment of the present application, Figure 18 FIG. 1 is a schematic diagram of a cross-sectional structure of a display panel provided by an embodiment of the present application, Figure 19 Figure 17 FIG. 2 is a cross-sectional view along the direction of A1-A2. The light emitting unit 2 includes a light emitting element 15, which is an LED, and can be a micro LED, a mini LED, or the like. In the embodiment of the present application, one light emitting unit 2 can include one light emitting element 15, or one light emitting unit 2 can include two or more light emitting elements 15. In this case, at least one light emitting element 15 in the light emitting unit 2 can be a regular light emitting element, and the remaining light emitting elements 15 can be backup light emitting elements.

[0117] The display panel further includes a driving backplane 16. The driving backplane 16 includes a substrate 17, a circuit layer 18 located on one side of the substrate 17, and a first metal layer 19 located on a side of the circuit layer 18 away from the substrate 17.

[0118] The circuit layer 18 includes a pixel circuit 1. The first metal layer 19 includes a first output electrode 20 electrically connected to a first electrode of the light emitting element 15, a second output electrode 21 electrically connected to a second electrode of the light emitting element 15, and a second power supply line PVEE electrically connected to the second output electrode 21. In a direction perpendicular to the plane in which the substrate 17 is located, the first output electrode 20 overlaps the first electrode of the light emitting element 15, and the first output electrode 20 can be soldered to the first electrode of the light emitting element 15 by soldering, in which case the first output electrode 20 can be regarded as an anode pad. In a direction perpendicular to the plane in which the substrate 17 is located, the second output electrode 21 overlaps the second electrode of the light emitting element 15, and the second output electrode 21 can be soldered to the second electrode of the light emitting element 15 by soldering, in which case the second output electrode 21 can be regarded as a cathode pad.

[0119] Furthermore, for the first output electrode 20 and the second output electrode 21 connected to the same light emitting element 15, the first output electrode 20 is located on a side of the second output electrode 21 close to the second sub-circuit group 11, and the second power supply line PVEE overlaps the first sub-circuit group 10 in a direction perpendicular to the plane in which the substrate 17 is located.

[0120] The first output electrode 20 includes a first sub-electrode 22 and a second sub-electrode 23. The first sub-electrode 22 is electrically connected to the pixel circuit 1 in the first sub-circuit group 10 through a first connecting line 24, and the second sub-electrode 23 is electrically connected to the pixel circuit 1 in the second sub-circuit group 11 through a second connecting line 25. The second connecting line 25 is located on the first metal layer 19, and the first connecting line 24 is located on a side of the first metal layer 19 close to the substrate 17.

[0121] ​In the above configuration, both the first connecting line 24 and the second power line PVEE are located on the side of the first output electrode 20 away from the second sub-circuit group 11. Since the first connecting line 24 will inevitably overlap with the second power line PVEE, the first connecting line 24 can be positioned with the second power line PVEE to avoid short-circuiting between them. Because the second connecting line 25 and the second power line PVEE are located on different sides of the first output electrode 20, and the positions of the first connecting line 24 and the second power line PVEE are staggered, the second connecting line 25 can be positioned on the same layer as the second power line PVEE, so that the second connecting line 25 does not occupy additional film layers.

[0122] Regarding the second power line PVEE and the second output electrode 21, in one configuration, such as Figure 20 As shown, Figure 20 This is a schematic diagram of a structure of the second power line PVEE and the second output electrode 21 provided in an embodiment of the present invention. The second power line PVEE can be located on the side of the second output electrode 21 away from the first output electrode 20, and the second output electrode 21 is connected to the second power line PVEE. Alternatively, in another configuration, such as... Figure 21 As shown, Figure 21 This is another structural schematic diagram of the second power line PVEE and the second output electrode 21 provided in the embodiment of the present invention. Alternatively, a portion of the second power line PVEE can be reused as the second output electrode 21.

[0123] Furthermore, such as Figure 22 and Figure 23 As shown, Figure 22 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. Figure 23 for Figure 22 A cross-sectional view along the B1-B2 direction shows that the drive backplane 16 also includes a second metal layer 26 located between the circuit layer 18 and the first metal layer 19, a first connecting line 24 located in the second metal layer 26, and the second metal layer 26 also includes a first connecting electrode 27 and a second connecting electrode 28.

[0124] In the second sub-circuit group 11, the pixel circuit 1 is electrically connected to the second connecting line 25 through the second connecting electrode 28. In the first sub-circuit group 10, the pixel circuit 1 is electrically connected to the first metal part 29 through the first connecting electrode 27. The first metal part 29 is located in the first metal layer 19. The second power line PVEE includes a cutout 30. At least part of the first metal part 29 is located in the cutout 30 and is electrically insulated from the second power line PVEE.

[0125] In the above structure, the second connection electrode 28 serves as an auxiliary connection electrode between the pixel circuit 1 and the second connection line 25, avoiding the need to set a deep connection via when connecting the second connection line 25 to the pixel circuit 1. When the second connection electrode 28 is provided on the side where the second sub-circuit is located and is connected to the second connection line 25 through a connection via, a first metal part 29 can be further provided on the side of the first sub-circuit at a position corresponding to the second connection line 25, and the first metal part 29 is connected to the first connection line 24 through a connection via. At this time, the connection via between the first metal part 29 and the first connection line 24 corresponds to the connection via between the second connection electrode 28 and the second connection line 25, so that the distribution of the connection vias on both sides of the first light-emitting unit group 8 is consistent, and the connection vias on the side of the first sub-circuit do not need to be removed additionally, simplifying the layout design.

[0126] The first metal part 29 can be electrically connected to the first connection electrode 27 only and does not receive other signals.

[0127] In a feasible implementation, referring again to Figure 22 and Figure 23 The driving back plate 16 further includes a second metal layer 26 between the circuit layer 18 and the first metal layer 19, and the first connection line 24 is located in the second metal layer 26.

[0128] The thickness of the first metal layer 19 is different from the thickness of the second metal layer 26 in the direction perpendicular to the plane where the substrate 17 is located; and / or the width of the second connection line 25 is different from the width of the first connection line 24.

[0129] The width of the second connection line 25 refers to the line width of the second connection line 25 in the direction perpendicular to the extension direction of the second connection line 25, and the width of the first connection line 24 refers to the line width of the first connection line 24 in the direction perpendicular to the extension direction of the first connection line 24. Taking the first connection line 24 as an example, the line width of the part of the first connection line 24 extending in the first direction x is the width of the first connection line 24 in the second direction y, and the line width of the part of the first connection line 24 extending in the second direction y is the width of the first connection line 24 in the first direction x.

[0130] For the first connection line 24 and the second connection line 25, the thickness and / or line width of the two can be designed differently to balance the load by using the thickness and / or line width, thereby reducing the load difference between the first connection line 24 and the second connection line 25.

[0131] For example, referring to Figure 22 and Figure 23In one arrangement, the first metal layer 19 has a thickness in a direction perpendicular to the plane of the substrate 17 that is less than the thickness of the second metal layer 26 in a direction perpendicular to the plane of the substrate 17, and the second connecting line 25 has a width that is greater than the width of the first connecting line 24. In this way, the second connecting line 25 can use its greater line width to balance the effect of its smaller film thickness on loading, reducing the loading difference between the second connecting line 25 and the first connecting line 24.

[0132] Of course, in other alternative embodiments of the application, the second metal layer 26 can have a thickness in a direction perpendicular to the plane of the substrate 17 that is less than the thickness of the first metal layer 19 in a direction perpendicular to the plane of the substrate 17, and the first connecting line 24 can have a width that is greater than the width of the second connecting line 25, so that the first connecting line 24 uses its greater line width to balance the effect of its smaller film thickness on loading.

[0133] Furthermore, it should be noted that in embodiments of the application, the first metal layer 19 and the second metal layer 26 can be made of the same material or different materials. For example, at least one of the first metal layer 19 and the second metal layer 26 can be made of a titanium-aluminum-titanium (Ti-Al-Ti) stacked metal design, and / or at least one of the first metal layer 19 and the second metal layer 26 can be made of a molybdenum-aluminum-molybdenum (Mo-Al-Mo) stacked metal design. For example, in one arrangement, the first metal layer 19 and the second metal layer 26 are both made of a Ti-Al-Ti structure, or in another arrangement, the first metal layer 19 is made of a Ti-Al-Ti structure and the second metal layer 26 is made of a Mo-Al-Mo structure.

[0134] In one possible implementation, as shown in Figure 24 Figure 24 FIG. 6 is a schematic diagram of another film layer structure of a display panel according to an embodiment of the application, in which the first connecting line 24 does not overlap the first output electrode 20 and the second output electrode 21 in a direction perpendicular to the plane of the substrate 17.

[0135] The bonding of the light emitting element 15 can cause the underlying film layers to be penetrated under pressure. By making the first connecting line 24 not overlap the first output electrode 20 and the second output electrode 21, short-circuiting between the first connecting line 24 and the first output electrode 20 and the second output electrode 21 can be avoided when the film layers are penetrated.

[0136] Further, referring again to Figure 24 , the first connecting line 24 is electrically connected to the first sub-electrode 22 on the side of the first sub-electrode 22 that is closer to the second sub-circuit group 11.

[0137] ​On the one hand, the connection via between the first connecting line 24 and the first sub-electrode 22 will not occupy space between adjacent light-emitting elements 15, and thus will not affect the arrangement density of the light-emitting elements 15 in the first direction x. On the other hand, the connection via between the first connecting line 24 and the first sub-electrode 22 will not occupy space between the first sub-electrode 22 and its corresponding second output electrode 21, which can ensure that there is a sufficient distance between the first sub-electrode 22 and the second output electrode 21 to avoid short circuit between them.

[0138] More specifically, after the first connecting line 24 is led out from the pixel circuit 1, it can extend to the side of the first sub-electrode 22 near the second sub-circuit group 11 on the side of its corresponding light-emitting unit 2 in the first direction x, and be electrically connected to the first sub-electrode 22.

[0139] In one feasible implementation, such as Figure 25 and Figure 26 As shown, Figure 25 This is another schematic diagram of the structure of the first display unit 7 provided in an embodiment of the present invention. Figure 26 This is a schematic diagram of another film layer structure of the display panel provided in an embodiment of the present invention. The first light-emitting unit group 8 includes a first sub-unit group 12 and a second sub-unit group 13 arranged along the first direction x. The first sub-unit group 12 includes M1 light-emitting units 2, and the second sub-unit group 13 includes M2 light-emitting units 2. M1≥1, M2≥1, and M1 and M2 are both integers.

[0140] The pixel circuit 1 in the first sub-circuit group 10 is electrically connected to the light-emitting unit 2 in the first sub-unit group 12 via the first connecting line 24, and the pixel circuit 1 in the second sub-circuit group 11 is electrically connected to the light-emitting unit 2 in the second sub-unit group 13 via the second connecting line 25.

[0141] In this configuration, the pixel circuit 1 in the first sub-circuit group 10 is electrically connected to the first connecting line 24 via the first lead electrode 31, and the pixel circuit 1 in the second sub-circuit group 11 is electrically connected to the second connecting line 25 via the second lead electrode 32. The first lead electrode 31 and the second lead electrode 32 can be disposed in the same layer as the first source / drain metal electrode 5 and the second source / drain metal electrode 6. The first lead electrode 31 and the second lead electrode 32 protrude from the side of their respective pixel circuit 1 closest to the first light-emitting unit group 8.

[0142] The orthographic projection of the first lead electrode 31 on the plane of the display panel and the orthographic projection of the first sub-unit group 12 on the plane of the display panel overlap in the second direction y. The orthographic projection of the second lead electrode 32 on the plane of the display panel and the orthographic projection of the second sub-unit group 13 on the plane of the display panel overlap in the second direction y.

[0143] The above setting mode is to adjust the setting position of the leading electrode corresponding to the pixel circuit 1 in the first sub-circuit group 10 or the second sub-circuit group 11. By setting the first leading electrode 31 to overlap with the first sub-unit group 12 in the second direction y, the connection distance between the pixel circuit 1 in the first sub-circuit group 10 and the corresponding light emitting element 15 can be reduced. By setting the second leading electrode 32 to overlap with the second sub-unit group 13 in the second direction y, the distance between the pixel circuit 1 in the second sub-circuit group 11 and the corresponding light emitting element 15 can be reduced.

[0144] In a feasible implementation, as shown in Figure 27 , Figure 27 Another structure diagram of the first display unit 7 provided by the embodiment of the present application is shown in FIG. 6, wherein the light emitting unit 2 includes the light emitting element 15.

[0145] In combination with Figure 18 , the display panel includes a driving back plate 16, the driving back plate 16 includes a substrate 17, a circuit layer 18 located on one side of the substrate 17, and a first metal layer 19 located on a side of the circuit layer 18 away from the substrate 17.

[0146] The circuit layer 18 includes the pixel circuit 1, and the first metal layer 19 includes a first output electrode 20 electrically connected with the first pole of the light emitting element 15 and a second output electrode 21 electrically connected with the second pole of the light emitting element 15. The first output electrode 20 includes a first sub-electrode 22 and a second sub-electrode 23, the first sub-electrode 22 is further electrically connected with the pixel circuit 1 in the first sub-circuit group 10, and the second sub-electrode 23 is further electrically connected with the pixel circuit 1 in the second sub-circuit group 11.

[0147] For the first sub-electrode 22 and the second output electrode 21 electrically connected with the same light emitting element 15, the first sub-electrode 22 is located on the side of the second output electrode 21 close to the first sub-circuit group 10, so that the first sub-electrode 22 is closer to the first sub-circuit group 10, and the connection distance between the first sub-electrode 22 and the pixel circuit 1 in the first sub-circuit group 10 is reduced. For the second sub-electrode 23 and the second output electrode 21 electrically connected with the same light emitting element 15, the second sub-electrode 23 is located on the side of the second output electrode 21 close to the second sub-circuit group 11, so that the second sub-electrode 23 is closer to the second sub-circuit group 11, and the connection distance between the second sub-electrode 23 and the pixel circuit 1 in the second sub-circuit group 11 is reduced.

[0148] In a feasible implementation, as shown in Figures 28-31 , Figure 28 A film layer structure diagram of the pixel circuit 1 provided by the embodiment of the present application is shown in FIG. 7, Figure 29 A structure diagram of the driving transistor M0 provided by the embodiment of the present application is shown in FIG. 8, Figure 30A structure diagram of the first light-emitting control transistor M1 provided in the embodiment of the present application, Figure 31 A structure diagram of the second light-emitting control transistor M2 provided in the embodiment of the present application, the first sub-transistors 4 in the first transistor 3 are arranged along the first direction x and the second direction y, and the first direction x intersects the second direction y. That is, the first sub-transistors 4 in the first transistor 3 are arranged in multiple rows and multiple columns, that is, in a matrix form.

[0149] When the first transistor 3 includes multiple first sub-transistors 4 arranged in parallel, the matrix arrangement of the multiple first sub-transistors 4 can increase the horizontal space occupied by the first transistor 3 and compress the vertical space occupied by the first transistor 3, thereby reducing the vertical space pressure caused by the excessive number of the first sub-transistors 4 included in the first transistor 3 and avoiding the impact on the vertical length of the display panel.

[0150] In a feasible implementation, in the first transistor 3, the active layers al of the first sub-transistors 4 adjacent in the first direction x have a spacing therebetween, and the active layers al of the first sub-transistors 4 adjacent in the second direction y are arranged in communication. That is, whether the pixel circuit 1 includes one or two or more first transistors 3, the active layers al of the first sub-transistors 4 in the first transistor 3 follow the above design manner.

[0151] For details of the structure, refer to Figure 29 A structure of the first transistor 3. In the first transistor 3, for the first sub-transistors 4 arranged along the first direction x, as shown in Figure 32 , Figure 32 for Figure 29 corresponding to the first sub-transistors 4 arranged along the first direction x, the first doping regions dr1 in the active layers al of the multiple first sub-transistors 4 are all electrically connected to a first source-drain metal electrode 5 extending along the first direction x, the second doping regions dr2 in the active layers al of the multiple first sub-transistors 4 are all electrically connected to a second source-drain metal electrode 6 extending along the first direction x, the gates of the multiple first sub-transistors 4 are arranged along the first direction x and are in communication, but because there is a spacing between the active layers al of the adjacent first sub-transistors 4, the channels c of the adjacent first sub-transistors 4 have a spacing. For the first sub-transistors 4 arranged along the second direction y, as shown in Figure 33 , Figure 33 for Figure 29A structure diagram of the first sub-transistor 4 arranged along the second direction y, the channel c of the two adjacent first sub-transistors 4 is separated by a first doped region dr1 or a second doped region dr2, so the channel c of the two adjacent first sub-transistors 4 is also separated. Moreover, the first doped region dr1 of the active layer al of the two adjacent first sub-transistors 4 is connected together, or the second doped region dr2 of the active layer al of the two adjacent first sub-transistors 4 is connected together.

[0152] Alternatively, in the first transistor 3, the active layer al of the first sub-transistor 4 arranged along the first direction x is connected, and the active layer al of the first sub-transistor 4 arranged along the second direction y is separated. That is, no matter whether the pixel circuit 1 includes one or two or more first transistors 3, the active layer al of the first sub-transistor 4 in the first transistor 3 follows the above design.

[0153] The specific structure can be seen from Figure 30 and Figure 31 The first transistor 3 is shown. In this kind of first transistor 3, for the first sub-transistor 4 arranged along the first direction x, as Figure 34 shown, Figure 34 is Figure 30 and Figure 31 A structure diagram of the first sub-transistor 4 arranged along the first direction x, the channel c of the two adjacent first sub-transistors 4 is separated by a first doped region dr1 or a second doped region dr2, so the channel c of the two adjacent first sub-transistors 4 is also separated. Moreover, the first doped region dr1 of the active layer al of the two adjacent first sub-transistors 4 is connected together, or the second doped region dr2 of the active layer al of the two adjacent first sub-transistors 4 is connected together. For the first sub-transistor 4 arranged along the second direction y, as Figure 35 shown, Figure 35 is Figure 30 and Figure 31 A structure diagram of the first sub-transistor 4 arranged along the first direction x, the first doped region dr1 in the active layer al of the plurality of first sub-transistors 4 is electrically connected with a first source-drain metal electrode 5 extending along the second direction y, the second doped region dr2 in the active layer al of the plurality of first sub-transistors 4 is electrically connected with a second source-drain metal electrode 6 extending along the second direction y, the gate of the plurality of first sub-transistors 4 is arranged along the second direction y and connected together, but because the active layer al of the adjacent first sub-transistors 4 is separated, so the channel c of the adjacent first sub-transistors 4 is separated.

[0154] Alternatively, referring to Figure 28 , the pixel circuit 1 includes at least two first transistors 3. In combination with Figure 29In some of the first transistors 3, the active layers al of the first sub-transistors 4 adjacent in the first direction x are spaced apart, and the active layers al of the first sub-transistors 4 adjacent in the second direction y are connected. The present embodiment is exemplified by the arrangement of the first sub-transistors 4 in the driving transistor M0 satisfying the above condition. In combination with Figure 32 and Figure 33 The specific structure of the first sub-transistors 4 in the first transistors 3 has been described above and will not be repeated here. In combination with Figure 30 and Figure 31 In some of the first transistors 3, the active layers al of the first sub-transistors 4 adjacent in the first direction x are connected, and the active layers al of the first sub-transistors 4 adjacent in the second direction y are spaced apart. The present embodiment is exemplified by the arrangement of the first sub-transistors 4 in the first light-emitting control transistor M1 and the second light-emitting control transistor M2 satisfying the above condition. In combination with Figure 34 and Figure 35 The specific structure of the first sub-transistors 4 in the first transistors 3 has been described above and will not be repeated here.

[0155] That is, when the pixel circuit 1 includes at least two first transistors 3, the first sub-transistors 4 in the at least two first transistors 3 can follow different arrangements.

[0156] In a possible implementation, referring again to Figure 28 The first light-emitting control transistor M1, the driving transistor M0, and the second light-emitting control transistor M2 are all first transistors 3.

[0157] Among them, the driving transistor M0 plays a more important role in the pixel circuit 1, so the current output capability of the driving transistor M0 is required to be higher. In this regard, the number of the first sub-transistors 4 in the driving transistor M0 can be set to be greater than the number of the first sub-transistors 4 in the first light-emitting control transistor M1 and the second light-emitting control transistor M2, so that the driving transistor M0 has a larger equivalent width-length ratio. For example, the driving transistor M0 includes 30 first sub-transistors 4, and the first light-emitting control transistor M1 and the second light-emitting control transistor M2 each include 20 first sub-transistors 4. Alternatively, as shown in Figure 28 The driving transistor M0 includes 56 first sub-transistors 4, and the first light-emitting control transistor M1 and the second light-emitting control transistor M2 each include 20 first sub-transistors 4.

[0158] Of course, in other optional embodiments, the first light-emitting control transistor M1, the driving transistor M0, and the second light-emitting control transistor M2 can also include other numbers of first sub-transistors 4, which are not limited by the present application.

[0159] When a larger number of first sub-transistors 4 are set in the driving transistor M0, the number of first sub-transistors 4 arranged along the first direction x in the driving transistor M0 can be further set to be greater than the number of first sub-transistors 4 arranged along the second direction y, so as to compress the vertical space of the driving transistor M0 as much as possible and avoid the vertical space occupied by a single pixel circuit 1 being too large.

[0160] In one feasible implementation, see again Figure 28 The first light-emitting control transistor M1, the driving transistor M0, and the second light-emitting control transistor M2 are all first transistors 3.

[0161] The first light-emitting control transistor M1 and the second light-emitting control transistor M2 are both electrically connected to a light-emitting control signal line Emit extending along a first direction x. The light-emitting control signal line Emit is located between the second light-emitting control transistor M2 and the first light-emitting control transistor M1, and the driving transistor M0 is located on the side of the first light-emitting control transistor M1 away from the second light-emitting control transistor M2.

[0162] When the first light-emitting control transistor M1 and the second light-emitting control transistor M2 are electrically connected to the same light-emitting control signal line Emit, placing the light-emitting control signal line Emit between these two light-emitting control transistors will facilitate the connection between Emit and these two light-emitting control transistors. Furthermore, combined with... Figure 12 The driving transistor M0 is located on the side of the first light-emitting control transistor M1 away from the second light-emitting control transistor M2. The driving transistor M0 is not positioned between the second light-emitting control transistor M2 and the first light-emitting unit group 8, so it will not affect the connection between the second light-emitting control transistor M2 and the light-emitting unit 2.

[0163] In one feasible implementation, such as Figure 36 As shown, Figure 36 This is a schematic diagram of the distribution of the temperature sensor 33 provided in an embodiment of the present invention. The length of the driving transistor M0 in the first direction x is greater than the lengths of the first light-emitting control transistor M1 and the second light-emitting control transistor M2 in the first direction x.

[0164] The display panel also includes a temperature sensor 33 for detecting the panel temperature. At least a portion of the temperature sensor 33 is located on one side of the first light-emitting control module in the first direction x, and / or at least a portion of the temperature sensor 33 is located on one side of the second light-emitting control module in the first direction x, so as to achieve reasonable utilization of the space on one side of the first light-emitting control module and / or the second light-emitting control module in the first direction x.

[0165] In one feasible implementation, combined with Figure 2 and Figure 28 The pixel circuit 1 further comprises a gate reset module 34 and a data write module 35. The gate reset module 34 is electrically connected with the first scan signal line Scan1, and the data write module 35 is electrically connected with the second scan signal line Scan2.

[0166] More specifically, referring again to Figure 2 The pixel circuit 1 further has a third node O3, a fourth node O4 and a fifth node O5. The first light emitting control transistor M1 is coupled between the first node O1 and the third node O3, the driving transistor M0 is coupled between the third node O3 and the fourth node O4, and the second light emitting control transistor M2 is coupled between the fourth node O4 and the second node O2. The gate of the first sub transistor 4 in the driving transistor M0 is electrically connected with the fifth node O5.

[0167] The gate reset module 34 comprises a gate reset transistor M3. The gate of the gate reset transistor M3 is electrically connected with the first scan signal line Scan1, the first pole of the gate reset transistor M3 is electrically connected with the reset signal line Vref, and the second pole of the gate reset transistor M3 is electrically connected with the fifth node O5. The data write module 35 comprises a data write transistor M4. The gate of the data write transistor M4 is electrically connected with the second scan signal line Scan2, the first pole of the data write transistor M4 is electrically connected with the data line Data, and the second pole of the data write transistor M4 is electrically connected with the third node O3.

[0168] In the embodiment, the width of the light emitting control signal line Emit in the direction perpendicular to the extending direction of the light emitting control signal line Emit is greater than the width of the first scan signal line Scan1 and / or the width of the second scan signal line Scan2 in the direction perpendicular to the extending direction of the first scan signal line Scan1 and / or the second scan signal line Scan2.

[0169] As described above, the light emitting control signal line Emit needs to be connected with the first light emitting control transistor M1 and the second light emitting control transistor M2. Therefore, the light emitting control signal line Emit needs to drive a large number of first sub transistors 4, resulting in a large load. Moreover, in a display panel with high lateral resolution, the length of the light emitting control signal line Emit is large, which also increases the response time of the light emitting control transistor. In the embodiment, the line width of the light emitting control signal line Emit is set to be large, so as to weaken the load and reduce the response time of the light emitting control transistor.

[0170] In a feasible implementation manner, as shown in Figure 37 , the light emitting control signal line Emit is electrically connected with the second metal part 36, and the light emitting control signal line Emit and the second metal part 36 overlap in the direction perpendicular to the plane where the display panel is located. Figure 37 As shown in FIG. 6, the light emitting control signal line Emit is electrically connected with the second metal part 36, and the light emitting control signal line Emit and the second metal part 36 overlap in the direction perpendicular to the plane where the display panel is located.

[0171] The setting mode is equivalent to double-layer wiring design for the overall structure of the light emitting control signal line Emit, which not only can further reduce the load of the light emitting control signal line Emit, but also can reduce the line width requirement of the light emitting control signal line Emit. Under the condition that the load of the light emitting control signal line Emit meets the requirement, the light emitting control signal line Emit can not be set too wide, thereby reducing the longitudinal space occupied by the light emitting control signal line Emit.

[0172] In a possible implementation, in combination with Figure 2 and Figure 28 , the pixel circuit 1 further includes a data writing module 35, the data writing module 35 is electrically connected with the data line Data, and the extension direction of the data line Data intersects with the extension direction of the light emitting control signal line Emit.

[0173] In combination with Figure 37 and Figure 38 , Figure 38 Figure 37 is a sectional view along the C1-C2 direction, the second metal part 36 is arranged in the same layer as the data line Data, the light emitting control signal line Emit is electrically connected with the plurality of second metal parts 36, and the second metal part 36 is located between adjacent data lines Data. In this way, the second metal part 36 can be formed by using the same patterning process as the data line Data, and there is sufficient wiring space between the adjacent data lines Data, so that a larger area can be provided for the second metal part 36.

[0174] In a possible implementation, in combination with Figure 2 and Figure 28 , the pixel circuit 1 further has a third node O3, a fourth node O4 and a fifth node O5, the first light emitting control transistor M1 is coupled between the first node O1 and the third node O3, the driving transistor M0 is coupled between the third node O3 and the fourth node O4, the second light emitting control transistor M2 is coupled between the fourth node O4 and the second node O2, and the gate of the first sub-transistor 4 in the driving transistor M0 is electrically connected with the fifth node O5.

[0175] The pixel circuit 1 further includes a gate reset module 34, a data writing module 35, a compensation module 37 and an anode reset module 38, wherein the gate reset module 34 is electrically connected with the fifth node O5, the data writing module 35 is electrically connected with the third node O3, the compensation module 37 is respectively electrically connected with the fourth node O4 and the fifth node O5, and the anode reset module 38 is electrically connected with the second node O2.

[0176] More specifically, referring again to Figure 2 ​The gate reset module 34 comprises a gate reset transistor M3, a gate of the gate reset transistor M3 is electrically connected with the first scan signal line Scan1, a first pole of the gate reset transistor M3 is electrically connected with the reset signal line Vref, and a second pole of the gate reset transistor M3 is electrically connected with the fifth node O5.

[0177] The data write module 35 comprises a data write transistor M4, a gate of the data write transistor M4 is electrically connected with the second scan signal line Scan2, a first pole of the data write transistor M4 is electrically connected with the data line Data, and a second pole of the data write transistor M4 is electrically connected with the third node O3.

[0178] The compensation module 37 comprises a compensation transistor M5, a gate of the compensation transistor M5 is electrically connected with the second scan signal line Scan2, a first pole of the compensation transistor M5 is electrically connected with the fourth node O4, and a second pole of the compensation transistor M5 is electrically connected with the fifth node O5.

[0179] The anode reset module 38 comprises an anode reset transistor M6, a first pole of the anode reset transistor M6 is electrically connected with the reset signal line Vref, and a second pole of the anode reset transistor M6 is electrically connected with the second node O2.

[0180] In the pixel circuit 1, the first node O1 is electrically connected with the first light-emitting control transistor M1, the second node O2 is electrically connected with the second light-emitting control transistor M2, the third node O3 is electrically connected with the data write transistor M4, the fourth node O4 is electrically connected with the compensation transistor M5, the fifth node O5 is electrically connected with the gate reset transistor M3 and the compensation transistor M5, and the sixth node O6 is electrically connected with the driving transistor M0. Figure 28 The gate reset module 34, the data write module 35, the compensation module 37 and the anode reset module 38 are all located between the first light-emitting control transistor M1 and the driving transistor M0.

[0181] By arranging these modules between the first light-emitting control transistor M1 and the driving transistor M0, on the one hand, the gate reset module 34, the data write module 35 and the compensation module 37 are close to the driving transistor M0, which facilitates the connection between these modules and the driving transistor M0, and on the other hand, compared with arranging these modules on the side of the driving transistor M0 away from the first light-emitting control transistor M1, the anode reset module 38 is also close to the second light-emitting control transistor M2, which facilitates the connection between the anode reset module 38 and the second light-emitting control transistor M2, and further facilitates the connection with the light-emitting element 15.

[0182] In addition, as shown in Figure 2 and Figure 28 , the pixel circuit 1 can further comprise a storage capacitor Cst, a first plate of the storage capacitor Cst is electrically connected with the first node O1, and a second plate of the storage capacitor Cst is electrically connected with the fifth node O5.

[0183] In a feasible implementation manner, as shown in Figure 39 and Figure 40 , Figure 39 is Figure 5 another structural schematic diagram corresponding to the region A in , the first light-emitting control transistor M1, the driving transistor M0, the gate reset transistor M3, the data write transistor M4, the compensation transistor M5, the anode reset transistor M6, the first node O1, the second node O2, the third node O3, the fourth node O4, the fifth node O5 and the sixth node O6 are all located in the region A. Figure 40 This is a schematic diagram of a structure of a second display unit 60 provided in an embodiment of the present invention. The display panel includes the second display unit 60, and the second display unit 60 includes a second light-emitting unit group 61 and a second pixel circuit group 39. The second light-emitting unit group 61 includes a plurality of light-emitting units 2 arranged along a first direction x, and the second pixel circuit group 39 includes a plurality of pixel circuits 1 arranged along the first direction x.

[0184] Furthermore, in the second display unit 60, the second light-emitting unit group 61 and the second pixel circuit group 39 are arranged along the second direction y, and the light-emitting unit 2 and the pixel circuit 1 connected to it can be arranged along the second direction y. At this time, the light-emitting unit 2 and its corresponding pixel circuit 1 are relatively close, which facilitates their connection.

[0185] In one feasible implementation, such as Figure 41 As shown, Figure 41 This is another structural schematic diagram of the first transistor 3 provided in an embodiment of the present invention. The first sub-transistors 4 in the first transistor 3 are arranged along the second direction y, and there is a gap between the active layers a1 of two adjacent first sub-transistors 4. The second direction y intersects with the first direction x.

[0186] In this structure, each first sub-transistor 4 connected in parallel in the first transistor 3 has a small aspect ratio, which can improve the performance of the first transistor 3 while increasing the equivalent aspect ratio. Moreover, in this design, the gates of X first sub-transistors 4 are connected together, the first doped region dr1 of the active layer al of X first sub-transistors 4 is electrically connected to a first source / drain metal electrode 5 extending along the second direction y, and the second doped region dr2 of the active layer al of X first sub-transistors 4 is electrically connected to a second source / drain metal electrode 6 extending along the second direction y, making the layout design of the first transistor 3 simpler.

[0187] In one feasible implementation, such as Figure 42 As shown, Figure 42 This is a schematic diagram of the dimensions of the first sub-transistor 4 provided in an embodiment of the present invention. In the first transistor 3, the channel width W of the first sub-transistor 4 is less than 20 μm. At this time, the channel width W of the first sub-transistor 4 is small, which can avoid abnormal characteristic curves of the transistor structure, so that the transistor has a faster turn-on speed and better performance.

[0188] In one feasible implementation, see again Figure 42 In the first transistor 3, the first doped region dr1 of the active layer al in the first sub-transistor 4 is electrically connected to the first source / drain metal electrode 5 through the first connection via 40, and the second doped region dr2 is electrically connected to the second source / drain metal electrode 6 through the second connection via 41.

[0189] The distance h1 between the projection of the gate g of the first sub-transistor 4 in the direction perpendicular to the plane where the display panel is located and the projection of the first connection via 40 in the direction perpendicular to the plane where the display panel is located is greater than or equal to 2.5 μm, and the distance h2 between the projection of the gate g of the first sub-transistor 4 in the direction perpendicular to the plane where the display panel is located and the projection of the second connection via 41 in the direction perpendicular to the plane where the display panel is located is greater than or equal to 2.5 μm. The distance between the projection of the gate g of the sub-transistor and the projection of the connection via can be the distance between the point in the projection of the connection via closest to the projection of the gate and the projection of the gate.

[0190] In this way, the gate g and the connection via are spaced apart by a sufficient distance, preventing the metal material in the connection via from being short-circuited with the gate g.

[0191] In a feasible implementation, referring again to Figure 42 , in the first transistor 3, the distance k between the active layers al of two adjacent first sub-transistors 4 in the second direction y is greater than or equal to 2.5 μm, preventing the channels c of the adjacent first sub-transistors 4 from being spaced apart due to abnormal exposure in the process.

[0192] In a feasible implementation, in combination with Figure 2 , as shown in Figures 43-47 , Figure 43 is a simplified structure diagram of the pixel circuit 1 provided by an embodiment of the present application, Figure 44 is another circuit structure diagram of the pixel circuit 1 provided by an embodiment of the present application, Figure 45 is Figure 43 a structure diagram corresponding to the region D in Figure 46 is Figure 43 a structure diagram corresponding to the region E in Figure 47 is Figure 43 a structure diagram corresponding to the region F in The pixel circuit 1 includes a first light-emitting control transistor M1, a driving transistor M0, and a second light-emitting control transistor M2, wherein the first light-emitting control transistor M1 is coupled between the first node O1 and the driving transistor M0, and the second light-emitting control transistor M2 is coupled between the driving transistor M0 and the second node O2. The first light-emitting control transistor M1, the driving transistor M0, and the second light-emitting control transistor M2 are all first transistors 3.

[0193] Wherein, along the second direction y, the driving transistor M0 is located between the second light-emitting control transistor M2 and the first light-emitting control transistor M1.

[0194] When the plurality of first sub-transistors 4 in the first transistor 3 are arranged along the second direction y, the longitudinal length of the first transistor 3 is large, and the driving transistor M0 is arranged between the first light-emitting control transistor M1 and the second light-emitting control transistor M2, so that the driving transistor M0 is spaced apart from the second light-emitting unit group 61 by a large distance, and the heat emitted by the second light-emitting unit group 61 does not affect the characteristics of the driving transistor M0.

[0195] In an embodiment, the first light-emitting control transistor M1 is electrically connected to the first light-emitting control signal line Emit1 extending along the first direction x, and the second light-emitting control transistor M2 is electrically connected to the second light-emitting control signal line Emit2 extending along the first direction x. Figure 43 、 Figure 45 and Figure 47

[0196] In the above embodiment, the distance between the first light-emitting control transistor M1 and the first light-emitting control signal line Emit1 is less than the distance between the first light-emitting control transistor M1 and the second light-emitting control signal line Emit2, and the distance between the second light-emitting control signal line Emit2 and the second light-emitting control signal line Emit2 is less than the distance between the second light-emitting control transistor M2 and the first light-emitting control signal line Emit1.

[0197] The longitudinal length of the first light-emitting control transistor M1 and the second light-emitting control transistor M2 is large, and the driving transistor M0 is arranged between the first light-emitting control transistor M1 and the second light-emitting control transistor M2, so that the distance between the first light-emitting control transistor M1 and the second light-emitting control transistor M2 is large. By electrically connecting the two light-emitting control transistors to two independent light-emitting control signal lines respectively, the connection design of the light-emitting control transistors and the light-emitting control signal lines can be simplified. Moreover, if only one light-emitting control signal line is used to electrically connect the two light-emitting control transistors, the load of the light-emitting control signal line is too large, and the first sub-transistor 4 in the two light-emitting control transistors will also be turned on slowly. The above arrangement can effectively solve the problem.

[0198] Further, as shown in Figure 48 , Figure 48 is another structure diagram of the first light-emitting control signal line Emit1 provided by the embodiment of the present application. The first light-emitting control signal line Emit1 is electrically connected to the first electrode part 42 extending along the second direction y, the first electrode part 42 is multiplexed as the gate g of each first sub-transistor 4 in the first light-emitting control transistor M1, and the width of the first light-emitting control signal line Emit1 in the second direction y is greater than the width of the first electrode part 42 in the first direction x, so that the first light-emitting control signal line Emit1 has a larger line width, and the larger line width is used to weaken the load.

[0199] As shown in Figure 49 , Figure 49 ​Another structural diagram of the second light emitting control signal line Emit2 provided by the embodiment of the present application is shown in FIG. 6, the second electrode part 43 of the second light emitting control transistor M2 extending along the second direction y is electrically connected, the second electrode part 43 is multiplexed as the gate g of each first sub transistor 4 in the second light emitting control transistor M2, the width of the second light emitting control signal line Emit2 in the second direction y is greater than the width of the second electrode part 43 in the first direction x, at this time, the first light emitting control signal line Emit1 has a greater line width, and the greater line width is used to weaken the load thereof.

[0200] In a feasible implementation manner, the present application is combined with Figure 43 、 Figure 44 and Figure 50 , Figure 50 for Figure 43 corresponding to the region G in FIG. 4, a structural diagram is shown in FIG. 5, Figure 51 for Figure 43 corresponding to the region H in FIG. 4, a structural diagram is shown in FIG. 6, the pixel circuit 1 further has a third node O3, a fourth node O4 and a fifth node O5, the first light emitting control transistor M1 is coupled between the first node O1 and the third node O3, the driving transistor M0 is coupled between the third node O3 and the fourth node O4, the second light emitting control transistor M2 is coupled between the fourth node O4 and the second node O2, and the gate of the first sub transistor 4 in the driving transistor M0 is electrically connected with the fifth node O5.

[0201] The pixel circuit 1 further includes a data writing module 35, a compensation module 37 and an anode reset module 38, wherein the data writing module 35 is electrically connected with the third node O3, the compensation module 37 is electrically connected with the fourth node O4 and the fifth node O5 respectively, and the anode reset module 38 is electrically connected with the second node O2.

[0202] The anode reset module 38 and the compensation module 37 are located between the second light emitting control transistor M2 and the driving transistor M0, and the data writing module 35 is located between the driving transistor M0 and the first light emitting control transistor M1.

[0203] The anode reset module 38 has a connection relationship with the second light emitting control transistor M2, and the compensation module 37 has a connection relationship with the driving transistor M0. By arranging the anode reset module 38 and the compensation module 37 between the second light emitting control transistor M2 and the driving transistor M0, the connection of the anode reset module 38 with the second light emitting control transistor M2 and the connection of the compensation module 37 with the driving transistor M0 can be facilitated. The data writing module 35 has a connection relationship between the driving transistor M0 and the first light emitting control transistor M1. By arranging the data writing module 35 between the driving transistor M0 and the first light emitting control transistor M1, the connection between the data writing module 35 and the driving transistor M0 and the first light emitting control transistor M1 can be facilitated.

[0204] In an implementation, as shown in Figure 52 , Figure 52 For Figure 50 A corresponding partial enlarged view, the anode reset module 38 includes an anode reset transistor M6, the gate of the anode reset transistor M6 is electrically connected with the first scan signal line Scan1, the first electrode of the anode reset transistor M6 is electrically connected with the reset signal line Vref, and the second electrode of the anode reset transistor M6 is electrically connected with the second node O2.

[0205] Wherein, the reset signal line Vref is located on the side of the first scan signal line Scan1 close to the second light-emitting control transistor M2, the reset signal line Vref is electrically connected with one end of the first wire 45 through the first via hole 44, the first wire 45 extends along the second direction y, and the other end of the first wire 45 is electrically connected with the first electrode of the anode reset transistor M6 through the second via hole 46 on the side of the first scan signal line Scan1 away from the reset signal line Vref, and the second electrode of the anode reset transistor M6 is electrically connected with the second light-emitting control transistor M2 through the third via hole 47 on the side of the reset signal line Vref away from the first scan signal line Scan1.

[0206] And, in the direction perpendicular to the plane where the display panel is located, the first wire 45 overlaps with the active layer al of the anode reset transistor M6, so that the first wire 45 does not need to occupy additional horizontal space, which helps to further reduce the horizontal length of the pixel circuit 1.

[0207] In an implementation, as shown in Figure 44 , the pixel circuit 1 further includes a gate reset module 34, the gate reset module 34 includes a gate reset transistor M3, the gate of the gate reset transistor M3 is electrically connected with the first scan signal line Scan1, the first electrode of the gate reset transistor M3 is electrically connected with the reset signal line Vref, and the second electrode of the gate reset transistor M3 is electrically connected with the fifth node O5.

[0208] Again, as shown in Figure 52 , the gate reset transistor M3 is located between the second light-emitting control transistor M2 and the driving transistor M0. Wherein, the reset signal line Vref is also electrically connected with one end of the second wire 49 through the fourth via hole 48, the second wire 49 extends along the second direction y, and the other end of the second wire 49 is connected with the first electrode of the gate reset transistor M3 through the fifth via hole 50 on the side of the first scan signal line Scan1 away from the reset signal line Vref.

[0209] And, in the direction perpendicular to the plane where the display panel is located, the second trace 49 overlaps with the active layer al of the gate reset transistor M3, so that the second trace also does not need to occupy additional horizontal space, which helps to further reduce the horizontal length of the pixel circuit 1.

[0210] Further, referring to Figure 44 , the compensation module 37 comprises a compensation transistor M5, the gate of the compensation transistor M5 is electrically connected with the second scan signal line Scan2, the first pole of the compensation transistor M5 is electrically connected with the fourth node O4, and the second pole of the compensation transistor M5 is electrically connected with the fifth node O5.

[0211] As shown in Figure 53 , Figure 53 , the first pole of the compensation transistor M5 is electrically connected with the second light-emitting control transistor M2 through a third trace 51, the third trace 51 extends along the second direction y, and the third trace 51 is arranged in a different layer from the second trace 49. Figure 50 If the third trace 51 and the second trace 49 are arranged in the same layer, a sufficient distance needs to be kept between the third trace 51 and the second trace 49 to avoid short circuit, and by arranging the third trace 51 in a different layer from the second trace 49, the distance between the orthogonal projection of the third trace 51 on the plane where the display panel is located and the orthogonal projection of the second trace 49 on the plane where the display panel is located can be reduced, or the third trace 51 can directly overlap with the second trace 49, so as to further reduce the horizontal wiring space occupied by the pixel circuit 1.

[0212] In a feasible implementation, in combination with

[0213] , Figure 44 and Figure 50 , the data writing module 35 is electrically connected with the second scan signal line Scan2, and the compensation module 37 is electrically connected with the third scan signal line Scan3, wherein the signals transmitted by the second scan signal line Scan2 and the third scan signal line Scan3 at the same time are the same. Figure 51 The third scan signal line Scan3 is located between the second light-emitting control transistor M2 and the driving transistor M0, and the second scan signal line Scan2 is located between the driving transistor M0 and the first light-emitting control transistor M1.

[0214] Because the data writing module 35 and the compensation module 37 are respectively located on the opposite sides of the driving transistor M0 in the second direction y, they are far apart, so in the embodiment of the application, an independent scan signal line can be arranged for each of them for connection with the scan signal line.

[0215]

[0216] ​Based on the same inventive concept, the embodiment of the present application further provides a display device, such as Figure 54 as shown in the figure, Figure 54 A structural schematic diagram of the display device provided by the embodiment of the present application is shown in the figure, which comprises the display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiment, and will not be repeated here. Of course, Figure 54 The display device shown in the figure is only for illustrative purposes, and the display device can be any electronic device with display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic paper, or a television.

[0217] The above is only the preferred embodiment of the present application, and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0218] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized by, The pixel circuit and the light emitting unit are included; The pixel circuit has a first node and a second node, the first node is electrically connected with a first power supply line, and the second node is electrically connected with the light emitting unit; The pixel circuit includes a first transistor, and the first transistor is coupled between the first node and the second node; wherein the first transistor includes X first sub-transistors, the gates of the X first sub-transistors are connected, the first poles are connected, and the second poles are connected, X≥2 and X is an integer; The display panel includes a first display unit, and the first display unit includes a first light emitting unit group and a first pixel circuit group, wherein the first light emitting unit group includes M light emitting units arranged along a first direction, the first pixel circuit group includes N pixel circuits arranged along a second direction, the N pixel circuits in the first pixel circuit group are electrically connected with the M light emitting units in the first light emitting unit group, and the pixel circuits in the first pixel circuit group are electrically connected with at least one light emitting unit in the first light emitting unit group; M≥2, N≥2, and M and N are integers, the first direction and the second direction intersect; and / or the display panel includes a second display unit, and the second display unit includes a second light emitting unit group and a second pixel circuit group, wherein the second light emitting unit group includes a plurality of light emitting units arranged along a first direction, and the second pixel circuit group includes a plurality of pixel circuits arranged along the first direction; the first sub-transistors in the first transistor are arranged along a second direction, and there is a spacing between the active layers of adjacent two first sub-transistors, and the second direction intersects the first direction.

2. The display panel of claim 1, wherein The pixel circuit includes a first light emitting control transistor, a driving transistor, and a second light emitting control transistor, wherein the first light emitting control transistor is coupled between the first node and the driving transistor, and the second light emitting control transistor is coupled between the driving transistor and the second node; At least one of the first light emitting control transistor, the driving transistor, and the second light emitting control transistor is the first transistor.

3. The display panel of claim 1, wherein M=N.

4. The display panel of claim 1, wherein In the first display unit, the N pixel circuits in the first pixel circuit group are located on at least one side of the first light emitting unit group in the second direction.

5. The display panel of claim 4, wherein The length of the pixel circuit in the first direction is D, (M-1)×(d1+d2)≤D≤M×(d1+d2), wherein d1 is the length of the light emitting unit in the first direction, and d2 is the spacing between adjacent light emitting units.

6. The display panel of claim 1, wherein ​ The first pixel circuit group comprises a first sub-circuit group and a second sub-circuit group, the first sub-circuit group comprises N1 pixel circuits, the second sub-circuit group comprises N2 pixel circuits, N1+N2=N, N1≥1, N2≥1, and N1 and N2 are integers; The first light emitting unit group is located between the first sub-circuit group and the second sub-circuit group.

7. The display panel of claim 6, wherein, M=N, N1≥2, N2≥2; The first light emitting unit group comprises a first sub-unit group and a second sub-unit group arranged along a first direction, the first sub-unit group comprises N1 light emitting units, and the second sub-unit group comprises N2 light emitting units; wherein, N1 pixel circuits in the first sub-circuit group arranged in a direction from the first sub-circuit group to the second sub-circuit group are electrically connected to N1 light emitting units in the first sub-unit group arranged in a direction from the first sub-unit group to the second sub-unit group in sequence; N2 pixel circuits in the second sub-circuit group arranged in a direction from the first sub-circuit group to the second sub-circuit group are electrically connected to N2 light emitting units in the second sub-unit group arranged in a direction from the first sub-unit group to the second sub-unit group in sequence.

8. The display panel of claim 6, wherein, N1=N2.

9. The display panel of claim 6, wherein, The pixel circuit comprises a first light emitting control transistor, a driving transistor, and a second light emitting control transistor, the first light emitting control transistor is coupled between the first node and the driving transistor, and the second light emitting control transistor is coupled between the driving transistor and the second node; At least one of the first light emitting control transistor, the driving transistor, and the second light emitting control transistor is the first transistor; In the pixel circuit in the first sub-circuit group and / or the second sub-circuit group, the distance between the second light emitting control transistor and the first light emitting unit group is less than the distance between the first light emitting control transistor and the first light emitting unit group.

10. The display panel of claim 9, wherein, The pixel circuit in the first sub-circuit group and the pixel circuit in the second sub-circuit group are in a mirror relationship along the first direction.

11. The display panel of claim 6, wherein, The light emitting unit comprises a light emitting element; The display panel further comprises a driving backplane, the driving backplane comprises a substrate, a circuit layer located on one side of the substrate, and a first metal layer located on a side of the circuit layer away from the substrate; wherein, The circuit layer comprises the pixel circuit; the first metal layer comprises a first output electrode electrically connected to a first pole of the light emitting element, a second output electrode electrically connected to a second pole of the light emitting element, and a second power supply line electrically connected to the second output electrode, wherein the first output electrode is located on the same side of the light emitting element as the second output electrode close to the second sub-circuit group, and the second power supply line overlaps the first sub-circuit group in a direction perpendicular to the plane in which the substrate lies; The first output electrode comprises a first sub-electrode and a second sub-electrode, the first sub-electrode is electrically connected to the pixel circuit in the first sub-circuit group through a first connecting line, and the second sub-electrode is electrically connected to the pixel circuit in the second sub-circuit group through a second connecting line, wherein the second connecting line is located in the first metal layer, and the first connecting line is located on the side of the first metal layer close to the substrate.

12. The display panel of claim 11, wherein, The driving backplate further comprises a second metal layer between the circuit layer and the first metal layer, and the first connecting line is located in the second metal layer; the second metal layer further comprises a first connecting electrode and a second connecting electrode; The pixel circuit in the second sub-circuit group is electrically connected to the second connecting line through the second connecting electrode, and the pixel circuit in the first sub-circuit group is electrically connected to a first metal part in the first metal layer through the first connecting electrode; the second power supply line comprises a hollow part, and at least part of the first metal part is located in the hollow part and is electrically insulated from the second power supply line.

13. The display panel of claim 11, wherein, The driving backplate further comprises a second metal layer between the circuit layer and the first metal layer, and the first connecting line is located in the second metal layer; The thickness of the first metal layer and the thickness of the second metal layer are different in a direction perpendicular to the plane in which the substrate lies; and / or the width of the second connecting line and the width of the first connecting line are different.

14. The display panel of claim 11, wherein, The first connecting line does not overlap the first output electrode and the second output electrode in a direction perpendicular to the plane in which the substrate lies.

15. The display panel of claim 14, wherein, The first connecting line is electrically connected to the first sub-electrode on the side of the first sub-electrode close to the second sub-circuit group.

16. The display panel of claim 6, wherein, The first light emitting unit group comprises a first sub-unit group and a second sub-unit group arranged along the first direction, the first sub-unit group comprises M1 light emitting units, and the second sub-unit group comprises M2 light emitting units, M1≥1, M2≥1, and M1 and M2 are integers. The pixel circuit in the first sub-circuit group is electrically connected with the light emitting unit in the first sub-unit group through a first connecting line, and the pixel circuit in the second sub-circuit group is electrically connected with the light emitting unit in the second sub-unit group through a second connecting line; The pixel circuit in the first sub-circuit group is electrically connected with the first connecting line through a first lead-out electrode, and the pixel circuit in the second sub-circuit group is electrically connected with the second connecting line through a second lead-out electrode; The first lead-out electrode and the first sub-unit group are overlapped in the second direction in the projection on the plane of the display panel, and the second lead-out electrode and the second sub-unit group are overlapped in the second direction in the projection on the plane of the display panel.

17. The display panel of claim 6, wherein The light emitting unit comprises a light emitting element; The display panel comprises a driving back plate, the driving back plate comprises a substrate, a circuit layer on one side of the substrate, and a first metal layer on a side of the circuit layer away from the substrate; wherein The circuit layer comprises the pixel circuit, and the first metal layer comprises a first output electrode electrically connected with a first pole of the light emitting element and a second output electrode electrically connected with a second pole of the light emitting element; the first output electrode comprises a first sub-electrode and a second sub-electrode, the first sub-electrode is further electrically connected with the pixel circuit in the first sub-circuit group, and the second sub-electrode is further electrically connected with the pixel circuit in the second sub-circuit group; The first sub-electrode is located on a side of the second output electrode of the same light emitting element close to the first sub-circuit group, and the second sub-electrode is located on a side of the second output electrode of the same light emitting element close to the second sub-circuit group.

18. The display panel of claim 1, wherein The first sub-transistor in the first transistor is arranged along a first direction and a second direction, and the first direction intersects the second direction.

19. The display panel of claim 18, wherein In the first transistor, the active layers of the first sub-transistors adjacent in the first direction have a spacing therebetween, and the active layers of the first sub-transistors adjacent in the second direction are arranged in communication; Or, in the first transistor, the active layers of the first sub-transistors adjacent in the first direction are arranged in communication, and the active layers of the first sub-transistors adjacent in the second direction have a spacing therebetween. Alternatively, the pixel circuit includes at least two first transistors, in some of the first transistors, the active layers of the first sub-transistors adjacent in the first direction are spaced apart, and the active layers of the first sub-transistors adjacent in the second direction are arranged in communication; in some of the first transistors, the active layers of the first sub-transistors adjacent in the first direction are arranged in communication, and the active layers of the first sub-transistors adjacent in the second direction are spaced apart.

20. The display panel of claim 18, wherein, the pixel circuit includes a first light-emitting control transistor, a driving transistor, and a second light-emitting control transistor, wherein the first light-emitting control transistor is coupled between the first node and the driving transistor, and the second light-emitting control transistor is coupled between the driving transistor and the second node; the first light-emitting control transistor, the driving transistor, and the second light-emitting control transistor are all the first transistors; wherein the number of the first sub-transistors in the driving transistor is greater than the number of the first sub-transistors in the first light-emitting control transistor and the second light-emitting control transistor, and the number of the first sub-transistors arranged in the first direction in the driving transistor is greater than the number of the first sub-transistors arranged in the second direction.

21. The display panel of claim 18, wherein, the pixel circuit includes a first light-emitting control transistor, a driving transistor, and a second light-emitting control transistor, wherein the first light-emitting control transistor is coupled between the first node and the driving transistor, and the second light-emitting control transistor is coupled between the driving transistor and the second node; the first light-emitting control transistor, the driving transistor, and the second light-emitting control transistor are all the first transistors; wherein the first light-emitting control transistor and the second light-emitting control transistor are both electrically connected with a light-emitting control signal line extending in the first direction, the light-emitting control signal line is located between the second light-emitting control transistor and the first light-emitting control transistor, and the driving transistor is located on a side of the first light-emitting control transistor away from the second light-emitting control transistor.

22. The display panel of claim 21, wherein, the length of the driving transistor in the first direction is greater than the lengths of the first light-emitting control transistor and the second light-emitting control transistor in the first direction; the display panel further includes a temperature sensor, at least part of the temperature sensor is located on a side of the first light-emitting control transistor in the first direction, and / or at least part of the temperature sensor is located on a side of the second light-emitting control transistor in the first direction.

23. The display panel of claim 21, wherein, the pixel circuit further includes a gate reset module and a data writing module, the gate reset module is electrically connected with a first scan signal line, and the data writing module is electrically connected with a second scan signal line. The width of the light-emitting control signal line in a direction perpendicular to the extension direction of the light-emitting control signal line is greater than the width of the first scan signal line and / or the second scan signal line in a direction perpendicular to the extension direction of the first scan signal line and / or the second scan signal line.

24. The display panel of claim 21, wherein, The light-emitting control signal line is also electrically connected to the second metal part, and the light-emitting control signal line overlaps the second metal part in a direction perpendicular to the plane in which the display panel lies.

25. The display panel of claim 24, wherein, The pixel circuit further comprises a data writing module, and the data writing module is electrically connected to a data line, and the extension direction of the data line intersects the extension direction of the light-emitting control signal line. The second metal part is arranged in the same layer as the data line, and the light-emitting control signal line is electrically connected to a plurality of the second metal parts, and the second metal part is located between adjacent data lines.

26. The display panel of claim 21, wherein, The pixel circuit further has a third node, a fourth node, and a fifth node, the first light-emitting control transistor is coupled between the first node and the third node, the driving transistor is coupled between the third node and the fourth node, the second light-emitting control transistor is coupled between the fourth node and the second node, and the gate of the first sub-transistor in the driving transistor is electrically connected to the fifth node. The pixel circuit further comprises a gate reset module, a data writing module, a compensation module, and an anode reset module, wherein the gate reset module is electrically connected to the fifth node, the data writing module is electrically connected to the third node, the compensation module is electrically connected to the fourth node and the fifth node respectively, and the anode reset module is electrically connected to the second node. The gate reset module, the data writing module, the compensation module, and the anode reset module are all located between the first light-emitting control transistor and the driving transistor.

27. The display panel of claim 1, wherein, In the first transistor, the channel width of the first sub-transistor is less than 20 μm.

28. The display panel of claim 1, wherein, In the first transistor, the first doped region of the active layer of the first sub-transistor is electrically connected to the first source / drain metal electrode through a first connection via, and the second doped region is electrically connected to the second source / drain metal electrode through a second connection via; the distance between the projection of the gate of the first sub-transistor in a direction perpendicular to the plane in which the display panel lies and the projection of the first connection via in the direction perpendicular to the plane in which the display panel lies is greater than or equal to 2.5 μm, and the distance between the projection of the gate of the first sub-transistor in a direction perpendicular to the plane in which the display panel lies and the projection of the second connection via in the direction perpendicular to the plane in which the display panel lies is greater than or equal to 2.5 μm.

29. The display panel of claim 1, wherein, In the first transistor, a distance between active layers of two adjacent first sub-transistors in the second direction is greater than or equal to 2.5 μm. 30.The display panel of claim 1, wherein, The pixel circuit comprises a first light-emitting control transistor, a driving transistor and a second light-emitting control transistor, wherein the first light-emitting control transistor is coupled between the first node and the driving transistor, and the second light-emitting control transistor is coupled between the driving transistor and the second node. The first light-emitting control transistor, the driving transistor and the second light-emitting control transistor are all the first transistors. In the second direction, the driving transistor is located between the second light-emitting control transistor and the first light-emitting control transistor. 31.The display panel of claim 30, wherein, The first light-emitting control transistor is electrically connected with a first light-emitting control signal line extending in the first direction, and the second light-emitting control transistor is electrically connected with a second light-emitting control signal line extending in the first direction. A distance between the first light-emitting control transistor and the first light-emitting control signal line is less than a distance between the first light-emitting control transistor and the second light-emitting control signal line, and a distance between the second light-emitting control signal line and the second light-emitting control signal line is less than a distance between the second light-emitting control transistor and the first light-emitting control signal line. 32.The display panel of claim 31, wherein, The first light-emitting control signal line is electrically connected with a first electrode part extending in the second direction, the first electrode part is multiplexed as a gate electrode of each first sub-transistor in the first light-emitting control transistor, and a width of the first light-emitting control signal line in the second direction is greater than a width of the first electrode part in the first direction. A second electrode part extending in the second direction in the second light-emitting control transistor is electrically connected, the second electrode part is multiplexed as a gate electrode of each first sub-transistor in the second light-emitting control transistor, and a width of the second light-emitting control signal line in the second direction is greater than a width of the second electrode part in the first direction. 33.The display panel of claim 30, wherein, The pixel circuit further has a third node, a fourth node and a fifth node, the first light-emitting control transistor is coupled between the first node and the third node, the driving transistor is coupled between the third node and the fourth node, the second light-emitting control transistor is coupled between the fourth node and the second node, and a gate electrode of the first sub-transistor in the driving transistor is electrically connected with the fifth node. The pixel circuit further comprises a data writing module, a compensation module and an anode reset module, wherein the data writing module is electrically connected with the third node, the compensation module is respectively electrically connected with the fourth node and the fifth node, and the anode reset module is electrically connected with the second node. The anode reset module and the compensation module are located between the second light-emitting control transistor and the driving transistor, and the data writing module is located between the driving transistor and the first light-emitting control transistor. 34.The display panel of claim 33, wherein, The anode reset module comprises an anode reset transistor, a gate electrode of the anode reset transistor is electrically connected with the first scan signal line, a first electrode of the anode reset transistor is electrically connected with a reset signal line, and a second electrode of the anode reset transistor is electrically connected with the second node. The reset signal line is located on a side of the first scan signal line close to the second light-emitting control transistor, the reset signal line is electrically connected with one end of a first wire through a first via, the first wire extends along the second direction, and the other end of the first wire is electrically connected with the first electrode of the anode reset transistor on a side of the first scan signal line away from the reset signal line through a second via, and the second electrode of the anode reset transistor is electrically connected with the second light-emitting control transistor through a third via on a side of the reset signal line away from the first scan signal line. In a direction perpendicular to a plane where the display panel is located, the first wire overlaps an active layer of the anode reset transistor. 35.The display panel of claim 34, wherein, The pixel circuit further comprises a gate reset module, the gate reset module comprises a gate reset transistor, a gate electrode of the gate reset transistor is electrically connected with the first scan signal line, a first electrode of the gate reset transistor is electrically connected with the reset signal line, and a second electrode of the gate reset transistor is electrically connected with the fifth node. The gate reset transistor is located between the second light-emitting control transistor and the driving transistor. The reset signal line is further electrically connected with one end of a second wire through a fourth via, the second wire extends along the second direction, and the other end of the second wire is connected with the first electrode of the gate reset transistor through a fifth via on a side of the first scan signal line away from the reset signal line. In a direction perpendicular to a plane where the display panel is located, the second wire overlaps an active layer of the gate reset transistor. 36.The display panel of claim 35, wherein, The compensation module comprises a compensation transistor, a gate electrode of the compensation transistor is electrically connected with a second scan signal line, a first electrode of the compensation transistor is electrically connected with the fourth node, and a second electrode of the compensation transistor is electrically connected with the fifth node. The first electrode of the compensation transistor is electrically connected with the second light-emitting control transistor through a third wire, the third wire extends along the second direction, and the third wire is disposed in a layer different from the second wire. 37.The display panel of claim 33, wherein, The data writing module is electrically connected with a second scan signal line, and the compensation module is electrically connected with a third scan signal line, wherein the second scan signal line and the third scan signal line transmit the same signal at the same time. The third scan signal line is located between the second light-emitting control transistor and the driving transistor, and the second scan signal line is located between the driving transistor and the first light-emitting control transistor.

38. A display device comprising: The display panel comprises the display panel as claimed in any one of claims 1 to 37.

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