Terminal structure of power semiconductor chip, manufacturing method and power device

Abstract

A terminal structure, manufacturing method and power device of a power semiconductor chip belong to the technical field of semiconductor devices. The terminal structure is located at the edge of a power semiconductor chip and is connected to the active area of ​​the chip; the surface of the terminal structure has a bevel structure, so that the terminal structure part forms a negative angle with the first main surface of the chip; a cut-off ring is formed on the bevel structure part of the terminal, and the cut-off ring is formed on one side of the terminal edge inside the first semiconductor base region, and extends longitudinally to contact the first conductive type semiconductor region. The present invention uses a cut-off ring to extend the planar PN junction that the bevel terminal needs to pass through to the longitudinal structure, so that the preparation process of the bevel terminal structure does not need to strictly consider the junction depth, which increases the process window, improves the process yield, and enhances the device's electric field blocking performance and voltage resistance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a terminal structure and a manufacturing method of a power device and a power device. Background Art

[0002] Power semiconductor devices are an important component of modern power electronic devices and are used to control and convert electrical energy. The terminal structure is a key component of the device and directly determines the blocking performance and reliability of the device. In the design of the terminal structure, the main factors to be considered include the electric field distribution during the conduction and shutdown process, the leakage size, the structural size ratio, etc., to ensure that the device has high withstand voltage, small blocking leakage, and reasonable structure.

[0003] Common terminal structures of power semiconductor devices include bevel terminals, field-limiting ring terminals, step-type gradual-change terminals, composite terminal structures, etc. Among them, the field-limiting ring structure using graphic technology is usually used for discrete devices, such as IGBT, MOSFET, JBS diode and other types of devices; for whole-wafer chips, their terminal structures usually use bevel terminals, such as GTO, IGCT chips, etc., through terminal bevel grinding, etching and other technologies, a circle of bevel rings is prepared at the edge area of ​​the chip terminal, and the processing of this structure is now mature.

[0004] Typical angled terminals are as follows: Figure 1 As shown in the figure, its main working principle is to use the angled shape to widen the depletion region in the P base region (the width of the depletion region changes from WP to WS), thereby reducing the surface electric field and increasing the blocking voltage. Figure 2 As shown in , when subjected to forward blocking voltage, its depletion region expands near the J2 junction; when subjected to reverse blocking voltage, its depletion region expands near the J1 junction, as shown in Figure 3 as shown in .

[0005] Therefore, for high-voltage and ultra-high-voltage thyristor devices, in order to achieve a higher blocking voltage, the device is required to have a deeper P-base junction depth and a lower P-base doping concentration, and the terminal shaping angle θ must be very small. However, the above requirements bring the following problems: (1) For base PN junctions with a larger junction depth, the doping process during the wafer production process is difficult to accurately control the uniformity within and between wafers, that is, the junction depth of the PN junction is not uniform, which leads to the instability of the terminal process of the device. The processed devices have problems such as low yield, large leakage, and substandard blocking in terms of withstand voltage; (2) To achieve a certain withstand voltage, the bevel edge must pass through the second PN junction of the thyristor device, which increases the process accuracy requirements of the bevel and the area proportion of the terminal in the chip.

[0006] The current patent solution is mainly to improve the chip characteristics by using P-base regions with different junction depths in the chip active area and terminal area of ​​thyristor devices. For example, in 2010, ABB of Switzerland proposed a shallow P-base power semiconductor device (CN103222056B), which adopted a negative bevel terminal structure. The terminal P-base region has a deeper junction depth than the active area P-base region, and the concentration is lower than the concentration in the active area. The doping concentration in the terminal area decreases rapidly in the lateral direction compared with the active area, which enhances the avalanche capability and improves the breakdown voltage. Tsinghua University proposed a power semiconductor device (CN111755501A) in 2020, and the patent structure is similar to the ABB patent. However, the proportion of the terminal area of ​​this improved method is still large, and when the junction depth is increased, the uniformity within and between chips during the doping process during the tape-out process is difficult to accurately control, that is, the junction depth of the PN junction is not uniform, which leads to the instability of the terminal process of the device. Therefore, the above-mentioned problems of the terminal area of ​​the chip with the existing patent structure have not been well solved. Summary of the invention

[0007] In view of this, the main purpose of the present invention is to provide a terminal structure of a power device, a manufacturing method and a power device, so as to at least partially solve the above technical problems.

[0008] In order to achieve the above-mentioned purpose, in the first aspect, the present invention adopts a terminal structure of a power semiconductor chip, wherein the terminal structure is located at the edge portion of the power semiconductor chip and connected to the active area of ​​the chip; the terminal structure has at least a first conductive type semiconductor region, and a first semiconductor base region located on one side of the first conductive type semiconductor region, the first semiconductor base region has a second conductive type, and the second conductive type is opposite to the first conductive type; the surface of the first semiconductor base region has a slope structure, so that the terminal structure portion forms a negative angle with the first main surface of the power semiconductor chip; a first cut-off ring is formed in the terminal structure, the first cut-off ring is formed on one side of the first semiconductor base region close to the terminal edge, and extends longitudinally to connect with the first conductive type semiconductor region, the first cut-off ring has a first conductive type.

[0009] In a second aspect, the present invention further provides a power semiconductor chip, wherein the semiconductor device comprises an active region and a terminal region, and the terminal region adopts the terminal structure as described above.

[0010] In a third aspect, the present invention further provides a power semiconductor device comprising the above-mentioned power semiconductor chip, wherein the power semiconductor device is a common thyristor, a phase-controlled thyristor, a gate turn-off thyristor, an integrated gate-commutated thyristor or a derivative device of the above-mentioned devices.

[0011] In a fourth aspect, the present invention further provides a power electronic device, wherein the power electronic device adopts the power semiconductor device as described above, and the power electronic device is a rectifier, an inverter, a frequency converter, a chopper or a circuit breaker.

[0012] In a fifth aspect, the present invention further provides a method for manufacturing the terminal structure of the above-mentioned power semiconductor chip, wherein the cutoff ring structure in the terminal structure is formed by pre-doping and high-temperature driving process.

[0013] In a sixth aspect, the present invention also provides another method for manufacturing a power semiconductor chip terminal structure, wherein the power semiconductor device chip comprises an active region and a terminal region, wherein the terminal region is located at an edge portion of the power semiconductor device chip and is connected to the chip active region; the terminal region has at least one first conductive type semiconductor region, and a first semiconductor base region located on one side of the first conductive type semiconductor region, wherein the first semiconductor base region has a second conductive type, and the second conductive type is opposite to the first conductive type; the preparation of the terminal region comprises the following steps:

[0014] A stop ring pre-doping step: preparing a pre-doping layer required for a stop ring PN junction in a region near the edge of the chip on the surface of the first semiconductor base region of the terminal region, wherein the pre-doping layer has a first conductivity type of doping;

[0015] The stop ring high temperature driving step: using high temperature diffusion technology to drive the pre-doped layer to a depth that allows it to be connected to the semiconductor region of the first conductivity type;

[0016] Chamfering step: forming a slope structure on at least a portion of the first semiconductor base region on the surface of the terminal region.

[0017] In a seventh aspect, the present invention also provides another method for manufacturing a terminal structure of a power semiconductor chip, wherein the power semiconductor device chip comprises an active region and a terminal region, wherein the terminal region is located at an edge portion of the power semiconductor device chip and is connected to the chip active region; the terminal region has at least one semiconductor region of a first conductivity type, and a first semiconductor base region located on one side of the semiconductor region of the first conductivity type, wherein the first semiconductor base region has a second conductivity type, and the second conductivity type is opposite to the first conductivity type; and the preparation of the terminal region comprises the following steps:

[0018] Chamfering step: forming a slope structure on at least a portion of the first semiconductor base region on the surface of the terminal region;

[0019] A stop ring pre-doping step: preparing a pre-doping layer required for a stop ring PN junction in an area near the chip edge on the surface of the first semiconductor base region of the terminal region, wherein the pre-doping layer has a first conductivity type of doping and is formed on a bevel structure portion;

[0020] The step of high temperature driving-in of the stop ring: using high temperature diffusion technology, driving the pre-doped layer to a depth that allows it to be connected to the semiconductor region of the first conductivity type.

[0021] Based on the above scheme, it can be known that the angled terminal structure of the present invention improves the PN junction that the angled edge of the terminal structure must pass through from a planar structure to a longitudinal vertical structure, so that when processing the angled terminal, only the minimum width requirement of the angle needs to be considered to pass through the PN junction, and no larger width grinding and polishing is required. The preparation process of the angled terminal structure does not need to strictly consider the junction depth, which greatly increases the process window, improves the process yield, and enhances the device's blocking electric field performance and voltage resistance. Compared with the prior art, the terminal structure, manufacturing method and power device of the power device of the present invention have the following main beneficial effects:

[0022] (1) The compatibility window between the terminal bevel angle and the PN junction of the chip base region is widened: the application scope of the present invention can cover the batch preparation of PN junctions with uneven junction depth, without considering the problem of excessive deviation of doping depth uniformity caused by high-temperature diffusion process;

[0023] (2) Improving process yield: The terminal process of a device is usually located at the end of the device processing flow, so the yield of the terminal process usually determines the final yield of the device. However, since the window of the through-angle terminal process is very small, many devices do not achieve the designed withstand voltage performance after the terminal process. The present invention can completely solve this problem and greatly improve the yield of the device.

[0024] (3) Reduce process costs: Due to the widening of the process window, there is no need to add too much wafer inspection or process inspection during the terminal bevel processing, which reduces the process cost. At the same time, due to the improvement of yield, the device cost will be further reduced.

[0025] (4) High process stability: The present invention can realize the preparation process through the currently mature semiconductor process and can be used for mass production. Compared with the traditional process, the process stability and uniformity are extremely high;

[0026] (5) Wide scope of application: The present invention can be applied to the integrated design and preparation of other bevel terminal structures, and can be applied to the field of various whole-wafer bevel terminal semiconductor devices such as GTO, GTR, IGCT, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the existing negative bevel terminal structure;

[0028] Figure 2 , 3 It is a schematic diagram of the existing double negative bevel terminal structure;

[0029] Figure 4 A schematic diagram of a cut-off ring structure of a negative bevel terminal according to an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a cut-off ring structure of a double negative bevel terminal according to an embodiment of the present invention;

[0031] Figure 6 It is a schematic diagram of the cut-off ring structure of a double negative bevel terminal according to another embodiment of the present invention;

[0032] Figure 7 A schematic diagram of a cut-off ring structure pre-doping process according to an embodiment of the present invention;

[0033] Figure 8 A schematic diagram of a high-temperature advancement process of a cut-off ring structure according to an embodiment of the present invention;

[0034] Fig.9A This is the carrier concentration distribution diagram of the traditional terminal structure under 8kV blocking voltage;

[0035] Fig. 9B The carrier concentration distribution diagram of the terminal structure of the present invention under 8kV blocking withstand voltage;

[0036] Fig. 10A This is the electric field distribution diagram of the traditional terminal structure under 8kV blocking withstand voltage;

[0037] Fig. 10B This is the electric field distribution diagram of the terminal structure of the present invention under 8kV blocking withstand voltage. DETAILED DESCRIPTION

[0038] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0039] The meanings of some terms in this invention are as follows:

[0040] Positive photoresist: Positive photoresist is also called positive photoresist. Positive photoresist is a phenolic formaldehyde called linear phenolic resin, which provides the adhesion and chemical resistance of the photoresist. When there is no dissolution inhibitor, the linear phenolic resin will dissolve in the developer to obtain the desired pattern, in which the photosensitive agent is a photosensitive compound.

[0041] Negative photoresist: Negative photoresist, also known as photoresist, is a light-sensitive mixed liquid composed of three main components: photosensitive resin, sensitizer (see spectral sensitizing dye) and solvent.

[0042] Graphical process: a process that uses mask lithography, printing, laser printing, etching and other technologies to transfer the designed graphics to the target surface. In the semiconductor field, it usually refers to lithography, etching, corrosion and other processes to transfer the designed graphics from the photomask to the wafer surface.

[0043] PN junction: A structure formed by the contact between a P-type semiconductor and an N-type semiconductor, which has unidirectional conductivity.

[0044] Figure 4 The chip structure of a thyristor device according to one embodiment of the present invention is exemplarily shown. In terms of shape and structure, the device structure of the present invention is similar to the structure of a conventional thyristor device. The chip includes a chip active area and a chip terminal area. The chip active area has a chip thickness measured between the first main surface and the second main surface. The chip terminal area is located at the edge of the chip, surrounds the chip active area and is connected to the chip active area.

[0045] In the terminal area of ​​the chip, the surface of the chip is a bevel structure, that is, a surface of the chip in the terminal area forms at least one first angle with the plane where the first main surface is located, so that the chip thickness decreases at a negative bevel angle at least on the first main surface.

[0046] In some exemplary embodiments, the slope structure formed in the terminal region may extend from the vicinity of the connection between the chip terminal region and the active region to the edge of the chip, so that the chip thickness decreases in the terminal region as the distance to the chip active region increases.

[0047] In other exemplary embodiments, the inclined surface structure formed in the terminal area may include a first inclined surface and a second inclined surface, wherein the first inclined surface is close to the active area of ​​the chip, one end of the second inclined surface is connected to the first inclined surface, and the other end extends to the edge of the chip; the second inclined surface forms a second angle with the first main surface of the chip, and the angle of the second angle is greater than the first angle.

[0048] like Figure 4 As shown, in some embodiments, the chip has at least a first P+ region 101, a first P base region 102, and an N-drift region 103 from top to bottom; the inclined surface structure is at least formed on the surface of the first P base region 102. In the technical solution of the present invention, the difference from the traditional type of thyristor is that a first cut-off ring structure 106 is formed at the edge of the terminal region (i.e., the side away from the chip active region).

[0049] Specifically, the cut-off ring structure 106 is formed on one side of the first P-base region 102 near the terminal edge, and extends vertically downward to contact the N-drift region 103. In the case of this embodiment, the cut-off ring has an opposite doping type to the first P-base region 102, that is, the cut-off ring is N-type doped. Thus, the PN junction that the angled edge of the terminal structure must pass through is improved from a planar structure to a vertical structure.

[0050] Preferably, the doping concentration of the cut-off ring is higher than the doping concentration of the N-drift region; further, the doping concentration of the cut-off ring is preferably more than 5 times higher than the doping concentration of the N-drift region.

[0051] Preferably, the cut-off ring structure is formed by pre-doping and then high-temperature advancement. In this embodiment, the N-type doping width of the cut-off ring after high-temperature advancement should not affect the terminal width as much as possible; therefore, preferably, the pre-doping width should be less than 5% of the junction interface depth, and the cut-off ring width finally formed should be less than or equal to one-quarter of the terminal area width.

[0052] Preferably, the cutoff depth needs to be greater than or equal to the junction interface depth;

[0053] Preferably, the stop ring extends into the N-drift region 103 .

[0054] Optionally, the cutoff ring has a distance s from the edge of the chip.

[0055] like Figure 5 As shown, in other embodiments, the chip has a double negative bevel terminal structure. Similar to the above embodiment, the chip has at least a first P+ region 201, a first P base region 202, an N-drift region 203, a second P base region 204 and a second P+ region 205 from top to bottom. The difference is that, in the terminal region of the chip, the bevel structure is formed at least on the upper surface of the first P base region 202 and the lower surface of the second P base region 204. At the edge of the terminal region (i.e., the side away from the active area of ​​the chip), a first stop ring structure 206 and a second stop ring structure 207 are formed;

[0056] The first stop ring structure 206 is formed on one side of the first P base region 202 near the terminal edge, and extends vertically downward to contact the N-drift region 203; the second stop ring structure 207 is formed on one side of the second P base region 204 near the terminal edge, and extends vertically upward to contact the N-drift region 203. Although the embodiment shows a symmetrical layer structure, those skilled in the art can know that, according to the type of different periods, the upper and lower layer structures may also be asymmetrical, which is not limited here.

[0057] like Figure 6As shown, in other embodiments, the chip has an angled structure with different inclinations at the terminal portion. Similar to the above embodiment, the chip has at least a first P+ region 301, a first P base region 302, an N-drift region 303, a second P base region 304, and a second P+ region 305 from top to bottom. The difference is that in the terminal region of the chip, the inclined surface structure is divided into two parts: a first inclined surface 310 and a second inclined surface 320; wherein the first inclined surface is close to the chip active area and forms a first angle α with the first main surface of the chip. 1 One end of the second inclined surface is connected to the first inclined surface, and the other end extends to the edge of the chip; the second inclined surface forms a second angle α with the first main surface of the chip 2 , the second angle is greater than the first angle.

[0058] Optionally, the third inclined surface 330 and the fourth inclined surface 340 may be formed on the lower surface of the chip in the same manner.

[0059] Preferably, the first stop ring structure 306 is formed in a region corresponding to the second inclined surface 320 in the first P base region 302 ; and the second stop ring structure 307 is formed in a region corresponding to the fourth inclined surface 340 in the second P base region 304 .

[0060] In the above embodiment, a PNPN chip structure is used as an example, however, the N-type or P-type doping is not a limitation of the present invention, and those skilled in the art can understand that each layer structure in the example can also have completely opposite conductivity types. In addition, NPN and PNP structures are also possible.

[0061] Figure 7-8 The present invention is shown Figure 5 The intermediate state of the partial preparation process of the structure shown in FIG. Figure 5 Taking the embodiment shown as an example, the preparation method may optionally include the following steps:

[0062] R1) Surface treatment of wafer terminal area:

[0063] Specifically, wafer materials include silicon, silicon carbide, gallium nitride, gallium arsenide, other III-IV compounds, etc. Wafer surface inspection and processing should fully consider whether there are defects, edge collapse, cracks and other factors that affect device performance, as well as pollutants, dust, particles, protective layers and metal layers remaining on the wafer surface that affect subsequent terminal processes;

[0064] Optionally, the size of the semiconductor substrate may be 2-16 inches.

[0065] Optionally, the surface treatment method includes organic cleaning, wet etching, ultrasonic cleaning, RCA cleaning, decontamination, drying after cleaning and other process methods.

[0066] Optionally, after cleaning, surface detection is performed; surface detection methods include optical microscopic detection, terminal doping concentration detection, etc.

[0067] Preferably, in order to ensure the subsequent chamfering process, no metal or the like should exist in the terminal area.

[0068] R2) Pre-doping of cut-off ring:

[0069] Specifically, based on the cut-off ring structure design, a pre-doped layer required for the cut-off ring PN junction is prepared in the outermost area of ​​the wafer terminal surface. The schematic diagram after this step is shown in the attached figure. Figure 7 ;

[0070] Optionally, the doping element is a Group V element such as phosphorus, arsenic, antimony, etc., preferably phosphorus.

[0071] Optionally, the pre-doping process includes ion implantation, pre-deposition, local doping source diffusion and other techniques.

[0072] Optionally, the depth of the pre-doping process is 0.5-10 μm, and the pre-doping concentration is 1E15-9.99E20 / cm 2 , the unevenness requirement is ≤10%.

[0073] Preferably, in order to ensure that the N-type doping width of the cut-off ring after high-temperature advancement does not affect the terminal width, the pre-doping width should be less than 5% of the junction interface depth.

[0074] Optionally, the patterning process in the pre-doping process also includes the preparation of a pre-doping masking layer, a photolithography mask required for patterning the masking layer, patterning etching of the masking layer, removal of the photolithography mask, pre-doping process, removal of the masking layer, surface cleaning and other process processes.

[0075] R3) High temperature advancement of the cut-off ring:

[0076] Specifically, the stop ring pre-doping layer prepared in step R2) is advanced to a desired depth using a high temperature diffusion technique;

[0077] Preferably, the driving depth of the pre-doped layer reaches the penetration of the N-drift region of the underlying chip structure. Figure 8 , the driving depth can be further extended into the N-drift region.

[0078] Necessarily, the N-type doping width of the cut-off ring after high-temperature advancement should not affect the terminal width as much as possible, and its doping concentration should be higher than the doping concentration of the N-Drift region.

[0079] R4) Chamfering steps:

[0080] Specifically, based on the structural design parameters, a fixed-angle rotary grinding and polishing process is used to grind the terminal surface area into the required bevel structure, including bevel width, bevel angle, bevel structure shape, such as double bevel, etc. The schematic diagram of the structure after chamfering is shown in the attached figure. Figure 5 As shown;

[0081] Necessarily, during the bevel grinding and polishing process, a polishing granular liquid needs to be added, wherein the particle size can be selected according to the surface polishing roughness during the grinding and polishing process.

[0082] Optionally, the rotation rate during grinding and polishing etc. needs to be developed according to the structural shape and the bevel surface pressure during chamfering.

[0083] Optionally, the angle control error during the chamfering process should be ≤5%, and the bevel width error should be ≤10%.

[0084] Preferably, the width of the chamfered bevel terminal should be ensured not to exceed the outside of the transition area between the chip active area and the terminal area.

[0085] In particular, for steps R2, R3) and R4), if some doping elements are difficult to diffuse deeply or the high-temperature diffusion process of the cut-off ring doping affects the structure of the chip active area, a chamfering process can be used first to prepare a bevel terminal, and then a deep junction injection process can be used to prepare a cut-off ring at the outer edge of the bevel. Preferably, the injection depth is recommended to form a connection with the underlying N-Drift area.

[0086] Optionally, for a terminal with multiple bevel angles or multiple table structures, multiple chamfering processes are required; for example, two chamfering processes may be performed to form a terminal with multiple bevel angles or multiple table structures. Figure 6 The multi-segment inclined structure shown.

[0087] R5) Flattening of angled surfaces:

[0088] Specifically, it includes flattening the terminal bevel surface after grinding and polishing in step R4) to reduce the surface roughness and improve the flatness of the bevel surface, so as to improve the electric field buffering capacity during the blocking process;

[0089] Optionally, the surface planarization process method includes surface immersion etching, flushing etching, spin etching, grinding, cleaning, etc.

[0090] Preferably, the roughness of the bevel surface needs to be reduced to below 10 nm.

[0091] R6) Terminal bevel surface passivation process: Specifically, a layer of passivation medium is prepared on the surface after the treatment in step R5) for surface protection, surface leakage reduction, etc.

[0092] Optionally, the preparation process of the passivation dielectric layer may be an oxidation process, a LPCVD process, a PECVD process, a TEOS process, etc.

[0093] Optionally, the material of the passivation dielectric layer may be silicon dioxide, silicon nitride, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, DLC film, or the like.

[0094] Optionally, the thickness of the passivation dielectric layer is greater than 0.1 μm, and the thickness non-uniformity is required to be ≤5%.

[0095] Optionally, the preparation process may also include preparation of a passivation dielectric layer, a patterning process of the passivation dielectric layer, etc.

[0096] It is understandable that both the negative bevel terminal structure and the double negative bevel terminal structure shown above are exemplary. When actually applied to thyristor devices, their actual structures may be different, such as ordinary thyristors (Silicon Controlled Rectifier, SCR; also known as Thyristor), phase-controlled thyristors (Phase controlled thyristor, PCT), gate turn-off thyristors (GTO), integrated gate-commutated thyristors (IGCT) conventional structures. For example, thyristor devices all contain a 4-layer PNPN structure, and a buffer layer and other structures can be introduced into the device structure according to differences such as whether reverse blocking characteristics are required. In some cases, it is also applicable to other whole wafer devices and large-size wafer devices suitable for adopting bevel terminal molding technology.

[0097] Fig.9A , 9B 10A and 10B respectively show the carrier concentration distribution of the conventional structure and the terminal structure of the present invention under a blocking withstand voltage of 8 kV, and the electric field distribution of the conventional structure and the terminal structure of the present invention under a blocking withstand voltage of 8 kV.

[0098] Compared with the traditional structure, the terminal structure of the present invention has a cut-off ring structure, and the depletion region of the carrier concentration is controlled inside the cut-off ring structure, which effectively limits the leakage phenomenon of the depletion region extending at the edge of the terminal; and optimizes the electric field distribution, eliminating the concentration effect of the electric field at the edge;

[0099] The comparison of carrier concentration and electric field distribution shows that the structure can effectively reduce the terminal width. Taking the above simulation example, under the condition of 8kV blocking withstand voltage, the terminal width can be reduced by more than 10% and the leakage current can be reduced by more than 37%.

[0100] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A terminal structure of a power semiconductor chip, characterized in that: The terminal structure is located at the edge of the power semiconductor chip and is connected to the active area of ​​the chip; the terminal structure has at least a first conductive type semiconductor region and a first semiconductor base region located on one side of the first conductive type semiconductor region, the first semiconductor base region has a second conductive type, and the second conductive type is opposite to the first conductive type; the surface of the first semiconductor base region has a slope structure, so that the terminal structure part forms a negative angle with the first main surface of the power semiconductor chip; a first cut-off ring is formed in the terminal structure, the first cut-off ring is formed on one side of the first semiconductor base region close to the terminal edge, and extends longitudinally to connect with the first conductive type semiconductor region, the first cut-off ring has a first conductive type.

2. The terminal structure of the power semiconductor chip according to claim 1, characterized in that: The terminal structure also includes a second semiconductor base region located on the other side of the first conductive type semiconductor region. In the terminal structure, an inclined structure is formed only on the surface of the first semiconductor base region and the first main surface of the power semiconductor chip, and a planar structure is formed on the second main surface side relative to the first main surface.

3. The terminal structure of the power semiconductor chip according to claim 1, characterized in that: The terminal structure also includes a second semiconductor base region located on the other side of the first conductive type semiconductor region, and in the terminal structure, a slope structure is also formed on the surface of the second semiconductor base region and the second main surface of the power semiconductor chip; a second cut-off ring is formed on one side of the second semiconductor base region close to the terminal edge and extends longitudinally to connect with the first conductive type semiconductor region, and the second cut-off ring has the first conductive type.

4. The terminal structure of a power semiconductor chip according to any one of claims 1 to 3, characterized in that: The doping concentration of the first and / or second cutoff ring is higher than the doping concentration of the first conductive type semiconductor region.

5. The terminal structure of a power semiconductor chip according to any one of claims 1 to 3, characterized in that: The width of the first and / or second stop ring does not exceed one quarter of the width of the terminal structure; and / or, The first and / or second cutoff ring further extends into the first conductive type semiconductor region; and / or, The doping concentration of the first and / or second cutoff ring is more than 5 times higher than that of the first conductive type semiconductor region.

6. The terminal structure of a power semiconductor chip according to any one of claims 2 to 3, characterized in that: The bevel structure of the first semiconductor base region includes a first bevel region and a second bevel region, wherein the first bevel region is close to the chip active region and forms a first angle α1 with the first main surface of the chip; one end of the second bevel region is connected to the first bevel region, and the other end extends to the edge of the chip; the second bevel forms a second angle with the first main surface of the chip, and the second angle is greater than the first angle; and / or The bevel structure of the second semiconductor base region includes a third bevel region and a fourth bevel region, wherein the third bevel region is close to the chip active area and forms a first angle with the second main surface of the chip; one end of the fourth bevel region is connected to the third bevel region, and the other end extends to the edge of the chip; the fourth bevel region forms a second angle with the second main surface of the chip, and the second angle is greater than the first angle.

7. The terminal structure of a power semiconductor chip according to any one of claims 1 to 3, characterized in that: The first conductivity type is N type, and the second conductivity type is P type; or the first conductivity type is P type, and the second conductivity type is N type.

8. The terminal structure of a power semiconductor chip according to claim 2 or 3, characterized in that: The first conductive type semiconductor region is an N-type drift region; the first semiconductor base region is a P-base region, and the second semiconductor base region is a P-base region.

9. The terminal structure of a power semiconductor chip according to claim 2 or 3, characterized in that: The first conductive type semiconductor region is an N-type drift region; the first semiconductor base region is a P base region, and the second semiconductor base region is a P base region; it also includes a first P+ region located on one side of the first semiconductor base region, and a second P+ region on one side of the second semiconductor base region.

10. A power semiconductor chip, characterized in that: The semiconductor device including the power semiconductor chip comprises an active area and a terminal area, and the terminal area adopts the terminal structure as described in any one of claims 1-9.

11. A power semiconductor device comprising the power semiconductor chip according to claim 10, characterized in that: The power semiconductor device is a common thyristor, a phase-controlled thyristor, a gate turn-off thyristor, an integrated gate-commutated thyristor or a derivative device of the above devices.

12. A power electronic device, characterized in that: The power electronic device adopts the power semiconductor device as claimed in claim 11, and the power electronic device is a rectifier, an inverter, a frequency converter, a chopper or a circuit breaker.

13. A method for manufacturing a terminal structure of a power semiconductor chip according to any one of claims 1 to 9, characterized in that: The first and / or second cut-off rings in the terminal structure are formed by pre-doping and high-temperature driving processes.

14. A method for manufacturing a power semiconductor chip, wherein the power semiconductor chip comprises an active region and a terminal region, wherein the terminal region is located at the edge of the power semiconductor chip and is connected to the chip active region; wherein the terminal region has at least a first conductive type semiconductor region and a first semiconductor base region located on one side of the first conductive type semiconductor region, wherein the first semiconductor base region has a second conductive type, and the second conductive type is opposite to the first conductive type; wherein: The preparation of the terminal region comprises the following steps: A stop ring pre-doping step: preparing a pre-doping layer required for a stop ring PN junction in a region near the edge of the chip on the surface of the first semiconductor base region of the terminal region, wherein the pre-doping layer has a first conductivity type of doping; The stop ring high temperature driving step: using high temperature diffusion technology to drive the pre-doped layer to a depth that allows it to be connected to the semiconductor region of the first conductivity type; Chamfering step: forming a slope structure on at least a portion of the first semiconductor base region on the surface of the terminal region.

15. A method for manufacturing a power semiconductor chip, wherein the power semiconductor chip comprises an active region and a terminal region, wherein the terminal region is located at the edge of the power semiconductor chip and is connected to the chip active region; the terminal region has at least a first conductive type semiconductor region and a first semiconductor base region located on one side of the first conductive type semiconductor region, wherein the first semiconductor base region has a second conductive type, and the second conductive type is opposite to the first conductive type; characterized in that: The preparation of the terminal region comprises the following steps: Chamfering step: forming a slope structure on at least a portion of the first semiconductor base region on the surface of the terminal region; A stop ring pre-doping step: preparing a pre-doping layer required for a stop ring PN junction in a region near the chip edge on the surface of the first semiconductor base region of the terminal region, wherein the pre-doping layer has a first conductivity type of doping and is formed on a slope structure portion; The step of high temperature driving-in of the stop ring: using high temperature diffusion technology, driving the pre-doped layer to a depth that allows it to be connected to the semiconductor region of the first conductivity type.

16. The method for manufacturing a power semiconductor chip according to claim 14, wherein: Before the stop ring pre-doping step, a terminal region surface treatment step is also included; After the chamfering step, the method further includes a planarization step of the bevel surface and a passivation step of the bevel surface.

17. The method for manufacturing a power semiconductor chip according to claim 15, characterized in that: Before the chamfering step, a terminal area surface treatment step is also included; After the stop ring high temperature driving step, the method further includes a bevel surface flattening step and a bevel surface passivation step.

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