A solar cell device

Abstract

The application discloses a solar cell device, and relates to the technical field of new energy cells, which comprises a silicon wafer, a tunneling oxide layer and a doped conductive layer which are sequentially arranged in a stack, the two sides of the silicon wafer are defined as a first side and a second side, the tunneling oxide layer is arranged on the second side of the silicon wafer, and the doped conductive layer is arranged on a layer of the tunneling oxide layer which is far away from the silicon wafer; the solar cell device further comprises a first passivation layer and a second passivation layer, the first passivation layer is arranged on the first side of the silicon wafer, the second passivation layer is arranged outside the first passivation layer, and the thickness of the part of the second passivation layer which is close to at least one side perpendicular to the first side of the silicon wafer is greater than the thickness of the part of the second passivation layer which is far away from the side perpendicular to the first side of the silicon wafer. The application has the beneficial effect that by changing the thickness and the refractive index of the silicon nitride on the two sides of the silicon wafer, the occurrence of the recombination phenomenon of the solar cell wafer is effectively reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new energy batteries, and more particularly to a solar cell device. BACKGROUND

[0002] With the development of the photovoltaic industry, improving the conversion efficiency of solar cells has also become the goal pursued by photovoltaic enterprises. In order to achieve high efficiency of solar cells, people design various cell structures, among which, the tunnel oxide passivated contact (TOPCon) technology is to prepare an ultra-thin tunnel oxide layer and a highly doped polysilicon thin layer on the back of the cell to form a passivated contact structure, which has the advantages of high efficiency, long life, no LID and good weak light response.

[0003] In existing solar cells, double-sided solar cells greatly improve the photoelectric conversion efficiency of the cell per unit area because they can utilize double-sided light absorption. Therefore, they are increasingly attracting attention from all walks of life. However, due to the need for cutting silicon wafers during production and manufacturing of solar cells, damage will occur in the edge region, and in the actual use process, the damage region will produce recombination phenomenon, affecting the performance of the cell.

[0004] How to reduce the occurrence of recombination phenomenon in the edge region of the solar cell is a problem that needs to be solved. SUMMARY

[0005] The summary section of the present application is used to introduce the concepts in a brief form, which will be described in detail in the specific embodiments section. The summary section of the present application is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions.

[0006] Some embodiments of the present application propose a solar cell device to solve the technical problems mentioned in the background section.

[0007] As a first aspect of the present application, some embodiments of the present application provide a solar cell device, comprising: a silicon wafer, a tunnel oxide layer and a doped conductive layer which are sequentially stacked, defining two sides of the silicon wafer as a first side and a second side, the tunnel oxide layer is arranged on the second side of the silicon wafer, and the doped conductive layer is arranged on the layer away from the silicon wafer, the solar cell device further comprises a first passivation layer and a second passivation layer, the first passivation layer is arranged on the first side of the silicon wafer, and the second passivation layer is arranged outside the first passivation layer, the thickness of the part of the second passivation layer close to at least one side perpendicular to the first side of the silicon wafer is greater than the thickness of the part of the second passivation layer away from the side perpendicular to the first side of the silicon wafer.

[0008] Further, a second passivation layer is disposed on the side of the doped conductive layer away from the tunneling oxide layer.

[0009] Further, the second passivation layer disposed on the side of the doped conductive layer away from the tunneling oxide layer has a thickness of the portion close to the side of the doped conductive layer greater than that of the portion away from the side of the doped conductive layer.

[0010] Further, the second passivation layer disposed on the side of the doped conductive layer away from the tunneling oxide layer has a thickness of the portion close to the side of the doped conductive layer greater than that of the portion away from the side of the doped conductive layer.

[0011] Further, the second passivation layer disposed on the side of the doped conductive layer away from the tunneling oxide layer has a thickness of the portion close to the side of the doped conductive layer greater than that of the portion away from the side of the doped conductive layer.

[0012] Further, the second passivation layer disposed on the side of the doped conductive layer away from the tunneling oxide layer has a thickness of the portion close to the side of the doped conductive layer greater than that of the portion away from the side of the doped conductive layer.

[0013] Further, the second passivation layer disposed on the side of the doped conductive layer away from the tunneling oxide layer has a thickness of the portion close to the side of the doped conductive layer greater than that of the portion away from the side of the doped conductive layer.

[0014] Further, the first passivation layer is aluminum oxide.

[0015] Further, the second passivation layer is silicon nitride.

[0016] Further, the second passivation layer is a plurality of silicon nitride film layers stacked together.

[0017] Further, the first side of the silicon wafer is provided with a textured structure configured to have a pyramid shape.

[0018] Further, an emitter is disposed between the first side of the silicon wafer and the first passivation layer.

[0019] Further, the doped conductive layer is a polysilicon layer.

[0020] Further, the doped conductive layer is a stacked structure of a plurality of polysilicon layers.

[0021] Further, the solar cell further comprises a front electrode and a back electrode, the front electrode and the back electrode are respectively disposed on the two sides of the silicon wafer.

[0022] Further, the back electrode is a silver electrode; and / or, the front electrode is a silver electrode or an aluminum electrode.

[0023] Further, the solar cell further comprises two metal electrodes, the two metal electrodes are disposed on the second side of the silicon wafer.

[0024] The application has the beneficial effect that by changing the thickness and refractive index of the silicon nitride on both sides of the silicon wafer, the recombination phenomenon of the solar cell wafer is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which form a part of this application, are intended to provide further understanding of the application and are incorporated herein in their entirety, and they are intended to explain the application further and to make the other features, objects and advantages of the application more apparent. The illustrative embodiments of the drawings and their descriptions serve to explain the present application, and do not constitute an undue limitation on the scope of the present application.

[0026] In addition, throughout the drawings, same or similar reference numerals are used to represent same or similar elements. It should be understood that the drawings are schematic, and the elements and elements are not necessarily drawn according to the scale.

[0027] In the drawings:

[0028] Figure 1 is a structural schematic diagram of a solar cell wafer device according to an embodiment of the present application;

[0029] Figure 2 is a structural schematic diagram of a solar cell wafer device according to an embodiment of the present application, in which the thickened area in the second passivation layer is a whole-thickened silicon nitride structure;

[0030] The meanings of the specific reference numerals in the drawings are as follows:

[0031] 100, silicon wafer;

[0032] 200, tunneling oxide layer;

[0033] 300, doped conductive layer;

[0034] 400, first passivation layer;

[0035] 500, second passivation layer;

[0036] 600, emitter. DETAILED DESCRIPTION

[0037] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes, and are not intended to limit the scope of protection of the present disclosure.

[0038] In addition, it needs to be noted that only parts related to the present application are shown in the drawings for the convenience of description. The embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0039] It should be noted that the concepts of “first”, “second”, and the like mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0040] It should be noted that the modification of “one” or “multiple” mentioned in the present disclosure is illustrative and not restrictive, and those skilled in the art should understand that unless the context clearly indicates otherwise, it should be understood as “one or more”.

[0041] The names of the messages or information exchanged between the plurality of devices in the embodiments of the present disclosure are only for illustrative purposes, and are not used to limit the scope of the messages or information.

[0042] The present disclosure will be described in detail below with reference to the drawings and in conjunction with embodiments.

[0043] As shown in Figure 1 and Figure 2 An embodiment of the solar cell device of the present application comprises: a silicon wafer 100, a tunneling oxide layer 200 and a doped conductive layer 300 arranged in sequence, defining the first side and the second side of the silicon wafer 100, the tunneling oxide layer 200 is arranged on the second side of the silicon wafer 100, the doped conductive layer 300 is arranged on the layer of the tunneling oxide layer 200 away from the silicon wafer 100, the solar cell device further comprises a first passivation layer 400 and a second passivation layer 500, the first passivation layer 400 is arranged on the first side of the silicon wafer 100, the second passivation layer 500 is arranged outside the first passivation layer 400, the thickness of the part of the second passivation layer 500 close to at least one side perpendicular to the first side of the silicon wafer 100 is greater than the thickness of the part of the second passivation layer 500 away from the side perpendicular to the first side of the silicon wafer 100.

[0044] In an implementable embodiment, the solar cell device is a TOPCon structure cell, and the TOPCon structure cell has an emitter 600, a silicon wafer 100, a tunneling oxide layer 200 and a doped conductive layer 300 arranged in sequence from the top surface to the bottom surface. In the present application, the terms “top” and “bottom”, “top surface” and “bottom surface”, or “bottom” and “top”, or “front surface” and “back surface” refer to the direction from the light-receiving front surface to the back surface of the solar cell, and the part close to the light-receiving front surface is called “top”, and the part close to the back surface is called “bottom”.

[0045] Specifically, the tunneling oxide layer 200 is arranged on the second surface of the silicon wafer 100, i.e. the side of the silicon wafer 100 close to the bottom surface. The tunneling oxide layer 200 is arranged on the back surface of the silicon wafer 100 to provide good surface passivation for the back surface of the silicon wafer 100. The tunneling oxide layer 200 can enable multi-carriers (electrons) to tunnel into the doped conductive layer 300 while blocking the recombination of minority carriers (holes), and then the multi-carriers are laterally transported in the doped conductive layer 300 and collected by the metal, thereby greatly reducing the metal contact recombination current, improving the open-circuit voltage and short-circuit current of the battery, and depositing a layer of metal as an electrode to achieve a passivated contact structure without the need for opening holes.

[0046] The tunneling oxide layer 200 is a silicon oxide layer, which utilizes the quantum tunneling effect to enable electrons to pass through smoothly and prevent the recombination of holes. The full-area passivation surface eliminates the silicon / metal contact interface, which is beneficial to improving the open-circuit voltage Voc. The full-area carrier collection reduces the lifetime sensitivity and is beneficial to improving the fill factor FF. The blocking of minority carriers while the easy passage of multi-carriers can reduce recombination. The carrier recombination on the surface of the silicon wafer 100 can be inhibited, the minority carrier lifetime of the silicon wafer 100 and the open-circuit voltage of the battery can be improved, and the carrier selection and collection passivated contact structure can be applied to the full surface of the battery without the need for opening holes to form a local passivated contact. This not only simplifies the manufacturing process, but also enables the carrier to only perform one-dimensional transport without additional lateral transport, thereby achieving a higher fill factor.

[0047] The doped conductive layer 300 is a polysilicon layer, and the doped conductive layer 300 is a stack structure of a plurality of polysilicon layers. Polysilicon is deposited on the ultra-thin silicon oxide tunneling layer, and phosphorus doping of the polysilicon is performed using a pulsed laser. Then, a silicon nitride anti-reflection layer is deposited on the back surface of the silicon wafer 100 by plasma-enhanced chemical vapor deposition, and the doped conductive layer 300 is a stack structure of a plurality of polysilicon layers.

[0048] In one specific embodiment, the solar cell wafer device further comprises a first passivation layer 400 and a second passivation layer 500, wherein the first passivation layer 400 is aluminum oxide and the second passivation layer 500 is silicon nitride. The aluminum oxide can effectively improve the battery efficiency, and the key factor that restricts the further improvement of the efficiency of the traditional crystalline silicon (c-Si) solar cell is the carrier recombination loss at the interface between the metal electrode and the silicon wafer 100, which causes the Jo load current to be too high.

[0049] Since the silicon wafer 100 is prone to recombination at the edge area during the production process, affecting the electrical performance of the battery, the use of aluminum oxide can to some extent reduce the occurrence of recombination, that is, to increase the thickness of the aluminum oxide in part of the area of the battery, but the area coated with aluminum oxide will have a white color performance, if the method of simply increasing the thickness of the aluminum oxide can to some extent reduce the occurrence of recombination, but at the same time it will also bring another problem, that is, the color difference of the battery wafer surface with thick aluminum oxide and thin aluminum oxide and no aluminum oxide will be too obvious, which may cause a large number of battery wafer appearance defects.

[0050] Therefore, the present application adopts another method to reduce the occurrence of battery recombination. Specifically, the second passivation layer 500 is provided outside the first passivation layer 400, and the thickness of the second passivation layer 500 near the side surface perpendicular to the first surface of the silicon wafer 100 is greater than the thickness of the second passivation layer 500 away from the side surface perpendicular to the first surface of the silicon wafer 100. That is, the thickness of the second passivation layer 500 near the edge of the silicon wafer 100 is thickened, and the second passivation layer 500 is silicon nitride, and the thickened silicon nitride can increase the passivation effect at the edge of the silicon wafer 100, thereby effectively reducing the occurrence of recombination. That is, the thickness of the second passivation layer 500 on the side of the doped conductive layer 300 away from the tunnel oxide layer 200 is greater near the side of the doped conductive layer 300 than away from the side of the doped conductive layer 300. Specifically, the thickness ratio of the thicker region to the thinner region of the second passivation layer 500 provided outside the first passivation layer 400 is in the range of 103% to 150%. The thickened region of the second passivation layer 500 can be a whole thickened silicon nitride structure (as shown in Figure 2 , or can be a multi-layer silicon nitride film stacked (as shown in Figure 1 ).

[0051] In a specific embodiment, the thickness of the second passivation layer 500 on the side of the doped conductive layer 300 away from the tunnel oxide layer 200 is 90.9 nm away from the side of the doped conductive layer 300, and the thickness of the second passivation layer 500 on the side of the doped conductive layer 300 away from the tunnel oxide layer 200 is 94-100 nm near the side of the doped conductive layer 300. The thickness of the second passivation layer 500 on the side of the doped conductive layer 300 away from the tunnel oxide layer 200 is 79.5 nm away from the side of the doped conductive layer 300, and the thickness of the second passivation layer 500 on the side of the doped conductive layer 300 away from the tunnel oxide layer 200 is 88-96 nm near the side of the doped conductive layer 300.

[0052] The ratio of the thickness of the thicker region to the thickness of the thinner region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is in the range of 103% to 150%. For example, the edge of the thickness of the thinner region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is 76.9 nm, the edge of the thickness of the thicker region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is 86.8-110.6 nm, the edge of the thickness of the thinner region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is 80.3 nm, and the edge of the thickness of the thicker region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is 83.9-103.7 nm.

[0053] Further, while the edge of the silicon wafer 100 is thickened, a SiN layer with a slightly higher refractive index (increasing the silicon content of the film layer) can also be deposited to improve the passivation effect. The ratio of the refractive index of the thicker region to the refractive index of the thinner region of the second passivation layer 500 disposed outside the first passivation layer 400 is in the range of 100.5% to 104%, and the ratio of the refractive index of the thicker region to the refractive index of the thinner region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is in the range of 100.5% to 104%. Specifically, the refractive index of the silicon wafer 100 is 1.823 for a region 10 mm away from the edge towards the center, and the refractive index of the silicon wafer 100 is 1.834-1.893 for a region 10 mm or less from the edge towards the center. The refractive index of the silicon wafer 100 is 1.834 for a region 10 mm away from the edge towards the center, and the refractive index of the silicon wafer 100 is 1.840-1.905 for a region 10 mm or less from the edge towards the center.

[0054] Similarly, the ratio of the refractive index of the thicker region to the refractive index of the thinner region of the second passivation layer 500 disposed on one side of the doped conductive layer 300 is in the range of 100.5% to 104%. Specifically, the refractive index of the silicon wafer 100 is 2.089 for a region 10 mm away from the edge towards the center, and the refractive index of the silicon wafer 100 is 2.095-2.158 for a region 10 mm or less from the edge towards the center. The refractive index of the silicon wafer 100 is 2.102 for a region 10 mm away from the edge towards the center, and the refractive index of the silicon wafer 100 is 2.108-2.171 for a region 10 mm or less from the edge towards the center.

[0055] In one embodiment, the solar cell is produced in two forms. In one form, the solar cell is produced as a whole unit. The second passivation layer 500 is thicker near the portions of the four sides perpendicular to the first side of the silicon wafer 100 than the portions away from the four sides. In another form, the solar cell is produced as two units that are joined together. The two units are produced separately and joined together to form a complete solar cell. In this form, the second passivation layer 500 near the first side and the second side of the portion to be joined does not need to vary in thickness. The second passivation layer 500 is thicker near the portions of the three sides perpendicular to the first side of the silicon wafer 100 than the portions away from the three sides. The two units are joined together to form a complete solar cell. The production efficiency is improved and the transportation of the solar cell is facilitated.

[0056] In one embodiment, a tube or plate PECVD is used to deposit the anti-reflective layer on the front side of the silicon wafer 100. The anti-reflective layer on the front side is one or a combination of SiNx, SiOxNy, and SiOx, and has a thickness of 70-150 nm. A tube or plate PECVD is used to deposit the anti-reflective layer on the back side of the silicon wafer 100. The anti-reflective layer on the back side is one or a combination of SiNx, SiOxNy, and SiOx, and has a thickness of 70-150 nm.

[0057] In one embodiment, the first passivation layer and the second passivation layer or one of the first passivation layer and the second passivation layer are also provided in the edge region of the solar cell. The moisture and heat resistance of the solar cell is improved. The attenuation of the solar cell caused by ultraviolet light is reduced. The carrier lifetime of the solar cell caused by the bare edge is reduced.

[0058] In one specific embodiment, the solar cell piece further comprises a front electrode and a back electrode, which are respectively arranged on two sides of the silicon piece 100. The back electrode is a silver electrode. The front electrode is a silver electrode or an aluminum electrode. The front and back electrodes are printed and sintered with Ag paste, and the front Ag paste electrode is treated with light-assisted micro-guiding; after the Ag paste is printed on the front and back of the silicon piece 100 and sintered, the back Ag paste forms a good ohmic contact with the N-type phosphorus-doped polycrystalline silicon layer. The metal electrodes are screen-printed or sintered on the front and back of the silicon piece 100, and the above electrode material configuration can obtain better conductivity and connection tension between the electrodes and the silicon piece 100, thereby improving the conductivity effect and the structural stability of the cell.

[0059] The solar cell piece can further comprise two metal electrodes arranged on the same side, which are arranged on the second surface of the silicon piece 100. That is, the solar cell piece covers not only the TOPCon cell structure, but also a back contact type solar cell device, a P+ region and an N+ region, and a metal electrode in contact with the P+ region and the N+ region to form a cell device on the second surface of the silicon piece 100.

[0060] In one specific embodiment, the silicon piece 100 is an N-type monocrystalline silicon, and the N-type silicon substrate does not have boron-oxygen recombination when exposed to light, which to some extent reduces the case of light-induced degradation and thermal-assisted light-induced degradation. An emitter 600 is arranged between the first surface of the silicon piece 100 and the first passivation layer 400. The emitter 600 is a P-type emitter 600 formed by diffusing boron elements into the silicon piece 100 to form a P+ layer, thereby forming a PN junction.

[0061] More specifically, the top surface of the silicon piece 100 also has a textured structure. In one feasible embodiment, a copper metal catalytic etching method is used to form a pyramid-shaped textured structure on the top surface of the silicon piece 100. The pyramid textured structure has a certain angle with the incident angle of sunlight, so that the reflected sunlight can enter the cell interior again, thereby increasing the amount of sunlight entering the cell interior. According to the light trapping principle, when light is incident at a certain angle of inclination, the light will be reflected to another angle of inclination, forming secondary or multiple absorption, thereby increasing the light absorption rate, and ultimately improving the photoelectric conversion efficiency of the cell.

[0062] The above description is merely exemplary of some of the many possible embodiments of the present disclosure and of the principles thereof. It is to be understood that those skilled in the art will be able to devise various embodiments of the present disclosure without departing from the scope of the present disclosure as disclosed in the above description and attached claims, and that the scope of the present disclosure is not limited to the specific technical features described above. For example, the technical features described above can be replaced with other technical features with similar functions disclosed in the embodiments of the present disclosure (but not limited to) to form other technical solutions.

Claims

1. A solar cell device, characterized in that, The battery is a TOPCon battery, comprising: A silicon wafer, a tunneling oxide layer, and a doped conductive layer are stacked sequentially. The two sides of the silicon wafer are defined as a first side and a second side, respectively. The tunneling oxide layer is disposed on the second side of the silicon wafer, and the doped conductive layer is disposed on a layer away from the silicon wafer from the tunneling oxide layer. The solar cell device also includes a first passivation layer and a second passivation layer. The first passivation layer is disposed on the first side of the silicon wafer, and the second passivation layer is disposed outside the first passivation layer. The thickness of the second passivation layer near at least one side perpendicular to the first side of the silicon wafer is greater than the thickness of the portion away from the side of the silicon wafer. A second passivation layer is provided on the side of the doped conductive layer away from the tunneling oxide layer. The thickness of the second passivation layer on the side of the doped conductive layer away from the tunneling oxide layer is greater than the thickness of the portion of the passivation layer away from the side of the doped conductive layer. The ratio of the thickness of the thicker region to the thickness of the thinner region of the second passivation layer disposed outside the first passivation layer ranges from 103% to 150%. The ratio of the thickness of the thicker region to the thickness of the thinner region of the second passivation layer disposed on one side of the doped conductive layer ranges from 103% to 150%. The ratio of the refractive index of the thicker region to the refractive index of the thinner region of the second passivation layer disposed outside the first passivation layer ranges from 100.5% to 104%. The ratio of the refractive index of the thicker region to the refractive index of the thinner region of the second passivation layer disposed on one side of the doped conductive layer ranges from 100.5% to 104%.

2. The solar cell device according to claim 1, characterized in that, The first passivation layer is aluminum oxide.

3. The solar cell device according to claim 1, characterized in that, The second passivation layer is silicon nitride.

4. The solar cell device according to claim 3, characterized in that, The second passivation layer is composed of multiple layers of silicon nitride film stacked together.

5. The solar cell device according to any one of claims 1 to 4, characterized in that, The first side of the silicon wafer has a textured surface structure configured in a pyramid shape.

6. The solar cell device according to claim 5, characterized in that, An emitter is provided between the first side of the silicon wafer and the first passivation layer.

7. The solar cell device according to any one of claims 1 to 4, 6, characterized in that, The doped conductive layer is a polycrystalline silicon layer.

8. The solar cell device according to claim 7, characterized in that, The doped conductive layer is a stacked structure of complex polycrystalline silicon layers.

9. The solar cell device according to any one of claims 1 to 4, 6, and 8, characterized in that, It also includes a front electrode and a back electrode, which are respectively disposed on both sides of the silicon wafer.

10. The solar cell device according to claim 9, characterized in that, The back electrode is a silver electrode; and / or, the front electrode is a silver electrode or an aluminum electrode.

11. The solar cell device according to claim 10, characterized in that, It also includes two metal electrodes disposed on the second side of the silicon wafer.

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