A secure access method and device based on PassID
By introducing the matching mechanism of PassID tag and bridge decoder module in the chip, the problem of the complexity of security access permission configuration in the existing technology is solved, and a simple and easy-to-use secure access method is realized, reducing design difficulty and saving bus resources .
Patent Information
- Application Number
- CN202410736467.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-06
- Publication Date
- 2024-12-20
- Estimated Expiration
- 2044-06-06
AI Technical Summary
In the prior art, Trust Zone technology and FlexNOC systems have problems with low complexity and ease of use in chip secure access rights control, especially in the process of security access rights configuration and decoding of devices and buses, which require users to write manually. Code and follow specific timing protocols, resulting in high design difficulty and poor versatility.
Using a PassID-based secure access method and device, the configuration and processing of secure access rights are realized by configuring PassID tags for each master and slave device in the bus interconnection architecture, and judging and matching PassID tags with the bridge decoder module, and the configuration and processing of secure access rights are reduced. The difficulty of module design is simplified and bus resource management is simplified.
It realizes a simple and easy secure access register configuration, reduces the chip design area, supports different register definition methods and CPU processing address mapping, ensures access rights of DDR, bootrom and bootRam, and rationally utilizes storage space and address space.
Smart Images
Figure CN118627091B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip security, and in particular to a PassID-based secure access method and device. Background Art
[0002] Trust Zone technology provides chip-level protection and isolation for hardware resources and has been widely used in the chip field. Figure 1 In order to control the processor's access to hardware resources in different states, ARM has expanded the AXI (Advanced Extensible Interface) system bus. On the basis of the original AXI bus, an additional control signal AWPROT or ARPROT is added to each read and write channel to indicate whether the current read and write operation is a safe operation or a non-safe operation. Among them, AWPROT represents the bus write transaction control signal, a low level is a safe write transaction, and a high level is a non-safe write transaction. ARPROT is the bus read transaction control signal, a low level is a safe read transaction, and a high level is a non-safe read transaction. When a device makes a read or write transaction request to the bus, it must send this control signal to the bus. The bus determines whether it can read and write based on this signal and the world to which the CPU currently belongs, preventing non-safe programs / devices from reading and writing safe devices.
[0003] In the prior art, taking FlexNOC developed by Arterist as an example, it contains a Firmwall address and memory, but requires users to manually write code, the address configuration method is relatively complicated, and it is also necessary to follow the manufacturer's IP-specific timing protocol, so it is less usable and less versatile. Summary of the invention
[0004] The purpose of this application is to provide a PassID-based security access method and device, aiming to reduce the difficulty of security module design by configuring access rights through registers.
[0005] According to a first aspect of the present application, a PassID-based secure access method is provided, comprising:
[0006] A PassID tag is configured for each master device and slave device in the bus interconnection architecture. When the first master device initiates an access request to a target slave device, the access request is received through a bridge decoder module to determine whether the PassID tag of the target slave device is modified by the CPU.
[0007] If the PassID tag of the target slave device has not been modified by the CPU, the PassID tag of the first master device is transparently transmitted to the target slave device through the bridge decoder module; if the PassID tag of the target slave device has been modified by the CPU, the PassID tag of the target slave device is parsed through the bridge decoder module;
[0008] The PassID tag of the first master device is matched with the PassID tag of the target slave device, and the access request is processed based on the matching result.
[0009] In an optional implementation manner, processing the access request based on the matching result further includes:
[0010] If the PassID tag of the first master device is a pre-agreed value, the target slave device allows read and write access and returns data to the first master device.
[0011] In an optional implementation manner, processing the access request based on the matching result further includes:
[0012] If the PassID tag of the first master device is consistent with the PassID tag of the target slave device, the target slave device allows access and returns data to the first master device.
[0013] In an optional implementation, if the PassID tag of the first master device is not a pre-agreed value and the PassID tag of the first master device is inconsistent with the PassID tag of the target slave device, the target slave device does not allow access and returns an error message to the first master device.
[0014] In an optional implementation, the security attributes of the bridge decoder module are configured by the CPU and security attribute encryption module of the secure world.
[0015] According to a second aspect of the present application, a PassID-based secure access device is provided, comprising:
[0016] an access request receiving unit, configured to configure a PassID tag for each master device and slave device in the bus interconnection architecture, and when a first master device initiates an access request to a target slave device, receive the access request and determine whether the PassID tag of the target slave device is modified by the CPU;
[0017] a tag parsing unit, configured to transparently transmit the PassID tag of the first master device to the target slave device through the bridge decoder module if the PassID tag of the target slave device has not been modified by the CPU, and to parse the PassID tag of the target slave device through the bridge decoder module if the PassID tag of the target slave device has been modified by the CPU;
[0018] A matching unit is used to match the PassID tag of the first master device with the PassID tag of the target slave device, and process the access request based on the matching result.
[0019] Compared with the related art, the technical solution of the present application has at least the following advantages:
[0020] A simple and easy method for securely accessing registers is implemented by utilizing the existing register interconnection bus structure. Access rights are flexibly configured through registers, and the agreed encoding and decoding protocols are kept confidential, which reduces the difficulty of module design, saves bus resources, reduces the design area of the chip, and supports different register definition methods and CPU address mapping methods to achieve DDR access and bootrom, bootRam access, and rationally utilize storage space and address space.
[0021] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained through the structures and processes indicated in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. It is obvious that the drawings described below are certain embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figure 1 It is an AXI bus interconnection architecture diagram based on related technology.
[0024] Figure 2 4 is a flow chart of a PassID-based secure access method according to an exemplary embodiment of the present application.
[0025] Figure 3 It is a bridging topology diagram of master and slave devices according to an exemplary embodiment of the present application.
[0026] Figure 4 and 5It is a schematic diagram of the PassID-based access process according to an exemplary embodiment of the present application.
[0027] Figure 6 4 is a flowchart of determining write access rights according to an exemplary embodiment of the present application.
[0028] Figure 7 4 is a flowchart of determining read access rights according to an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0030] In the bus interconnection architecture, some slave devices (Slaver) do not use the bus with secure access function of the AXI v4 or APB4 (Advanced Peripheral Bus) protocol, which may lead to leakage when different master devices (Master) access the registers used to control the secret key. Based on the above analysis, the present application provides a secure access method and device based on PassID. According to the security national secret requirements, after internal negotiation, the Master carries the specified PassID to access different Slavers. Slaver can be a device that stores secret keys, such as DDR, BOOTROM and BOOTRAM. PassID comes from the security attributes of the access bus carried by the Master itself or configured by the CPU and security attribute encryption module (security) of the secure world. PassID is used as a mark to distinguish the secure world from the non-secure world. If a Slaver can be accessed without any PassID match, the Slaver is called the non-secure world. If it is matched by PassID, the Slaver is determined to be the secure world. In other words, if Figure 3 As shown, the Slaver parses the PassID signal sent by the Master. If the PassID of the Master matches the PassID of the Slaver, it is determined to be a secure access. If they do not match, it is determined to be an unsecure access and no response is made.
[0031] See also Figure 2 The PassID-based secure access method provided by the present application includes:
[0032] Step 101: configure a PassID tag for each master device and slave device in the bus interconnection architecture. When the first master device initiates an access request to a target slave device, the access request is received through a bridge decoder module to determine whether the PassID tag of the target slave device is modified by the CPU.
[0033] For example, Figure 4 As shown, a PassID tag is marked for each Master and Slaver, and the access rights of each master are set in the address decoding module.
[0034] The CPU sets the PassID of each slaver and the transparent transmission attribute of Bridge decode in the Bridge decode module. Bridge decode parses the PassID and sets the PassID to a pre-agreed value based on the access rights configured by the CPU. The transparent transmission attribute can be set to directly transparently transmit the passID to the slave without parsing it in Bridge decode. The slave directly parses and determines whether the master can access it.
[0035] Step 102: If the PassID tag of the target slave device has not been modified by the CPU, the PassID tag of the first master device is transparently transmitted to the target slave device through the bridge decoder module; if the PassID tag of the target slave device has been modified by the CPU, the PassID tag of the target slave device is parsed through the bridge decoder module.
[0036] For example, Figure 5 As shown, the Bridge decoder module Bridge decode determines whether the CPU modifies the PassID of each Slaver, thereby determining whether to parse the PassID sent by the Master or to transparently pass the PassID to the Slaver for parsing and judgment. The security attributes of Bridge decode can be configured by the CPU and security module of the secure world. The security attributes may include the Slaver's passID configurable by the secure CPU, or the access rights to the Slaver device.
[0037] If the CPU does not modify the PassID of each Slaver, the Bridge decode module transparently transmits the PassID carried by the Master to each Slaver, and each Slaver parses and determines whether the Master can access the Slaver.
[0038] If the CPU has modified the PassID of each Slaver, the Bridge decode module parses the PassID configured by the CPU to determine whether the Master can access the Slaver.
[0039] Step 103: Match the PassID tag of the first master device with the PassID tag of the target slave device, and process the access request based on the matching result.
[0040] Each Slaver or Bridge decode module determines whether the Master can access the Slaver based on the Master's PassID and the Slaver's PassID.
[0041] For example, see Figure 6 and Figure 7 If PassID is a pre-agreed value, it means that Slaver allows read and write access and returns normal data. Otherwise, Slaver determines whether the PassID of Master is consistent with its own PassID: if they are consistent, it also means that Slaver allows access; if they are inconsistent, Slaver does not allow access and returns error ERR with empty data.
[0042] In summary, the PassID-based secure access method provided by this application has at least the following advantages over related technologies:
[0043] The existing register interconnection bus structure is used to implement a simple and easy method for securely accessing registers. Access rights are flexibly configured through registers to keep the agreed encoding and decoding protocols confidential, which reduces the difficulty of module design, saves bus resources, reduces the design area of the chip, and supports different register definition methods and CPU address mapping methods to achieve DDR access and bootrom, bootRam access (each memory, peripheral interface and register space can be used as a slave device). Access rights to different DDR storage space addresses can be configured through access rights or passID, so as to make rational use of storage space and address space.
[0044] Accordingly, the present application provides a PassID-based secure access device in a second aspect, comprising:
[0045] an access request receiving unit, configured to configure a PassID tag for each master device and slave device in the bus interconnection architecture, and when a first master device initiates an access request to a target slave device, receive the access request and determine whether the PassID tag of the target slave device is modified by the CPU;
[0046] a tag parsing unit, configured to transparently transmit the PassID tag of the first master device to the target slave device through the bridge decoder module if the PassID tag of the target slave device has not been modified by the CPU, and to parse the PassID tag of the target slave device through the bridge decoder module if the PassID tag of the target slave device has been modified by the CPU;
[0047] A matching unit is used to match the PassID tag of the first master device with the PassID tag of the target slave device, and process the access request based on the matching result.
[0048] The above-mentioned device can be implemented by the PassID-based secure access method provided by the embodiment of the first aspect above. The specific implementation method can be found in the description of the embodiment of the first aspect, which will not be repeated here.
[0049] It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above embodiments according to the use requirements, and should not limit the concept of the present application to the specific details of the above examples.
[0050] Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that he or she may still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A secure access method based on PassID, characterized in that: include: A PassID tag is configured for each master device and slave device in the bus interconnection architecture. When the first master device initiates an access request to a target slave device, the access request is received through a bridge decoder module to determine whether the PassID tag of the target slave device is modified by the CPU. If the PassID tag of the target slave device has not been modified by the CPU, the PassID tag of the first master device is transparently transmitted to the target slave device through the bridge decoder module; if the PassID tag of the target slave device has been modified by the CPU, the PassID tag of the target slave device is parsed through the bridge decoder module; matching the PassID tag of the first master device with the PassID tag of the target slave device, and processing the access request based on the matching result; The processing of the access request based on the matching result further includes: If the PassID tag of the first master device is a pre-agreed value, the target slave device allows read and write access and returns data to the first master device; If the PassID tag of the first master device is consistent with the PassID tag of the target slave device, the target slave device allows access and returns data to the first master device.
2. The PassID-based secure access method according to claim 1, characterized in that: Also includes: If the PassID tag of the first master device is not a pre-agreed value, and the PassID tag of the first master device is inconsistent with the PassID tag of the target slave device, the target slave device does not allow access and returns error information to the first master device.
3. The PassID-based secure access method according to claim 1, characterized in that: The security attributes of the bridge decoder module are configured by the CPU of the secure world and the security attribute encryption module.
4. A secure access device based on PassID, characterized in that: include: an access request receiving unit, configured to configure a PassID tag for each master device and slave device in the bus interconnection architecture, and when a first master device initiates an access request to a target slave device, receive the access request and determine whether the PassID tag of the target slave device is modified by the CPU; a tag parsing unit, configured to transparently transmit the PassID tag of the first master device to the target slave device through a bridge decoder module if the PassID tag of the target slave device has not been modified by the CPU, and to parse the PassID tag of the target slave device through the bridge decoder module if the PassID tag of the target slave device has been modified by the CPU; a matching unit, configured to match the PassID tag of the first master device with the PassID tag of the target slave device, and process the access request based on the matching result; The matching unit is further used for: If the PassID tag of the first master device is a pre-agreed value, the target slave device allows read and write access and returns data to the first master device; If the PassID tag of the first master device is consistent with the PassID tag of the target slave device, the target slave device allows access and returns data to the first master device.
5. The PassID-based secure access device according to claim 4, characterized in that: The matching unit is further used for: If the PassID tag of the first master device is not a pre-agreed value, and the PassID tag of the first master device is inconsistent with the PassID tag of the target slave device, the target slave device does not allow access and returns error information to the first master device.
6. The PassID-based secure access device according to claim 4, characterized in that: The security attributes of the bridge decoder module are configured by the CPU of the secure world and the security attribute encryption module.