A self-aligned t-gate gan high frequency device and method of fabrication

Abstract

The application relates to a self-aligned T-shaped gate GaN high-frequency device and a preparation method thereof, which comprises the following steps: obtaining an epitaxial wafer; growing a first dielectric layer on a barrier layer; etching the first dielectric layer of a gate region to expose the upper surface of the barrier layer to form a gate window; growing a second dielectric layer in the gate window exposing the channel layer and on the barrier layer; etching part of the second dielectric layer and the first dielectric layer directly below the second dielectric layer to expose the barrier layer to form two active region areas; performing ion implantation in the active region areas to form ion implantation areas, and then performing annealing treatment to form an ohmic contact; growing a first dielectric layer on the barrier layer, the ion implantation areas and the T-shaped second dielectric layer; removing the T-shaped second dielectric layer to prepare a T-shaped gate electrode on the gate window and the first dielectric layer; removing the first dielectric layer at the active region areas, and then growing a source electrode and a drain electrode on the ion implantation areas. The application improves the alignment precision between the metal line and the semiconductor, improves the manufacturing precision of the device, and has superior performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor high-frequency devices, and in particular to a self-aligned T-gate GaN high-frequency device and a preparation method thereof. Background Art

[0002] The original purpose of the invention of self-aligned technology was to address the problem of overlapping regions between the gate and source / drain electrodes caused by overlay errors in the photolithography machine during the fabrication of semiconductor transistors. This caused overlap capacitance between the gate electrode and the source / drain electrodes, which seriously affected the electrical performance of the transistor. The key to the self-aligned process is to first grow a hard mask in the gate area and then dope the source and drain electrodes to avoid the overlap capacitance caused by overlay errors in the photolithography.

[0003] Gate self-alignment technology has evolved to its current state through several key stages, the most important of which was the discovery that heavily doped polysilicon was conductive enough to replace aluminum. This key discovery meant that gate growth could be inserted at any step in the overall manufacturing process. In the self-aligned process, the gate material is deposited on top of the insulating layer, and then the source and drain are doped (in the case of polysilicon, the gate is doped at the same time). Since the source-drain overlap region only represents the outer edges of the source and drain, and the inner edges of these parts are masked by the gate itself, the source and drain can be "self-aligned" to the gate. Since they are always in perfect position, there is no need to make the gate wider than expected, and parasitic capacitance is greatly reduced.

[0004] After early experiments with various gate materials, including aluminum, molybdenum, and amorphous silicon, the semiconductor industry ultimately adopted self-aligned gates made of polycrystalline silicon, known as silicon-gate technology (SGT), which offers numerous additional benefits in terms of reducing parasitic capacitance. Among MOS transistor parasitic capacitances, the gate overlap capacitance, Cgd, is the most significant factor affecting device performance. According to the well-known Miller effect, Cgd multiplied by the gain of the circuit in which the transistor resides increases the transistor's gate-source capacitance. This significantly reduces transistor switching speeds. Another key feature of SGT is that the transistor is completely buried beneath a high-quality thermal oxide (one of the best known insulators), further broadening the possibilities for researchers to create novel device structures.

[0005] In essence, self-aligned gate technology ensures that the gate is naturally and precisely aligned with the edges of the source and drain. The use of self-aligned gates in MOS transistors was one of the key innovations that led to the dramatic increase in computing power in the 1970s. Unlike conventional MOS transistors, the fabrication process for high-electron-mobility transistors (HEMTs) requires high-temperature annealing to achieve N-type doping. However, metal gates cannot withstand the high temperatures of annealing, making self-alignment impossible in HEMT devices. Summary of the Invention

[0006] In order to solve the above problems existing in the prior art, the present invention provides a self-aligned T-gate GaN high-frequency device and a preparation method. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] A method for preparing a self-aligned T-gate GaN high-frequency device, the method comprising:

[0008] Step 1: Obtain an epitaxial wafer, wherein the epitaxial wafer includes, from bottom to top, a stacked substrate layer, a composite buffer layer, a channel layer, and a barrier layer;

[0009] Step 2: using a mesa etching method to etch away a portion of the channel layer and the barrier layer in the end region to achieve mesa isolation;

[0010] Step 3: growing a first dielectric layer on the barrier layer;

[0011] Step 4: etching the first dielectric layer in the gate region until the upper surface of the barrier layer is exposed to form a gate window;

[0012] Step 5: growing a second dielectric layer in the gate window exposing the channel layer and on the barrier layer, wherein the corrosion resistance of the second dielectric layer is less than that of the first dielectric layer;

[0013] Step 6: etching a portion of the second dielectric layer and the first dielectric layer directly below the second dielectric layer to expose the barrier layer to form two active regions, leaving a T-shaped second dielectric layer and the first dielectric layer below the T-shaped second dielectric layer;

[0014] Step 7: performing ion implantation in the active region to form an ion implantation region, and then performing annealing to form an ohmic contact;

[0015] Step 8: growing a first dielectric layer on the barrier layer, the ion implantation region and the T-shaped second dielectric layer;

[0016] Step 9: removing the T-shaped second dielectric layer to prepare a T-shaped gate electrode on the gate window and the first dielectric layer;

[0017] Step 10: remove the first dielectric layer in the active area, and then grow a source electrode and a drain electrode on the ion implantation area.

[0018] In one embodiment of the present invention, the material of the substrate layer includes any one of silicon, sapphire, silicon carbide, diamond, and glass single crystal substrate layer;

[0019] The composite buffer layer includes, from bottom to top, a stacked AlN nucleation layer, an AlGaN transition layer, and a buffer layer. The thickness of the AlN nucleation layer is 100-300 nm, the thickness of the AlGaN transition layer is 200-1000 nm, the material of the buffer layer includes GaN or AlGaN, and the thickness of the buffer layer is 100-3000 nm.

[0020] The material of the channel layer includes GaN or InGaN, and the thickness of the channel layer is 50nm-500nm;

[0021] The material of the barrier layer includes AlGaN, InAlN, AlN or InAlGaN, and the thickness of the barrier layer is 2-40 nm.

[0022] In one embodiment of the present invention, step 2 includes:

[0023] The first dielectric layer is deposited and grown on the surface of the barrier layer by adopting LPCVD technology.

[0024] In one embodiment of the present invention, the first dielectric layer includes a silicon nitride dielectric layer, and the second dielectric layer includes a silicon dioxide dielectric layer.

[0025] In one embodiment of the present invention, growing a second dielectric layer in the gate window exposing the channel layer and on the barrier layer comprises:

[0026] A second dielectric layer is grown in the gate window exposing the channel layer and on the barrier layer using PECVD technology.

[0027] In one embodiment of the present invention, ion implantation is performed in the active region to form an ion implantation region, comprising:

[0028] An ion implantation method is adopted to implant Si ions into the active region through an ion implanter to form an ion implantation region.

[0029] In one embodiment of the present invention, before step 9, the method further includes:

[0030] The first dielectric layer is polished by using a CMP polishing technology.

[0031] In one embodiment of the present invention, removing the T-shaped second dielectric layer includes:

[0032] The T-shaped second dielectric layer is removed using HF or BOE solution.

[0033] In one embodiment of the present invention, the materials of the bottom two layers of the source electrode and the drain electrode include Ti / Al, Ta / Al or Mo / Al, and the material of the bottom first layer of the gate electrode includes Ti, Ni, Al, Ta, TiN or TaN.

[0034] In one embodiment of the present invention, the GaN high-frequency device is manufactured using the manufacturing method described in any one of the above embodiments, and the GaN high-frequency device includes:

[0035] substrate layer;

[0036] a composite buffer layer, the composite buffer layer being disposed on the substrate layer;

[0037] a channel layer, the channel layer being disposed on the composite buffer layer;

[0038] a barrier layer, the barrier layer being disposed on the channel layer;

[0039] a source electrode, a drain electrode and a T-shaped gate electrode, wherein the source electrode, the drain electrode and the gate electrode are all disposed on the barrier layer, and the gate electrode is located between the source electrode and the drain electrode;

[0040] A passivation layer is provided on the source electrode, the drain electrode and the barrier layer.

[0041] Compared with the prior art, the present invention has the following beneficial effects:

[0042] First, the GaN high-frequency device fabricated by this invention enhances relevant electrical performance, reducing the contact resistance between the metal wire and the semiconductor, thereby improving device performance and operating speed. By avoiding the problem of overlap capacitance, this invention allows for further control of the distance between the metal electrode and the source and drain electrodes, thereby increasing the channel length and, consequently, the device's operating voltage. The gate self-alignment process improves the alignment accuracy between the metal wire and the semiconductor, enhancing device manufacturing precision and resulting in superior performance.

[0043] 2. Compared with traditional manufacturing methods, the gate self-alignment process with a T-type gate structure can increase reliability: the self-alignment process can reduce the contact resistance between the metal wire and the semiconductor, thereby reducing the thermal effect of the device and improving the reliability of the device.

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic flow chart of a method for preparing a self-aligned T-gate GaN high-frequency device provided by an embodiment of the present invention;

[0046] Figure 2a-2j This is a schematic flow chart of a method for preparing a self-aligned T-gate GaN high-frequency device provided by an embodiment of the present invention;

[0047] Figure 3 It is a structural schematic diagram of a self-aligned T-gate GaN high-frequency device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0049] Example 1

[0050] See Figure 1 、 Figure 2a-2j , Figure 1 1 is a flow chart of a method for preparing a self-aligned T-gate GaN high-frequency device provided by an embodiment of the present invention. Figure 2a-2j The present invention provides a method for preparing a self-aligned T-gate GaN high-frequency device. The method comprises:

[0051] Step 1. Please refer to Figure 2a , obtaining an epitaxial wafer, which includes, from bottom to top, a stacked substrate layer 1, a composite buffer layer 2, a channel layer 3 and a barrier layer 4.

[0052] Specifically, first, a substrate layer is selected and the surface of the substrate layer is cleaned, and then a composite buffer layer, a channel layer and a barrier layer are grown in sequence on the substrate layer using epitaxial technology.

[0053] Furthermore, the material of the substrate layer includes any one of silicon, sapphire, silicon carbide, diamond, and glass single crystal substrate layer;

[0054] The composite buffer layer includes, from bottom to top, a stacked AlN nucleation layer, an AlGaN transition layer, and a buffer layer. The thickness of the AlN nucleation layer is 100-300 nm, the thickness of the AlGaN transition layer is 200-1000 nm, the material of the buffer layer includes GaN or AlGaN, and the thickness of the buffer layer is 100-3000 nm.

[0055] The material of the channel layer includes GaN or InGaN, and the thickness of the channel layer is 50nm-500nm;

[0056] The material of the barrier layer includes AlGaN, InAlN, AlN or InAlGaN, and the thickness of the barrier layer is 2-40 nm.

[0057] Step 2: Please refer to Figure 2b The mesa etching method is used to etch away part of the channel layer and the barrier layer in the end area to achieve mesa isolation.

[0058] Step 3: growing a first dielectric layer 5 on the barrier layer.

[0059] Specifically, the first dielectric layer is deposited and grown on the surface of the barrier layer using LPCVD (Low Pressure Chemical Vapor Deposition) technology.

[0060] Optionally, the first dielectric layer includes a silicon nitride dielectric layer.

[0061] Step 4, see Figure 2c , etching the first dielectric layer in the gate region to expose the upper surface of the barrier layer to form a gate window.

[0062] Specifically, a preliminary gate window is etched on the first dielectric layer using RIE equipment, and a photoresist layer such as AZ5214, AZ6112, or SF6 is used as a mask to protect portions that do not need to be etched during the etching process.

[0063] Step 5. Please refer to Figure 2d A second dielectric layer 6 is grown in the gate window exposing the channel layer and on the barrier layer. The corrosion resistance of the second dielectric layer 6 is lower than that of the first dielectric layer 5 .

[0064] Specifically, a second dielectric layer is grown in the gate window exposing the channel layer and on the barrier layer using PECVD (Plasma Enhanced Chemical Vapor Deposition) technology.

[0065] Optionally, the second dielectric layer includes a silicon dioxide dielectric layer.

[0066] Step 6, see Figure 2e , etching a portion of the second dielectric layer and the first dielectric layer directly below the second dielectric layer to expose the barrier layer to form two active regions, retaining a T-shaped second dielectric layer and the first dielectric layer below the T-shaped second dielectric layer.

[0067] Specifically, a corresponding photoresist is used to etch out windows in the source and drain active regions. Specifically, a resist mask is used to make windows in the active region, and RIE etching equipment is used to etch out windows in the active region that directly reach the surface of the barrier layer.

[0068] Step 7, see Figure 2f , ion implantation is performed in the active area to form an ion implantation region, and then annealing is performed to form an ohmic contact.

[0069] Specifically, an ion implantation method is used to implant Si ions into the active region using an ion implanter to form an ion implantation region 7 , and then an annealing process is performed to form an ohmic contact.

[0070] Step 8. Please refer to Figure 2g A first dielectric layer 5 is grown on the barrier layer, the ion implantation region, and the T-shaped second dielectric layer.

[0071] In this example, see Figure 2h After the first dielectric layer 5 is grown, it is polished using a CMP (Chemical Mechanical Polishing) process to smoothen the surface of the epitaxial wafer where the dielectric gate exists, which is beneficial for the subsequent growth of the metal gate electrode.

[0072] In this embodiment, a new silicon nitride dielectric layer is grown on the silicon dioxide dielectric layer to maintain the etched T-shaped gate shape. If the silicon nitride layer is not regrown, the gate trench remaining after the silicon dioxide dielectric is washed away with BOE will be a conventional stripe gate. After metal growth, the resulting gate will also be a conventional gate, not a T-shaped gate. This allows the formation of a T-shaped gate electrode.

[0073] Step 9, see Figure 2i and Figure 2j , removing the T-shaped second dielectric layer to form a T-shaped groove to prepare a T-shaped gate electrode 10 on the gate window and the first dielectric layer.

[0074] Specifically, HF or BOE solution is used to remove the T-shaped second dielectric layer, and the silicon nitride dielectric layer grown using LPCVD has a much stronger ability to resist corrosion from HF or BOE solution than the silicon dioxide dielectric layer. Therefore, only the silicon dioxide dielectric layer can be removed, and the silicon nitride dielectric layer is retained. The present invention has confirmed through experiments that the growth quality and BOE corrosion resistance of the dielectric layer formed by the LPCVD growth process are significantly stronger than those of the dielectric layer grown by the PECVD process. The reasons are as follows: 1. LPCVD is a low-pressure chemical vapor deposition that can grow silicon nitride films at relatively high pressures, making the silicon nitride film microstructure denser and having good chemical inertness and corrosion resistance. 2. The LPCVD growth process can greatly reduce the growth rate of the silicon nitride dielectric layer through parameter control, and the formed film has better chemical stability and mechanical strength.

[0075] A gate window is formed by photolithography using a resist mask, and a gate metal layer is grown using an ei-5z metal growth device. A metal lift-off process is performed using an acetone and isopropyl alcohol solution to form a gate electrode 10, which is then subjected to high-temperature annealing at 400°C with a nitrogen flow rate of 1 m / s.

[0076] Optionally, the material of the bottom first layer of the gate electrode includes Ti, Ni, Al, Ta, TiN or TaN.

[0077] Step 10: remove the first dielectric layer in the active area, and then grow the source electrode 8 and the drain electrode 9 on the ion implantation area.

[0078] Specifically, the metal gate electrode is used as a mask and RIE equipment is used to etch the entire epitaxial wafer, thereby removing the silicon nitride dielectric layer in the ion implantation area, and then the source electrode 8 and the drain electrode 9 are grown.

[0079] Optionally, the materials of the bottom two layers of the source electrode and the drain electrode include Ti / Al, Ta / Al or Mo / Al.

[0080] There have always been two technical routes for gate manufacturing, namely the so-called "gate first" and "gate last" problems, that is, when making metal electrodes, should the source and drain ohmic contact electrodes be made first or the gate electrode be made first. Since the annealing temperature required for ohmic resistors is relatively high and the gate electrode cannot withstand it, the mainstream device manufacturing process uses the "gate last" route, that is, first making the ohmic metal and completing the annealing before making the gate electrode. This has caused some technical problems: the distance between the source and drain areas in the device layout used in digital circuits is very small (reducing the source-drain distance itself is also the only way to miniaturize the device). First of all, this increases the difficulty in overlay and increases the chance of errors in multiple overlays. Once the overlay accuracy is not enough, it is easy for the gate and source to overlap. Overlapping metal electrode layers will cause geometric parasitic capacitance and edge capacitance of the device. The so-called self-aligned process, or the "gate-first" process, is based on growing the gate first and then using the finished gate as part of the mask for the source and drain regions. For example, in the present invention, a dielectric gate is first made, and the silicon dioxide dielectric gate can naturally protect the area under the gate that belongs to the gate metal electrode. This area will not be implanted with silicon ions, and thus no source and drain active region will be formed. In principle, this avoids the overlap of the source and gate metal electrodes caused by overlay errors, improves alignment accuracy, and reduces the additional resistance caused by metal overlap. By avoiding metal overlap of the gate and source electrodes, the self-aligned technology facilitates further reducing the source-drain distance and shortening the conductive channel length.

[0081] Therefore, the present invention improves the relevant electrical performance of the device, reduces the contact resistance between the metal wire and the semiconductor, and thus improves the performance and operating speed of the device. Since the problem of overlapping capacitance is avoided, the present invention provides a possibility for further controlling the distance between the metal electrode and the source and drain, thereby increasing the channel length and thereby increasing the operating voltage of the device. The gate self-alignment process improves the alignment accuracy between the metal wire and the semiconductor, improves the device manufacturing accuracy, and has more superior performance. Compared with traditional manufacturing methods, the gate self-alignment process with a T-type gate structure can increase reliability: the self-alignment process can reduce the contact resistance between the metal wire and the semiconductor, thereby reducing the thermal effect of the device and improving the reliability of the device.

[0082] Example 2

[0083] See Figure 3 , Figure 3 Schematic diagram of the structure of a self-aligned T-gate GaN high-frequency device provided by an embodiment of the present invention. The present invention provides a self-aligned T-gate GaN high-frequency device, which is prepared using the preparation method described in any of the above embodiments, and includes:

[0084] substrate layer;

[0085] a composite buffer layer, the composite buffer layer being disposed on the substrate layer;

[0086] a channel layer, the channel layer being disposed on the composite buffer layer;

[0087] a barrier layer, the barrier layer being disposed on the channel layer;

[0088] a source electrode, a drain electrode and a T-shaped gate electrode, wherein the source electrode, the drain electrode and the gate electrode are all disposed on the barrier layer, and the gate electrode is located between the source electrode and the drain electrode;

[0089] A passivation layer is provided on the source electrode, the drain electrode and the barrier layer.

[0090] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0091] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0092] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0093] The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention cannot be considered to be limited to these descriptions. For those skilled in the art of the present invention, any modifications made without departing from the concept of the present invention should be deemed to fall within the scope of protection of the present invention.

Claims

1. A method for preparing a self-aligned T-gate GaN high-frequency device, characterized in that: The preparation method comprises: Step 1: Obtain an epitaxial wafer, wherein the epitaxial wafer includes, from bottom to top, a stacked substrate layer, a composite buffer layer, a channel layer, and a barrier layer; Step 2: using a mesa etching method to etch away a portion of the channel layer and the barrier layer in the end region to achieve mesa isolation; Step 3: Using LPCVD technology to deposit and grow a first dielectric layer on the surface of the barrier layer; the first dielectric layer includes a silicon nitride dielectric layer; Step 4: etching the first dielectric layer in the gate region until the upper surface of the barrier layer is exposed to form a gate window; Step 5: using PECVD technology to grow a second dielectric layer in the gate window exposing the barrier layer, on the first dielectric layer and on the barrier layer, wherein the corrosion resistance of the second dielectric layer is lower than that of the first dielectric layer; the second dielectric layer comprises a silicon dioxide dielectric layer; Step 6: etching a portion of the second dielectric layer and the first dielectric layer directly below the second dielectric layer to expose the barrier layer to form two active regions, leaving a T-shaped second dielectric layer and the first dielectric layer below the T-shaped second dielectric layer; Step 7: performing ion implantation in the active region to form an ion implantation region, and then performing annealing to form an ohmic contact; Step 8: growing a first dielectric layer on the barrier layer, the ion implantation region and the T-shaped second dielectric layer; Step 9: removing the T-shaped second dielectric layer to prepare a T-shaped gate electrode on the gate window and the first dielectric layer; Step 10: remove the first dielectric layer in the active area, and then grow a source electrode and a drain electrode on the ion implantation area.

2. The method for preparing a self-aligned T-gate GaN high-frequency device according to claim 1, wherein: The material of the substrate layer includes any one of silicon, sapphire, silicon carbide, diamond, and glass single crystal substrate layer; The composite buffer layer includes, from bottom to top, a stacked AlN nucleation layer, an AlGaN transition layer, and a buffer layer. The thickness of the AlN nucleation layer is 100-300 nm, the thickness of the AlGaN transition layer is 200-1000 nm, the material of the buffer layer includes GaN or AlGaN, and the thickness of the buffer layer is 100-3000 nm. The material of the channel layer includes GaN or InGaN, and the thickness of the channel layer is 50nm-500nm; The material of the barrier layer includes AlGaN, InAlN, AlN or InAlGaN, and the thickness of the barrier layer is 2-40 nm.

3. The method for preparing a self-aligned T-gate GaN high-frequency device according to claim 1, wherein: Performing ion implantation in the active region to form an ion implantation region includes: An ion implantation method is adopted to implant Si ions into the active region through an ion implanter to form an ion implantation region.

4. The method for preparing a self-aligned T-gate GaN high-frequency device according to claim 1, wherein: Before step 9, the method further includes: The first dielectric layer is polished by using a CMP polishing technology.

5. The method for preparing a self-aligned T-gate GaN high-frequency device according to claim 1, wherein: Removing the T-shaped second dielectric layer includes: The T-shaped second dielectric layer is removed using HF or BOE solution.

6. The method for preparing a self-aligned T-gate GaN high-frequency device according to claim 1, wherein: The materials of the bottom two layers of the source electrode and the drain electrode include Ti / Al, Ta / Al or Mo / Al, and the material of the bottom first layer of the gate electrode includes Ti, Ni, Al, Ta, TiN or TaN.

7. A self-aligned T-gate GaN high-frequency device, characterized in that: The GaN high-frequency device is manufactured using the manufacturing method according to any one of claims 1 to 6, and the GaN high-frequency device comprises: substrate layer; a composite buffer layer, the composite buffer layer being disposed on the substrate layer; a channel layer, the channel layer being disposed on the composite buffer layer; a barrier layer, the barrier layer being disposed on the channel layer; a source electrode, a drain electrode and a T-shaped gate electrode, wherein the source electrode, the drain electrode and the gate electrode are all disposed on the barrier layer, and the gate electrode is located between the source electrode and the drain electrode; A passivation layer is provided on the source electrode, the drain electrode and the barrier layer.

Images