Three-dimensional integrated quantum chip and preparation method thereof

Abstract

The application provides a three-dimensional integrated quantum chip and a preparation method thereof, metal marks for positioning are prepared on the surface of an epitaxial growth layer of a scanning tunneling microscope hydrogen mask direct writing precision device after packaging; the metal marks are scanned by a scanning probe microscope, and three-dimensional precise positioning of the device is realized; after a gate oxide layer is grown, field overlay is written on the gate oxide layer by using the positioning effect of the metal marks, and a top electrode, a multilayer stacked electrode or a through-silicon via three-dimensional electrode is prepared. The preparation method described in the embodiment realizes high-precision three-dimensional integrated processing by using a scanning probe microscope, and provides important technical support for silicon-based semiconductor quantum computing, quantum simulation and quantum chips.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor quantum chip manufacturing, and in particular to a high-precision three-dimensional integrated quantum chip and a preparation method thereof. BACKGROUND

[0002] The key to the development from simple devices to complex chips is integration, and the implementation of silicon-based semiconductor complex quantum chips also requires integration technology. Internationally, it has been attempted to continue to use scanning tunneling microscope hydrogen mask direct writing technology (STM hydrogen mask direct writing technology for short) to process the second layer electrode structure on the surface of the device packaging layer of the scanning tunneling microscope hydrogen mask direct writing. Such "STM-MBE-STM-MBE" integration technology has been verified to a certain extent on the tunnel junction device, but due to the limitations of low-temperature epitaxial growth quality and the difficulty of positioning scheme, and the problems of easy leakage of critical voltage, too low, electrode processing size is too large, vertical cross interconnection is difficult, etc., the integration technology is difficult to realize precise integration processing of more complex devices. SUMMARY

[0003] In view of the deficiencies of the prior art, the present application aims to provide a high-precision three-dimensional integrated quantum chip and a preparation method thereof, which overcomes the defects that the prior art cannot realize precise integration processing of three-dimensional complex devices.

[0004] The technical solution of the present application is as follows:

[0005] In a first aspect, the present embodiment provides a preparation method of a high-precision three-dimensional integrated quantum chip, which comprises

[0006] Processing a metal mark for positioning on the surface of the packaging layer of the device processed by the scanning tunneling microscope hydrogen mask direct writing technology;

[0007] Scanning the device with the metal mark by using a scanning probe microscope (including but not limited to an atomic force microscope AFM, an electrostatic force microscope EFM, a scanning capacitance microscope, a scanning Kelvin microscope, etc.) to obtain a scanning image;

[0008] Growth of a gate oxide layer on the device with the metal mark on the surface;

[0009] Using the scanning image and the metal mark to etch a top electrode or a multi-layer stacked electrode or a through-silicon via three-dimensional electrode on the gate oxide layer to obtain a prepared three-dimensional integrated quantum chip.

[0010] Optionally, the step of processing the surface of the encapsulation layer of the device processed by the scanning tunneling microscope hydrogen mask direct writing technology to process a metal mark for positioning comprises:

[0011] manufacturing a silicon substrate with multiple different preset size etching marks;

[0012] under an ultra-high vacuum environment, degassing, high-temperature flash silicon and surface hydrogen passivation are performed on the silicon substrate, and a core part and a first layer electrode of a chip structure are directly written on the surface of the hydrogen passivated silicon substrate;

[0013] the core part and the first layer electrode of the chip structure directly written on the surface of the silicon substrate are metalized with a hydrogen desorption pattern to obtain a metalized device;

[0014] a pure silicon or isotopic silicon epitaxial growth is performed on the metalized device by using a molecular beam epitaxy growth technology to realize encapsulation of the device;

[0015] a metal mark is positioned and etched on the device by using the preset size etching mark.

[0016] Optionally, the step of positioning and etching the metal mark on the device by using the preset size etching mark comprises:

[0017] a scanning electron microscope picture of the device is obtained by using a scanning electron microscope;

[0018] a position for processing an ohmic contact on the device is positioned by using the scanning electron microscope picture, and an electrode for the ohmic contact is processed at the positioned position of the ohmic contact;

[0019] and a metal mark is positioned and etched on the surface of the device according to the preset size etching mark in the scanning electron microscope picture.

[0020] Optionally, the preset size etching mark comprises a first preset size etching mark, a second preset size etching mark and a third preset size etching mark; wherein the first preset size is greater than the second preset size, and the second preset size is greater than the third preset size;

[0021] the step of positioning and etching the metal mark on the surface of the device according to the preset size etching mark in the scanning electron microscope picture comprises:

[0022] a first preset size etching mark in the scanning electron microscope picture is used to preliminarily three-point calibrate the surface of the device, so that a coordinate system in which the surface of the device is located coincides with a coordinate system of the picture;

[0023] The chip structure on the device surface is three-point calibrated with the second preset size etching mark to the chip structure on the scanning electron microscope picture, so that the chip structure on the device surface is coincided with the chip structure on the scanning electron microscope picture.

[0024] The third preset size etching mark is used to align the metal mark on the located device surface.

[0025] Optionally, the device with the metal mark is scanned by the scanning probe microscope.

[0026] Optionally, the step of growing the gate oxide layer on the device with the metal mark on the surface comprises:

[0027] The atomic layer deposition device is used to grow the gate oxide layer on the silicon wafer with the metal mark.

[0028] Optionally, the step of aligning the top electrode on the gate oxide layer using the scanning image and the metal mark comprises:

[0029] The relative position between the metal mark and the chip structure bit in the scanning electron microscope picture is used to locate the position of the chip structure in the scanning image.

[0030] The located position of the chip structure in the scanning image is used to determine the corresponding position of the chip structure on the gate oxide layer.

[0031] The preset first write field is called, and the linear structure of the top electrode is obtained by aligning the metal mark with the given size and interval at the corresponding position of the chip structure on the gate oxide layer.

[0032] The preset second write field is called, and the fan-out structure of the top electrode is obtained by aligning the metal mark with the preset size and interval at the connection of the linear structure of the top electrode, thereby obtaining the top electrode.

[0033] Optionally, the preset first write field is called, and the linear structure of the top electrode is obtained by aligning the metal mark with different sizes and intervals.

[0034] In a second aspect, the embodiment further provides a quantum chip, wherein the quantum chip is prepared by the preparation method of the three-dimensional integrated quantum chip.

[0035] Beneficial effects: the application provides a high-precision three-dimensional integrated quantum chip and a preparation method thereof, metal marks for positioning are processed on the surface of a packaging layer of a device processed by an STM hydrogen mask direct writing technology; a scanning probe microscope is used to scan the device with the metal marks to obtain a scanning image; a gate oxide layer is grown on the device with the metal marks on the surface; a top electrode, a multi-layer stacked electrode or a through-silicon via three-dimensional electrode is made on the gate oxide layer by using the scanning image and the metal marks to obtain the prepared three-dimensional integrated quantum chip. The quantum chip preparation method disclosed in the embodiment improves the manufacturing precision of the top electrode under the assistance of the scanning probe microscope, reduces the size limit of the electrode processing, meets the processing requirements of the atomic-level silicon-based quantum device, and effectively avoids problems such as too low leakage critical voltage and difficult vertical cross interconnection of the interlayer gate oxide layer of the three-dimensional integrated chip, so that more precise and complex effective quantum device integrated processing can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a step flow chart of the preparation method of the three-dimensional integrated quantum chip disclosed in the application;

[0037] Figure 2 is a step flow chart of a specific application embodiment of the preparation method disclosed in the application;

[0038] Figure 3 is a structural schematic diagram of a preset first etching mark in the embodiment of the application;

[0039] Figure 4 is a structural schematic diagram of a preset second etching mark and a preset third etching mark in the embodiment of the application;

[0040] Figure 5 is a structural schematic diagram of a first layer of a chip in the embodiment of the application;

[0041] Figure 6 is a schematic diagram of an actual device core part of a first layer of a chip in the embodiment of the application;

[0042] Figure 7 is a structural schematic diagram of a Chessy focusing pattern in the embodiment of the application;

[0043] Figure 8 is a structural schematic diagram of a metal mark in the embodiment of the application;

[0044] Figure 9 is a schematic diagram of actual processing of a metal mark in the embodiment of the application;

[0045] Figure 10 is a schematic diagram of a quantum device and a metal mark in the embodiment of the application;

[0046] Figure 11 is a structural schematic diagram of a top electrode processed in an embodiment of the present application;

[0047] Figure 12 is a structural schematic diagram of a top electrode containing a fan-out structure actually processed in an embodiment of the present application. DETAILED DESCRIPTION

[0048] To make the objectives, technical solutions, and advantages of the present application clearer and more explicit, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0049] Those skilled in the art can understand that, unless specifically stated otherwise, the singular forms "a", "an", and "the" used herein also include the plural forms. It should be further understood that the phrase "comprising" used in the specification of the present application means that the features, integers, steps, operations, elements, and / or components exist, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say that an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be an intermediate element. In addition, "connected" or "coupled" used herein can include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any single unit and all combinations of the associated listed items.

[0050] Those skilled in the art can understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as that generally understood by those skilled in the art to which the present application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have meanings consistent with those in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as such.

[0051] With the advent of the information age, chip technology is increasingly widely used in human society. Chips in various electronic products not only improve the computing and processing capabilities of the products, but also enable these products to interact with the Internet, greatly enriching and expanding human life. Currently, chip technology has been deeply integrated into human society and has become an indispensable infrastructure in the information age. In the future, chip technology will continue to progress and play an increasingly important role in cutting-edge fields such as quantum computing and artificial intelligence, having a profound impact on human society.

[0052] Compared with the computer based on the traditional semiconductor chip, the quantum computer uses quantum bits as the basic operation unit, and can complete the complex calculation that the traditional computer almost cannot complete. With the development of quantum computing theory and the rapid progress of quantum devices, quantum computers have become a new generation of computing platform, which has a disruptive impact on the information technology industry. The advent of the quantum computing era will also promote the realization of major breakthroughs in semiconductor materials and devices, opening up new prospects for the traditional semiconductor microelectronics industry. In the future, the traditional semiconductor and the emerging quantum device are expected to achieve deep integration, and together build a new computing system with stronger computing power and function.

[0053] The silicon-based quantum dot system is one of the most promising quantum computing schemes, and the basic elements such as single electron transistors and high-fidelity two-bit gates have been verified based on STM hydrogen mask direct writing technology. The key to the development from simple devices to complex chips is integration, and the realization of silicon-based semiconductor complex quantum chips also requires integration process. The international community has attempted to continue using STM hydrogen mask direct writing technology to process the second layer of electrode structure on the surface of the STM hydrogen mask direct writing device packaging layer. This kind of "STM-MBE-STM-MBE" integration process has been verified to a certain extent on the tunnel junction device, but due to the limitations of low-temperature epitaxial growth quality and the difficulty of positioning scheme, and the problems such as low critical voltage of leakage current, large electrode processing size, and difficulty in vertical cross interconnection, the integration process is difficult to realize accurate integration processing of more complex devices.

[0054] In order to overcome the problem of low positioning accuracy of the top electrode processed above, the embodiment provides a preparation method of high-precision quantum chip top electrode and a quantum chip. The silicon wafer with metal marks on the surface is prepared; the silicon wafer with the metal marks is scanned by a scanning probe microscope to obtain a scanning image; a gate oxide layer is grown on the silicon wafer with the metal marks on the surface; and the top electrode is etched on the gate oxide layer by using the scanning image and the metal marks. In the method disclosed in the embodiment, the metal marks produced have smaller interval size, so that higher precision positioning and etching of the top electrode under the scanning probe microscope can be realized, thereby preparing a higher precision quantum chip top electrode, improving the control ability of the spin state, local chemical potential, electron wave function overlap and charge loading of the quantum device, and ensuring the accurate quantum control of the silicon-based quantum chip.

[0055] The method and quantum chip of the embodiment will be taken as an example to further explain the present application more accurately.

[0056] As shown in Figure 1 The embodiment discloses a preparation method of a high-precision three-dimensional integrated quantum chip, and the steps of the preparation method include:

[0057] S1, processing a metal mark for positioning on a packaging layer surface of a device processed by a scanning tunneling microscope hydrogen mask direct writing technology (STM hydrogen mask direct writing technology for short);

[0058] In order to realize the preparation of a quantum chip top electrode with higher precision, a metal mark with a smaller interval size is prepared in this step. Specifically, in this step, a plurality of etching marks (Mark) with different sizes are processed first, and then the metal mark to be processed is obtained by using the plurality of etching marks (Mark) with different sizes processed.

[0059] Specifically, processing a metal mark for positioning on a packaging layer surface of a device processed by a scanning tunneling microscope hydrogen mask direct writing technology includes the following steps:

[0060] S11, preparing a silicon wafer with a plurality of different pre-set size etching marks.

[0061] In combination Figure 3 and Figure 4 exposing first, second and third pre-set size etching marks with different sizes on a silicon wafer, the sizes of the first, second and third pre-set size etching marks correspondingly are gradually reduced, so as to realize accurate positioning and overlay of the quantum chip device.

[0062] S12, in an ultrahigh vacuum environment, the silicon substrate is degassed, high temperature flash silicon and surface hydrogen passivation, and the core part and the first layer electrode of the chip structure are directly written on the surface of the silicon substrate after hydrogen passivation.

[0063] Place the cleaned silicon substrate in an ultrahigh vacuum system, and sequentially perform background and direct current heating degassing on the silicon substrate, and then perform high temperature flash silicon treatment to obtain a silicon reconstructed bare silicon surface. Heat the bare silicon substrate in the hydrogen atom atmosphere obtained by cracking hydrogen, and realize hydrogen passivation of the surface of the silicon substrate. Hydrogen passivation not only protects the surface of the substrate, but also plays a role of mask in the subsequent direct writing process.

[0064] In an ultrahigh vacuum system, a scanning tunneling microscope probe is used to directly write the core part and the first layer electrode structure on the surface of the hydrogen passivated silicon substrate.

[0065] Using a scanning tunneling microscope needle tip to remove hydrogen atoms at any target position by atomic manipulation, and using STM hydrogen mask direct writing technology to directly write large patterns of core part and electrode extension part. After the STM hydrogen mask direct writing technology, the H-Si bond is broken, the hydrogen atom is desorbed, and the bare silicon with active dangling bonds is left in the surface pattern.

[0066] S13, the core part and the first layer electrode of the chip structure directly written on the surface of the silicon substrate are metallized by hydrogen desorption pattern, to obtain the device after metallization.

[0067] The dangling bond of silicon atom is very active, and it is easy to adsorb a small amount of substances in the vacuum chamber. It is necessary to dose and dope in time, that is, in the atmosphere of precursor gas containing III / V or IV atoms such as PH3, B2H6, BCl3 and H2Se, the gas molecules are adsorbed on the dangling bond of silicon to provide P, B and Se atoms, realize device pattern metallization, and in a certain sense, it is also a kind of protection for direct writing pattern.

[0068] By using the dissociation of gas molecules such as phosphine and hydrogen desorption bare silicon under the action of electric field and heat, phosphorus atoms replace silicon atoms in the lattice in a substitutional manner, and complete two-dimensional patterns filled with phosphorus atoms can be formed in the preset device structure. Because one extra electron is provided in addition to satisfying the covalent bond coordination, the dense arrangement of phosphorus atoms causes a significant increase in the concentration of conduction band electrons, which is called pattern metallization.

[0069] The chip structure directly written in this step is the core part and the first layer electrode of the chip structure, and the core part and the first layer electrode of the chip structure are the first layer structure of the three-dimensional integrated quantum chip.

[0070] S14, using molecular beam epitaxy growth technology, pure silicon or isotopic silicon is epitaxially grown on the device after metallization to realize the packaging of the device after metallization.

[0071] After the first layer structure of the quantum chip is processed in the above steps, pure silicon or isotopic silicon thin film is epitaxially grown on it at low temperature by using molecular beam epitaxy growth technology, to realize the packaging and protection of the device structure, so as to ensure the stable existence of the device in the atmospheric environment.

[0072] Low temperature epitaxy is to limit the thermal budget in growth, and molecular beam epitaxy is used to improve the lattice quality as much as possible, and the crystal packaging can realize better packaging effect at a relatively thin thickness.

[0073] S15, using a preset size etching mark to position and etch a metal mark on the device.

[0074] The scanning electron microscope picture of the electron microscope device is used. First, the silicon wafer obtained in the above step S12 is placed in the field of view of the scanning electron microscope, and after setting the parameters such as acceleration voltage and scanning range, the scanning electron microscope picture containing the above-mentioned preset size etching mark and chip structure is taken.

[0075] The position for processing ohmic contact on the device is located by scanning electron microscope photos, an array pattern of ohmic contact holes is drawn on the positions by drawing software, the pattern is transferred to photoresist by electron beam exposure, and ohmic contact holes are finally processed on the chip by dry etching.

[0076] The pattern of ohmic contact electrode is drawn on the drawing software, the pattern is transferred to photoresist by electron beam exposure, and ohmic contact electrode is finally processed by metal deposition through electron beam evaporation equipment.

[0077] Next, metal marks are processed on the surface of the device, and the specific steps are as follows:

[0078] First, the mark source file is imported in the graphic editing software, then the scanning electron microscope picture for positioning is imported, the approximate position of the chip structure is drawn, the file is saved and exported. The file is imported into the flat design software, and a plurality of metal marks are arranged at equal intervals around the chip structure. The file containing the data information of the designed metal mark and chip structure is imported into the electron beam exposure system to complete the positioning of the chip structure.

[0079] After the positioning of the chip structure is completed according to the scanning electron microscope picture, the metal marks are obtained by etching mark lithography of different sizes.

[0080] Specifically, a mask used for lithography is first made, and then the metal marks are obtained by exposure and overlay.

[0081] The preset size etching mark includes a first preset size etching mark, a second preset size etching mark and a third preset size etching mark; wherein the first preset size is greater than the second preset size, and the second preset size is greater than the third preset size; the step of positioning and overlaying the metal mark on the silicon wafer with the chip structure according to the preset size mark in the picture of the chip structure includes:

[0082] In the drawing software, the picture of the chip structure is inserted, the first preset size etching mark in the picture is used to preliminarily calibrate three points on the silicon wafer, and the coordinate system of the silicon wafer is coincided with the coordinate system of the picture; the second preset size etching mark is used to calibrate three points on the chip structure on the silicon wafer and the chip structure on the picture, so that the chip structure on the silicon wafer is coincided with the chip structure on the picture; finally, the third preset size etching mark is used to overlay the metal mark on the positioned silicon wafer.

[0083] S2, scanning the silicon wafer with the metal mark by scanning probe microscope to obtain a scanning image.

[0084] The silicon wafer with the metal mark is scanned by an atomic force microscope to obtain a silicon wafer image with the metal mark. Specifically, the silicon wafer with the mark is placed on a sample holder, and the silicon wafer image is scanned by adjusting the scanning parameters.

[0085] S3. Growing a gate oxide layer on the silicon wafer with the metal mark on the surface.

[0086] After the scanning image is obtained, a gate oxide layer is grown on the surface of the silicon wafer. In an embodiment, the method of growing the gate oxide layer is atomic layer deposition equipment growth. Since the atomic layer deposition equipment is used to grow a high-quality gate oxide layer, the interface defects are less than those of a thin film prepared by other growth methods, and thus the electrical noise introduced in the electrical measurement is less.

[0087] S4. Using the scanning image and the metal mark to etch the top electrode on the gate oxide layer. The preparation of the gate oxide layer and the top electrode is cycled to obtain a multi-layer stacked top electrode, or a through-silicon via three-dimensional electrode is processed using a through-silicon via technology, and S5. Finally, a three-dimensional integrated quantum chip is obtained.

[0088] The top electrode is processed using the scanning image obtained in step S2 and the metal mark. Specifically, a mask is first prepared, then exposed by an electron beam exposure system, and the structure of the top electrode is obtained by etching using the prepared mark. After developing, fixing, plating, removing glue, and plating by an electron beam evaporation device, the prepared top electrode is obtained.

[0089] In addition, in addition to processing a single-layer top electrode using the prepared metal mark, the process can be continued to process a multi-layer stacked electrode, that is, a gate oxide layer is grown on the first layer of top electrode, and a second layer of top electrode is processed using the same set of marks; or a through-silicon via three-dimensional electrode is processed, that is, the through-silicon via is precisely positioned by the metal mark, a through hole is processed by deep silicon etching process, a conductive material is deposited on the hole wall by atomic layer deposition equipment, and then chemical mechanical polishing is performed to expose the conductive structure on the back of the wafer for rewiring.

[0090] Specifically, the step of using the scanning image and the metal mark to etch the top electrode on the gate oxide layer includes:

[0091] The relative position between the metal mark and the core part of the chip structure in the scanning electron microscope picture is used to locate the position of the core part of the chip structure in the scanning picture; the position of the core part of the chip structure in the scanning picture is determined; a first writing field is preset; a metal mark with a given size and interval is used to etch a linear structure of the top electrode on the determined position corresponding to the core part of the chip structure on the gate oxide layer; a second writing field is called to etch a fan-out structure of the top electrode at the connection of the linear structure by using a mark with a preset size interval, thereby obtaining the top electrode.

[0092] In this step, since the position of the core part of the chip structure has been obtained when the metal mark is made by using the scanning electron microscope picture, the relative position between the metal mark and the core part of the chip structure is known. When the gate oxide layer is grown on the silicon wafer with the metal mark on the surface, since the gate oxide layer covers the surface of the chip structure, the position of the core part of the chip structure under the gate oxide layer cannot be directly determined. In this embodiment, by taking a scanning picture with the metal mark, the position of the core part of the chip structure after the gate oxide layer is grown on the silicon wafer is determined according to the known relative position between the metal mark and the core part of the chip structure, thereby achieving the etching of the top electrode on the gate oxide layer.

[0093] Further, in this step, the etching of the linear structure and the fan-out structure of the top electrode is completed in two writing fields, thereby obtaining the top electrode prepared by the method. Specifically, the silicon wafer processed in the above step is placed in an electron beam exposure system, appropriate writing fields and exposure parameters are set, the metal mark with a given large interval size is positioned and focused, the silicon wafer is moved to the position of the metal mark with a given small interval size, the core structure region is positioned, and finally the writing field is called to etch the linear structure of the top electrode by using the metal mark with different given interval sizes, then the writing field is called again to etch the fan-out structure connected to the linear structure by using the metal mark with a given interval size, and finally the top electrode is prepared through the development and metal deposition processes.

[0094] If the traditional etching technology is used, the etching mark with a 50um interval will produce an etching deviation of dozens to hundreds of nanometers, and the substrate needs to pass through high-temperature flash silicon in a vacuum chamber to remove surface impurities and oxide layers. In this process, the surface of the silicon wafer is in a semi-melted state, which causes the deformation and displacement of the pre-processed etching mark, and finally leads to the decline of etching accuracy.

[0095] Compared with the single-layer two-dimensional STM hydrogen mask direct writing device processing technology, the preparation method provided in the embodiment can significantly improve the space utilization, allow more electrodes to be arranged in a limited chip size, and allow more complex device structures. Compared with the "STM-MBE-STM-MBE" three-dimensional device processing technology, the preparation method provided in the embodiment can more accurately identify the specific position, size and shape of the first layer complex device, and can realize efficient processing after high-precision alignment, greatly shortening the processing time. Compared with the gate electrode full micro-nano processing technology, the preparation method provided in the embodiment effectively utilizes the atomic-level high precision of the STM hydrogen mask direct writing technology, greatly improves the positioning accuracy of the core part, is beneficial to precise quantum regulation, and realizes atomic-level quantum calculation and analog quantum simulation.

[0096] The specific application examples of the method will be described below. Figures 2 to 12 The steps S1 to S5 will be described in more detail.

[0097] Step H1: Pre-processing etching marks of different preset sizes and slicing and cleaning.

[0098] Laser direct writing was performed on a 4-inch Si (100) single-polished silicon wafer, and the exposure was as shown in Figure 3 and Figure 4 The three different sizes and spacings of the preset first size etching marks, the preset second size etching marks and the preset third size etching marks were used for the purpose of step-by-step calibration of coordinates, so as to realize precise processing of the device. The device used was HEIDELBERG INSTRUMENTS DWL66+, the photoresist used for exposure was S1805, the developing solution was AZ Develpoer, after development, the sample was rinsed with deionized water, and finally dried with a nitrogen gun.

[0099] The dry etching device used was OXFORD INSTRUMENTS PlasmaPro 100 RIE.

[0100] In the semi-automatic slicer, the 4-inch silicon wafer was cut into a strip-shaped sample according to the pre-set program, which was convenient for subsequent processing.

[0101] The silicon wafer was cleaned, and the solutions used were piranha solution and RCA2 solution. First, the piranha solution was prepared in a beaker according to the given ratio, and the sample was immersed in the piranha solution. This process can remove heavy organic contamination and part of the metal on the surface of the silicon wafer. The silicon wafer was taken out and rinsed under the deionized water stream. Then, the RCA2 solution was prepared in a beaker according to the given ratio, and the sample was immersed in the RCA2 solution, and the beaker was placed on a hot plate for heating. This process can be used to remove Na, Fe, Mg and other metal contamination on the surface of the silicon wafer. The silicon wafer was taken out and rinsed under the deionized water stream, and finally dried with a nitrogen gun.

[0102] Step H2: Substrate processing and surface hydrogen passivation under ultra-high vacuum environment.

[0103] In an ultra-high vacuum system, the silicon substrate is degassed, high-temperature flash silicon, and surface hydrogen passivation.

[0104] Step H3: Direct writing of the core part of the chip structure and the first layer electrode structure on the hydrogen passivated Si(100) surface using a scanning tunneling microscope probe. Figure 5 The design of the first layer electrode structure is shown in FIG. 2, and the actual device schematic diagram of the first layer is shown in FIG. 3. Figure 6 The design of the first layer electrode structure is shown in FIG. 2, and the actual device schematic diagram of the first layer is shown in FIG. 3.

[0105] Using a scanning tunneling microscope needle to remove hydrogen atoms at any target position, the part of H-Si bond broken by STM hydrogen mask direct writing, hydrogen atoms desorption, leaving bare silicon with active dangling bonds in the surface pattern.

[0106] Step H4: Metallization of the hydrogen desorption pattern after direct writing.

[0107] The dangling bonds of silicon atoms are very active and easily adsorb a small amount of substances in the vacuum chamber. It is necessary to dose and dope in time, that is, in the atmosphere of precursor gas containing III / V or IV atoms such as PH3, B2H6, BCl3, H2Se, etc. The gas molecules are adsorbed on the dangling bonds of silicon to provide P, B, Se atoms, realize device pattern metallization, and in a certain sense, it is also a kind of protection for direct writing pattern.

[0108] Using phosphine and other gas molecules to dissociate the bond of bare silicon after hydrogen desorption under the effect of electric field and heat, phosphorus atoms replace silicon atoms in the lattice in a substitutional manner, and a complete two-dimensional pattern filled with phosphorus atoms can be formed in the preset device structure. Due to the provision of an extra electron in addition to the covalent bond coordination, the dense arrangement of phosphorus atoms causes a significant increase in the concentration of conduction band electrons, which is called pattern metallization.

[0109] Step H5: MBE low-temperature epitaxial growth of silicon to encapsulate the first layer of the device.

[0110] After the first layer structure of the chip is processed, pure silicon or isotopic silicon thin film is grown on it by molecular beam epitaxy at low temperature to realize encapsulation and protection of the device structure, so as to ensure the stable existence of the device in the atmospheric environment.

[0111] This step is also carried out in an ultra-high vacuum system. Low-temperature epitaxy is used to limit the thermal budget during growth, and molecular beam epitaxy is used to improve the lattice quality as much as possible. Crystal encapsulation can achieve better encapsulation effect at a relatively thin thickness.

[0112] Step H6: Positioning the core structure of the quantum chip by scanning electron microscope.

[0113] The model of the electron microscope used for positioning is ZEISS Gemini scanning electron microscope 300. First, the silicon wafer with the straight-written quantum chip core structure is fixed on the Universal Sample Holder for sample loading. Then, the brightness and contrast of the scanning electron microscope image are adjusted appropriately in the area near the target etching mark. Finally, the field of view is moved to the target etching mark, and a scanning electron microscope picture containing the etching mark and the quantum chip core structure is taken.

[0114] First, import the mark source file in the software Inkscape, then import the scanning electron microscope photo for positioning, and draw the approximate position of the chip structure. Save and export as a GDS2 file. Import the GDS2 file in the drawing software, and draw a given number and size of marks around the chip structure at equal intervals. Then import the file into the electron beam exposure system, and set the exposure dose.

[0115] Step H7: First layer electrode ohmic contact.

[0116] The positions for processing ohmic contact on the STM hydrogen mask straight-written device are located by scanning electron microscope photo. Through drawing software, an array pattern of ohmic contact holes is drawn on these positions. Then the pattern is transferred to the photoresist by electron beam exposure. Finally, the contact holes are processed on the chip by dry etching.

[0117] Draw the pattern of the ohmic contact electrode on the drawing software. Transfer the pattern to the photoresist by electron beam exposure. Deposit metal by electron beam evaporation equipment, and finally process the electrode for ohmic contact.

[0118] Step H8: Processing metal marks.

[0119] The brand of the spin coater used is LEBO science. First, the surface of the sample is modified with a tackifier to enhance the adhesion of the photoresist to the sample. Then, PMMA reagent is used to spin the photoresist. Then, the sample with the spin-coated photoresist is placed on a hot plate for heating, and then naturally cooled to room temperature to obtain the mask.

[0120] Exposure is performed using ZEISS Gemini scanning electron microscope 300. The silicon wafer is fixed on the Universal Sample Holder for sample loading. After setting the acceleration voltage and other parameters, first move to the Chessy to adjust the focus, brightness, contrast, etc. Figure 7Focus on the pattern in Chessy. Call the preset write field, correct the write field and save. Move to the Faraday cup position to measure the beam current and record.

[0121] Further, move the scanning electron microscope sample stage so that the field of view comes to the region of the silicon wafer, calibrate the silicon wafer sample zero point, locate one of the pre-set largest size markers for three-point calibration, so that the sample coordinate system of the silicon wafer coincides with the drawing coordinate system. Move to the marker area containing the chip core chip structure, use the second pre-set size marker to perform three-point calibration again, and punch a point near the last marker, and adjust the focus. Call the write field, and use the pre-processed third pre-set size marker to perform overlay. Select the number of exposure layers, the working area range, fill in the beam current measurement value, set the exposure step size and other parameters in the exposure parameter menu, and then perform metal marker exposure.

[0122] Develop with MIBK:IPA = 1:3 reagent as a developing solution, then quickly transfer to the IPA reagent for fixing, and then dry the silicon wafer with a nitrogen gun.

[0123] Fix the fixed silicon wafer on the sample disc of the magnetron sputtering film coating machine, pre-evacuate in the transition chamber (Loadlock), then sample from the transition chamber to the evaporation chamber, call the film coating program to start metal film coating, after sampling, put the silicon wafer into a beaker containing 1165 remover solution (1165 Remover) for lift-off, during which the beaker is placed on a hot plate for heating. Spray the silicon wafer with a spray bottle containing acetone (AC) solution, then spray it with a spray bottle containing isopropyl alcohol (IPA) solution, and finally dry the silicon wafer with a nitrogen gun, as shown in Figure 8 The design diagram of the metal marker is shown in Figure 9 The actual processed metal marker diagram is shown in

[0124] Scan the silicon wafer with metal markers using the scanning probe microscope device model BRUKER innova, and the probe model BRUKER RTESPA-300, set the scanning parameters, obtain the scanning image with metal markers, as shown in Figure 10 The scanning image with metal markers and chip structure is shown in. Export the scanning image as a JPG format, first import the metal marker source file in the drawing software, then import the scanning image for positioning, and depict the approximate position of the chip core structure, save and export as a GDS2 file. Import the GDS2 file in the drawing software, design the top electrode and fan-out structure at the corresponding position, save the file and import it into the electron beam exposure system, and set the exposure dose.

[0125] Step H9: Gate oxide layer growth.

[0126] Device model: PICSUN, grow the gate oxide layer.

[0127] Step H10: Processing the top electrode.

[0128] The brand of the used spin coater is LEBO science. First, the adhesion promoter is used, then the PMMA reagent is used for spin coating, and then the sample with the spin-coated glue is placed on the hot plate for heating, and then naturally cooled to room temperature to obtain the mask.

[0129] Exposure is performed using a ZEISS Gemini scanning electron microscope 300. The sample is fixed on a universal sample holder for sample loading, the focus is adjusted on the Chessy, the write field is called, and the write field correction is performed, moved to the Faraday cup position to measure the beam current and record, switch the aperture, adjust the focus on the Chessy, call the write field, and perform the write field correction, move to the Faraday cup position to measure the beam current and record, move to the sample, determine the sample zero point and positive direction, focus on one of the etching marks, flatten, and three-point calibration.

[0130] Move to the area containing the core structure of the device, three-point calibration, and punch a dot near the last mark, and adjust the focus. Call the write field, use the pre-processed etching mark and the given interval metal mark for overlay, and expose the internal structure of the top electrode. Call the write field, use the given interval mark for overlay, expose the fan-out structure of the top electrode, and take out the sample. Develop with MIBK:IPA = 1:3 reagent as the developing solution, then quickly transfer to the IPA reagent for fixing, and then blow dry the sample with a nitrogen gun.

[0131] Device model: PLASSYS 550S. Fix the fixed sample on the PLASSYS sample disc, put it into the evaporation cavity to vacuum, call the film plating program to start metal evaporation; take out the sample, and put the plated sample into a beaker containing 1165 remover for lift-off, during which the beaker is heated on a hot plate. Spray the sample with a spray bottle containing acetone (AC) solution, then spray with a spray bottle containing isopropyl alcohol (IPA) solution, and finally dry with a nitrogen gun to obtain the prepared top electrode. Combined with Figure 11 and Figure 12 The line structure of the top electrode prepared by the preparation method provided in the embodiment and the top electrode with a fan-out structure are shown. If step H9 and step H10 are cycled, a multi-layer stacked top electrode can be obtained.

[0132] On the basis of the above-mentioned method, the embodiment also provides a quantum chip, which comprises: a top electrode prepared by the preparation method of the quantum chip top electrode, or a multi-layer stacked top electrode, or a through-silicon electrode.

[0133] Since the preparation method provided by the embodiment meets the processing requirements of atomic-level silicon-based quantum devices in the width and spacing of the top electrode, better signal control effect can be achieved, thereby ensuring the normal work of the silicon-based quantum chip.

[0134] It should be noted that the above application scenarios are only shown for the convenience of understanding the present application, and the embodiments of the present application are not limited in this respect. On the contrary, the embodiments of the present application can be applied to any applicable scenario.

[0135] It can be understood that, for those skilled in the art, equivalent replacements or changes can be made according to the technical solutions and inventive concepts of the present application, and all such changes or replacements shall fall within the protection scope of the claims appended to the present application.

Claims

1. A method of fabricating a three-dimensional integrated quantum chip, the method comprising: comprising ​ directly writing a core part of a chip structure and a first layer electrode pattern on a surface of a silicon substrate with a scanning tunneling microscope, the surface of the silicon substrate being etched with different preset size marks; metallizing the core part of the chip structure and the first layer electrode directly written on the surface of the silicon substrate to obtain a metallized device; packaging the metallized device; positioning and overlaying a metal mark on a surface of a packaging layer of the device using a scanning electron microscope; scanning the device with the metal mark using a scanning probe microscope to obtain a scanning image; growing a gate oxide layer on the device with the metal mark on the surface; overlaying a top electrode or a multi-layer stacked electrode or a through-silicon via three-dimensional electrode on the gate oxide layer using the scanning image and the metal mark to obtain a prepared three-dimensional integrated quantum chip.

2. The method of claim 1, wherein The step of positioning and overlaying a metal mark on a surface of a packaging layer of the device using a scanning electron microscope comprises: obtaining a scanning electron microscope image of the device after packaging using a scanning electron microscope; positioning a location for processing an ohmic contact on the device using the scanning electron microscope image, and processing an electrode for the ohmic contact at the positioned location for the ohmic contact; and positioning and overlaying a metal mark on the surface of the device according to a preset size etching mark in the scanning electron microscope image.

3. The preparation method of the three-dimensional integrated quantum chip according to claim 2, characterized in that the preset size etching mark comprises a first preset size etching mark, a second preset size etching mark and a third preset size etching mark; wherein the first preset size is greater than the second preset size, and the second preset size is greater than the third preset size; the step of positioning and overlaying a metal mark on the surface of the device according to the preset size etching mark in the scanning electron microscope image comprises: initially three-point calibrating the surface of the device using the first preset size etching mark in the scanning electron microscope image to make the coordinate system of the surface of the device coincide with the coordinate system of the image; three-point calibrating the chip structure on the surface of the device with the chip structure on the scanning electron microscope image using the second preset size etching mark to make the chip structure on the surface of the device coincide with the chip structure on the scanning electron microscope image; overlaying a metal mark on the positioned surface of the device using the third preset size etching mark.

4. The method of claim 1, wherein The step of growing a gate oxide layer on the device with the metal mark on the surface comprises: growing a gate oxide layer on the silicon wafer with the metal mark using an atomic layer deposition device.

5. The method of claim 1, wherein The step of overlaying a top electrode on the gate oxide layer using the scanning image and the metal mark comprises: determining a position on the gate oxide layer corresponding to the core part of the chip structure using the scanning image; calling a preset first writing field, and overlaying a linear structure of the top electrode on the determined position on the gate oxide layer corresponding to the core part of the chip structure using metal marks of a given size and interval; calling a preset second writing field, and overlaying a fan-out structure of the top electrode at the connection of the linear structure of the top electrode using metal marks of a given size and interval to obtain the fabricated top electrode.

6. The method of claim 1, wherein The step of using the scanning image and the metal mark to align and manufacture the top electrode or the multi-layer stacked electrode or the through-silicon via three-dimensional electrode on the gate oxide layer comprises: The steps of growing the gate oxide layer on the device with the metal mark on the surface and using the scanning image and the metal mark to align and manufacture the top electrode on the gate oxide layer are repeated to obtain a multi-layer stacked top electrode structure or a through-silicon via three-dimensional electrode by using a through-silicon via technology.

7. A quantum chip, characterized by The quantum chip is prepared by the method for preparing the three-dimensional integrated quantum chip according to any one of claims 1 to 6.

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