Digital Array Signal Processing Superstructure Chip

Abstract

The present invention discloses a digital array signal processing super-structure chip, the super-structure chip comprising: a multi-channel communication interface for receiving collected data; a dynamic random access memory interconnected with the multi-channel communication interface for storing collected data and beamformed data; a reconfigurable computing array connected to the dynamic random access memory through a plurality of data lines and address lines for performing matrix operations on the collected data according to a beamforming algorithm; the reconfigurable computing array comprises a plurality of super-computing units capable of performing real number operations and / or complex number operations, the super-computing unit comprises a plurality of computing units capable of performing real number operations; the computing units and the super-computing units can both adjust data transmission links and / or connection relationships according to configuration commands. The super-structure chip provided by the present invention can perform matrix operations, and the area overhead and power consumption of the super-structure chip provided by the present invention are small.

Description

Technical Field

[0001] The invention belongs to the technical field of radar signal processing, and in particular relates to a digital array signal processing superstructure chip. Background Art

[0002] Coarse-Grained Reconfigurable Architecture (CGRA) is an emerging technology in the field of computer architecture that provides highly customized computing resources for specific algorithm implementation processes. The core feature of CGRA is coarse-grained reconfigurability, that is, at the hardware level, it can reconfigure its computing units and connection structures according to the needs of the application. This flexibility enables CGRA to support a variety of different algorithm operations on the same hardware architecture, thereby reducing the complexity and cost of the system.

[0003] Digital Array Radar (DAR) and Digital Beamforming (DBF) are important components of modern radar technology. Digital beamforming and digital array radar are widely used in military, aerospace, meteorological monitoring, geological exploration and other fields.

[0004] Currently, there is a chip-based reconfigurable elastic multi-beam digital array technology that is mainly used in the field of digital phased arrays. Although this method has the advantages of large-scale expansion and increasing the number of beams, it only uses the existing digital chips on the market to build the system of the original analog digital beamforming method. Although the volume and power consumption are superior to traditional digital array multi-beam radars, the actual values ​​are still relatively high and difficult to further control, and cannot meet the requirements of low-power equipment in special environments.

[0005] Another in-memory computing method based on coarse-grained reconfigurable arrays aims to solve the memory wall problem in data-intensive applications and improve computing performance and energy efficiency. However, this method is an architectural innovation in the packaging and physical memory block logic layer using three-dimensional stacking technology and silicon via technology. It does not make corresponding architectural optimizations and design targeted computing cores for matrix computing. It cannot calculate the operations that have special requirements for resources and architecture in the digital beamforming process, such as matrix multiplication and addition, transposition and inversion, and it is difficult to meet the computing task requirements in the specific field of radar.

[0006] Therefore, the current devices used for beamforming either have high power consumption and low applicability, or cannot implement the matrix operations required for beamforming. Summary of the invention

[0007] The embodiment of the present invention provides a digital array signal processing super-structure chip, which can solve the problems that the current devices used for beamforming have high power consumption, low applicability or cannot implement matrix operations required in beamforming.

[0008] In a first aspect, an embodiment of the present invention provides a digital array signal processing super-structure chip, wherein the digital array signal processing super-structure chip comprises: a multi-channel communication interface, a reconfigurable computing array, and a dynamic random access memory;

[0009] The multi-channel communication interface is used to receive the collected data from each array element of the radar; the reconfigurable computing array is used to perform matrix operations on the collected data according to the beamforming algorithm to obtain beamformed data, wherein the matrix operations include one or more of the following: matrix multiplication, matrix addition, matrix transposition, and matrix inversion; the dynamic random access memory is used to store the collected data and the beamformed data;

[0010] The reconfigurable computing array includes a plurality of super computing units, and the super computing unit includes a plurality of computing units. Each computing unit and the super computing unit are used to adjust the data transmission link and / or the connection relationship according to the configuration command to adapt to different beamforming algorithms; the computing unit is also used to perform real number operations on the collected data according to the beamforming algorithm, and the super computing unit is also used to perform real number operations and / or complex number operations on the collected data according to the beamforming algorithm;

[0011] The input end of the dynamic random access memory is connected to the output end of the multi-channel communication interface, and the dynamic random access memory is connected to the reconfigurable computing array through a write data line, a write address line, a read data line, and a read address line.

[0012] In a second aspect, an embodiment of the present invention provides an operation unit, the operation unit comprising: a seventh data selector, an eighth data selector, a floating-point multiplier, a ninth data selector, a tenth data selector, a floating-point adder / subtractor, and a register;

[0013] The 1 input terminal of the seventh data selector is connected to the first input interface of the operation unit; the 1 input terminal of the eighth data selector is connected to the second input interface of the operation unit; the output terminals of the seventh data selector and the eighth data selector are respectively connected to the first input terminal and the second input terminal of the floating-point multiplier; the 1 input terminal of the ninth data selector is connected to the third input interface of the operation unit; the 0 input terminal of the tenth data selector is connected to the output terminal of the ninth data selector; the first input terminal of the floating-point adder / subtractor is connected to the output terminal of the floating-point multiplier, and the second input terminal of the floating-point adder / subtractor is connected to the output terminal of the tenth data selector; the input terminal of the register is connected to the output terminal of the floating-point adder / subtractor, the output terminal of the register is connected to the 1 input terminal of the tenth data selector and the output interface of the operation unit, and the clear terminal of the register is connected to the clear interface of the operation unit;

[0014] Among them, the seventh data selector, the eighth data selector, the ninth data selector, and the tenth data selector are used to select the data input from the 0 input terminal or the 1 input terminal according to the configuration command to be transmitted to the floating-point multiplier and the floating-point adder / subtractor, so that the floating-point multiplier and the floating-point adder / subtractor perform real number operations; the registers are used to store the primary calculation results of the floating-point multiplier and the floating-point adder / subtractor.

[0015] In a third aspect, an embodiment of the present invention provides a super operation unit, the super operation unit comprising: a first operation unit, a first data selector, a second operation unit, a second data selector, a secondary buffer memory, a third operation unit, a third data selector, a fourth data selector, a fifth data selector, a fourth operation unit, a sixth data selector, and an inverter;

[0016] The 1 input terminal of the first data selector is connected to the output interface of the first operation unit; the third input interface of the second operation unit is connected to the output terminal of the first data selector; the 1 input terminal of the second data selector is connected to the output interface of the second operation unit; the first input terminal of the secondary buffer memory is connected to the output terminal of the second data selector; the 1 input terminal of the third data selector is connected to the output interface of the first operation unit, and the output terminal of the third data selector is connected to the second input terminal of the secondary buffer memory; the 1 input terminal of the fourth data selector is connected to the output interface of the third operation unit, and the output terminal of the fourth data selector is connected to the third input terminal of the secondary buffer memory; the 1 input terminal of the fifth data selector is connected to the output interface of the third operation unit; the third input interface of the fourth operation unit is connected to the output terminal of the fifth data selector; the 1 input terminal of the sixth data selector is connected to the output interface of the fourth operation unit, and the output terminal of the sixth data selector is connected to the fourth input terminal of the secondary buffer memory; the configuration input interface is respectively connected to the configuration interfaces of the third data selector and the fourth data selector through an inverter, and the configuration input interface is also respectively connected to the configuration interfaces of the first data selector, the second data selector, the fifth data selector, and the sixth data selector;

[0017] Among them, the first data selector, the second data selector, the third data selector, the fourth data selector, the fifth data selector, and the sixth data selector are used to select the data input from the 1 input terminal or the 0 input terminal according to the configuration command to be transmitted to the operation unit connected to itself, so that the first operation unit, the second operation unit, the third operation unit, and the fourth operation unit perform real number operations and / or complex number operations according to the beamforming algorithm to obtain intermediate results, and the secondary buffer memory is used to store the intermediate results.

[0018] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the reconfigurable computing array in the super-structure chip of the present invention is composed of super-computing units that can perform real number operations and complex number operations, the super-structure chip in the present invention can perform matrix operations on the collected data and realize beamforming processing on the collected data; since the super-computing units and the computing units in the chip can adjust the data transmission links and connection relationships through configuration commands, the super-structure chip in the present invention can adjust the hardware structure of the computing units according to different beamforming algorithms, and there is no need to set a computing module for each different beamforming algorithm, thereby reducing the area overhead of the chip and reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a digital array signal processing super-structure chip provided by an embodiment of the present invention;

[0020] Figure 2A schematic diagram of the structure of a reconfigurable computing array provided by an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of the structure of a computing unit provided by an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of the structure of a super computing unit provided in an embodiment of the present invention.

[0023] Reference numerals:

[0024] 1: Multi-channel communication interface; 2: Reconfigurable computing array; 21: Array state configurator; 22: State configuration buffer memory; 23: Super operation unit; 231: First operation unit; 232: First data selector; 233: Second operation unit; 2331: Seventh data selector; 2332: Eighth data selector; 2333: Floating-point multiplier; 2334: Ninth data selector; 2335: Tenth data selector; 2336: Floating-point adder / subtractor; 2337: Register ; 234: second data selector; 235: secondary buffer memory; 236: third data selector; 237: third operation unit; 238: fourth data selector; 239: fifth data selector; 2310: fourth operation unit; 2311: sixth data selector; 2312: inverter; 24: read address generation module; 25: write address generation module; 26: input buffer memory; 27: output buffer memory; 28: result output buffer memory; 3: dynamic random access memory; : Configuration interface of the seventh data selector; : Configuration interface of the eighth data selector; : Configuration interface of the ninth data selector; : Configuration interface of the tenth data selector; : Configure input interface; : Configuration interface of the first data selector; : Configuration interface of the second data selector; : Configuration interface of the third data selector; : Configuration interface of the fourth data selector; : Configuration interface of the fifth data selector; : Configuration interface of the sixth data selector; CLE: Clear interface of the operation unit. DETAILED DESCRIPTION

[0025] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0026] Example 1

[0027] Figure 1 The structure diagram of a digital array signal processing super structure chip provided by an embodiment of the present invention is shown. As an example but not limitation, the digital array signal processing super structure chip may include a multi-channel communication interface 1, a reconfigurable computing array 2, and a dynamic random access memory 3.

[0028] Specifically, see Figure 1 The multi-channel communication interface 1 may include multiple communication interfaces, and its output end may be connected to the input end of the dynamic random access memory 3. The dynamic random access memory 3 is connected to the reconfigurable computing array (i.e., CGRA computing array) 2 through a write data line, a write address line, a read data line, and a read address line.

[0029] Exemplarily, the collected data of each array element of the external digital array radar can be transmitted to the superstructure chip through the corresponding communication interface. Each data corresponds to a unique storage address code to ensure accurate data storage. The reconfigurable computing array 2 is used to perform matrix operations on the collected data according to a preset beamforming algorithm to obtain beamformed data. The dynamic random access memory 3 is used to store the collected data and the beamformed data.

[0030] Optionally, the multi-channel communication interface 1 may support parallel data transmission, which can improve the speed and bandwidth of data input.

[0031] In one example, the reconfigurable computing array can be composed of multiple super computing units, for example, 4096 super computing units with 64 rows and 64 columns; and each super computing unit can be composed of multiple computing units, for example, 4. Each super computing unit and computing unit are used to adjust the data transmission link and / or connection relationship according to the configuration command to adapt to different beamforming algorithms. Each super computing unit can perform real number operations and / or complex number operations on the collected data according to the beamforming algorithm, and each computing unit can perform real number operations on the collected data according to the beamforming algorithm. Therefore, the reconfigurable computing array composed of multiple super computing units can perform matrix operations on the collected data.

[0032] Exemplarily, the real number operation may include one or more of the following: real number multiplication, real number addition, real number multiplication and addition mixed operation, real number accumulation operation, and real number self-increment counting operation.

[0033] Exemplarily, the complex operations may include complex addition and / or complex multiplication.

[0034] Exemplarily, the matrix operation may include one or more of the following: matrix addition, matrix multiplication, matrix transposition, and matrix inversion.

[0035] Since division and subtraction can be implemented by multiplication and addition respectively, no special explanation is given here.

[0036] In one example, the reconfigurable computing array 2 can also be used to transmit the read address of the collected data to be read to the dynamic random access memory 3 through the read address line, and the dynamic random access memory 3 transmits the collected data to be read to the reconfigurable computing array 2 through the read data line. The reconfigurable computing array 2 performs matrix operations on these data to obtain beamformed data, and then transmits the write address of the beamformed data to be written to the dynamic random access memory 3 through the write address line. The dynamic random access memory 3 obtains the beamformed data to be written from the reconfigurable computing array 2 through the write data line and writes it to the write address. The calculation results (i.e., the beamformed data) in the dynamic random access memory 3 can be output to an external device through the multi-channel communication interface 1.

[0037] Since the reconfigurable computing array in the super-structure chip of the present invention is composed of super-computing units that can perform real number operations and complex number operations, the super-structure chip in the present invention can perform matrix operations on the collected data and realize beamforming processing of the collected data; since the super-computing units and the computing units in the chip can adjust the data transmission links and connection relationships through configuration commands, the super-structure chip in the present invention can adjust the hardware structure of the computing unit according to different beamforming algorithms, and there is no need to set a computing module for each different beamforming algorithm, thereby reducing the area overhead of the chip and reducing power consumption. Furthermore, the reconfigurable computing array and the dynamic random access memory in the chip use different data lines and address lines to transmit different data and addresses, which can accurately manage the flow of data and control functions, thereby improving the performance of the chip in complex computing and real-time data processing applications.

[0038] Example 2

[0039] Based on Example 1, Figure 2 Shown is a schematic diagram of the structure of a reconfigurable computing array provided by an embodiment of the present invention.

[0040] As an example but not limitation, the reconfigurable computing array 2 may include: an array state configurator 21 , a state configuration buffer memory 22 , and a plurality of super computing units 23 .

[0041] Specifically, the super operation units 23 can be connected through a row bus and a column bus, the state configuration buffer memory 22 is connected to each super operation unit 23 through the row bus, and the input end of the state configuration buffer memory 22 is connected to the first output end of the array state configurator 21 through the state configuration command line.

[0042] Exemplarily, the array state configurator 21 can generate a configuration command according to the beamforming algorithm to configure the data transmission link and / or connection relationship of the super operation unit. The state configuration buffer memory 22 can store and send the corresponding configuration command to each super operation unit. After the super operation unit 23 completes the configuration according to the configuration command, it can perform real number operation and complex number operation on the collected data according to the beamforming algorithm to obtain the beamformed data.

[0043] In a possible implementation, the array state configurator 21 may first generate an initial configuration command according to the beamforming algorithm to initially configure the super operation unit 23. Then, the beamforming algorithm is disassembled into multiple calculation frames according to the requirements of the beamforming algorithm for hardware resources, and configuration commands, read commands, and write commands corresponding to each calculation frame are generated. The array state configurator 21 may store the configuration commands corresponding to each current calculation frame in the state configuration buffer memory 22, and then the state configuration buffer memory 22 sends them to each super operation unit 23 through each row bus. The super operation unit 23 adjusts the connection relationship of its internal operation units and the data transmission link structure according to the configuration command corresponding to the current calculation frame to realize the hardware calculation circuit structure required by the current calculation frame.

[0044] In an example, the reconfigurable computing array 2 may further include a read address generation module 24 , a write address generation module 25 , an input buffer memory 26 , an output buffer memory 27 , and a result output buffer memory 28 .

[0045] Specifically, the second output terminal and the third output terminal of the array state configurator 21 are connected to the read address generation module 24 and the write address generation module 25 through the read command line and the write command line respectively; the fourth output terminal of the array state configurator 21 is connected to the input buffer memory 26 through the data distribution line. The input buffer memory 26 and the output buffer memory 27 are connected to each super operation unit 23 through the column bus. The result output buffer memory 28 is connected to each super operation unit 23 through the row bus. The read address generation module 24 is connected to the dynamic random access memory 3 through the read address line, the write address generation module 25 is connected to the dynamic random access memory 3 through the write address line, and the result output buffer memory 28 is connected to the dynamic random access memory 3 through the write data line.

[0046] Exemplarily, the read address generation module 24 can generate the read address of the acquisition data required for the current calculation frame according to the read command, and send the read address to the dynamic random access memory 3 through the read address line. The write address generation module 25 can generate the write address of the beamformed data according to the write command, and send it to the dynamic random access memory 3 through the write address line. The input buffer memory 26 is used to store the acquisition data read according to the current calculation frame, and send the corresponding acquisition data processed by it to each super operation unit through the column bus. Generally, if the beamformed data needs to go through multiple calculation frames to obtain, the super operation unit can send the intermediate results to the output buffer memory 27 through the column bus for storage; when these intermediate results are needed for subsequent calculations, they are obtained from the output buffer memory 27 through the column bus. The result output buffer memory 28 can be used to store the beamformed data calculated by the last calculation frame, and can also transmit the beamformed data to the dynamic random access memory 3 through the write data line. The row bus and the column bus can communicate with each other and exchange data.

[0047] Optionally, the state configuration buffer memory 22, the read address generation module 24, the write address generation module 25, the input buffer memory 26, the output buffer memory 27 and the result output buffer memory 28 can all be static random access memory (SRAM).

[0048] Through this flexible and efficient data transmission and computing configuration, the configurable computing array 2 can meet the real-time, high-precision and high-computation requirements of the digital array radar beamforming algorithm.

[0049] Example 3

[0050] Figure 3 Shown is a schematic diagram of the structure of a computing unit provided in an embodiment of the present invention.

[0051] By way of example and not limitation, see Figure 3 The operation unit may include a seventh data selector 2331, an eighth data selector 2332, a floating-point multiplier 2333, a ninth data selector 2334, a tenth data selector 2335, a floating-point adder / subtractor 2336, and a register 2337.

[0052] Specifically, see Figure 3, the 1 input terminal of the seventh data selector 2331 is connected to the first input interface of the operation unit, the 1 input terminal of the eighth data selector 2332 is connected to the second input interface of the operation unit, and the first input terminal and the second input terminal of the floating-point multiplier 2333 are respectively connected to the output terminals of the seventh data selector 2331 and the eighth data selector 2332. The 0 input terminals of the seventh data selector 2331, the eighth data selector 2332, and the ninth data selector 2334 are respectively connected to an interface line with a bit width of 1. The 1 input terminal of the ninth data selector 2334 is connected to the third input interface of the operation unit. The 0 input terminal of the tenth data selector 2335 is connected to the output terminal of the ninth data selector 2334, and the 1 input terminal is connected to the output terminal of the register 2337. The output terminal of the register 2337 is also connected to the output interface of the operation unit. The input terminal of the register 2337 is connected to the output terminal of the floating-point adder / subtractor 2336, and the clear terminal is connected to the clear interface CLE of the operation unit.

[0053] Optionally, the bit width of the first input interface and the second input interface of the operation unit may be 16 bits, and the bit width of the third input interface and the output interface may be 32 bits.

[0054] For example, see Figure 3 The first input interface and the second input interface of the operation unit can respectively input 16-bit data A and B with a data structure of [15:0], and the third input interface can input 32-bit data C with a data structure of [31:0], and then the output interface outputs the data structure [31:0] as 32-bit data D.

[0055] In some embodiments, see Figure 3 , configuration interface of the seventh data selector 2331 , Configuration interface of the eighth data selector 2332 , Configuration interface of the ninth data selector 2334 , Configuration interface of the tenth data selector 2335 They are respectively connected to an interface line with a bit width of 1 for receiving configuration commands.

[0056] Exemplarily, the seventh data selector 2331, the eighth data selector 2332, the ninth data selector 2334, and the tenth data selector 2335 can select the data input from the 1 input terminal or the 0 input terminal according to the configuration command, and input it to the floating-point multiplier 2333 and the floating-point adder / subtractor 2336, so that the floating-point multiplier 2333 and the floating-point adder / subtractor 2336 perform real number operations on the input data. The register 2337 is used to store the primary calculation results obtained by the floating-point multiplier 2333 and the floating-point adder / subtractor 2336.

[0057] In a possible implementation, the configuration command may consist of data bits for each data selector.

[0058] Specifically, the configuration commands can refer to the following Table 1:

[0059] Table 1

[0060]

[0061] In one example, referring to Table 1, when the configuration command is 1100, the seventh data selector 2331 selects data A at the 1 input terminal to the floating-point multiplier 2333. The eighth data selector 2332 selects data B at the 1 input terminal to the floating-point multiplier 2333. The ninth data selector 2334 selects 0 at the 0 input terminal to the tenth data selector 2335. The tenth data selector 2335 selects 0 at the 0 input terminal to the floating-point adder / subtractor 2336, so that real number multiplication can be performed to realize D=A×B. The output interface outputs D. The operation unit in the configuration command state is equivalent to deleting the connection relationship between the output terminal of the tenth data selector 2335 and the input terminal of the floating-point adder / subtractor 2336.

[0062] In one example, referring to Table 1, when the configuration command is 1010, the data transmission link inside the operation unit can be adjusted through the configuration command; the input of the floating-point adder / subtractor 2336 is the data A of the first input interface and the data C of the second input interface; and at the same time, it is equivalent to deleting the connection relationship between the output end of the register 2337 and the 1 input end of the tenth data selector 2335. In this state, the operation unit can perform real number addition operations to achieve D=A+C.

[0063] In one example, referring to Table 1, when the configuration command is 1110, the data transmission link inside the operation unit can be adjusted through the configuration command so that the input of the floating-point multiplier 2333 is A and B; the input of the floating-point adder / subtractor 2336 is A×B and C, and real number multiplication and addition mixed operations can be performed to achieve D=A×B+C.

[0064] In one example, referring to Table 1, when the configuration command is 1101, the inputs of the floating-point multiplier 2333 are A and B. A×B and the primary calculation result obtained in the previous calculation frame are input to the floating-point adder / subtractor 2336 through the output interface. . Real number accumulation operation can be performed to achieve D=A×B+ .

[0065] In one example, referring to Table 1, when the configuration command is 0010, the input of the floating-point multiplier 2333 is two 0s. The input of the floating-point adder / subtractor 2336 is C, 0. The initial state of the real number self-increment counting operation can be performed to achieve D=C+1. When the configuration command is 0001, the input of the floating-point multiplier 2333 is two 0s. The input of the floating-point adder / subtractor 2336 is the primary calculation result. , 0. Normal real number increment operations can be performed to achieve D= +1.

[0066] Example 4

[0067] Based on Example 3 or in combination with Example 1 and Example 2, Figure 4 Shown is a schematic diagram of the structure of a super computing unit provided in an embodiment of the present invention.

[0068] As an example but not limitation, the super operation unit 23 may include: a first operation unit 231, a first data selector 232, a second operation unit 233, a second data selector 234, a secondary buffer memory 235, a third data selector 236, a third operation unit 237, a fourth data selector 238, a fifth data selector 239, a fourth operation unit 2310, a sixth data selector 2311, and an inverter 2312.

[0069] Exemplarily, the first operation unit 231 , the second operation unit 233 , the third operation unit 237 , and the fourth operation unit 2310 may all be operation units with the same structure as those shown in Embodiment 3.

[0070] Specifically, the 1 input terminal of the first data selector 232 may be connected to the output interface of the first operation unit 231, the third input interface of the second operation unit 233 may be connected to the output terminal of the first data selector 232, and the output interface may be connected to the 1 input terminal of the second data selector 234. The output terminal of the second data selector 234 may be connected to the first input terminal of the secondary buffer memory 235. The 1 input terminal of the third data selector 236 may also be connected to the output interface of the first operation unit 231, and the output terminal may be connected to the second input terminal of the secondary buffer memory 235. The output interface of the third operation unit 237 may be connected to the 1 input terminal of the fourth data selector 238 and the 1 input terminal of the fifth data selector 239. The output terminal of the fourth data selector 238 may be connected to the third input terminal of the secondary buffer memory 235. The output terminal of the fifth data selector 239 may be connected to the third input interface of the fourth operation unit 2310. The output interface of the fourth operation unit 2310 may be connected to the 1 input terminal of the sixth data selector 2311. The output terminal of the sixth data selector 2311 can be connected to the fourth input terminal of the secondary buffer memory 235. Configuring the Input Interface The configuration interface of the third data selector 236 is respectively connected to the inverter 2312 , configuration interface of the fourth data selector 238 connected to the configuration interface of the first data selector 232 , configuration interface of the second data selector 234 , Configuration interface of the fifth data selector 239 , Configuration interface of the sixth data selector 2311 Directly connected.

[0071] In one possible implementation, the configuration command can be configured via the input interface Input to the configuration interface of each data selector. Then each data selector selects the data of the 1 input terminal or the 0 input terminal according to the configuration command and sends it to the operation unit connected to itself for subsequent operation, or stores it in the secondary buffer memory 235.

[0072] Optionally, configure the input interface The bit width can be 1 bit.

[0073] In one example, when performing complex number addition, the input interface is configured Output 0, then the configuration command of the super computing unit ( ) can be 001100. At the same time, the first operation unit 231 and the third operation unit 237 are configured for real number addition operation. The first input interface and the second input interface of the first operation unit 231 respectively input the real parts of two complex numbers. a ,c The first input interface and the second input interface of the third operation unit 237 respectively input the imaginary parts of two complex numbers b , d ; Complex number addition can be realized: ,in A plural unit.

[0074] In one example, when performing complex number addition, the input interface is configured Output 1, then the configuration command of the super operation unit can be 110011. The first operation unit 231 and the third operation unit 237 are configured as real number multiplication operations, and complex number multiplication operations can be performed: .

[0075] The super-structure chip provided by the present invention includes a multi-level memory architecture: the first level is a dynamic random access memory 3; the second level is an input buffer memory 26, a state configuration buffer memory 22, an output buffer memory 27, and a result output buffer memory 28; the third level is a secondary buffer memory 235. The multi-level memory architecture can flexibly select the storage location of the calculated data, the intermediate results, and the data after beamforming according to the algorithm requirements and the current calculation frame; thereby achieving high-speed multi-level data access. Because the digital beamforming algorithm involves multiple recursive data calculations, the multi-level memory architecture provided by the present invention can improve the interconnection communication efficiency in the data calculation process, save a lot of time consumed by data access, improve the real-time performance of the chip, and further improve the bandwidth.

[0076] At the same time, the floating-point adder / subtractor and floating-point multiplier in the present invention strictly follow the binary floating-point arithmetic standard to ensure that the processing of the sign bit, exponent bit and mantissa bit, as well as the rounding mode and exception handling, all meet the standard. Through extensive testing of different floating-point operations, it can be found that the operation results are completely consistent with the floating-point operation results of modern central processing units (Central Processing Units, CPUs), proving that the chip provided by the present invention has reached the accuracy required by the binary floating-point arithmetic standard. Detailed accuracy test results further show that the relative errors of the operation results of the randomly generated floating-point pairs are all within the standard range, ensuring the calculation accuracy and consistency of the present invention.

[0077] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A digital array signal processing superstructure chip, characterized in that: include: A multi-channel communication interface, wherein the multi-channel communication interface is used to receive collected data from each array element of the radar; A reconfigurable computing array, wherein the reconfigurable computing array is used to perform matrix operations on the collected data according to a beamforming algorithm to obtain beamformed data, wherein the matrix operations include one or more of the following: matrix multiplication, matrix addition, matrix transposition, and matrix inversion; The reconfigurable computing array includes a plurality of super computing units, and the super computing unit includes a plurality of computing units. Each of the computing units and the super computing unit is used to adjust the data transmission link and / or the connection relationship according to the configuration command to adapt to different beamforming algorithms; the computing unit is also used to perform real number operations on the collected data according to the beamforming algorithm, and the super computing unit is also used to perform real number operations and / or complex number operations on the collected data according to the beamforming algorithm; A dynamic random access memory, wherein the dynamic random access memory is used to store the collected data and the beamformed data; Wherein, the reconfigurable computing array comprises: An array state configurator, the array state configurator being used to generate a configuration command according to the beamforming algorithm to configure a data transmission link and / or a connection relationship between the super computing unit and the computing unit; A state configuration buffer memory, the state configuration buffer memory is used to store and send the configuration command to each super computing unit; A plurality of super operation units, wherein the super operation units are used to perform real number operation and / or complex number operation on the collected data according to the beamforming algorithm to obtain the beamformed data; The super operation units are connected via a row bus and a column bus, the state configuration buffer memory is connected to the super operation unit via the row bus, and the input end of the state configuration buffer memory is connected to the first output end of the array state configurator via a state configuration command line; The input end of the dynamic random access memory is connected to the output end of the multi-channel communication interface, and the dynamic random access memory is connected to the reconfigurable computing array through a write data line, a write address line, a read data line, and a read address line.

2. The digital array signal processing superstructure chip according to claim 1, characterized in that: The reconfigurable computing array is used to send a read address of the collected data to be read to the dynamic random access memory through the read address line; The dynamic random access memory is used to read the to-be-read collected data according to the read address and send the to-be-read collected data to the reconfigurable computing array through the read data line; The reconfigurable computing array is also used to send the write address of the beamformed data to be written to the dynamic random access memory through the write address line; and send the beamformed data to be written to the dynamic random access memory through the write data line.

3. The digital array signal processing superstructure chip according to claim 2, characterized in that: The array state configurator is specifically used for: Decomposing the beamforming algorithm into a plurality of computation frames; A plurality of frame configuration commands corresponding to the computing frames in a one-to-one manner are generated according to the computing frames.

4. The digital array signal processing superstructure chip according to claim 3, characterized in that: The input end of the array state configurator is connected to the dynamic random access memory through the read data line; the array state configurator is also used to generate a read command and a write command according to the calculation frame; Wherein, the reconfigurable computing array further includes: A read address generation module, the read address generation module is used to generate the read address according to the read command, and send the read address to the dynamic random access memory through the read address line; A write address generation module, the write address generation module is used to generate the write address according to the write command, and send the write address to the dynamic random access memory through the write address line; An input buffer memory, the input buffer memory is used to store the collected data read according to the current calculation frame, and send the collected data read according to the current calculation frame to each of the super computing units through the column bus; an output buffer memory, the output buffer memory being used to receive and / or send, through the column bus, an intermediate result obtained by the super computing unit performing calculations according to the current computing frame, and the output buffer memory being also used to store the intermediate result; A result output buffer memory, wherein the result output buffer memory is used to store the beamformed data; Among them, the second output end and the third output end of the array state configurator are connected to the read address generation module and the write address generation module through a read command line and a write command line respectively; the fourth output end of the array state configurator is connected to the input buffer memory through a data distribution line, the input buffer memory and the output buffer memory are connected to each of the super operation units through the column bus, and the result output buffer memory is connected to each of the super operation units through the row bus.

5. The digital array signal processing superstructure chip according to claim 4, characterized in that: The super computing unit comprises: A first arithmetic unit; A first data selector, wherein an input terminal 1 of the first data selector is connected to an output interface of the first operation unit; a second operation unit, wherein a third input interface of the second operation unit is connected to an output end of the first data selector; A second data selector, wherein an input terminal 1 of the second data selector is connected to an output interface of the second operation unit; A secondary buffer memory, wherein a first input terminal of the secondary buffer memory is connected to an output terminal of the second data selector; a third data selector, wherein an input terminal 1 of the third data selector is connected to an output interface of the first operation unit, and an output terminal of the third data selector is connected to a second input terminal of the secondary buffer memory; The third operation unit; a fourth data selector, wherein an input terminal 1 of the fourth data selector is connected to the output interface of the third operation unit, and an output terminal of the fourth data selector is connected to the third input terminal of the secondary buffer memory; a fifth data selector, wherein an input terminal 1 of the fifth data selector is connected to an output interface of the third operation unit; a fourth operation unit, wherein a third input interface of the fourth operation unit is connected to an output end of the fifth data selector; a sixth data selector, wherein an input terminal 1 of the sixth data selector is connected to the output interface of the fourth operation unit, and an output terminal of the sixth data selector is connected to a fourth input terminal of the secondary buffer memory; an inverter, wherein the configuration input interface is respectively connected to the configuration interfaces of the third data selector and the fourth data selector through the inverter, and the configuration input interface is also respectively connected to the configuration interfaces of the first data selector, the second data selector, the fifth data selector, and the sixth data selector; Among them, the first data selector, the second data selector, the third data selector, the fourth data selector, the fifth data selector, and the sixth data selector are used to select the data input from the 1 input terminal or the 0 input terminal according to the configuration command to be transmitted to the operation unit connected to itself, so as to make the first operation unit, the second operation unit, the third operation unit, and the fourth operation unit perform the real number operation and / or the complex number operation according to the beamforming algorithm to obtain the intermediate result, and the secondary buffer memory is used to store the intermediate result.

6. The digital array signal processing superstructure chip according to claim 5, characterized in that: The first computing unit, the second computing unit, the third computing unit, and the fourth computing unit have the same structure; Wherein, the second operation unit includes: a seventh data selector, wherein an input terminal 1 of the seventh data selector is connected to a first input interface of the second operation unit; an eighth data selector, wherein an input terminal 1 of the eighth data selector is connected to a second input interface of the second operation unit; A floating-point multiplier, wherein the output terminals of the seventh data selector and the eighth data selector are respectively connected to the first input terminal and the second input terminal of the floating-point multiplier; a ninth data selector, wherein an input terminal 1 of the ninth data selector is connected to a third input interface of the second operation unit; a tenth data selector, wherein a zero input terminal of the tenth data selector is connected to an output terminal of the ninth data selector; a floating-point adder / subtractor, wherein a first input terminal of the floating-point adder / subtractor is connected to an output terminal of the floating-point multiplier, and a second input terminal of the floating-point adder / subtractor is connected to an output terminal of the tenth data selector; A register, wherein the input end of the register is connected to the output end of the floating-point adder / subtractor, the output end of the register is connected to the 1 input end of the tenth data selector and the output interface of the second operation unit, and the reset end of the register is connected to the reset interface of the second operation unit; Among them, the seventh data selector, the eighth data selector, the ninth data selector, and the tenth data selector are used to select the data input from the 1 input terminal or the 0 input terminal according to the configuration command to be transmitted to the floating-point multiplier and the floating-point adder / subtractor, so as to enable the floating-point multiplier and the floating-point adder / subtractor to perform the real number operation; the register is used to store the primary calculation results of the floating-point multiplier and the floating-point adder / subtractor.

7. The digital array signal processing superstructure chip according to claim 6, characterized in that: The configuration command consists of a data bit for each data selector.

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