A solar cell and photovoltaic module

Abstract

The application provides a solar cell and a photovoltaic module, and relates to the technical field of photovoltaics.The solar cell comprises a silicon substrate; the silicon substrate comprises a first side and a second side; a first semiconductor layer is located on the first side; a first conductive layer is located on the side of the first semiconductor layer away from the silicon substrate; and the roughness of the interface between the first semiconductor layer and the silicon substrate is smaller than the roughness of the interface between the first semiconductor layer and the first conductive layer.The interface between the first semiconductor layer and the silicon substrate is relatively smooth, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, reducing the requirement for the thickness of the first semiconductor layer, reducing the light absorption of the first semiconductor layer, and improving the short circuit current of the cell.The interface between the first semiconductor layer and the first conductive layer is relatively rough, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, and is beneficial to improving the fill factor.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. BACKGROUND

[0002] Solar cells can convert solar energy into electric energy, and thus have a wide application prospect due to the use of clean energy.

[0003] A thicker semiconductor layer in a solar cell can effectively improve the passivation performance. However, a thicker semiconductor layer is beneficial to passivation but is not conducive to the transmission of photo-generated carriers and the improvement of fill factor, that is, there is a contradiction between the improvement of passivation performance and the improvement of fill factor of the semiconductor layer, resulting in poor performance of the solar cell. SUMMARY

[0004] The present application provides a solar cell and a photovoltaic module, and aims to solve the problem of the contradiction between the improvement of passivation performance and the improvement of fill factor of the semiconductor layer of the existing solar cell.

[0005] In a first aspect of the present application, a solar cell is provided, comprising:

[0006] a silicon substrate, the silicon substrate comprising: opposite first and second sides;

[0007] a first semiconductor layer on the first side;

[0008] a first conductive layer on a side of the first semiconductor layer away from the silicon substrate;

[0009] In a cross-section of the solar cell, the roughness of the interface line between the first semiconductor layer and the silicon substrate is less than the roughness of the interface line between the first semiconductor layer and the first conductive layer.

[0010] In the embodiment of the present application, the roughness of the interface between the first semiconductor layer and the silicon substrate is smaller than the roughness of the interface between the first semiconductor layer and the first conductive layer, that is, the interface between the first semiconductor layer and the silicon substrate is relatively smooth, or the first semiconductor layer and the silicon substrate have a relatively smooth contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer, and further improving the short circuit current of the battery. At the same time, the interface between the first semiconductor layer and the first conductive layer is relatively rough, or the first semiconductor layer and the first conductive layer have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell battery. Moreover, the interface between the first semiconductor layer and the first conductive layer is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short circuit current. In summary, through the smooth interface between the first semiconductor layer and the silicon substrate, and the rough interface between the first semiconductor layer and the first conductive layer, the present application solves the problem of contradiction between the improvement of the passivation performance of the first semiconductor layer of the existing solar cell and the improvement of the fill factor, not only improves the passivation effect of the interface, thereby improving the open circuit voltage, but also improves the fill factor and short circuit current of the solar cell battery.

[0011] Optionally, the first semiconductor layer comprises: a first surface close to the first conductive layer; the first surface comprises a plurality of concave-convex structures; at least part of the concave-convex structures in the first surface are arranged in order.

[0012] Optionally, the surface roughness of the interface between the first semiconductor layer and the first conductive layer is greater than the surface roughness of the silicon substrate.

[0013] Optionally, the roughness of the interface between the first semiconductor layer and the silicon substrate is less than or equal to 1.5 nm; and / or,

[0014] The roughness of the interface between the first semiconductor layer and the first conductive layer is greater than 1.5 nm.

[0015] Optionally, the first semiconductor layer is composed of a intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in a stack; the intrinsic amorphous silicon layer is arranged immediately adjacent to the silicon substrate.

[0016] Optionally, the solar cell further comprises: a second semiconductor layer and a second conductive layer disposed on the second side of the silicon substrate; the first semiconductor layer and the second semiconductor layer are of different doping types; and a roughness of an interface between the second semiconductor layer and the silicon substrate on the second side of the solar cell is less than a roughness of an interface between the second semiconductor layer and the second conductive layer.

[0017] Optionally, the silicon substrate and the first semiconductor layer are of the same doping type, and a roughness of an interface between the first semiconductor layer and the first conductive layer is greater than a roughness of an interface between the second semiconductor layer and the second conductive layer.

[0018] Optionally, the solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer disposed on the second side of the silicon substrate in a stack; the tunneling oxide layer is immediately adjacent to the silicon substrate; and the doped amorphous silicon layer and the doped polysilicon layer are of different doping types.

[0019] Optionally, the first side surface of the silicon substrate comprises: first conductive regions and second conductive regions distributed at intervals;

[0020] the first semiconductor layer is disposed on the first conductive regions and the second conductive regions; a portion of the first semiconductor layer on the first conductive regions and a portion of the first semiconductor layer on the second conductive regions are of different doping types; or,

[0021] the first side surface of the silicon substrate comprises: first conductive regions and second conductive regions distributed at intervals;

[0022] the first semiconductor layer is disposed on the first conductive regions;

[0023] the solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer disposed on the second conductive regions in a stack; the tunneling oxide layer is immediately adjacent to the silicon substrate; and the first semiconductor layer and the doped polysilicon layer are of different doping types.

[0024] Optionally, a roughness of an interface between the doped polysilicon layer on the second conductive regions and the first conductive layer is greater than a roughness of an interface between the first semiconductor layer and the first conductive layer.

[0025] Optionally, a doping concentration of a portion of the first semiconductor layer close to the first conductive layer is greater than a doping concentration of a portion of the first semiconductor layer close to the silicon substrate.

[0026] In a second aspect, the present application provides a photovoltaic module comprising: a plurality of any of the solar cells.

[0027] The above-mentioned solar cell and photovoltaic module both have the same or similar beneficial effects, and thus the description thereof will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments of the present application will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0029] Figure 1 A partial transmission electron microscope image of a solar cell in an embodiment of the present application is shown;

[0030] Figure 2 A partial transmission electron microscope image of a first semiconductor layer close to a first surface of a first conductive layer in an embodiment of the present application is shown;

[0031] Figure 3 A partial transmission electron microscope image of a first semiconductor layer close to a second surface of a silicon substrate in an embodiment of the present application is shown;

[0032] Figure 4 A structural schematic diagram of a solar cell in an embodiment of the present application is shown.

[0033] BRIEF DESCRIPTION OF DRAWINGS

[0034] a-ion beam deposition of platinum, b-ion beam deposition of platinum, c-first conductive layer, d-first semiconductor layer, e-silicon substrate, 11-intrinsic amorphous silicon layer, 12-doped amorphous silicon layer, 13-second semiconductor, 14-second conductive layer, 2-first electrode, 3-second electrode. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort fall within the protection scope of the present application.

[0036] Transmission electron microscope is abbreviated as TEM (Transmission Electron Microscope). The TEM in the present application can also be replaced by SEM (Scanning Electron Microscope) and the like, which is not specifically limited.

[0037] The present application provides a solar cell, referring to Figure 1 The solar cell can include a silicon substrate e, wherein the doping type, structure, and the like of the silicon substrate are not specifically limited. The silicon substrate includes opposite first and second sides, wherein one of the first and second sides is a light-receiving side and the other is a back light-receiving side. During normal operation of the solar cell, the side of the silicon substrate that mainly receives light is the light-receiving side, and the back light-receiving side is opposite to the light-receiving side. Figure 1 In some embodiments, the surface of the silicon substrate e can have a textured structure, Figure 1 In some embodiments, the protruding corner of the silicon substrate e is a textured structure.

[0038] The solar cell further includes a first semiconductor layer d located on the first side of the silicon substrate e, that is, the first semiconductor layer d is only located on the first side of the silicon substrate e. The first side of the silicon substrate e can be the back light-receiving side or the light-receiving side, and no specific limitation is made thereto. Referring to Figure 1 The silicon substrate e and the first semiconductor layer d are in direct contact. The inventors have found that the first semiconductor layer d in the solar cell can effectively passivate the dangling bond defects of the silicon substrate, reduce activity, thereby reducing the rate of minority carrier recombination, obtaining a longer minority carrier lifetime, improving the open-circuit voltage of the solar cell, and enhancing the performance of the solar cell. However, a thicker first semiconductor layer d is beneficial to the passivation of the defects of the silicon substrate, but is not conducive to the transmission of photo-generated carriers and the improvement of the fill factor and short-circuit current, that is, there is a contradiction between the improvement of the passivation performance and the improvement of the fill factor of the first semiconductor layer d, resulting in poor performance of the solar cell.

[0039] The solar cell further includes a first conductive layer c located on the side of the first semiconductor layer d away from the silicon substrate e. In the case where the first semiconductor layer d is located on the first side of the silicon substrate e, the first conductive layer c is also located on the first side of the silicon substrate e, and the silicon substrate e, the first semiconductor layer d, and the first conductive layer c are sequentially stacked and in contact with each other. The intersection line between the first semiconductor layer d and the silicon substrate e refers to the boundary between the profile line of the first semiconductor layer d and the profile line of the silicon substrate e that overlap each other in the cross section of the solar cell. In Figure 1 In some embodiments, the intersection line between the first semiconductor layer d and the silicon substrate e is a clear and straight boundary at the intersection of the first semiconductor layer d and the silicon substrate e. The intersection line between the first semiconductor layer d and the first conductive layer c refers to the edges of the first semiconductor layer d and the first conductive layer c that are in contact with each other, and the boundary that is connected is the part of the profile lines of the two that overlap each other, in Figure 1 In some embodiments, the intersection line between the first semiconductor layer d and the first conductive layer c is a boundary that is uneven and relatively blurred at the intersection of the first semiconductor layer d and the first conductive layer c.

[0040] The roughness of the interface line refers to the concave-convex degree of the interface line, or the uneven degree caused by the micro-convex or micro-concave in the interface line, which can be the fluctuation degree of the interface line. To solve the above technical problems, in the solar cell, the roughness of the interface line between the first semiconductor layer d and the silicon substrate e is smaller than the roughness of the interface line between the first semiconductor layer d and the first conductive layer c. For example, the number of convexities and / or concavities of the interface line between the first semiconductor layer d and the silicon substrate e can be smaller than the number of convexities and / or concavities of the interface line between the first semiconductor layer d and the first conductive layer c; or the degree of convexity and / or concavity of the interface line between the first semiconductor layer d and the silicon substrate e can be smaller than the degree of convexity and / or concavity of the interface line between the first semiconductor layer d and the first conductive layer c; or the arrangement of convexity and / or concavity of the interface line between the first semiconductor layer d and the silicon substrate e can be more orderly than the arrangement of convexity and / or concavity of the interface line between the first semiconductor layer d and the first conductive layer c; or the depth of convexity and / or concavity of the interface line between the first semiconductor layer d and the silicon substrate e can be smaller than the depth of convexity and / or concavity of the interface line between the first semiconductor layer d and the first conductive layer c. Specifically, that is to say, the interface line between the first semiconductor layer and the silicon substrate is relatively flat, or the first semiconductor layer and the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the absorption of light by the first semiconductor layer, and further improving the short-circuit current of the cell. At the same time, the interface line between the first semiconductor layer and the first conductive layer is relatively rough, or the first semiconductor layer and the first conductive layer have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface line between the first semiconductor layer and the first conductive layer is relatively rough, and the rough interface line can further reduce the reflection of light, which is beneficial to improve the short-circuit current. In summary, the present application solves the contradiction between the improvement of the passivation performance of the first semiconductor layer and the improvement of the fill factor of the existing solar cell by the flat interface line between the first semiconductor layer and the silicon substrate, and the rough interface line between the first semiconductor layer and the first conductive layer, which not only improves the passivation effect of the interface, thereby improving the open circuit voltage, but also improves the fill factor and short-circuit current of the solar cell. Here, the difference between the roughness of the interface line between the first semiconductor layer d and the first conductive layer c and the roughness of the interface line between the first semiconductor layer d and the silicon substrate e is not specifically limited.

[0041] The roughness of the interface line can be the arithmetic mean value Ra of the absolute value of the distance between each point in the sampling length of the interface line and a reference straight line, where the reference straight line passes at least one point in the sampling length of the interface line and is located between a wave crest and a wave trough in the sampling length of the interface line, or the roughness of the interface line can be the distance between a wave crest and a wave trough in the interface line, where the highest point of the protrusion in the interface line can be the wave crest and the lowest point of the depression in the interface line can be the wave trough. Specifically, in the present application, the actual sampling length of the roughness of the interface line between the first semiconductor layer d and the first conductive layer c is within 500 nm, which is not affected by the observation of the concave-convex of the suede of the silicon substrate in the range of the sampling length, and the tested roughness of the interface line can accurately represent the morphology (roughness) of the interface line between the first semiconductor layer d and the silicon substrate e and the interface line between the first semiconductor layer d and the first conductive layer c formed by the growth of the first semiconductor layer on the silicon substrate. Further, the roughness Ra (nm) of the interface line between the conductive layer d and the silicon substrate e is less than or equal to 1.5, and the roughness Ra (nm) of the interface line between the first semiconductor layer d and the first conductive layer c is greater than 1.5. In the present application, the roughness Ra (nm) of the interface line between the conductive layer d and the silicon substrate e is less than or equal to 1.5, which is verified to find that the structure surface of the suede formed by the anisotropic growth after the full chemical solution etching in the process of suede making of the silicon substrate is not the surface of the silicon substrate cutting remaining on the silicon substrate, and the sidewall surface of the pyramid is smoother after the full chemical etching, which reduces the surface defects of the silicon substrate. In the present application, the roughness Ra (nm) of the interface line between the first semiconductor layer d and the first conductive layer c is greater than 1.5, where the roughness matches the roughness of the interface line between the silicon substrate e and the first conductive layer d, avoids the formation of 100% amorphous silicon, increases the number and size of the crystal grains in the formation process of the first semiconductor layer, so as to achieve a larger roughness between the silicon substrate e and the first semiconductor layer d, which is beneficial to the current transmission effect of the first semiconductor layer, reduces the square resistance, and increases the light trapping effect.

[0042] It should be noted that, Figure 1 a in the above formula is ion beam deposition of platinum, and b is electron beam deposition of platinum, Figure 1 a and b in the above formula are auxiliary settings with better conductive performance added for clearer TEM imaging, and are not the actual structure in the solar cell.

[0043] The first semiconductor layer d includes a first surface close to the first conductive layer c and a second surface close to the silicon substrate e, that is, in the solar cell, one of the first surface and the second surface of the first semiconductor layer is the light-facing surface of the first semiconductor layer and the other is the back light-facing surface of the first semiconductor layer. Optionally, referring to Figure 2, the first surface of the first semiconductor layer close to the first conductive layer comprises a plurality of concave-convex structures, at least part of the concave-convex structures in the first surface are arranged in order, such as Figure 2 The concave-convex structures circled by the middle red dashed line are arranged in order. The concave-convex structures arranged in order can be considered as crystallization parts, Figure 2 The concave-convex structures outside the concave-convex structures arranged in order in the middle can be understood as amorphous parts. That is to say, the crystallization degree of at least part of the regions of the first surface is higher. The concave-convex structures of the crystallization parts are columnar structures extending along the thickness direction of the semiconductor. However, due to the different heights of the columnar structures, the first surface has a relatively large roughness. In other words, the interface between the first semiconductor layer and the first conductive layer has a relatively large surface roughness. This can enhance the contact between the first semiconductor layer and the first conductive layer and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer is relatively rough. The rough interface can further reduce the reflection of light, which is beneficial to improve the short-circuit current. The above structure can be realized by only partial crystallization assistance. Therefore, the solar cell is easy to obtain. More specifically, the first semiconductor layer is composed of an intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in layers. The intrinsic amorphous silicon layer is adjacent to the silicon substrate. Therefore, the first surface of the first semiconductor layer close to the first conductive layer is the surface of the doped amorphous silicon layer. In the present application, the intrinsic amorphous silicon layer can be first subjected to plasma treatment, and then the doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer after plasma treatment. Because the intrinsic amorphous silicon layer is induced by plasma treatment, it plays a role in surface dehydrogenation and partial crystallization. Furthermore, the doped amorphous silicon layer formed on the intrinsic amorphous silicon layer after plasma treatment is more ordered. Therefore, the first surface with at least part of the concave-convex structures arranged in order can be formed. The doped amorphous silicon layer in the present application is relative to doped polycrystalline silicon. Specifically, the doped amorphous silicon can be a doped layer formed by one or a mixture of several of doped amorphous silicon, doped nanocrystalline silicon, and doped microcrystalline silicon.

[0044] Optionally, referring to Figure 3 , the second surface of the first semiconductor layer close to the silicon substrate comprises a plurality of concave-convex structures, referring to Figure 2 , Figure 3 , the first surface of the first semiconductor layer close to the first conductive layer comprises a plurality of concave-convex structures, the arrangement of at least part of the concave-convex structures in the first surface is more ordered than the arrangement of the concave-convex structures of the second surface, such as Figure 2 The concave-convex structures circled by the middle red dashed line are arranged in order. The concave-convex structures arranged in order are crystallization parts, Figure 2 The concave-convex structures outside the part arranged in order in the middle and Figure 3 The concave-convex structures in the middle can be understood as amorphous parts. The concave-convex structures circled by the middle red dashed line in Figure 2 The concave-convex structures circled by the middle red dashed line inFigure 3 The arrangement of the uneven structure shown is more ordered, or in other words, at least some areas of the first surface have a higher degree of crystallization. Figure 2 The uneven structure circled in red is the crystallized portion. This crystallized portion forms columnar structures along the thickness direction of the first semiconductor layer. However, due to the varying heights of these columnar structures, the first surface has a relatively large roughness. This results in a larger roughness at the interface between the first semiconductor layer and the first conductive layer, or in other words, a larger surface roughness at the interface between the first semiconductor layer and the first conductive layer. This enhances the contact between the first semiconductor layer and the first conductive layer and strengthens the transport of charge carriers to the first conductive layer, thus improving the fill factor of the solar cell. Furthermore, the rougher interface between the first semiconductor layer and the first conductive layer further reduces light reflection, which helps to increase the short-circuit current. This structure can be achieved with partial crystallization assistance, making this solar cell readily available. More specifically, the first semiconductor layer consists of an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer stacked together. The intrinsic amorphous silicon layer is adjacent to the silicon substrate. Therefore, the second surface of the first semiconductor layer near the silicon substrate is the surface of the intrinsic amorphous silicon layer, and the first surface of the first semiconductor layer near the first conductive layer is the surface of the doped microcrystalline silicon layer. In this application, the intrinsic amorphous silicon layer is first subjected to plasma treatment, and then a doped microcrystalline silicon layer is formed on the plasma-treated intrinsic amorphous silicon layer. Because the intrinsic amorphous silicon layer is induced by plasma treatment, it plays a role in surface dehydrogenation and partial crystallization, thereby making the doped microcrystalline silicon layer formed on the plasma-treated intrinsic amorphous silicon layer more ordered. Therefore, at least a portion of the uneven structure is arranged in an orderly manner on the first surface. Thus, the arrangement of at least a portion of the uneven structure on the first surface is more ordered than the arrangement of the uneven structure on the second surface.

[0045] Optionally, the first semiconductor layer includes: microcrystalline silicon, such as the aforementioned crystalline uneven structure or ordered uneven structure, which is the microcrystalline silicon portion, also known as nanocrystalline silicon. The film thickness of the microcrystalline silicon is grown to 5-35 nm. Microcrystalline silicon is easy to crystallize, so the first semiconductor layer is easy to obtain, and therefore the solar cell is easy to obtain.

[0046] The surface roughness refers to the degree of concave-convex of the surface, or the degree of unevenness caused by the micro-convex or micro-concave in the surface, or the degree of fluctuation of the surface. Optionally, in the solar cell, the surface roughness of the interface between the first semiconductor layer d and the first conductive layer c is greater than the surface roughness of the silicon substrate e. For example, the number of convexities and / or concavities in the surface of the silicon substrate e can be less than the number of convexities and / or concavities in the interface between the first semiconductor layer d and the first conductive layer c; in another case, the degree of convexity and / or concavity in the surface of the silicon substrate e can be less than the degree of convexity and / or concavity in the interface between the first semiconductor layer d and the first conductive layer c; or, the arrangement of convexities and / or concavities in the surface of the silicon substrate e can be more ordered than the arrangement of convexities and / or concavities in the interface between the first semiconductor layer d and the first conductive layer c; or, the depth of convexities and / or concavities in the surface of the silicon substrate e can be less than the depth of convexities and / or concavities in the interface between the first semiconductor layer d and the first conductive layer c. Specifically, that is, the silicon substrate e has a relatively flat surface, so that the first semiconductor layer has a relatively flat contact surface with the silicon substrate, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer, and further improving the short-circuit current of the cell. At the same time, the first semiconductor layer has a relatively rough contact surface with the first conductive layer, which can enhance the contact between the first semiconductor layer and the first conductive layer, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short-circuit current. In summary, through the relatively flat surface of the silicon substrate and the rough contact interface between the first semiconductor layer and the first conductive layer, the present application solves the problem of contradiction between the improvement of the passivation performance of the first semiconductor layer and the improvement of the fill factor of the solar cell, not only improves the passivation effect of the interface, thereby improving the open circuit voltage, but also improves the fill factor and short-circuit current of the solar cell.

[0047] The surface roughness can be the arithmetic mean of the profile deviation in a sampling length in the surface or interface (i.e., Ra), or the surface roughness can be the distance between the peak top line and the valley bottom line in the interface or surface (i.e., Rz).

[0048] Optionally, with reference to Figure 4The first semiconductor layer d is composed of an intrinsic amorphous silicon layer 11 and a doped amorphous silicon layer 12 which are stacked, the intrinsic amorphous silicon layer 11 is adjacent to the silicon substrate e, the intrinsic amorphous silicon layer 11 here can play a good passivation effect, can reduce the silicon substrate interface recombination loss, improve the passivation effect of the interface, thereby improve the open circuit voltage, in combination with the structure of the first semiconductor layer d, the application can reduce the requirement for the thickness of the intrinsic amorphous silicon layer 11, thereby reducing the light absorption of the intrinsic amorphous silicon layer 11, and further improving the short-circuit current of the battery. The doped amorphous silicon layer 12 here can participate in the formation of a pn junction and play a role in separating carriers.

[0049] Optionally, referring to Figure 4The solar cell further comprises a second semiconductor layer 13 and a second conductive layer 14 arranged on the second side of the silicon substrate. The first semiconductor layer and the second semiconductor layer are of different doping types, one of which is of n-type and the other of which is of p-type. The first conductive layer is arranged on the first side of the silicon substrate, and the second conductive layer is arranged on the second side of the silicon substrate. The first semiconductor layer and the first conductive layer arranged on the first side of the silicon substrate are sequentially stacked on the silicon substrate, and the second semiconductor layer and the second conductive layer arranged on the second side of the silicon substrate are sequentially stacked on the silicon substrate, so that the solar cell is a bifacial solar cell. In the cross section of the solar cell, the surface roughness of the interface between the first semiconductor layer and the silicon substrate is less than the surface roughness of the interface between the first semiconductor layer and the first conductive layer, and the surface roughness of the interface between the second semiconductor layer and the silicon substrate is less than the surface roughness of the interface between the second semiconductor layer and the second conductive layer. Moreover, the roughness of the interface between the first semiconductor layer and the first conductive layer arranged on the first side of the silicon substrate is less than the roughness of the interface between the first semiconductor layer and the first conductive layer arranged on the first side of the silicon substrate, and the roughness of the interface between the second semiconductor layer and the second conductive layer arranged on the second side of the silicon substrate is less than the roughness of the interface between the second semiconductor layer and the second conductive layer arranged on the second side of the silicon substrate. On the first side of the silicon substrate, the first semiconductor layer and the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open-circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer, and further improving the short-circuit current of the cell. On the second side of the silicon substrate, the second semiconductor layer and the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open-circuit voltage, and can reduce the requirement for the thickness of the second semiconductor layer, thereby reducing the light absorption of the second semiconductor layer, and further improving the short-circuit current of the cell. At the same time, the semiconductor layer and the conductive layer arranged on the same side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the semiconductor layer and the conductive layer arranged on the same side of the silicon substrate, and enhance the transmission of carriers to the conductive layer, which is conducive to improving the fill factor of the solar cell. That is, the first semiconductor layer and the first conductive layer arranged on the first side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer arranged on the first side of the silicon substrate, and enhance the transmission of carriers to the conductive layer, which is conducive to improving the fill factor of the solar cell. The second semiconductor layer and the second conductive layer arranged on the second side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the second semiconductor layer and the second conductive layer arranged on the second side of the silicon substrate, and enhance the transmission of carriers to the conductive layer, which is conducive to improving the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer arranged on the first side of the silicon substrate is relatively rough, and the rough interface can further reduce the reflection of light, which is conducive to improving the short-circuit current.The interface between the second semiconductor layer and the second conductive layer on the second side of the silicon substrate is rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short-circuit current. In addition, the bifacial solar cell generally has the advantages of low process temperature, high conversion efficiency, good high-temperature characteristics, etc. It should be noted that the first conductive layer on the light side of the silicon substrate needs to have good light transmittance.

[0050] Optionally, referring to Figure 4 As described above, the silicon substrate and the first semiconductor layer have the same doping type, and the roughness of the interface between the first semiconductor layer and the first conductive layer is greater than the roughness of the interface between the second semiconductor layer and the second conductive layer. Here, the first semiconductor layer is specifically located on the light side or the back side of the silicon substrate, and the silicon substrate and the first semiconductor layer form a high-low junction, and the silicon substrate and the second semiconductor layer 13 form a pn junction. Here, the first semiconductor layer and the second semiconductor layer can have the same or different crystal types, which are not limited. Among the first conductive layer and the second conductive layer, the conductive layer located on the light side of the silicon substrate has better light transmittance.

[0051] For example, the silicon substrate is n-type, the first semiconductor layer includes an n-type doped microcrystalline silicon layer, the first semiconductor layer is located on the light side of the silicon substrate, the second semiconductor layer is located on the back side of the silicon substrate, the second semiconductor layer includes a doped microcrystalline silicon layer with a p-type doping type, and the surface roughness of the interface between the first semiconductor layer with an n-type doping type and the first conductive layer located on the light side of the silicon substrate (light Ra) is greater than the surface roughness of the interface between the second semiconductor layer with a p-type doping type and the second conductive layer located on the back side of the silicon substrate (back Ra). This can improve the light trapping effect. For example, the light Ra (nm) is 3.68, and the back Ra is 2.30 (nm). The above structure is set by adjusting the nucleation crystallinity in the first semiconductor layer on the front side or the light side, so that the front grain crystallinity is higher and the nucleation size is larger, thereby forming better light transmittance on the front side of the cell and improving the photoelectric conversion efficiency. Moreover, the pn junction formed by the second semiconductor layer and the silicon substrate is located on the back side of the silicon substrate, which can further improve the efficiency of the solar cell. The bifacial solar cell can further include a first electrode 2 on the first conductive layer and a second electrode 3 on the second conductive layer, and the first electrode 2 and the second electrode 3 are used to conduct current outward.

[0052] Optionally, the first semiconductor layer is located on a first side of the silicon substrate, and the solar cell further comprises a tunneling oxide layer and a doped polysilicon layer which are sequentially located on a second side of the silicon substrate, the tunneling oxide layer is adjacent to the silicon substrate, the doped polysilicon layer and the doped amorphous silicon layer have different doping types, one of the doping types is n-type and the other is p-type, one of the first side and the second side of the silicon substrate is a light-receiving side of the silicon substrate, and the other is a back side of the silicon substrate, and the first side and the second side can be referred to the related description above, and details are not described herein again to avoid repetition. The solar cell can be considered as a high-low temperature hybrid bifacial cell, for example, the first semiconductor layer can be located on the back side of the silicon substrate, the tunneling oxide layer and the doped polysilicon layer are sequentially located on the light-receiving side of the silicon substrate, and the first semiconductor layer is composed of the intrinsic amorphous silicon layer and the doped amorphous silicon layer which are sequentially located, and the short-circuit current of the cell is further improved due to the fact that the light-receiving side does not have the intrinsic amorphous silicon layer but the tunneling oxide layer. The pn junction of the solar cell can be formed on the back side of the silicon substrate, and details are not limited herein.

[0053] Optionally, the first side surface of the silicon substrate comprises: first conductive regions and second conductive regions which are spaced apart, the spacing between the first conductive regions and the second conductive regions is used to avoid electric leakage, the first side surface can be a back side surface of the silicon substrate, the first semiconductor layer is located on the first side of the silicon substrate, or the first semiconductor layer is located on the back side of the silicon substrate, and the first semiconductor layer is located on the first conductive regions and the second conductive regions, the doping types of the part of the first semiconductor layer located on the first conductive regions and the part of the first semiconductor layer located on the second conductive regions are different, one of the doping types is n-type and the other is p-type, the first conductive layer is located on the first side of the silicon substrate, and the first conductive layer is located on the side of the first semiconductor layer away from the silicon substrate, the projection of the first conductive layer on the first side surface of the silicon substrate also falls within the first conductive regions and the second conductive regions, that is, the solar cell is a back contact solar cell, the pn junction and the metal contact in the cell are arranged on the back of the cell, so that the front side is not shielded by the electrode grid lines, the area of the cell for absorbing solar radiation is larger, and thus the conversion efficiency is improved and more electric power can be generated.

[0054] In the back contact solar cell, the roughness of the interface between the part of the first semiconductor layer on the first conductive region and the first conductive region of the silicon substrate is less than the roughness of the interface between the part of the first semiconductor layer on the first conductive region and the part of the first conductive layer on the first conductive region, the roughness of the interface between the part of the first semiconductor layer on the second conductive region and the second conductive region of the silicon substrate is less than the roughness of the interface between the part of the first semiconductor layer on the second conductive region and the part of the first conductive layer on the second conductive region, and the first semiconductor layer and the back light side of the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage, and can reduce the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer, and further improving the short circuit current of the cell. At the same time, the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate, and enhance the transmission of carriers to the first conductive layer, which is beneficial to improve the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improve the short circuit current. The difference between the roughness of the interface between the first semiconductor layer and the first conductive layer on the same conductive region of the back light side of the silicon substrate and the roughness of the interface between the first semiconductor layer and the silicon substrate on the same conductive region of the back light side of the silicon substrate is not specifically limited.

[0055] Optionally, the first side surface of the silicon substrate comprises: first conductive regions and second conductive regions distributed at intervals, the intervals between the first conductive regions and the second conductive regions being used to avoid electric leakage, the first side surface can be the backside surface of the silicon substrate, the first semiconductor layer is located only on the first side of the silicon substrate, or the first semiconductor layer is located only on the backside of the silicon substrate, the first semiconductor layer is located only on the first conductive regions, the solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer which are located on the second conductive regions in a stacked manner, the tunneling oxide layer is adjacent to the silicon substrate, the first conductive layer is also located on the first side of the silicon substrate, the first conductive layer is located on the side of the doped polysilicon layer and the first semiconductor layer away from the silicon substrate, the projection of the first conductive layer on the first side surface of the silicon substrate also falls within the first conductive regions and the second conductive regions, the doped polysilicon layer and the first semiconductor layer are different in doping type, one of the two is n-type and the other is p-type, the solar cell is a hybrid back contact solar cell, the pn junction and the metal contact in the cell are both arranged on the back of the cell, so that the front surface is not blocked by electrode grid lines, the area of the cell for absorbing solar radiation is larger, and the doped polysilicon layer has better conductivity, the reflectivity of the doped polysilicon layer on the back of the silicon substrate is better, thereby improving the conversion efficiency and enabling the cell to generate more electricity.

[0056] In the hybrid back contact solar cell, the roughness of the interface between the first semiconductor layer and the first conductive regions on the backside of the silicon substrate is smaller than the roughness of the interface between the first semiconductor layer and the first conductive layer, the first semiconductor layer and the first conductive regions on the backside of the silicon substrate have a relatively flat contact surface, which can reduce the interface recombination loss, improve the passivation effect of the interface, thereby improving the open circuit voltage and reducing the requirement for the thickness of the first semiconductor layer, thereby reducing the light absorption of the first semiconductor layer and further improving the short circuit current of the cell. At the same time, the first semiconductor layer and the first conductive layer on the first conductive regions on the backside of the silicon substrate have a relatively rough contact surface, which can enhance the contact between the first semiconductor layer and the first conductive layer on the first conductive regions on the backside of the silicon substrate and enhance the transport of carriers to the first conductive layer, which is beneficial to improving the fill factor of the solar cell. Moreover, the interface between the first semiconductor layer and the first conductive layer on the first conductive regions on the backside of the silicon substrate is relatively rough, and the rough interface can further reduce the reflection of light, which is beneficial to improving the short circuit current. The difference between the roughness of the interface between the first semiconductor layer and the first conductive layer on the first conductive regions on the backside of the silicon substrate and the roughness of the interface between the first semiconductor layer and the silicon substrate on the first conductive regions on the backside of the silicon substrate is not specifically limited.

[0057] Optionally, the roughness of the junction line between the doped polysilicon layer on the second conductive region and the first conductive layer is greater than the roughness of the junction line between the first semiconductor layer and the first conductive layer, and specifically, the grain size of the doped polysilicon layer is greater, and the reflectivity of the doped polysilicon layer on the back surface of the silicon substrate is better, thereby improving the conversion efficiency and enabling more electric energy to be emitted.

[0058] Optionally, the doping concentration of the conductive element in the first semiconductor layer close to the first conductive layer is greater than the doping concentration of the conductive element in the first semiconductor layer close to the silicon substrate, that is, a certain concentration gradient can be formed, and the performance of the solar cell can be improved. For example, the first semiconductor layer is composed of a stacked intrinsic amorphous silicon layer and a doped microcrystalline silicon layer, and the intrinsic amorphous silicon layer is arranged immediately adjacent to the silicon substrate, so the side of the first semiconductor layer close to the silicon substrate is the side of the intrinsic amorphous silicon close to the silicon substrate. The doped elements in the doped microcrystalline silicon layer can diffuse into the intrinsic amorphous silicon, and the doping concentration in the silicon substrate can also diffuse into the intrinsic amorphous silicon, resulting in a certain doping concentration on the side of the intrinsic amorphous silicon close to the silicon substrate. However, the doping concentration on the side of the intrinsic amorphous silicon close to the silicon substrate is less than the doping concentration on the side of the doped microcrystalline silicon layer close to the first conductive layer.

[0059] Optionally, to further illustrate the implementation method of the above solar cell, the first semiconductor layer can be deposited on the silicon substrate after texturing or polishing, and then the surface of the first semiconductor layer is etched. The etching solution can be selected according to the prior art. After etching, the surface roughness of the first semiconductor layer can be changed. For example, after etching, the amorphous state or smaller nanocrystals on the surface of the first semiconductor layer are etched away, thereby leaving larger nanocrystal particles on the surface, thereby forming a larger rough surface structure. After depositing the transparent first conductive layer, the roughness of the interface between the first semiconductor layer and the transparent first conductive layer is increased, thereby forming better light trapping and contact performance between the first semiconductor layer and the first conductive layer, thereby improving the collection effect of the carriers.

[0060] Optionally, to further illustrate the implementation method of the above solar cell, the first semiconductor layer can be deposited on the silicon substrate after texturing or polishing, and then the surface of the first semiconductor layer is etched. The etching solution can be selected according to the prior art. After etching, the surface roughness of the first semiconductor layer can be changed. For example, after etching, the amorphous state or smaller nanocrystals on the surface of the first semiconductor layer are etched away, thereby leaving larger nanocrystal particles on the surface, thereby forming a larger rough surface structure. After depositing the transparent first conductive layer, the roughness of the interface between the first semiconductor layer and the transparent first conductive layer is increased, thereby forming better light trapping and contact performance between the first semiconductor layer and the first conductive layer, thereby improving the collection effect of the carriers.

[0061] Optionally, in order to further illustrate the implementation method of the solar cell, the first semiconductor layer can be deposited on the silicon substrate after texturing or polishing, wherein an intrinsic amorphous silicon layer is first deposited in the process of depositing the first semiconductor layer, then plasma treatment is performed, and then deposition of doped microcrystalline silicon is performed. The plasma treatment increases the grain size and deposition order of the doped microcrystalline silicon layer, thereby forming a larger roughness. Subsequently, after depositing the transparent first conductive layer, the roughness of the interface between the first semiconductor layer and the transparent first conductive layer is increased, thereby forming better light trapping and contact performance between the first semiconductor layer and the transparent first conductive layer, thereby improving the collection effect of the carriers.

[0062] The following provides a method for preparing the above-mentioned solar cell by taking plasma treatment as an example, which specifically comprises:

[0063] Step 101, providing a silicon substrate after texturing; the silicon substrate comprises a first side and a second side opposite to each other.

[0064] Step 102, preparing an intrinsic amorphous silicon layer on at least one of the first side and the second side.

[0065] The formation method of the intrinsic amorphous silicon layer is not specifically limited, for example, plasma chemical vapor deposition can be used for deposition. The main function of the intrinsic amorphous silicon layer is to passivate the dangling bonds on the surface of the crystalline silicon, reduce surface recombination, and improve the electrical performance of the cell.

[0066] Step 103, performing plasma treatment on the intrinsic amorphous silicon layer using a first reaction gas containing hydrogen, carbon dioxide and silane.

[0067] Using the first reaction gas containing hydrogen, carbon dioxide and silane, the intrinsic amorphous silicon layer is mainly subjected to surface dehydrogenation and partial crystallization by plasma chemical vapor deposition. The dehydrogenation effect of hydrogen plasma combined with carbon dioxide in the first reaction gas promotes the transformation of the original amorphous state on the surface of the intrinsic amorphous silicon layer into a partially nanocrystalline state, i.e., partial nanocrystallization is achieved, so that the surface nucleation point is larger and more, and “self-repairing nucleation” is achieved.

[0068] Optionally, in the plasma processing, the pressure in the reaction chamber can be 2 mbar to 3.5 mbar, for example, can be 2 mbar, 2.21 mbar, 2.5 mbar, 2.84 mbar, 3 mbar, 3.17 mbar, 3.5 mbar, etc., the dilution ratio of hydrogen to silane in the first reaction gas is greater than or equal to 600, for example, can be 600, 650, 700, 7470, 800, 862, 900, 930, 1000, etc., the flow ratio of carbon dioxide to silane can be 30% to 100%, for example, can be 30%, 38%, 40%, 46%, 50%, 60%, 65%, 72%, 80%, 84.2%, 100%, etc., the power density can be 2000 W / m 2 -2600 W / m 2 , for example, can be 2000 W / m 2 , 2100 W / m 2 , 2145 W / m 2 , 2200 W / m 2 , 2300 W / m 2 , 2400 W / m 2 , 2406 W / m 2 , 2500 W / m 2 , 2600 W / m 2 , etc., the glow time can be 3 s to 10 s, for example, can be 3 s, 4 s, 5 s, 6 s, 7 s, 8 s, 9 s, 10 s, etc. Under the above larger hydrogen dilution ratio (H2 / SiH4≥600), by optimizing the carbon dioxide flow and matching the reaction chamber pressure and power settings, it is more conducive to effectively inducing the doped microcrystalline silicon layer, such as the doped nanocrystalline silicon layer, to grow into a generally columnar structure along its thickness direction, and the columnar structure has different degrees of concave-convex.

[0069] Step 104, preparing a doped microcrystalline silicon layer on the intrinsic amorphous silicon layer after plasma processing.

[0070] The doping type of the doped microcrystalline silicon layer here can be n-type doping or p-type doping. Due to the aforementioned plasma processing of the intrinsic amorphous silicon layer, at least part of the doped microcrystalline silicon layer away from the silicon substrate in the doped microcrystalline silicon layer grows into a concave-convex columnar structure along its thickness direction, and further makes the surface roughness of at least part of the doped microcrystalline silicon layer away from the silicon substrate in the doped microcrystalline silicon layer larger.

[0071] Optionally, the doped microcrystalline silicon layer is formed on the side of the intrinsic amorphous silicon layer away from the silicon substrate by plasma chemical vapor deposition after the aforementioned plasma treatment, and the doped microcrystalline silicon layer is also formed by plasma chemical vapor deposition, which continues the aforementioned plasma treatment, is simple in process and high in production efficiency. The second reaction gas used in the process of forming the doped microcrystalline silicon layer includes hydrogen and silane, wherein the dilution ratio of hydrogen to silane is greater than or equal to 200 and less than or equal to 700, for example, can be 200, 260, 300, 340, 350, 400, 440, 500, 600, 700, etc. In the process of forming the doped microcrystalline silicon layer, the pressure of the reaction chamber is greater than or equal to 1.5 mbar and less than or equal to 4 mbar, for example, can be 1.5 mbar, 1.92 mbar, 2 mbar, 2.5 mbar, 2.75 mbar, 3 mbar, 3.5 mbar, 4 mbar, etc. The thickness of the formed doped microcrystalline silicon layer is greater than or equal to 11 nm and less than or equal to 38 nm, for example, can be 11 nm, 13.4 nm, 15 nm, 19.1 nm, 19.5 nm, 20 nm, 22.5 nm, 25.8 nm, 28 nm, 30 nm, 33 nm, 35.2 nm, 37 nm, 38 nm, etc.

[0072] Optionally, in the case of the doped microcrystalline silicon layer being an n-type doped microcrystalline silicon layer, the second reaction gas including phosphine (PH3), hydrogen and silane can be used in the process of preparing the doped microcrystalline silicon layer. The aforementioned step 104 can include: using the second reaction gas containing silane, hydrogen and phosphine to prepare an n-type doped microcrystalline silicon layer on the intrinsic amorphous silicon layer after plasma treatment by plasma chemical vapor deposition, wherein the flow ratio of phosphine to silane in the second reaction gas is 3%-20%, for example, can be 3%, 3.9%, 4.3%, 5.7%, 6.9%, 8.4%, 9.5%, 10%, 11.5%, 13%, 15.3%, 18%, 19.2%, 20%, etc. The dilution ratio of hydrogen to silane in the second reaction gas can be 200-500, for example, can be 200, 260, 300, 340, 350, 400, 440, 500, etc. In the process of preparing the n-type doped microcrystalline silicon layer, the pressure of the reaction chamber is 1.5 mbar-4 mbar, for example, can be 1.5 mbar, 1.92 mbar, 2 mbar, 2.5 mbar, 2.75 mbar, 3 mbar, 3.5 mbar, 4 mbar, etc. The power density can be 950 W / m 2 -2400 W / m 2 , for example, can be 950 W / m 2 , 1000 W / m 2 , 1007 W / m 2 , 1233 W / m2 , 1500 W / m 2 , 1675 W / m 2 , 1780 W / m 2 , 1950 W / m 2 , 2000 W / m 2 , 2200 W / m 2 , 2400 W / m 2 , etc. The deposition thickness can be 11 nm-18 nm, for example, 11 nm, 11.4 nm, 12 nm, 13.1 nm, 14 nm, 14.7 nm, 15 nm, 15.8 nm, 16 nm, 17 nm, 18 nm, etc. Since the n-type doping gas, i.e. phosphine, will inhibit crystallization, the gas doping ratio (PH3 / SiH4) needs to be controlled within a suitable range. By optimizing the gas doping ratio (PH3 / SiH4), the conductivity of the nanocrystalline or microcrystalline can be adjusted, the defect density is controlled within a suitable range, and the n-type doped microcrystalline silicon layer prepared under the above process conditions is rough on the side away from the silicon substrate.

[0073] Optionally, in the case of a p-type doped microcrystalline silicon layer, a second reaction gas including a p-type doping gas, hydrogen and silane can be used in the process of preparing the doped microcrystalline silicon layer. The foregoing step 104 can include: using a second reaction gas containing silane, hydrogen and a p-type doping gas to prepare a p-type doped microcrystalline silicon layer on the plasma-treated intrinsic amorphous silicon layer by plasma chemical vapor deposition, wherein the p-type doping gas in the second reaction gas includes: diborane (B2H6) and / or trimethylborane (TMB), and the flow ratio of the p-type doping gas to silane can be 0.5%-10%, for example, 0.5%, 0.97%, 1%, 2.7%, 2.25%, 3%, 3.9%, 4.1%, 4.9%, 5%, 6%, 7.5%, 8.3%, 10%, etc. In the process of preparing the p-type doped microcrystalline silicon layer, the dilution ratio of hydrogen to silane in the second reaction gas can be 200-700, for example, 200, 240, 300, 340, 400, 450, 500, 600, 700, etc. In the process of preparing the p-type doped microcrystalline silicon layer, the reaction chamber pressure can be 1.5 mbar-4 mbar, for example, 1.5 mbar, 2 mbar, 2.25 mbar, 2.5 mbar, 3 mbar, 3.3 mbar, 3.5 mbar, 4 mbar, etc. The power density can be 950 W / m 2 -2400 W / m 2 , for example, 950 W / m 2 , 1000 W / m 2 , 1200 W / m 2 , 1500 W / m2 , 1720 W / m 2 , 1675 W / m 2 , 2000 W / m 2 , 2200 W / m 2 , 2400 W / m 2 etc. The thickness of the deposited p-type doped microcrystalline silicon layer can be 13 nm to 38 nm, for example, 13 nm, 14.2 nm, 15 nm, 16 nm, 17.3 nm, 20 nm, 25 nm, 25.5 nm, 30 nm, 32 nm, 38 nm, etc. Since the p-type doping gas, i.e. diborane and / or trimethylborane, will inhibit crystallization, it is necessary to control the gas doping ratio ((B2H6 and / or TMB) / SiH4) within a suitable range. By optimizing the gas doping ratio ((B2H6 and / or TMB) / SiH4), the electrical conductivity of the nanocrystals can be adjusted, the defect density is controlled within a suitable range, and the p-type doped microcrystalline silicon layer prepared under the above process conditions is relatively rough on the side away from the silicon substrate.

[0074] Based on the above plasma treatment and the deposition conditions of the doped microcrystalline silicon layer, the deposition rate of the n-type or p-type doped microcrystalline silicon layer can be greatly improved. Moreover, the above plasma treatment can effectively induce the growth of the doped microcrystalline silicon layer along the thickness direction, and at least part of the doped microcrystalline silicon is in a columnar structure. Compared with the case without the above surface dehydrogenation and partial crystallization, the number of columnar structures can be greatly increased by the above surface dehydrogenation and partial crystallization.

[0075] The doped microcrystalline silicon layer formed in the above steps 102 to 104 and the intrinsic amorphous silicon layer immediately adjacent thereto together form the aforementioned first semiconductor layer.

[0076] Step 105, preparing a first conductive layer on the doped microcrystalline silicon layer.

[0077] The first conductive layer herein can be prepared by deposition or the like, which is not specifically limited.

[0078] The prepared doped microcrystalline silicon layer is also subjected to performance testing. Specifically, the prepared doped microcrystalline silicon layer is placed in a Raman spectrometer for crystallization rate testing, and then subjected to peak fitting calculation of the crystallization rate. Two metal electrodes are prepared on the prepared doped microcrystalline silicon layer by evaporation, and then a semiconductor tester is used to test the dark state IV curve to calculate the conductivity. The prepared doped microcrystalline silicon layer is made into a sample cell, which is tested by an IV tester to obtain the energy conversion efficiency. Compared with the preparation of the doped microcrystalline silicon layer without plasma treatment on the intrinsic amorphous silicon layer, the crystallization rate and conductivity of the doped microcrystalline silicon layer formed on the intrinsic amorphous silicon layer subjected to plasma treatment are obviously improved.

[0079] The roughness of different layers in the battery structure is also measured. Specifically, a textured silicon substrate is provided, and the surface roughness Ra of the silicon substrate is measured to be 0.602 nm. An amorphous p-type doped layer is prepared on the silicon substrate, and the roughness Ra of the surface of the amorphous p-type doped layer away from the glass is measured to be 0.457 nm. An intrinsic amorphous silicon layer is prepared on the silicon substrate by the aforementioned preparation method, and then the intrinsic amorphous silicon layer is subjected to plasma treatment. Then, an n-type doped microcrystalline silicon layer is prepared on the intrinsic amorphous silicon layer subjected to plasma treatment, and the roughness Ra of the surface of the n-type doped microcrystalline silicon layer away from the glass is measured to be 3.68 nm. An intrinsic amorphous silicon layer is prepared on the silicon substrate by the aforementioned preparation method, and then the intrinsic amorphous silicon layer is subjected to plasma treatment. Then, a p-type doped microcrystalline silicon layer is prepared on the intrinsic amorphous silicon layer subjected to plasma treatment, and the roughness Ra of the surface of the p-type doped microcrystalline silicon layer away from the glass is measured to be 2.30 nm. It can be seen that the roughness of the surface of the n-type doped microcrystalline silicon layer and the p-type doped microcrystalline silicon layer away from the glass can indeed be improved by the aforementioned method.

[0080] The application also provides a photovoltaic module comprising any one of the aforementioned solar cells. The photovoltaic module can further comprise encapsulation adhesive films or other structures on the first and second sides of the solar cells, and other structures of the photovoltaic module are not specifically limited.

[0081] It should be noted that the preparation method of the solar cell, the solar cell and the photovoltaic module have the same or similar beneficial effects, and to avoid repetition, they will not be described here.

[0082] It should be noted that, for the method embodiments, the steps are described in a specific sequence for simplicity, but the skilled person should understand that the application is not limited to the sequence of the steps, and some steps can be performed in other sequences or at the same time according to the application. In addition, the skilled person should understand that the embodiments described in the specification are all preferred embodiments, and the steps involved are not necessarily essential to the application.

[0083] It should be noted that, in this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0084] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned method of the embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application or the part that contributes to the prior art can be embodied in the form of software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) execute the method described in each embodiment of the present application.

[0085] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. A solar cell, characterized by, Comprise: a silicon substrate; the silicon substrate comprises: opposite first and second sides, the first side is a back light side, and the second side is a light side; a first semiconductor layer is located on the first side and is different from the conductive type of the silicon substrate, a PN junction is formed between the first semiconductor layer and the silicon substrate; a first conductive layer is located on the side of the first semiconductor layer away from the silicon substrate; in the cross section of the solar cell, the roughness of the interface between the first semiconductor layer and the silicon substrate is less than the roughness of the interface between the first semiconductor layer and the first conductive layer; the roughness of the interface is the fluctuation within 500nm between the top and bottom of the silicon substrate roughness structure; the first semiconductor layer comprises: a first surface close to the first conductive layer; the first surface comprises a plurality of concave-convex structures; at least part of the concave-convex structures in the first surface are arranged in order; the concave-convex structure is a columnar structure extending along the thickness direction of the first semiconductor.

2. The solar cell according to claim 1, characterized in that, The surface roughness of the interface between the first semiconductor layer and the first conductive layer is greater than the surface roughness of the silicon substrate.

3. The solar cell according to claim 1, characterized in that, The first semiconductor layer is composed of a intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in layers; the intrinsic amorphous silicon layer is arranged immediately adjacent to the silicon substrate.

4. The solar cell according to claim 1 or 2, characterized in that, The solar cell further comprises: a second semiconductor layer and a second conductive layer arranged on the second side of the silicon substrate; the doping type of the first semiconductor layer and the second semiconductor layer is different, and in the cross section of the solar cell, the roughness of the interface between the second semiconductor layer on the second side of the silicon substrate and the silicon substrate is less than the roughness of the interface between the second semiconductor layer and the second conductive layer.

5. The solar cell according to claim 4, characterized in that, The doping type of the silicon substrate and the first semiconductor layer is the same, and the roughness of the interface between the first semiconductor layer and the first conductive layer is greater than the roughness of the interface between the second semiconductor layer and the second conductive layer.

6. The solar cell of claim 5, wherein: The solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer arranged in layers on the second side of the silicon substrate; the tunneling oxide layer is arranged immediately adjacent to the silicon substrate; the doping type of the doped amorphous silicon layer and the doped polysilicon layer is different.

7. The solar cell according to any one of claims 1 to 3, wherein The first side surface of the silicon substrate comprises: a first conductive region and a second conductive region distributed at intervals; The first semiconductor layer is located on the first conductive region and the second conductive region; the doping type of the part of the first semiconductor layer located on the first conductive region and the part of the first semiconductor layer located on the second conductive region is different; or, The first side surface of the silicon substrate comprises: a first conductive region and a second conductive region distributed at intervals; The first semiconductor layer is located on the first conductive region; The solar cell further comprises: a tunneling oxide layer and a doped polysilicon layer arranged in layers on the second conductive region; the tunneling oxide layer is arranged immediately adjacent to the silicon substrate; the doping type of the first semiconductor layer and the doped polysilicon layer is different.

8. The solar cell of claim 7, wherein, The roughness of the junction line between the doped polysilicon layer on the second conductive region and the first conductive layer is greater than the roughness of the junction line between the first semiconductor layer and the first conductive layer.

9. The solar cell according to any one of claims 1 to 3, wherein The doping concentration of the first semiconductor layer near the side of the first conductive layer is greater than the doping concentration of the first semiconductor layer near the side of the silicon substrate.

10. A photovoltaic module, characterized by, Comprise: A plurality of solar cells according to any one of claims 1 to 9.

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