A high performance DC power parallel system and control method

Abstract

The invention discloses a high-performance DC power parallel control system and control method, belongs to the field of DC power supply technology, includes loop control module, signal follower module, communication module, loop control module includes voltage outer loop control circuit, current outer loop control circuit, realizes accurate control of voltage and current; signal follower module includes two identical follower circuits, realizes voltage following and power amplification, and ensures that voltage signal has high driving ability; communication module includes STM32 control circuit, differential drive circuit and RS485 communication circuit, realizes signal communication such as current control, start-stop control and alarm control between host and slave; differential circuit ensures that analog signal is transmitted without attenuation. The present invention can be applied to the parallel control of DC power supply of the same model. When multiple power supplies are paralleled, the voltage outer loop control signal is transmitted with analog circuit, and the signal is continuously transmitted without interruption and the transmission speed is fast, which ensures the dynamic performance of power supply.

Description

Technical Field

[0001] The present invention relates to the technical field of direct current power supplies, and in particular to a high-performance direct current power supply parallel system and a control method. Background Art

[0002] In order to expand the application of power supply and improve the flexibility and scalability of power supply, the parallel technology of power supply is particularly important. By adding the output capacity of multiple power supply devices, the total output capacity of the system can be increased. Users can also reduce or increase power supply devices according to load requirements to adapt to applications of different scales and power requirements.

[0003] The parallel control of DC power supplies is generally controlled by an analog master-slave control method. The master controls the slaves, and signal transmission is mainly analog signal transmission. Due to the differences in the analog control circuits of the master and slaves, there are large differences in the output current of each power supply, and it is impossible to flexibly increase or decrease the number of slaves, and the accuracy of the total output current of the parallel power supply cannot be guaranteed. Summary of the invention

[0004] The purpose of the present invention is to provide a high-performance DC power parallel control method, which uses a mixed control method of analog circuits and digital circuits to achieve power parallel control. The voltage outer loop output signal adopts analog circuit control to ensure uninterrupted and continuous signal transmission, and the transmission speed is fast, which ensures the dynamic performance of the power supply. The RS485 digital communication control method can flexibly increase or decrease the number of parallel machines and ensure the accuracy of parallel current. Digital communication controls the transmission of power supply start, stop, alarm and other signals to ensure safe and reliable operation of the power supply.

[0005] In order to achieve the above object, the present invention is implemented through the following technical solutions:

[0006] A high-performance DC power parallel system includes N power supplies with the same structure, the N power supplies include a host power supply and N-1 slave power supplies, and N is a positive integer;

[0007] All power supplies are connected in parallel, and each power supply includes: a loop control module, a follower module, a differential circuit, and a communication module, and the output end of the loop control module is connected to the input end of the follower module;

[0008] The loop control module includes a voltage outer loop control circuit and a current outer loop control circuit, the follower module includes a first follower circuit and a second follower circuit, and the communication module includes an STM32 circuit, a differential drive circuit and an RS485 circuit connected in sequence.

[0009] Furthermore, the input ends of the voltage outer loop control circuit are respectively a voltage sampling Vmom signal and a given Vref signal, the input ends of the current outer loop control circuit are respectively a current sampling Imom signal and a given Iref signal, the output end of the current outer loop control circuit is connected to the input end of the first follower circuit, the first output end of the voltage outer loop control circuit is the output signal of the voltage follower through PI regulation of the voltage sampling Vmom signal and the given Vref signal, the signal is connected to the input end of the relay S1, the output end of the relay S1 is connected to the input end of the first follower circuit, the output end Vslave signal of the differential circuit is connected to the input end of the relay S2, the Vslave signal is the signal after the Share+ signal and the Share- signal of the power supply parallel host are differentially operated, the relay The output end of S2 is connected to the input end of the first follower circuit, and the output end of the first follower circuit is connected to the input end of the current inner loop control circuit. The second output end Vmaster signal of the voltage outer loop control circuit is connected to the input end of the second follower circuit, and the Vmaster signal is a signal output after the voltage sampling Vmom signal and the given Vref signal are adjusted by PI. The output end Vmaster-OUT signal of the second follower circuit is connected to the input end of the relay S3, and the differential circuit input end Vslave-IN signal is connected to the input end of the relay S4. The Vslave-IN signal is the Share+ signal sent by the host when the power supplies are paralleled. The output ends of the relays S3 and S4 are connected to the Share+ signal, the GND signal is connected to the Share- signal through the relay S5, and the GND-IN signal is connected to the Share- signal through the relay S6. The GND-IN signal is the GND signal of the host when the power supplies are paralleled. The RS485 circuit outputs RS485-A signal and RS485-B signal. The data bus connects the same signals of the host and slave power supplies respectively, and the output ends of the host and slave power supplies are connected positively to positive and negatively to negative.

[0010] Furthermore, the voltage outer loop control circuit includes an operational amplifier U1, an operational amplifier U7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R19, a capacitor C1, and a diode D1. The left side of the resistor R1 is connected to a voltage sampling Vmon signal, the right side of the resistor R1 and the left side of the resistor R3 are connected to the inverting input terminal of the operational amplifier U1, the left side of the resistor R2 is connected to a voltage given Vref signal, the right side of the resistor R2 is connected to the non-inverting input terminal of the operational amplifier U1, the right side of the resistor R3 is connected to the left side of the capacitor C1, the right side of the capacitor C1 and the anode of the diode D1 are connected to the non-inverting input terminal of the operational amplifier U7, the cathode of the diode D1 is connected in series with the resistor R4 and then connected to the output terminal of the operational amplifier U1, the inverting input terminal of the operational amplifier U7 and the right side of the resistor R19 are connected to the input terminal of the relay S1, and the left side of the resistor R19 is connected to the output terminal of the operational amplifier U7;

[0011] The current outer loop control circuit includes an operational amplifier U2, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C2, and a diode D2. The left side of the resistor R5 is connected to the current sampling Imon signal, the right side of the resistor R5 and the left side of the resistor R6 are connected to the inverting input terminal of the operational amplifier U2, the left side of the resistor R7 is connected to the voltage given Iref signal, the right side of the resistor R7 is connected to the non-inverting input terminal of the operational amplifier U2, the right side of the resistor R6 is connected in series with the capacitor C2 and then connected to the anode of the diode D2 and the output terminal of the relay S1, and the resistor R8 is connected in series between the cathode of the diode D2 and the output terminal of the operational amplifier U2;

[0012] The differential circuit includes an operational amplifier U5, a resistor R15, a resistor R16, a resistor R17, and a resistor R18. The left side of the resistor R15 is connected to the input terminal of the relay S6. The right side of the resistor R15 and the left side of the resistor R16 are connected to the inverting input terminal of the operational amplifier U5. The right side of the resistor R16 is respectively connected to the output terminal of the operational amplifier U5 and the input terminal of the relay S2. The left side of the resistor 17 is connected to the input terminal of the relay S4. The right side of the resistor 17 and the upper side of the resistor 18 are connected to the in-phase input terminal of the U5. The lower side of the resistor R18 is connected to the input terminal of the relay S5.

[0013] The first follower circuit includes an operational amplifier U3, a resistor R9, a resistor R10, a resistor R11, a capacitor C3, a capacitor C4, a diode D3, and a transistor Q1. The in-phase input terminal of the operational amplifier U3 is respectively connected to the output terminal of the relay S1 and the output terminal of the relay S2. The inverting input terminal of the operational amplifier U3 is respectively connected to the left side of the resistor R9, the left side of the capacitor C3, and the left side of the capacitor C4. The output terminal of the operational amplifier U3 is respectively connected to the right side of the capacitor C4, the cathode of the diode D3, and the base of the transistor Q1. The right side of the capacitor C3 is respectively connected to the anode of the diode D3, the top of the resistor R11, the left side of the resistor R10, and the emitter of the transistor Q1. The right side of the resistor R9 is connected to the right side of the resistor R10. The right side of the resistor R10 generates a current inner loop given signal and is connected to the input terminal of the current inner loop control circuit. The collector of the transistor Q1 is connected to the +VCC power supply, and the bottom of the resistor R11 is connected to the -VCC power supply.

[0014] The second follower circuit includes an operational amplifier U4, a resistor R12, a resistor R13, a resistor R14, a capacitor C5, a capacitor C6, a diode D4, and a transistor Q2. The non-inverting input terminal of the operational amplifier U4 is connected to the non-inverting input terminal of the operational amplifier U7, the inverting input terminal of the operational amplifier U4 is respectively connected to the left side of the resistor R12, the left side of the capacitor C5, and the left side of the capacitor C6, the output terminal of the operational amplifier U4 is respectively connected to the right side of the capacitor C6, the cathode of the diode D4, and the base of the transistor Q2, the right side of the capacitor C5 is respectively connected to the anode of the diode D4, the top of the resistor R14, the left side of the resistor R13, and the emitter of the transistor Q2, the right side of the resistor R12 is respectively connected to the right side of the resistor R13 and the input terminal of the relay S3, the output terminal of the relay S3 is the Share+ signal, the collector of the transistor Q2 is connected to the +VCC power supply, and the bottom of the resistor R14 is connected to the -VCC power supply.

[0015] Furthermore, the device models of operational amplifiers U3 and U4 are consistent, the device models of diodes D3 and D4 are consistent, the device models of capacitors C4 and C6 are consistent, the device models of capacitors C3 and C5 are consistent, the device models of resistors R9 and R12 are consistent, the device models of resistors R10 and R13 are consistent, the device models of resistors R11 and R14 are consistent, the device models of transistors Q1 and Q2 are consistent, and resistors R15=R16=R17=R18.

[0016] A high-performance DC power parallel control method, the power supply has two working conditions: single power supply and parallel power supply; the power supply works in constant voltage mode or constant current mode; when working in constant voltage mode, the voltage outer loop control circuit works; when working in constant current mode, the current outer loop control circuit works.

[0017] Furthermore, when the power supply is a single unit, the output end of the voltage outer loop control circuit is connected in parallel with the current outer loop control circuit, and the output end of the first follower circuit is connected to the current inner loop control circuit, the current inner loop control circuit is connected to the PWM control circuit to drive the main power circuit, the voltage outer loop control circuit outputs a Vmaster signal connected to the input end of the second follower circuit, the output end of the second follower circuit is connected to the Share+ signal through relay S3, and the GND signal is connected to the Share- signal through relay S5.

[0018] Furthermore, when the power supplies are connected in parallel, when the host and N-1 slave power supplies work in constant voltage mode, the host and N-1 slave power supplies use the host's voltage outer loop control circuit:

[0019] When Vref is greater than Vmon, the voltage outer loop control circuit increases the Vmaster output through PI regulation, and finally reaches Vref=Vmon;

[0020] When Vref is less than Vmon, the Vmaster output is reduced through PI regulation, and finally Vmon=Vref;

[0021] When Vref=Vmon, Vmaster remains relatively stable;

[0022] The voltage outer loop control circuits of the N-1 slaves do not participate in loop regulation, and use analog circuits to transmit the voltage outer loop output signals.

[0023] Furthermore, when the power supplies are connected in parallel, when the host power supply and N-1 slave power supplies work in constant voltage mode, the host power supply signal transmission path is: the output end of the voltage outer loop control circuit and the current outer loop control circuit are connected in parallel to the input end of the first follower circuit, the output end OUT signal of the first follower circuit is connected to the current inner loop control circuit, and the current inner loop control circuit is connected to the PWM control circuit to drive the main power circuit;

[0024] N-1 slave power supplies receive the host power supply voltage outer loop control signal transmission path: the host power supply voltage outer loop control output Vmaster signal is connected to the host power supply second follower circuit input end, the host power supply second follower circuit output Vmaster-OUT signal is connected to the Share+ signal through the host power supply relay S3, and the GND signal is connected to the Share- signal through the host power supply relay S5. The host power supply is connected to the Share+ signal and Share- signal in each slave power supply using the data bus. The relay S4 of each slave power supply is closed, and the input end of the relay S4 is connected to the Vslave-IN signal. The relay S6 of each slave power supply is closed, and the input end of the relay S6 is connected to the GND-IN signal. The output end Vslave signal of each slave power supply differential circuit is connected to the input end of the slave power supply relay S2. The relay S2 is closed, and the output end of the relay S2 is connected to the input end of the first follower circuit of the slave. The output end OUT signal of the first follower circuit is connected to the current inner loop control circuit, and the current inner loop control circuit is connected to the PWM control circuit to complete the driving of the main power circuit.

[0025] Furthermore, when the power supplies are connected in parallel, when the host power supply and N-1 slave power supplies work in constant current mode, the current outer loop control circuit works:

[0026] When Iref is greater than Imon, the current outer loop increases the output of the current outer loop through PI regulation, and finally reaches Iref=Imon;

[0027] When Iref is less than Imon, the current outer loop reduces the output of the current outer loop through PI regulation, and finally reaches Imon=Iref;

[0028] When Iref=Imon, the current outer loop output remains relatively stable;

[0029] Set the total current value of the host The actual current setting value of the power supply of the host and N-1 slaves is , The value error is within 1mA. The magnitude and amplitude of the current outer loop given signal Iref of the host and N-1 slave power supplies are the same. The sampling current Imon is the Imon signal sampled by each host or slave power supply. The output current of each power supply is consistent, and the current outer loop circuit of each power supply is independently adjusted.

[0030] Furthermore, when the power supplies are paralleled, the STM32 main control chip completes the interconnection between the host and the slaves through RS485 digital communication, and the host and N-1 slaves synchronously start, stop, transmit alarm signals, and set and display digital control power supply current.

[0031] The advantages of the present invention are: using a mixed control method of analog circuit and digital circuit to realize power parallel control, the voltage outer loop output signal adopts analog circuit control to ensure uninterrupted and continuous signal transmission, the transmission speed is fast, and the dynamic performance of the power supply is guaranteed;

[0032] The first follower circuit is used to enhance the output signal driving capability of the loop regulation module. When the power supplies are connected in parallel, the second power follower circuit of the host power supply is used to ensure the output signal driving capability of the voltage outer loop control circuit, reduce the number of analog circuit cascades, and reduce analog errors.

[0033] RS485 digital communication control mode is adopted. The STM32 control circuit completes the communication between the host and N-1 slave power supplies in real time through RS485 communication, ensuring that the magnitude and amplitude of the current outer loop given signal Iref of the host and N-1 slave power supplies are the same, ensuring that the output current of each power supply is consistent, and the current display value of each slave communicates with the host stm32 in real time through RS485 communication. The total display value of each power supply is summed to ensure the accuracy of the parallel current. There is no need to calibrate the total current accuracy, which is convenient for user operation. The current outer loop circuit of each power supply is adjusted independently, and does not involve the transmission of the output signal of the host and slave current outer loop. The number of slave power supplies can be increased or decreased according to actual conditions. Digital communication controls the transmission of power supply start, stop, alarm and other signals to ensure the safe and reliable operation of multiple power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a connection diagram of a high-performance DC power supply parallel control system according to Embodiment 1 of the present invention;

[0035] Figure 2 This is a schematic diagram of the connection of the functional modules of the high-performance DC power parallel control system according to Example 1 of the present invention;

[0036] Figure 3This is a power supply circuit diagram of Embodiment 1 of the present invention;

[0037] Figure 4 This is a wiring diagram of a high-performance DC power supply parallel control method according to Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0039] Example 1

[0040] This embodiment discloses a high-performance DC power parallel system. Figure 1 , including N power supplies with the same structure, the N power supplies include a host power supply and N-1 slave power supplies, N is a positive integer, and the parallel control only requires 4 signals, namely Share+ signal, Share- signal, RS485-A signal, and RS485-B signal. When paralleling, the same signal line connection is required, among which Share+ signal and Share- signal are analog signals, RS485-A signal and RS485-B signal are digital signals. The parallel control is completed through the analog and digital hybrid control method, and the output terminals of the host and slave power supplies are connected to the positive and the negative to the negative.

[0041] Please refer to Figure 2 All power supplies are connected in parallel, each power supply includes: a loop control module, a follower module, a differential circuit, and a communication module. The output end of the loop control module is connected to the input end of the follower module. The loop control module includes a voltage outer loop control circuit and a current outer loop control circuit. The follower module includes a first follower circuit and a second follower circuit. The communication module includes an STM32 circuit, a differential drive circuit, and an RS485 circuit connected in sequence.

[0042] Please refer to Figure 3The voltage outer loop control circuit includes an operational amplifier U1, an operational amplifier U7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R19, a capacitor C1, and a diode D1. The left side of the resistor R1 is connected to the voltage sampling Vmon signal, the right side of the resistor R1 and the left side of the resistor R3 are connected to the inverting input terminal of the operational amplifier U1, the left side of the resistor R2 is connected to the voltage given Vref signal, the right side of the resistor R2 is connected to the non-inverting input terminal of the operational amplifier U1, the right side of the resistor R3 is connected to the left side of the capacitor C1, the right side of the capacitor C1 and the anode of the diode D1 are connected to the non-inverting input terminal of the operational amplifier U7 to output the Vmaster signal, the cathode of the diode D1 is connected in series with the resistor R4 and then connected to the output terminal of the operational amplifier U1, the inverting input terminal of the operational amplifier U7 and the right side of the resistor R19 are connected to the input terminal of the relay S1, and the left side of the resistor R19 is connected to the output terminal of the operational amplifier U7. The power supply works in constant voltage (CV) mode. When the Vref voltage is greater than Vmon, the voltage outer loop increases the Vmaster output through PI regulation, and finally reaches Vref=Vmon; when the Vref voltage is less than Vmon, the voltage outer loop reduces the Vmaster output through PI regulation; finally reaches Vmon=Vref, when Vref=Vmon, Vmaster maintains relatively stable; the circuit composed of operational amplifier U7 and resistor R19 in the circuit prevents the host's current outer loop output signal from being transmitted to the slave when the power supply is parallel.

[0043] The current outer loop control circuit includes an operational amplifier U2, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C2, and a diode D2. The left side of the resistor R5 is connected to the current sampling Imon signal, the right side of the resistor R5 and the left side of the resistor R6 are connected to the inverting input terminal of the operational amplifier U2, the left side of the resistor R7 is connected to the voltage given Iref signal, the right side of the resistor R7 is connected to the in-phase input terminal of the operational amplifier U2, the right side of the resistor R6 is connected in series with the capacitor C2 and then connected to the anode of the diode D2 and the output terminal of the relay S1, and the resistor R8 is connected in series between the cathode of the diode D2 and the output terminal of the operational amplifier U2. When the Iref voltage is greater than Imon, the current outer loop increases the output of the current outer loop through PI regulation, and finally reaches Iref=Imon; when Iref is less than Imon, the current outer loop reduces the output of the current outer loop through PI regulation; and finally reaches Imon=Iref. When Iref=Imon, the output of the current outer loop remains relatively stable.

[0044] The differential circuit includes an operational amplifier U5, a resistor R15, a resistor R16, a resistor R17, and a resistor R18. The left side of the resistor R15 is connected to the input of the relay S6. The right side of the resistor R15 and the left side of the resistor R16 are connected to the inverting input of the operational amplifier U5. The right side of the resistor R16 is connected to the output Vslave signal of the operational amplifier U5 and the input of the relay S2. The left side of the resistor 17 is connected to the input Vslave-IN signal of the relay S4. The output of the relay S4 is connected to the Share+ signal. The right side of the resistor 17 and the top of the resistor 18 are connected to the in-phase input of the U5. The bottom of the resistor R18 is connected to the input of the relay S5. Resistors R15=R16=R17=R18. The data bus harness of multiple power supplies in parallel may be relatively long. A differential circuit is used to prevent the analog signal from being offset due to deviations in the GND network when the analog signal is transmitted over long distances.

[0045] The first follower circuit includes an operational amplifier U3, a resistor R9, a resistor R10, a resistor R11, a capacitor C3, a capacitor C4, a diode D3, and a transistor Q1. The non-inverting input terminal of the operational amplifier U3 is respectively connected to the output terminal of the relay S1 and the output terminal of the relay S2. The inverting input terminal of the operational amplifier U3 is respectively connected to the left side of the resistor R9, the left side of the capacitor C3, and the left side of the capacitor C4. The output terminal of the operational amplifier U3 is respectively connected to the right side of the capacitor C4, the cathode of the diode D3, and the base of the transistor Q1. The right side of the capacitor C3 is respectively connected to the anode of the diode D3, the top of the resistor R11, the left side of the resistor R10, and the emitter of the transistor Q1. The right side of the resistor R9 is connected to the right side of the resistor R10. The right side of the resistor R10 generates a current inner loop given signal OUT, which is connected to the input terminal of the current inner loop control circuit. The collector of the transistor Q1 is connected to the +VCC power supply, and the bottom of the resistor R11 is connected to the -VCC power supply. There are several identical power modules in a power supply, and the output signal of the loop control module needs to have a strong driving capability. A follower circuit module needs to be added. Its functional principle is: when the OUT signal drives multiple modules, its voltage drops. When the common-mode input terminal of the operational amplifier U3 is greater than the OUT signal, the output voltage of the operational amplifier U3 increases, and then the output current capacity of Q1 increases, thereby enhancing the driving capability of the OUT signal.

[0046] The second follower circuit includes an operational amplifier U4, a resistor R12, a resistor R13, a resistor R14, a capacitor C5, a capacitor C6, a diode D4, and a transistor Q2. The in-phase input terminal of the operational amplifier U4 is connected to the Vmaster signal, the inverting input terminal of the operational amplifier U4 is respectively connected to the left side of the resistor R12, the left side of the capacitor C5, and the left side of the capacitor C6. The output terminal of the operational amplifier U4 is respectively connected to the right side of the capacitor C6, the cathode of the diode D4, and the base of the transistor Q2. The right side of the capacitor C5 is respectively connected to the anode of the diode D4, the top of the resistor R14, the left side of the resistor R13, and the emitter of the transistor Q2. The right side of the resistor R12 is respectively connected to the right side of the resistor R13 and the input terminal Vmaster-OUT signal of the relay S3. The output terminal of the relay S3 is the Share+ signal. The collector of the transistor Q2 is connected to the +VCC power supply, and the bottom of the resistor R14 is connected to the -VCC power supply. Its principle is the same as the first follower circuit, except that the driving capability of the voltage outer loop output signal of the host power supply is increased. The device models used in the same position of the first and second follower circuits in the follower circuit module are consistent, the device models of operational amplifiers U3 and U4 are consistent, the device models of diodes D3 and D4 are consistent, the device models of capacitors C4 and C6 are consistent, the device models of capacitors C3 and C5 are consistent, the device models of resistors R9 and R12 are consistent, the device models of resistors R10 and R13 are consistent, the device models of resistors R11 and R14 are consistent, and the device models of transistors Q1 and Q2 are consistent, ensuring that the host voltage outer loop transmission signal is respectively transmitted to the host current inner loop and transmitted to the slave power follower circuit in a consistent manner.

[0047] The GND signal is connected to the Share- signal through relay S5, the GND-IN signal is connected to the Share- signal through relay S6, and the RS485 circuit outputs RS485-A signal and RS485-B signal.

[0048] Example 2

[0049] A high-performance DC power parallel control method, the power supply has two working conditions: single power supply and parallel power supply; the power supply works in constant voltage mode or constant current mode; when working in constant voltage mode, the voltage outer loop control circuit works; when working in constant current mode, the current outer loop control circuit works.

[0050] When paralleling the power supply, please refer to Figure 4The power supply uses its own voltage outer loop control circuit and current outer loop control circuit. The voltage outer loop control circuit is connected in parallel with the current outer loop control circuit. The relay control logic is that S1, S3, and S5 are closed, and S2, S4, and S6 are disconnected. When the power supply is in parallel, it is divided into the host and the slave. When the power supply is the host, the relay control logic is: S1, S3, and S5 are closed, and S2, S4, and S6 are disconnected. When the power supply is the slave, the relay control logic is: S1, S3, and S5 are disconnected, and S2, S4, and S6 are closed. The parallel power supply signal transmission requires a data bus to connect the same signals such as the Share+ signal, Share- signal, RS485-A signal, and RS485-B signal of the host and slave power supplies respectively to realize parallel control. The output terminals of the host and slave power supplies are connected positively and negatively. The host and N-1 slaves share the voltage outer loop control circuit of the host, and the host and N-1 slaves use their own current outer loop control circuits respectively.

[0051] When the power supplies are connected in parallel, when the host power supply and N-1 slave power supplies work in constant voltage (CV) mode, the host power supply signal transmission path is: after the voltage outer loop control circuit and the current outer loop control circuit are connected in parallel, the output end is connected to the input end of the first follower circuit, the output end OUT signal of the first follower circuit is connected to the current inner loop control circuit, and the current inner loop control circuit is connected to the PWM control circuit to complete driving the main power circuit.

[0052] N-1 slave power supplies receive the host power supply voltage outer loop control signal transmission path: the host power supply voltage outer loop control output Vmaster signal is connected to the host power supply second follower circuit input end, the host power supply second follower circuit output Vmaster-OUT signal is connected to the Share+ signal through the host power supply relay S3, and the GND signal is connected to the Share- signal through the host power supply relay S5. The host power supply is connected to the Share+ signal and Share- signal in each slave power supply using the data bus. The relay S4 of each slave power supply is closed, and the input end of the relay S4 is connected to the Vslave-IN signal. The relay S6 of each slave power supply is closed, and the input end of the relay S6 is connected to the GND-IN signal. The output end Vslave signal of each slave power supply differential circuit is connected to the input end of the slave power supply relay S2. The relay S2 is closed, and the output end of the relay S2 is connected to the input end of the first follower circuit of the slave. The output end OUT signal of the first follower circuit is connected to the current inner loop control circuit, and the current inner loop control circuit is connected to the PWM control circuit to complete the driving of the main power circuit.

[0053] When the power supplies are paralleled, when the host power supply and N-1 slave power supplies work in constant current (CC) mode, the current outer loop control circuit works to set the total host current value The actual current setting value of the power supply of the host and N-1 slaves is , The value error is within 1mA. The magnitude and amplitude of the given signal Iref of the current outer loop of the host and N-1 slave power supplies are the same. The sampling current Imon is the Imon signal sampled by each host or slave power supply itself. The output current of each power supply is consistent. The current outer loop circuit of each power supply is adjusted independently, and the transmission of the output signal of the host and slave current outer loop is not involved. The number of slave power supplies can be increased or decreased according to actual conditions, and there is no need to calibrate the total current accuracy, which is convenient for user operation.

[0054] When the power supplies are connected in parallel, the STM32 main control chip completes the interconnection between the host and the slaves through RS485 digital communication. The host and N-1 slaves synchronously start, stop, transmit alarm signals, and set and display the digital control power supply current.

[0055] Example 3

[0056] When the power supply is a single unit, the voltage outer loop control circuit and the current outer loop control circuit are connected in parallel, and the output end is connected to the input end of the first follower circuit, the output end of the first follower circuit is connected to the current inner loop control circuit, the current inner loop control circuit is connected to the PWM control circuit to drive the main power circuit, the voltage outer loop control circuit outputs the Vmaster signal connected to the input end of the second follower circuit, the output end of the second follower circuit is connected to the Share+ signal through relay S3, and the GND signal is connected to the Share- signal through relay S5.

[0057] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-performance DC power parallel system, characterized in that: The invention comprises N power supplies with the same structure, wherein the N power supplies include a host power supply and N-1 slave power supplies, and N is a positive integer; All power supplies are connected in parallel, and each power supply includes: a loop control module, a follower module, a differential circuit, and a communication module, and the output end of the loop control module is connected to the input end of the follower module; The loop control module includes a voltage outer loop control circuit and a current outer loop control circuit, the follower module includes a first follower circuit and a second follower circuit, and the communication module includes an STM32 circuit, a differential drive circuit and an RS485 circuit connected in sequence; The input ends of the voltage outer loop control circuit are respectively the voltage sampling Vmom signal and the given Vref signal, the input ends of the current outer loop control circuit are respectively the current sampling Imom signal and the given Iref signal, the output end of the current outer loop control circuit is connected to the input end of the first follower circuit, the first output end of the voltage outer loop control circuit is the output signal of the voltage follower through PI regulation of the voltage sampling Vmom signal and the given Vref signal, the signal is connected to the input end of the relay S1, the output end of the relay S1 is connected to the input end of the first follower circuit, the output end Vslave signal of the differential circuit is connected to the input end of the relay S2, the Vslave signal is the signal after the Share+ signal and the Share- signal of the power supply parallel host are differentially operated, the relay S 2 output end is connected to the input end of the first follower circuit, the output end of the first follower circuit is connected to the input end of the current inner loop control circuit, the second output end Vmaster signal of the voltage outer loop control circuit is connected to the input end of the second follower circuit, the Vmaster signal is a signal output after the voltage sampling Vmom signal and the given Vref signal are adjusted by PI, the output end Vmaster-OUT signal of the second follower circuit is connected to the input end of the relay S3, the differential circuit input end Vslave-IN signal is connected to the input end of the relay S4, the Vslave-IN signal is the Share+ signal sent by the host when the power supplies are parallel, the output ends of the relays S3 and S4 are connected to the Share+ signal, the GND signal is connected to the Share- signal through the relay S5, the GND-IN signal is connected to the Share- signal through the relay S6, the GND-IN signal is the GND signal of the host when the power supplies are parallel, the RS485 circuit outputs RS485-A signal and RS485-B signal, the data bus connects the same signals of the host and slave power supplies respectively, and the output ends of the host and slave power supplies are connected positively to positive and negatively to negative.

2. According to claim 1, the high-performance DC power parallel system is characterized in that: The voltage outer loop control circuit includes an operational amplifier U1, an operational amplifier U7, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R19, a capacitor C1, and a diode D1. The left side of the resistor R1 is connected to a voltage sampling Vmon signal, the right side of the resistor R1 and the left side of the resistor R3 are connected to the inverting input terminal of the operational amplifier U1, the left side of the resistor R2 is connected to a voltage given Vref signal, the right side of the resistor R2 is connected to the non-inverting input terminal of the operational amplifier U1, the right side of the resistor R3 is connected to the left side of the capacitor C1, the right side of the capacitor C1 and the anode of the diode D1 are connected to the non-inverting input terminal of the operational amplifier U7, the cathode of the diode D1 is connected in series with the resistor R4 and then connected to the output terminal of the operational amplifier U1, the inverting input terminal of the operational amplifier U7 and the right side of the resistor R19 are connected to the input terminal of the relay S1, and the left side of the resistor R19 is connected to the output terminal of the operational amplifier U7; The current outer loop control circuit includes an operational amplifier U2, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C2, and a diode D2. The left side of the resistor R5 is connected to a current sampling Imon signal, the right side of the resistor R5 and the left side of the resistor R6 are connected to the inverting input terminal of the operational amplifier U2, the left side of the resistor R7 is connected to a voltage given Iref signal, the right side of the resistor R7 is connected to the non-inverting input terminal of the operational amplifier U2, the right side of the resistor R6 is connected in series with the capacitor C2 and then connected to the anode of the diode D2 and the output terminal of the relay S1, and the resistor R8 is connected in series between the cathode of the diode D2 and the output terminal of the operational amplifier U2; The differential circuit includes an operational amplifier U5, a resistor R15, a resistor R16, a resistor R17, and a resistor R18. The left side of the resistor R15 is connected to the input end of the relay S6, the right side of the resistor R15 and the left side of the resistor R16 are connected to the inverting input end of the operational amplifier U5, the right side of the resistor R16 are respectively connected to the output end of the operational amplifier U5 and the input end of the relay S2, the left side of the resistor 17 is connected to the input end of the relay S4, the right side of the resistor 17 and the upper side of the resistor 18 are connected to the in-phase input end of the U5, and the lower side of the resistor R18 is connected to the input end of the relay S5; The first follower circuit includes an operational amplifier U3, a resistor R9, a resistor R10, a resistor R11, a capacitor C3, a capacitor C4, a diode D3, and a transistor Q1. The in-phase input terminal of the operational amplifier U3 is respectively connected to the output terminal of the relay S1 and the output terminal of the relay S2. The inverting input terminal of the operational amplifier U3 is respectively connected to the left side of the resistor R9, the left side of the capacitor C3, and the left side of the capacitor C4. The output terminal of the operational amplifier U3 is respectively connected to the right side of the capacitor C4, the cathode of the diode D3, and the base of the transistor Q1. The right side of the capacitor C3 is respectively connected to the anode of the diode D3, the top of the resistor R11, the left side of the resistor R10, and the emitter of the transistor Q1. The right side of the resistor R9 is connected to the right side of the resistor R10. The right side of the resistor R10 generates a current inner loop given signal and is connected to the input terminal of the current inner loop control circuit. The collector of the transistor Q1 is connected to the +VCC power supply, and the bottom of the resistor R11 is connected to the -VCC power supply. The second follower circuit includes an operational amplifier U4, a resistor R12, a resistor R13, a resistor R14, a capacitor C5, a capacitor C6, a diode D4, and a transistor Q2. The non-inverting input terminal of the operational amplifier U4 is connected to the non-inverting input terminal of the operational amplifier U7, the inverting input terminal of the operational amplifier U4 is respectively connected to the left side of the resistor R12, the left side of the capacitor C5, and the left side of the capacitor C6, the output terminal of the operational amplifier U4 is respectively connected to the right side of the capacitor C6, the cathode of the diode D4, and the base of the transistor Q2, the right side of the capacitor C5 is respectively connected to the anode of the diode D4, the top of the resistor R14, the left side of the resistor R13, and the emitter of the transistor Q2, the right side of the resistor R12 is respectively connected to the right side of the resistor R13 and the input terminal of the relay S3, the output terminal of the relay S3 is the Share+ signal, the collector of the transistor Q2 is connected to the +VCC power supply, and the bottom of the resistor R14 is connected to the -VCC power supply.

3. The high performance DC power parallel system according to claim 2, characterized in that: The operational amplifiers U3 and U4 have the same device model, the diodes D3 and D4 have the same device model, the capacitors C4 and C6 have the same device model, the capacitors C3 and C5 have the same device model, the resistors R9 and R12 have the same device model, the resistors R10 and R13 have the same device model, the resistors R11 and R14 have the same device model, the transistors Q1 and Q2 have the same device model, and the resistors R15=R16=R17=R18.

4. A high-performance DC power parallel control method, based on the high-performance DC power parallel system of claim 1, characterized in that: There are two working conditions of the power supply: single power supply and parallel power supply; the power supply works in constant voltage mode or constant current mode; when working in constant voltage mode, the voltage outer loop control circuit works; when working in constant current mode, the current outer loop control circuit works.

5. The high performance DC power parallel control method according to claim 4, characterized in that: When the power supply is a single unit, the voltage outer loop control circuit and the current outer loop control circuit are connected in parallel, and the output end is connected to the input end of the first follower circuit, the output end of the first follower circuit is connected to the current inner loop control circuit, the current inner loop control circuit is connected to the PWM control circuit to drive the main power circuit, the voltage outer loop control circuit outputs the Vmaster signal connected to the input end of the second follower circuit, the output end of the second follower circuit is connected to the Share+ signal through relay S3, and the GND signal is connected to the Share- signal through relay S5.

6. The high performance DC power parallel control method according to claim 4, characterized in that: When the power supplies are connected in parallel, when the host and N-1 slave power supplies work in constant voltage mode, the host and N-1 slave power supplies use the host's voltage outer loop control circuit: When Vref is greater than Vmon, the voltage outer loop control circuit increases the Vmaster output through PI regulation, and finally reaches Vref=Vmon; When Vref is less than Vmon, the Vmaster output is reduced through PI regulation, and finally Vmon=Vref; When Vref=Vmon, Vmaster remains relatively stable; The voltage outer loop control circuits of the N-1 slaves do not participate in loop regulation, and use analog circuits to transmit the voltage outer loop output signals.

7. The high performance DC power parallel control method according to claim 6, characterized in that: When the power supplies are connected in parallel, when the host power supply and N-1 slave power supplies work in constant voltage mode, the host power supply signal transmission path: the voltage outer loop control circuit and the current outer loop control circuit are connected in parallel, and the output end is connected to the input end of the first follower circuit, and the output end OUT signal of the first follower circuit is connected to the current inner loop control circuit, and the current inner loop control circuit is connected to the PWM control circuit to drive the main power circuit; N-1 slave power supplies receive the host power supply voltage outer loop control signal transmission path: the host power supply voltage outer loop control output Vmaster signal is connected to the host power supply second follower circuit input end, the host power supply second follower circuit output Vmaster-OUT signal is connected to the Share+ signal through the host power supply relay S3, and the GND signal is connected to the Share- signal through the host power supply relay S5. The host power supply is connected to the Share+ signal and Share- signal in each slave power supply using the data bus. The relay S4 of each slave power supply is closed, and the input end of the relay S4 is connected to the Vslave-IN signal. The relay S6 of each slave power supply is closed, and the input end of the relay S6 is connected to the GND-IN signal. The output end Vslave signal of each slave power supply differential circuit is connected to the input end of the slave power supply relay S2. The relay S2 is closed, and the output end of the relay S2 is connected to the input end of the first follower circuit of the slave. The output end OUT signal of the first follower circuit is connected to the current inner loop control circuit, and the current inner loop control circuit is connected to the PWM control circuit to complete the driving of the main power circuit.

8. The high performance DC power parallel control method according to claim 4, characterized in that: When the power supplies are connected in parallel, when the host power supply and N-1 slave power supplies work in constant current mode, the current outer loop control circuit works: When Iref is greater than Imon, the current outer loop increases the output of the current outer loop through PI regulation, and finally reaches Iref=Imon; When Iref is less than Imon, the current outer loop reduces the output of the current outer loop through PI regulation, and finally reaches Imon=Iref; When Iref=Imon, the current outer loop output remains relatively stable; Set the total current value of the host The actual current setting value of the power supply of the host and N-1 slaves is , The value error is within 1mA. The magnitude and amplitude of the current outer loop given signal Iref of the host and N-1 slave power supplies are the same. The sampling current Imon is the Imon signal sampled by each host or slave power supply. The output current of each power supply is consistent, and the current outer loop circuit of each power supply is independently adjusted.

9. The high performance DC power parallel control method according to claim 4, characterized in that: When the power supplies are connected in parallel, the STM32 main control chip completes the interconnection between the host and the slaves through RS485 digital communication. The host and N-1 slaves synchronously start, stop, transmit alarm signals, and set and display the digital control power supply current.

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