A data synchronization acquisition method, device, equipment and readable storage medium

Abstract

The present invention discloses a data synchronization acquisition method, device, equipment and readable storage medium, which are applied to the field of data acquisition, including: using the FPGA of each device to receive the PPS pulse sent by the GPS timing module; when the start condition is met and the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the current PPS pulse response ends; each equally divided node is calculated according to the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response. This method uses the GPS timing module and FPGA timestamp counting to realize multi-board data synchronization acquisition at the software level, so only the software needs to be modified, and the hardware does not need to be changed, the rectification cycle is short, the cost is low, and the effect is good.

Description

Technical Field

[0001] The present invention relates to the field of data acquisition, and in particular to a data synchronization acquisition method, device, equipment and readable storage medium. Background Art

[0002] Nowadays, many electronic and electrical products on the market involve crystal oscillators (full name: crystal oscillator). Due to the limitations of crystal oscillator materials and processes, the crystal oscillator is allowed to have an error of several to tens of ppm (precision capacitance value, representing one part per million, ppm indicates the accuracy and relative deviation of crystal oscillation), which leads to increasing delay errors of different electronic and electrical boards, making it impossible to achieve data acquisition synchronization; and due to errors between crystal oscillators and the crystal oscillator itself due to changes in temperature and time, the clock frequency and clock cycle will also be different, which makes the data collection time of each set of equipment asynchronous. The existing solution starts from the hardware and ensures that the crystal oscillator accuracy is as accurate as possible in hardware, but the hardware rectification cycle is long, the cost is high, and the effect is difficult to guarantee.

[0003] Therefore, how to achieve multi-board-level data acquisition synchronization is an urgent problem that needs to be solved. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a data synchronization acquisition method, device, equipment and readable storage medium, which solves the problem of asynchronous multi-board level data acquisition in the prior art.

[0005] In order to solve the above technical problems, the present invention provides a data synchronization acquisition method, comprising:

[0006] Use the FPGA of each device to receive the PPS pulse sent by the GPS timing module;

[0007] When the start condition is met, a PPS pulse response is performed; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the PPS pulse response ends;

[0008] The equal-division nodes are calculated based on the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the first PPS pulse response.

[0009] Optionally, the equally divided nodes include:

[0010] The number of the equally divided nodes is the preset total number of frames;

[0011] The time interval T between each of the equally divided nodes is the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames;

[0012] The collection time of each equally divided node is obtained according to the time interval T between the equally divided nodes.

[0013] Optionally, when the start condition is met, performing a PPS pulse response includes:

[0014] When each device receives the PPS pulse for the first time, it performs a PPS pulse response;

[0015] Or, when the power-on time reaches a preset time, a PPS pulse response is performed.

[0016] Optionally, the timestamp value of the first PPS pulse response is the total number of timestamps counted during the first PPS pulse response, including:

[0017] When each device receives the PPS pulse for the first time, it starts collecting data using the FPGA of each device and starts counting timestamps. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends and the value of the timestamp count is recorded.

[0018] The present invention also provides a data synchronization acquisition device, comprising:

[0019] The receiving module is used to use the FPGA of each device to receive the PPS pulse sent by the GPS timing module;

[0020] A response module is used to perform a PPS pulse response when a start condition is met; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the PPS pulse response ends; wherein, each equally divided node is calculated based on the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the time of the first PPS pulse response.

[0021] Optionally, the response module includes:

[0022] An equally divided node number subunit, used to determine the number of equally divided nodes to be the preset total number of frames;

[0023] The inter-node time interval subunit is used to calculate the time interval T between each of the equally divided nodes as the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames.

[0024] Optionally, the response module includes:

[0025] A first starting unit, configured to perform a PPS pulse response when each device receives the PPS pulse not for the first time;

[0026] or,

[0027] The second starting unit is used to perform a PPS pulse response when the power-on time reaches a preset time.

[0028] Optionally, the response module includes:

[0029] The timestamp value calculation unit of the first PPS pulse response is used to start collecting data using the FPGA of each device when each device receives the PPS pulse for the first time, and start timestamp counting at the same time. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends and the value of the timestamp count at this time is recorded.

[0030] The present invention also provides a data synchronization acquisition device, comprising:

[0031] Memory for storing computer programs;

[0032] A processor is used to implement the steps of the above-mentioned data synchronization acquisition method when executing the computer program.

[0033] The present invention also provides a readable storage medium, in which computer executable instructions are stored. When the computer executable instructions are loaded and executed by a processor, the steps of the above-mentioned data synchronization acquisition method are implemented.

[0034] It can be seen that the present invention utilizes the FPGA of each device to receive the PPS pulse sent by the GPS timing module; when the start condition is met, a PPS pulse response is performed; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the current PPS pulse response ends; each equally divided node is calculated based on the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the time of the first PPS pulse response. The method utilizes the GPS timing module and the FPGA timestamp counting to realize the synchronous acquisition of data between multiple boards or multiple devices containing boards, and corrects the time delay caused by the crystal oscillator to the board. The method realizes the synchronous acquisition of multi-board data at the software level, so only the software needs to be modified, and the hardware does not need to be changed. The rectification cycle is short, the cost is low, and the effect is good.

[0035] In addition, the present invention also provides a data synchronization acquisition device, equipment and readable storage medium, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A flowchart of a data synchronization acquisition method provided by an embodiment of the present invention;

[0038] Figure 2 A flowchart of a data synchronization acquisition method provided by an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the structure of a data synchronization acquisition device provided by an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the structure of a data synchronization acquisition device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] Please refer to Figure 1 , Figure 1 A flowchart of a data synchronization acquisition method provided by an embodiment of the present invention. The method may include:

[0043] S101: using the FPGA of each device to receive the PPS pulse sent by the GPS timing module.

[0044] It should be noted that each device has a crystal oscillator board. To ensure that the FPGA (Field-Programmable Gate Array) of each device can synchronously collect data when it receives the PPS (Pulse Per Second) pulse sent by the GPS (Global Positioning System) timing module, the total number of frames of data collected per second by each device should be the same. In other words, when each device responds to the PPS pulse, it can collect data at the same rate or ensure that each frame of data starts at the same time, thus achieving the purpose of synchronous data collection by the FPGA of each device. This embodiment does not limit the number of devices. The devices in this embodiment are all the same device, which ensures synchronous data collection of the same device.

[0045] Among them, PPS is formally defined as: the GPS receiver module (GPS Receiver) can generate a second pulse signal, which is used to indicate the time interval of the whole second, and the rising edge of PPS marks the specific time corresponding to the UTC (Coordinated Universal Time) time given by GPS. The accuracy of indicating the whole second time can reach tens of nanoseconds, without cumulative error. The PPS generated every second and the whole second time it gives can be used for precise frequency modulation of the crystal oscillator - clock synchronization.

[0046] S102: When the start conditions are met, a PPS pulse response is performed; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the PPS pulse response ends.

[0047] In this embodiment, each equally divided node is calculated based on the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted when the first PPS pulse response is received. Step S102 is a way of responding to the PPS pulse, a process of data collection, a process of data collection synchronization, and a process of correction or calibration.

[0048] This embodiment does not limit the startup conditions. For example, when the difference in the length of time for each device to respond to a PPS pulse exceeds a preset threshold, it means that there is a problem with the data acquisition synchronization of each device, and the data acquisition calibration can be started at this time, that is, step S102. Alternatively, it can also be that when the power-on time exceeds the preset time, step S102 is executed. Alternatively, it can also be that when responding to the PPS pulse for the second time, step S102 is executed. When the startup conditions are not met, the PPS pulse is responded to normally, that is, no correction is required. Normal response to the PPS pulse specifically means that the FPGA of each device collects data normally, and there is no need to collect data according to each equally divided node.

[0049] This embodiment does not limit the calculation process of the equally divided nodes. For example, it can be that when responding to the PPS pulse for the first time, the total number of timestamps counted from the first start of the response to the end of the first response is used to obtain the timestamp value of the first PPS pulse response, and each equally divided node is calculated using the timestamp value of the first PPS pulse response. Alternatively, each equally divided node can also be calculated using the timestamp of the last PPS pulse response. For better understanding, the following example is given: if the timestamp value of the first PPS pulse response is 800, the preset total number of frames is 100 frames, and the preset number of equally divided nodes is 50, then the time period between the equally divided nodes is 16 timestamps, that is, 2 frames of data are collected every 16 timestamps. Among them, this embodiment does not limit the number of preset equally divided nodes. For example, the number of equally divided nodes can be consistent with the preset total number of frames; or the user can also set the number of equally divided nodes according to actual needs, usually as long as it can be divided by the timestamp value.

[0050] Furthermore, in order to more conveniently obtain each equally divided node, the above equally divided nodes can be obtained by the following steps:

[0051] The number of equally divided nodes is the preset total number of frames;

[0052] The time interval T between each equally divided node is the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames;

[0053] The collection time of each equally divided node is obtained according to the time interval T between the equally divided nodes.

[0054] This embodiment directly sets the preset total number of frames to the number of equally divided nodes. In this way, there is no need to manually set the number of equally divided nodes, avoiding manual participation. For better understanding, an example is as follows: if the timestamp value of the first PPS pulse response is 800, and the preset total number of frames is 100 frames, then the time period between equally divided nodes is 8 timestamps, that is, 1 frame of data is collected every 8 timestamps.

[0055] In fact, the time interval T is equal to the sum of the time t1 of actually collecting one frame and the time margin t2. Because the crystal oscillators of various devices are different, the time t1 of actually collecting one frame for each set of equipment will also have deviations. If it is not resolved, the deviation will become larger and larger, resulting in asynchrony. Therefore, the time interval T in this embodiment is the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames N, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames N. In other words, only when the time reaches the time of the equally divided node will a frame of data be collected. In this way, it is ensured that each frame of data of different devices is collected from the same time, even if there are differences in the crystal oscillators themselves or there are delays in time, the synchronization of data collection will not be affected. The principle is that the device with a fast collection rate waits for the device with a slow collection rate to ensure that the collection of each frame of data starts at the same time, and the same number of frames are collected in the same time, thereby achieving a synchronization effect.

[0056] Furthermore, in order to ensure efficiency while achieving accurate synchronization, when the start condition is met, the PPS pulse response may include the following steps:

[0057] When each device receives a PPS pulse not for the first time, it performs a PPS pulse response;

[0058] Or, when the power-on time reaches a preset time, a PPS pulse response is performed.

[0059] When the system is powered on, the GPS timing module sends a PPS pulse once per second. When the GPS timing module sends a PPS pulse for the first time, within a PPS pulse interval, the number of frames collected between devices will not differ greatly, because the crystal oscillator error is at the ppm level, which is very small at the beginning (a few nanoseconds), but will accumulate with time delay. Therefore, when the first PPS pulse is received just after power-on, the FPGA of each device starts collecting at the same time. At this time, the data collection of each device is synchronized (that is, each device collects N frames per second, and the error between devices is very small and within the allowable range). It is just that with the delay of the device running time (for example, 0.5 hours, 1 hour or more), the error will become larger and larger. Therefore, step S102 of this embodiment can perform data collection synchronization correction when the second PPS pulse response is made; or the step of data collection synchronization correction (that is, step S102) can be performed after power-on for a period of time. This embodiment does not limit the preset time. For example, the data collection for the previous hour is executed according to the original PPS response, and step S102 is executed one hour after power-on to correct the data collection asynchronism that occurred in the previous period; or the data collection for the previous half hour is executed according to the original PPS response, and step S102 is executed half an hour after power-on to correct the data collection asynchronism that occurred in the previous period. The user can set it according to the crystal oscillator accuracy of the device.

[0060] Furthermore, in order to ensure the accuracy of data synchronization acquisition, the timestamp value of the first PPS pulse response can be obtained by the following steps:

[0061] When each device receives the PPS pulse for the first time, it uses the FPGA of each device to start collecting data and start timestamp counting at the same time. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends and the value of the timestamp count is recorded.

[0062] When the system is powered on, the GPS timing module sends a PPS to each device once per second. When each device receives the PPS pulse sent by the GPS timing module for the first time, the FPGA of each device starts to collect data and starts timestamp counting. When the number of collected data frames reaches the preset total number of frames N, the first PPS pulse response ends, and the value of the timestamp count at this time is recorded as the timestamp value of the first PPS pulse response.

[0063] The data synchronization acquisition method provided by the embodiment of the present invention is applied, and the PPS pulse sent by the GPS timing module is received by using the FPGA of each device; when the start condition is met, the PPS pulse response is performed; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the current PPS pulse response ends; each equally divided node is calculated according to the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted when the first PPS pulse response is responded. The method uses the GPS timing module and the FPGA timestamp counting to realize the synchronous acquisition of data between multiple boards or multiple devices containing boards, and corrects the time delay caused by the crystal oscillator to the board. The method realizes the synchronous acquisition of multi-board data at the software level, so only the software needs to be modified, and the hardware does not need to be changed, the rectification cycle is short, the cost is low, and the effect is good.

[0064] In order to make the present invention easier to understand, please refer to Figure 2 , Figure 2 A flowchart of a data synchronization acquisition method provided by an embodiment of the present invention may specifically include:

[0065] Use 3 sets of identical equipment, assuming they are equipment A, equipment B, and equipment C. Each set of equipment is equipped with an FPGA board with an Internet port, a 6400 dot matrix pressure sensor board, an interface board connecting the FPGA and the pressure sensor, and a switch. The pressure sensor board has 80 sensing points in each row and column. When powered on, the GPS timing module sends a PPS pulse to each device; when each device receives the PPS pulse sent by the GPS timing module for the first time, the FPGA of each device starts to collect data and starts counting timestamps at the same time. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends, and the value of the timestamp count at this time is recorded as the timestamp value of the first PPS response; if each device does not receive the PPS pulse sent by the GPS timing module for the first time, when the time reaches the collection time of each equally divided node, the FPGA of each device collects data once until the number of collected data frames reaches the preset total number of frames or the time exceeds the time of the last equally divided node, the PPS pulse response ends.

[0066] The following is an introduction to a data synchronization acquisition device provided by an embodiment of the present invention. The data synchronization acquisition device described below and the data synchronization acquisition method described above can be referenced to each other.

[0067] Please refer to Figure 3 , Figure 3A structural diagram of a data synchronization acquisition device provided by an embodiment of the present invention may include:

[0068] The receiving module 100 is used to receive the PPS pulse sent by the GPS timing module using the FPGA of each device;

[0069] The response module 200 is used to perform a PPS pulse response when the start condition is met; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the current PPS pulse response ends; wherein, each equally divided node is calculated based on the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the time of the first PPS pulse response.

[0070] Based on the above embodiment, the response module 200 may include:

[0071] An equally divided node number subunit, used to determine the number of equally divided nodes to be the preset total number of frames;

[0072] The inter-node time interval subunit is used to calculate the time interval T between each of the equally divided nodes as the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames.

[0073] Based on the above embodiment, the response module 200 may include:

[0074] A first starting unit, configured to perform a PPS pulse response when each device receives the PPS pulse not for the first time;

[0075] or,

[0076] The second starting unit is used to perform a PPS pulse response when the power-on time reaches a preset time.

[0077] Based on the above embodiment, the response module 200 may include:

[0078] The timestamp value calculation unit of the first PPS pulse response is used to start collecting data using the FPGA of each device when each device receives the PPS pulse for the first time, and start timestamp counting at the same time. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends and the value of the timestamp count at this time is recorded.

[0079] It should be noted that the order of the modules and units in the above-mentioned data synchronization acquisition device can be changed without affecting the logic.

[0080] The data synchronization acquisition device provided by the embodiment of the present invention is used, through the receiving module 100, to use the FPGA of each device to receive the PPS pulse sent by the GPS timing module; the response module 200 is used to perform the PPS pulse response when the start condition is met; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the current PPS pulse response ends; wherein, each equally divided node is calculated according to the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted when the first PPS pulse response is made. The device uses the GPS timing module and the FPGA timestamp counting to realize the synchronous acquisition of data between multiple boards or multiple devices containing boards, and corrects the time delay caused by the crystal oscillator to the board. The method realizes the synchronous acquisition of multi-board data at the software level, so only the software needs to be modified, and the hardware does not need to be changed, the rectification cycle is short, the cost is low, and the effect is good.

[0081] The following is an introduction to a data synchronization acquisition device provided by an embodiment of the present invention. The data synchronization acquisition device described below and the data synchronization acquisition method described above can be referenced to each other.

[0082] Please refer to Figure 4 , Figure 4 A structural diagram of a data synchronization acquisition device provided by an embodiment of the present invention may include:

[0083] A memory 10, used for storing computer programs;

[0084] The processor 20 is used to execute a computer program to implement the above-mentioned data synchronization acquisition method.

[0085] The memory 10 , the processor 20 , and the communication interface 31 all communicate with each other via the communication bus 32 .

[0086] In the embodiment of the present invention, the memory 10 is used to store one or more programs, and the program may include program code, and the program code includes computer operation instructions. In the embodiment of the present invention, the memory 10 may store programs for implementing the following functions:

[0087] Use the FPGA of each device to receive the PPS pulse sent by the GPS timing module;

[0088] When the start condition is met, a PPS pulse response is performed; the PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the PPS pulse response ends;

[0089] The equal-division nodes are calculated based on the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the first PPS pulse response.

[0090] In a possible implementation, the memory 10 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function, etc.; the data storage area may store data created during use.

[0091] In addition, the memory 10 may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory may also include NVRAM (Non-Volatile Random Access Memory). The memory stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, wherein the operating instructions may include various operating instructions for implementing various operations. The operating system may include various system programs for implementing various basic tasks and processing hardware-based tasks.

[0092] The processor 20 may be a central processing unit (CPU), an application specific integrated circuit, a digital signal processor, a field programmable gate array or other programmable logic device, a microprocessor or any conventional processor, etc. The processor 20 may call a program stored in the memory 10 .

[0093] The communication interface 31 may be an interface of a communication module, and is used to connect to other devices or systems.

[0094] Of course, it should be noted that Figure 4 The structure shown does not constitute a limitation on the data synchronization acquisition device in the embodiment of the present invention. In actual applications, the data synchronization acquisition device may include Figure 4 More or fewer components than shown, or combinations of certain components.

[0095] The following is an introduction to a readable storage medium provided in an embodiment of the present invention. The readable storage medium described below and the data synchronization acquisition method described above can be referenced to each other.

[0096] The present invention also provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned data synchronization acquisition method are implemented.

[0097] The readable storage medium may include: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.

[0098] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0099] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0100] Finally, it should be noted that, in this article, relationships such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0101] The above is a detailed introduction to a data synchronization acquisition method, device, equipment and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data synchronization acquisition method, characterized in that: include: Use the FPGA of each device to receive the PPS pulse sent by the GPS timing module; When the start condition is met, a PPS pulse response is performed; The PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches a preset total number of frames or the current time exceeds the time of the last equally divided node, then the PPS pulse response ends; Wherein, each equally divided node is calculated according to the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the first PPS pulse response; The equally divided nodes include: The number of the equally divided nodes is the preset total number of frames; The time interval T between each of the equally divided nodes is the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames; The collection time of each equally divided node is obtained according to the time interval T between the equally divided nodes.

2. The data synchronization acquisition method according to claim 1, characterized in that: When the start condition is met, a PPS pulse response is performed, including: When each device receives the PPS pulse not for the first time, it performs a PPS pulse response; Or, when the power-on time reaches a preset time, a PPS pulse response is performed.

3. The data synchronization acquisition method according to claim 1, characterized in that: The timestamp value of the first PPS pulse response is the total number of timestamps counted during the first PPS pulse response, including: When each device receives the PPS pulse for the first time, it starts collecting data using the FPGA of each device and starts counting timestamps. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends and the value of the timestamp count is recorded.

4. A data synchronization acquisition device, characterized in that: include: The receiving module is used to use the FPGA of each device to receive the PPS pulse sent by the GPS timing module; A response module, used for performing a PPS pulse response when the start condition is met; The PPS pulse response includes: when the current time reaches the acquisition time of each equally divided node, the FPGA of each device is used to collect data once, until the number of collected data frames reaches the preset total number of frames or the current time exceeds the time of the last equally divided node, then the current PPS pulse response ends; wherein, each equally divided node is calculated according to the timestamp value of the first PPS pulse response or the timestamp value of the last PPS pulse response; the timestamp value of the first PPS pulse response is the total number of timestamps counted at the time of the first PPS pulse response; The response module comprises: An equally divided node number subunit, used to determine the number of equally divided nodes to be the preset total number of frames; The inter-node time interval subunit is used to calculate the time interval T between each of the equally divided nodes as the ratio of the timestamp value of the first PPS pulse response to the preset total number of frames, or the ratio of the timestamp value of the last PPS pulse response to the preset total number of frames.

5. The data synchronization acquisition device according to claim 4, characterized in that: The response module comprises: A first starting unit, configured to perform a PPS pulse response when each device receives the PPS pulse not for the first time; or, The second starting unit is used to perform a PPS pulse response when the power-on time reaches a preset time.

6. The data synchronization acquisition device according to claim 4, characterized in that: The response module comprises: The timestamp value calculation unit of the first PPS pulse response is used to start collecting data using the FPGA of each device when each device receives the PPS pulse for the first time, and start timestamp counting at the same time. When the number of collected data frames reaches the preset total number of frames, the PPS pulse response ends and the value of the timestamp count at this time is recorded.

7. A data synchronization acquisition device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the data synchronization acquisition method as described in any one of claims 1 to 3 when executing the computer program.

8. A readable storage medium, characterized in that: The readable storage medium stores computer executable instructions, and when the computer executable instructions are loaded and executed by the processor, the steps of the data synchronization acquisition method according to any one of claims 1 to 3 are implemented.

Images