Method for predicting aging timing of critical path under time-varying load based on deep learning

Abstract

The application provides a key path aging timing prediction method under time-varying load based on deep learning, first, based on the adaptive multi-head attention mechanism in the space-time Transformer network STTN, the correlation of each unit in the path subgraph in the space and time dimensions is modeled, the influence of adjacent units in the path on the aging timing of the target unit is accurately captured, and the contribution degree of each element in the workload sequence to the aging process is accurately captured. On this basis, the graph attention network GAT is used to learn the path topological structure and timing information as the information supplement of the STTN model. Secondly, a feature fusion network based on a gating mechanism is designed to integrate the output information of the multi-scale graph learning model, and a multilayer perceptron is used to regress and predict the path aging delay of the fused features. The method is complete in capturing the aging circuit key path features, and is of great significance to realizing high-precision aging timing analysis and prediction and designing high-robustness circuits.

Description

Technical Field

[0001] This invention belongs to the field of critical path aging timing prediction for integrated circuits under NBTI aging, and specifically designs a critical path aging timing prediction method based on deep learning under time-varying loads. Background Technology

[0002] As integrated circuit process nodes continue to shrink, the effects of aging on transistors are becoming increasingly severe. Among these, the impact of negative bias temperature instability (NBTI) is becoming increasingly significant, and aging factors must be considered during timing analysis to improve chip reliability. Traditional aging-aware timing analysis methods mainly include aging-aware SPICE simulation and aging-aware STA. Existing aging-aware timing analysis methods still have some shortcomings: (1) SPICE-based transistor-level aging analysis is not suitable for full-chip-level analysis due to its huge computational overhead; (2) Analysis methods based on gate-level aging models have high analysis efficiency, but the library construction overhead and prediction accuracy are limited and have not been properly addressed. Machine learning modeling is currently the mainstream solution for circuit aging timing analysis, but existing modeling methods can only handle constant workloads and cannot deeply perceive time-varying workloads in real circuit operating scenarios. At the same time, they lack the ability to perceive path topology features, which also degrades the prediction accuracy of the model. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to provide a critical path aging timing prediction method based on deep learning under time-varying loads, so as to achieve a more realistic circuit timing analysis that is closer to the current process node with less simulation resources and running time.

[0004] Technical Solution: To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0005] A deep learning-based critical path aging timing prediction method under time-varying loads is disclosed. The deep learning refers to a regression task implemented using three algorithms: spatiotemporal Transformer network, graph attention network, and gated fusion prediction network. The time-varying load refers to a scenario where the chip's functionality continuously changes during operation. Aging refers to the aging effect caused by negative bias temperature instability (NBTI). The critical path is defined as the path with the longest timing delay from the data initiation point (usually the output of the start trigger) to the data capture point (usually the input of the capture trigger). The prediction method includes the following steps:

[0006] S1: When the PMOS transistor is subjected to continuous stress from time t0 to time t, the change in threshold voltage ΔV th This will continue to increase, known as the NBTI stress effect, as shown in the following formula:

[0007]

[0008] Where, ΔV th0 δ represents the change in the previous threshold voltage. v With a voltage correction constant of 5.0 mV, aging-related K v The formula is defined as follows:

[0009]

[0010] Where, ΔV th It is the change in the threshold voltage of the PMOS transistor at time t0, T ox Represents the gate oxide thickness, C ox The gate capacitance per unit area represents the capacitance, e is the natural constant, and V dd For the operating voltage, E0 and E a A is a device-related parameter and is a constant. NBTI Here are process-related constants, k is the Boltzmann constant, T represents temperature, and δ... v This is a constant that affects gate oxide traps and other charge quantities;

[0011] When a PMOS transistor is not subjected to stress, it is called the NBTI recovery effect; when the gate-source voltage V gs When = 0, the threshold voltage of pmos partially recovers. Assuming the recovery effect occurs at time t0, the formula is as follows:

[0012]

[0013] Where η is the process constant, ΔV th1 This represents the change in the PMOS threshold voltage in the previous stage.

[0014] To reduce computational resource consumption, the long-term effect formula for NBTI under dynamic operating conditions is as follows:

[0015]

[0016] Where, ΔV th,t V represents V after time t th Aging value; n is the process-related time constant, T clk The clock cycle is represented by α, and the stress probability is represented by t. This concept is defined as the time occupied by the NBTI stress phase in the overall working time. stress / t stress +t recovery , where tstress During the stress stage, t recovery The recovery phase; β t It is related to temperature, T clk α, time t-related process parameters;

[0017] S2: Based on the NBTI aging analysis model in step S1, construct the dataset required for the deep learning model. Specifically, the test baseline circuit is synthesized under a specified process to generate the corresponding gate-level netlist. Then, based on real application workload stimuli, a logic simulator is used to perform gate-level simulation on the synthesized netlist to obtain the sequence data on each node within the entire netlist and calculate the corresponding average duty cycle. For each node within the netlist, the average signal probability corresponding to each workload is combined into a signal probability sequence. Based on the obtained signal probability sequence and the pre-set workload duration, an HSPICE signal stimulus is generated and merged with the corresponding logic unit in the gate-level netlist to form an HSPICE simulation file. MOSRA aging simulation is then performed to obtain the aging status of all transistors within each unit. A static timing analysis tool is used to perform static timing analysis on the gate-level netlist before aging to generate a path timing report and generate the HSPICE netlist for the critical path. The transistor aging status obtained from the MOSRA simulation is then back-labeled into the critical path HSPICE netlist for HSPICE aging-after timing simulation to obtain the aging timing label value.

[0018] S3: Based on the dataset construction process in step S2, the parameters inside the critical path aging time series prediction model are generated through training with batches of training samples. The specific process is as follows: the training is divided into two stages. The input features of the first stage are the workload sequence, gate-level netlist, pre-aging time series report, and working stress conditions, which are fed into the spatiotemporal Transformer network and the GAT model, respectively. The input features of the second stage are the output features of the spatiotemporal Transformer network and the GAT model, which are fed into the gate control feature fusion network and the multilayer perceptron. The training label is the critical path aging time series.

[0019] S4: According to the model parameter training process in step S4, after the training parameters and the internal parameters of the model are fixed, the model inference process is an end-to-end critical path aging time series prediction; the predicted path time series values ​​are compared with the label values ​​obtained by the simulation software HSPICE, and the mean absolute percentage error (MAPE) is calculated.

[0020] Furthermore, in step S1, the selected standard cell library uses FinFET technology, and its aging analysis model needs to be adapted to the Level 3 formula in HSPICE MOSRA to meet the simulation conditions; the BTI aging model of MOSRA Level 3 is shown in equation (5).

[0021]

[0022] Where T is the Kelvin temperature, k is the Boltzmann constant, L is the polysilicon length of the device, and V is the Kelvin temperature. ds V is the drain-source voltage. gs t is the gate-source voltage, and t is the total stress time.

[0023] For digital circuit scenarios that only consider the long-term formula of slow traps, the long-term NBTI analysis model of the FinFET transistor model is shown in Equation (6).

[0024]

[0025] Compare the MOSRA Level 3 parameters with the FinFET long-term model, and replace the parameters: A ρ Replace A2 with G, replace B2 with Ea with Ea2, and assign 0 to D, m, and R; the final MOSRA L3 simplified fitting model is shown in equation (7);

[0026]

[0027] Among them, A p Here, G is a process-related constant, and V is the voltage acceleration factor. gs Where is the gate-source voltage, Ea is the activation energy, T is the Kelvin temperature, and k is the Boltzmann constant. The total stress time.

[0028] Furthermore, in step S3, the spatiotemporal Transformer network and the GAT network capture different features in the aging critical path: the spatiotemporal Transformer network focuses on the impact of time-varying workload on the aging of the critical path, while the GAT network focuses on extracting the temporal and topological information in the critical path before aging.

[0029] Furthermore, for the spatiotemporal Transformer network handling time-varying workload characteristics of aging, the critical path is extended along the first-order neighborhood of the logic gates to generate a first-order neighborhood subgraph of the path. In conjunction with the time-varying characteristics of the workload, the first-order neighborhood subgraph of the path is transformed into a spatiotemporal subgraph of the first-order neighborhood of the path. Adaptive local spatiotemporal attention is employed to model the correlation between each unit in the path subgraph in both spatial and temporal dimensions, accurately capturing the influence of adjacent units in the path on the aging sequence of the target unit, as well as the contribution of each element in the workload sequence to the aging process.

[0030] Furthermore, for the GAT network that processes path temporal features, the critical path is represented as a static undirected graph G = (V, E), where V is the set of nodes {v...} iLet E be the set of edges {e ∈V}. ij ∈E}. A node contains logical units, inputs (primary inputs, PIs), and outputs (primary outputs, POs), and edges are the interconnections between nodes. The connections between nodes can be represented using an adjacency matrix. This represents the number of nodes, where n is the number of nodes. If node v i ,v j There is a connection between them, A ij =1, otherwise A ij =0. The node feature matrix can be defined as... Where n is the number of nodes and d is the node feature dimension.

[0031] The graph attention network used is calculated as shown in Equation (8), which includes two parts: normalized attention coefficient calculation and feature weighted aggregation. For each pair of nodes (i,j), the unnormalized attention coefficient e between them is calculated. ij Where a is a learnable weight vector, W is a learnable weight matrix, and || denotes vector concatenation; this attention score reflects the raw estimate of the association strength between nodes; subsequently, the attention score is normalized using the softmax function to obtain the attention coefficient a. ij After normalization, the contributions of each logic gate's neighboring logic gates are converted into a probability distribution. Each neighbor has a relative weight, and the sum of these weights is constant, ensuring the balance and stability of information aggregation. Finally, the node logic gate cell... i The new feature vector can be obtained through weighted aggregation of neighbor node features. However, GAT using single-head attention lacks model expressiveness and stability. Therefore, multi-head attention, used in Transformers, is introduced here. The GAT calculation process based on the multi-head attention mechanism involves calculating the new feature vector of the node for each attention head separately, then concatenating the outputs of all attention heads, and obtaining the final node feature vector through a linear transformation. The new embedding vector of the node can be obtained through weighted aggregation of neighbor node embeddings, and multi-head attention is introduced to concatenate the outputs of all attention heads and obtain the final node embedding vector through a linear transformation.

[0032]

[0033] To mitigate the oversmoothing phenomenon in deep graph neural networks, the output node embedding matrices of the first two Batch Normalization (BN) layers are passed to the last BN layer via residual connections. For an L-layer GAT network, the full graph node embedding H of the last layer's output is... L-1Similarly, after the mean pooling operation, it is concatenated with the global features of the graph to generate a graph-level overall representation.

[0034]

[0035] Furthermore, in step S3, the feature fusion network uses a gating structure to jointly represent the output features of the spatiotemporal Transformer network and the GAT network, dynamically adjusts the importance of each input modal feature, emphasizes modal information that has a greater impact on the final output, and suppresses irrelevant or noisy information.

[0036] Furthermore, in step S2, the ΔV of each transistor in the standard cell under each workload... th The values ​​were obtained from HSPICEMOSRA simulation, and the temperature and voltage set in the simulation were randomly selected by the script; the operating voltage was selected as 0.85V, 0.9V, 1.0V, and 1.1V, the operating temperature was selected as 25℃, 50℃, 85℃, and 125℃, and the operating time was selected as 1 year, 3 years, 5 years, and 10 years.

[0037] Furthermore, in step S2, the VCD waveform file obtained by the gate-level simulation is converted into waveform excitation usable by HSPICE simulation through a script, which introduces the input excitation in the aging problem analysis and realizes the construction of the dataset of the aging standard cell.

[0038] Beneficial effects: The critical path aging time series prediction method based on deep learning under time-varying load proposed in this invention has the following advantages:

[0039] 1. This invention proposes a critical path aging timing prediction method based on deep learning under time-varying loads. A reference circuit is synthesized using Design Compiler, and HSPICE is used to measure the ΔV of the aging standard cell transistors. th We conducted time-series simulations of the critical path to build a sample dataset for training and prediction. We performed feature engineering on the load sequence and critical path topology, and then used deep learning methods to predict critical path latency.

[0040] 2. This invention employs three neural network methods to predict the timing of critical data, taking into account both load and topology scenarios in the aging features. The multi-task learning framework efficiently achieves the final timing prediction.

[0041] 3. This invention compares the proposed aging critical path time-series prediction model with feedforward neural networks and main neighborhood aggregation graph convolutional neural networks, and uses the average absolute percentage error comparison to prove the practical value of this method.

[0042] Therefore, in summary, this invention can predict the aging delay of critical data with less simulation resource consumption, and has good practical application value. Attached Figure Description

[0043] Figure 1 This is the overall process of the aging critical path timing prediction framework in this embodiment of the invention;

[0044] Figure 2 This describes the dataset construction and model training process in an embodiment of the present invention.

[0045] Figure 3 This is a schematic diagram of a spatiotemporal Transformer network according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram illustrating the transformation of key path data into a first-order neighborhood subgraph in an embodiment of the present invention;

[0047] Figure 5 This is a schematic diagram illustrating the transformation of key path data into a first-order neighborhood spatiotemporal subgraph in an embodiment of the present invention.

[0048] Figure 6 This is a schematic diagram illustrating the transformation of key data into a path subgraph in an embodiment of the present invention;

[0049] Figure 7 This is a schematic diagram of attention calculation according to an embodiment of the present invention;

[0050] Figure 8 This is a detailed diagram of the gating feature fusion network according to an embodiment of the present invention;

[0051] Figure 9 This is a detailed diagram of a multilayer perceptron according to an embodiment of the present invention. Detailed Implementation

[0052] To better understand the purpose, structure, and function of this invention, the following detailed description of the deep learning-based critical path aging time-varying load prediction method of this invention is provided in conjunction with the accompanying drawings.

[0053] This embodiment proposes a critical path aging time series prediction method based on deep learning under time-varying loads, and its overall process is illustrated as follows: Figure 1 As shown, the specific steps are as follows:

[0054] S1: When the PMOS transistor is subjected to continuous stress from time t0 to time t, the change in threshold voltage ΔV th This will continue to increase, known as the NBTI stress effect, as shown in the following formula:

[0055]

[0056] Where, ΔVth0 δ represents the change in the previous threshold voltage. v With a voltage correction constant of 5.0 mV, aging-related K v The formula is defined as follows:

[0057]

[0058] Where, ΔV th It is the change in the threshold voltage of the PMOS transistor at time t0, T ox Represents the gate oxide thickness, C ox The gate capacitance per unit area represents the capacitance, e is the natural constant, and V dd For the operating voltage, E0 and E a A is a device-related parameter and is a constant. NBTI Here are process-related constants, k is the Boltzmann constant, T represents temperature, and δ... v This is a constant that affects gate oxide traps and other charge quantities;

[0059] When a PMOS transistor is not subjected to stress, it is called the NBTI recovery effect; when the gate-source voltage V gs When = 0, the threshold voltage of pmos partially recovers. Assuming the recovery effect occurs at time t0, the formula is as follows:

[0060]

[0061] Where η is a process constant;

[0062] To reduce computational resource consumption, the long-term effect formula for NBTI under dynamic operating conditions is as follows:

[0063]

[0064] Where, ΔV th,t V represents V after time t th Aging value; T clk α represents the clock period and stress probability; α is defined as the time occupied by the NBTI stress phase in the overall working time, i.e., t stress / t stress +t recovery , where t stress During the stress stage, t recovery The recovery phase; β t It is related to temperature, T clk α, time t-related process parameters;

[0065] This method uses a 16nm FinFET transistor aging model as theoretical support. The trap trapping / release mechanism is the cause of the stress and recovery phases in the NBTI effect. For FinFET technology, both fast and slow traps exist within the transistor, contributing to the NBTI effect. Due to different time constants, FinFET also exhibits both short-term and long-term NBTI aging behaviors. The NBTI transient formulas are shown in Tables 1 and 2.

[0066] Table 1 Formulas for Transient Stress Stage

[0067] Table 2 Formulas for Transient Recovery Phase

[0068]

[0069] Where A i For process-related parameters, B i The voltage multiplication factor is denoted as f, and the other parameters are defined in the same way as in equation (1). R is the recovery rate factor, which is affected by the equivalent aging time. In the formula, f represents the change in transistor threshold voltage ΔV. th .

[0070] Similar to equation (4), a corresponding long-term NBTI aging model is proposed for this transient model to save computational resources. The long-term NBTI formula is shown in Table 3.

[0071] Table 3 Long-term NBTI Formula

[0072]

[0073] Where m is the modulation coefficient, T clock Let t be the clock cycle, t be the aging time, and df be the equivalent duty cycle. This long-term aging model makes the following assumptions: the stress waveform of each transistor is a regular AC waveform with a constant duty cycle and clock frequency.

[0074] S2: Based on the NBTI aging analysis model in step S1, the required dataset for the deep learning model can be constructed. The specific process is as follows: The open-source reference circuit is synthesized using Design Compiler under a specified process to obtain a gate-level netlist. Then, based on real application-level workload stimuli, the synthesized netlist is simulated using a VCS logic simulator to obtain the waveform sequence data for each node within the entire netlist. Through a waveform analysis program, the average signal probability of all internal nodes of the gate-level netlist under a certain application load is obtained. Since multiple workloads need to be combined into a single workload sequence, for each node within the netlist, the average signal probabilities corresponding to each workload are combined into a signal probability sequence. Based on the obtained signal probability sequence and the pre-set workload duration, it is converted into standard input stimuli for HSPICE using a script, and merged with the corresponding logic units in the gate-level netlist into a SPICE netlist file (.sp) for MOSRA pre-stress simulation to obtain the PMOS transistor threshold voltage offset ΔV_th within each unit. Simultaneously, based on PrimeTime, static timing analysis (Fresh STA) is performed on the gate-level netlist before aging, obtaining the path timing report, and generating the SPICE netlist of the timing path using the write_spice_deck command. Finally, the transistor degradation values ​​obtained from MOSRA simulation are back-annotated into the SPICE netlist of the timing path for post-stress timing simulation to obtain the path aging delay as the ground truth label, such as... Figure 2 As shown.

[0075] S3: Based on the dataset construction process in step S2, the parameters inside the critical path aging time series prediction model are generated through training with batches of training samples. The specific process is as follows: the training is divided into two stages. The input features of the first stage are the workload sequence, gate-level netlist, pre-aging time series report, and working stress conditions, which are fed into the spatiotemporal Transformer network and the GAT model, respectively. The input features of the second stage are the output features of the spatiotemporal Transformer network and the GAT model, which are fed into the gate control feature fusion network and the multilayer perceptron. The training label is the critical path aging time series.

[0076] S4: According to the model parameter training process in step S4, after the training parameters and the internal parameters of the model are fixed, the model inference process is an end-to-end critical path aging time series prediction; the predicted path time series values ​​are compared with the label values ​​obtained by the simulation software HSPICE, and the mean absolute percentage error (MAPE) is calculated.

[0077] The dataset contains six test circuits: RISC-V, FFT, AC97, and AES_CORE. RISC-V and FFT processors are used as the training set (known circuits), while the other five circuits are used as the test set (unknown circuits). 80% of the timing paths extracted from the training set circuits are randomly selected as training data for model training, and the remaining 20% ​​of timing paths are used to test the prediction performance of the prediction framework on the known circuits. See Table 4 for details.

[0078] Table 4. Statistical Information on Test Circuit Cases

[0079] Table 5 presents the MAPE (Mean Absolute Error) of the proposed aging path delay prediction results, the aging path delay prediction results based on the feedforward neural network, and the aging path delay prediction results based on the main neighborhood aggregation graph convolutional network, and indicates the accuracy improvement factor of the proposed model compared to existing work. Compared with the feedforward neural network, the proposed aging path delay prediction framework reduces MAPE by 4.0 times and 6.6 times on known circuits, respectively, and by 4.9 to 7.4 times on unknown circuits, with a mean absolute percentage error reduction of 6.0 times. Compared with the main neighborhood aggregation graph convolutional neural network, the proposed aging path delay prediction framework reduces MAPE by 2.7 times and 1.8 times on known circuits, respectively, and by 1.8 to 3.6 times on unknown circuits, with a mean absolute percentage error reduction of 2.4 times.

[0080] Table 5 Comparison of timing prediction errors of different models on the test circuit set

[0081]

[0082]

[0083] This embodiment proposes a preprocessing method for workload sequence features, as detailed below:

[0084] The spatiotemporal Transformer network structure designed in this invention is as follows: Figure 3As shown. The model's input includes a node feature matrix and a graph adjacency matrix. Spatiotemporal graph learning is achieved by stacking multiple spatiotemporal attention layers. Each spatiotemporal attention layer includes a local multi-head attention mechanism and a spatiotemporal embedding layer. The node embedding matrix output by the last layer is used to obtain the final graph representation through temporal and spatial graph pooling, respectively.

[0085] The specific calculation process of local spatiotemporal attention is as follows: the input feature matrix is ​​flattened into Where T represents the number of time steps, N represents the number of nodes in the graph, and D represents the feature dimension of the nodes. A spatiotemporal attention mask is also defined. This is used to limit the computational scope of attention. Next, the calculation is performed by projecting the input matrix onto the query matrix Q, the key matrix K, and the value matrix V, as follows:

[0086] Q = XW Q K = XW K V = XW V (5)

[0087] in The query matrix Q and the key matrix K have the same dimension D. QK The value matrix V has dimensions D. V In the specific implementation process, let D QK =D V The formula for calculating Local Self-Attention (LSA) is as follows:

[0088]

[0089] After concatenating the self-attention heads of multiple parallel computations, the output matrix W is used. O After performing a linear mapping, the calculation formula for Local Multi-Head Self-Attention (L-MSA) is as follows:

[0090] L-MSA(X,A st = [LSA(X,A)] st )1,…,LSA(X,A st ) h W O (7)

[0091] Furthermore, this invention introduces a learnable adaptive adjacency matrix A. apt Improved local spatiotemporal attention, A apt End-to-end training and learning can be achieved without any prior knowledge.

[69] The adaptive matrix is ​​achieved by randomly initializing two node embeddings with learnable parameters E1 and E2, and the adaptive adjacency matrix A is... apt The calculation formula is as follows:

[0092]

[0093] in E1 represents the original node embedding, and E2 represents the target node embedding. The spatial dependency weights between the original and target nodes can be obtained through these embeddings. ReLU is used to remove weak connections in the adjacency matrix, reducing the number of training parameters, and then softmax is used for normalization. To avoid high computational complexity, the Gumbel-Sigmoid method is used to normalize A. apt A binary mask `b` is generated to limit the in-degree of nodes and control the scope of attention calculation. This mask ensures the accuracy of the corrected adjacency matrix A'. apt The calculation formula is as follows: By using element-wise multiplication, only a finite number of neighbors of each node are retained.

[0094] A′ apt =b·A apt (9)

[0095] like Figure 4 , Figure 4 (a) is a sub-circuit diagram of the gate-level netlist after logic synthesis, which contains several timing paths; Figure 4 (b) is a timing path that passes through logic gates U2, U4, U7, and U10; Figure 4 (c) is a first-order neighborhood cell netlist based on the target time-series path, in which the fan-in and fan-out cells of each cell on the path are added to the path subgraph; Figure 4 (d) is the final constructed path 1-hop static subgraph.

[0096] For digital circuits, a single workload stimulus applied to the netlist will result in signal waveforms at all logic gate ports, which can be abstracted as signal probabilities to represent the aging effect on the logic gates. However, in real-world scenarios, a single workload transforms into a continuous workload sequence; that is, a different workload occurs at each time period, and the signal probability at the same logic gate port in the netlist changes over time. The proposed 1-hop spatiotemporal graph maintains the topology of the static path subgraph, but the node characteristics in the graph change over time, such as... Figure 5 As shown.

[0097] Table 6 presents a series of features extracted from the circuit's timing report, gate-level netlist, and workload file.

[0098] Table 6 Initial characteristics and descriptions of the spatiotemporal subgraph of path 1-hop.

[0099]

[0100] This embodiment proposes a path temporal feature preprocessing method, as detailed below:

[0101] like Figure 6 As shown, for the GAT network that processes path temporal features, the critical path is represented as a static undirected graph G = (V, E), where V is the set of nodes {v...} i Let E be the set of edges {e ∈V}. ij ∈E}. A node contains logical units, inputs (primary inputs, PIs), and outputs (primary outputs, POs), and edges are the interconnections between nodes. The connections between nodes can be represented using an adjacency matrix. This represents the number of nodes, where n is the number of nodes. If node v i ,v j There is a connection between them, A ij =1, otherwise A ij =0. The node feature matrix can be defined as... Where n is the number of nodes and d is the node feature dimension. Table 7 shows a series of features extracted from the timing report of the circuit.

[0102] Table 7 Initial characteristics and descriptions of static path subgraphs

[0103] The graph attention network used is calculated as shown in Equation (8), which includes two parts: normalized attention coefficient calculation and feature weighted aggregation. Figure 7 As shown. For each pair of nodes (i,j), calculate the normalized attention coefficient a between them. ij The new embedding vector of a node can be obtained by weighted aggregation of the embeddings of neighboring nodes, and multi-head attention is introduced to concatenate the outputs of all attention heads, and the final node embedding vector is obtained through a linear transformation.

[0104]

[0105] To mitigate the oversmoothing phenomenon in deep graph neural networks, the output node embedding matrices of the first two Batch Normalization (BN) layers are passed to the last BN layer via residual connections. For an L-layer GAT network, the full graph node embedding H of the last layer's output is... L-1 Similarly, after the mean pooling operation, it is concatenated with the global features of the graph to generate a graph-level overall representation.

[0106]

[0107] This embodiment proposes a gated feature fusion prediction method, as detailed below:

[0108] Graph embedding x for perceiving aging information output by spatiotemporal Transformer models v And the time-series information-aware graph embedding x output by the GAT model t Through linear transformation W v W t The corresponding feature vector h is obtained by processing the data and then applying the tanh activation function. v ,h t Next, x v ,x t After being connected in series, a linear transformation W is performed. z The process involves using a sigmoid activation function to obtain a weight z between 0 and 1. Finally, z is used to adjust h. v Weighting is performed, and h is calculated using 1-z. t The values ​​are weighted and then summed to obtain the final output h, where Θ represents the learnable parameters. The overall framework structure is as follows: Figure 9 As shown.

[0109] The formula for the gated feature fusion network is:

[0110]

[0111] The final path aging multi-scale graph representation is obtained through a gating fusion strategy. This graph representation fully integrates path temporal information and time-varying aging information. It can be used to perform regression prediction of the post-path aging temporal information y using a multilayer perceptron, such as... Figure 9 As shown.

[0112] The formula for a multilayer perceptron is:

[0113]

[0114] The loss function is the MSE function, assuming the path aging time-series prediction target is y1, y2, ..., y i ,…t n , where i is the i-th sample, and the total number of samples is n. The model predicts the value as follows: The formula for calculating the MSE loss function is:

[0115]

[0116] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A method for predicting the aging time series of critical paths under time-varying loads based on deep learning, characterized in that, The deep learning refers to the regression task implemented by three algorithms: spatiotemporal Transformer network, graph attention network, and feature fusion network; the time-varying load refers to the scenario in which the chip's functions change continuously during operation; the aging refers to the aging effect of negative bias temperature instability (NBTI). The critical path timing refers to the delay of the longest path from the data initiation point to the data acquisition point; the prediction method includes the following steps: S1: Building the dataset; The specific process is as follows: The test reference circuit is synthesized under a specified process to generate the corresponding gate-level netlist. Then, based on the actual application workload stimulus, a logic simulator is used to perform gate-level simulation on the synthesized netlist to obtain the sequence data on each node within the entire netlist and calculate the corresponding average duty cycle. For each node within the netlist, the average signal probabilities corresponding to each workload are combined into a signal probability sequence. Based on the obtained signal probability sequence and the pre-set workload duration, an HSPICE signal stimulus is generated and merged with the corresponding logic unit in the gate-level netlist to form an HSPICE simulation file. MOSRA aging simulation is then performed to obtain the aging status of all transistors within each unit. A static timing analysis tool is used to perform static timing analysis on the gate-level netlist before aging to generate a path timing report and generate the HSPICE netlist for the critical path. The transistor aging status obtained from the MOSRA simulation is then back-labeled into the critical path HSPICE netlist for post-HSPICE aging timing simulation to obtain the aging timing tag value. S2: Train the critical path aging time series prediction model using the dataset built in step S1. The specific process is as follows: The training is divided into two stages. The input features of the first stage are the workload sequence, gate-level netlist, pre-aging time series report and working stress conditions, which are fed into the spatiotemporal Transformer network and the graph attention network, respectively. The input features of the second stage are the output features of the spatiotemporal Transformer network and the graph attention network, which are fed into the feature fusion network and the multilayer perceptron. The training label is the critical path aging time series. S3: Once the internal parameters of the critical path aging time-series prediction model are fixed after training, the model inference process is an end-to-end critical path aging time-series prediction; the predicted path time-series values ​​are compared with the label values ​​obtained by the simulation software HSPICE, and the mean absolute percentage error (MAPE) is calculated.

2. The method for predicting the aging time series of critical paths under time-varying load based on deep learning according to claim 1, characterized in that, The transistor is a FinFET. Considering only the digital circuit scenario with slow trap long-term formula, the long-term NBTI analysis model of the FinFET transistor model is shown in equation (1): Among them, A p Here, G is a process-related constant, and V is the voltage acceleration factor. gs Where is the gate-source voltage, Ea is the activation energy, T is the Kelvin temperature, and k is the Boltzmann constant. The total stress time.

3. The method for predicting the aging time series of critical paths under time-varying load based on deep learning according to claim 1, characterized in that, In step S2, the spatiotemporal Transformer network and the graph attention network capture different features in the aging critical path, respectively: the spatiotemporal Transformer network focuses on the impact of time-varying workload on the aging of the critical path, while the graph attention network focuses on extracting temporal and topological information in the critical path before aging.

4. The critical path aging time series prediction method based on deep learning under time-varying load as described in claim 3, characterized in that, For the spatiotemporal Transformer network that handles the time-varying characteristics of aging workloads, the critical path is extended along the first-order neighborhood of the logic gates to generate a first-order neighborhood subgraph of the path. In addition, combined with the time-varying characteristics of the workload, the first-order neighborhood subgraph of the path is transformed into a spatiotemporal subgraph of the first-order neighborhood of the path. Adaptive local spatiotemporal attention is used to model the correlation between each unit in the path subgraph in both spatial and temporal dimensions, accurately capturing the influence of adjacent units in the path on the aging time of the target unit, as well as the contribution of each element in the workload sequence to the aging process.

5. The method for predicting the aging time series of critical paths under time-varying load based on deep learning according to claim 3, characterized in that, For graph attention networks that process temporal features of paths, the critical path is represented as a static undirected graph G = (V, E), where V is the set of nodes {v...} i Let E be the set of edges {e ∈V}. ij ∈E}; Nodes contain logical units, inputs, and outputs, and edges are the interconnections between nodes; the connections between nodes are represented by an adjacency matrix. This represents the number of nodes; if node v i ,v j There is a connection between them, A ij =1, otherwise A ij =0; The node feature matrix is ​​defined as follows: Where n is the number of nodes and d is the node feature dimension; The graph attention network used is calculated as shown in Equation (2), which includes two parts: normalized attention coefficient calculation and feature weighted aggregation; for each pair of nodes (i,j), the unnormalized attention coefficient e between them is calculated. ij The new embedding vector of a node is obtained by weighted aggregation of the embeddings of its neighboring nodes. Multi-head attention is introduced to concatenate the outputs of all attention heads, and a linear transformation is applied to obtain the final node embedding vector. Where a is a learnable weight vector, W is a learnable weight matrix, and || denotes vector concatenation operation. ij Attention coefficient; To mitigate the oversmoothing phenomenon in deep graph neural networks, the output node embedding matrices of the first two BN layers of the graph attention network are passed to the last BN layer via residual connections; for an L-layer graph attention network, the full graph node embedding H of the last layer's output is... L-1 Similarly, after mean pooling, it is concatenated with global graph features to generate a graph-level overall representation, as shown in the following formula:

6. The method for predicting the aging time series of critical paths under time-varying load based on deep learning according to claim 1, characterized in that, The feature fusion network employs a gating structure to jointly represent the output features of the spatiotemporal Transformer network and the graph attention network.

7. The method for predicting the aging time series of critical paths under time-varying load based on deep learning according to claim 1, characterized in that, In step S1, the aging values ​​of each transistor in the standard cell under each workload are obtained by HSPICE MOSRA simulation. The temperature and voltage set in the simulation are randomly selected by the script. The working voltage is selected as 0.85V, 0.9V, 1.0V, and 1.1V, the working temperature is selected as 25℃, 50℃, 85℃, and 125℃, and the working time is selected as 1 year, 3 years, 5 years, and 10 years.

8. The method for predicting the aging time series of critical paths under time-varying load based on deep learning according to claim 1, characterized in that, In step S1, the VCD waveform file obtained by the gate-level simulation is converted into waveform excitation usable by HSPICE simulation through a script, which introduces the input excitation in the aging problem analysis and realizes the construction of the dataset of the aging standard cell.

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