Device for panel impedance sensing by replicating current via a driver

Abstract

This disclosure relates to panel impedance sensing via a driver replicating current. A circuit includes: a driver that provides a voltage at a node of a load; and a first circuit that helps determine the load current at the node. The load is a capacitive load, and the first circuit helps determine the load current by measuring the replicated current and using the voltage and the value of the replicated current to determine the capacitance of the load.

Description

Technical Field

[0001] This specification generally relates to electronic circuits, including, for example, panel impedance sensing via a driver that replicates current. Background Technology

[0002] Many electronic displays (including displays of electronic devices such as consumer electronics, laptops, handheld electronic devices such as tablets and phones, and smartwatches) use display panels formed from two-dimensional sensor arrays. The sensor array is implemented as two or more layers formed on a cover glass. Sensor arrays are typically modeled using two-dimensional distributed resistor-capacitor (RC) circuits powered by driver circuitry. For example, an N×M pixel array panel is formed from a two-dimensional array of M×N pixels, with each pixel represented by an RC circuit. Resistors in each row or column are connected in series with each other, and capacitors are connected between continuous resistors and ground potential. For example, an N×M pixel array panel can be powered by N horizontal drivers and M vertical drivers. Summary of the Invention

[0003] In one aspect, this disclosure relates to an apparatus comprising: a driver circuit configured to provide a voltage at a node of a load, the voltage being based on a first current; a first circuit configured to generate a second current proportional to the first current; and a second circuit configured to measure the first current by: measuring the second current; and using the values ​​of the voltage and the second current to determine the capacitance of the load.

[0004] In another aspect, this disclosure relates to a circuit for impedance sensing, the circuit comprising: a driver circuit configured to provide a voltage at a node, the voltage being based on a first circuit configured to generate a third current based on the first circuit; and a second circuit coupled to the node, the second circuit being configured to: measure the third current; and determine the admittance at the node by using the third current and the voltage.

[0005] In another aspect, this disclosure relates to an apparatus comprising: a display panel; a first circuit configured to provide a voltage at a node of the display panel, wherein the voltage is based on a first current; and a second circuit coupled to the node and configured to: receive a second current proportional to the first current; determine the value of the second current; and determine the capacitance of the display panel by using the voltage and the peak-to-peak value of the second current. Attached Figure Description

[0006] Specific features of the present technology are set forth in the appended claims. However, for illustrative purposes, several aspects of the present technology are depicted in the following figures:

[0007] Figure 1 This is a schematic diagram illustrating an example of a circuit for performing panel impedance sensing, in which some aspects of the present technology are implemented.

[0008] Figure 2A and 2B This is a schematic diagram illustrating an example of a circuit for panel impedance sensing via a driver replicating current, according to various aspects of this technology, along with corresponding diagrams.

[0009] Figure 3A and 3B It is a diagram illustrating the simulated reproduction and pixel current of various aspects according to this technology.

[0010] Figure 4 It is a graph illustrating the estimation of total pixel capacitance according to various aspects of this technology.

[0011] Figure 5A and 5B These are diagrams illustrating simulation results with panel R / C scanning based on various aspects of this technology.

[0012] Figure 6A and 6B This is a diagram illustrating the extraction of total load capacitance using a single measurement based on various aspects of this technology.

[0013] Figure 7 This is a schematic diagram illustrating an example of a circuit for improved impedance estimation via pixel load reconfiguration according to various aspects of the present technology.

[0014] Figure 8A and 8B This is a diagram illustrating various aspects of the technology, including panel C. pix and R pix A graph of the simulation results of the scan.

[0015] Figure 9 This is a flowchart illustrating an example of a process for panel impedance sensing via a driver replicating current, according to various aspects of the present technology.

[0016] Figure 10 The illustrations illustrate examples of wireless communication devices in which some aspects of the present technology are implemented. Detailed Implementation

[0017] The detailed description below is intended to illustrate various configurations of the present technology and is not intended to represent the only configuration in which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description. For the purpose of providing a thorough understanding of the present technology, the detailed description includes specific details. However, the present technology is not limited to the specific details set forth herein and can be practiced using one or more embodiments. In one or more examples, structures and components are shown in block diagram form to avoid obscuring the concept of the present technology.

[0018] According to some aspects, this technology is for panel impedance sensing via a driver replicating current. The panel may comprise a touch display panel formed by an N×M array of resistor-capacitor (RC) circuits. Touch display panels can be used in electronic devices, such as consumer electronics, laptops, desktop computers, smart TVs, handheld electronic devices such as tablets and phones, smartwatches, and similar devices. This technology allows for panel impedance and / or bandwidth testing using minimal hardware. The disclosed technology uses a stimulation voltage (V... pix ) to drive the pixels, and use the replication current to measure the pixel current (I) pix In some embodiments, pixel current is the current drawn by the pixels of the display panel from the corresponding driver circuitry. A single measurement can provide an estimate of the total load capacitance. Using two different frequencies, this technique calculates a unipolar RC approximation. Additional measurements allow for the extraction of higher-order model parameters, as further discussed herein. This technique allows for the consideration of parasitic capacitive loads at the driver output.

[0019] In some embodiments, the circuitry of this technology includes a driver that provides voltage at a node of the load and a first circuit that helps determine the load current at the node. The load is a capacitive load, and the first circuitry helps determine the load current by measuring a replica current and using the values ​​of the voltage and the replica current to determine the capacitance of the load.

[0020] In some embodiments, the circuitry for impedance sensing includes a driver that provides a voltage at a node of the panel. A first circuit coupled to the node facilitates the measurement of a replicated current, and the admittance of the panel at the node is determined using the replicated current and voltage. In some embodiments, the admittance is capacitive admittance. In some embodiments, capacitive admittance refers to the admittance of a circuit formed by the interconnection of two or more capacitors, or may be simplified to an equivalent circuit containing one or more capacitors.

[0021] In some embodiments, the communication device includes a display panel and a driver that provides voltage at a node of the display panel. A first circuit is coupled to the node to facilitate the measurement of the replication current and to determine the capacitance of the display panel by using the peak-to-peak values ​​of the voltage and the replication current, as described in more detail herein.

[0022] Figure 1 This is a schematic diagram illustrating an example of a device 100 for performing panel impedance sensing, within which some aspects of the present technology are implemented. Device 100 includes a driver circuit 110, a current sensor 120, a load 130, and a current measurement circuit 140. In some embodiments, the driver circuit 110 provides a voltage Vx at node 128 of the load 130. In some embodiments, the driver circuit 110 may include amplifier and buffer circuitry. In some embodiments, the current sensor 120 is an operational amplifier current sensor or a Hall effect current sensor. In some embodiments, the load 130 is a capacitive load including a distributed (lumped) resistor-capacitor (RC) circuit, such as... Figure 1 As shown in the diagram. For example, load 130 includes several resistors Rx1, Rx2, ..., RxN connected between the terminals of the respective resistors and ground potential, and several capacitors Cx1, Cx2, ..., CxN, as shown in the diagram. Figure 1 As shown in the illustration. In some embodiments, load 130 represents the impedance of the touch-sensitive layer of the touch display panel of an electronic device. Current sensor 120 detects current 122 measured by current measurement circuit 140. Current 122 is proportional to current 112 (Ix), where the scaling factor is K. As seen from node 128, the measured current 142 (IxS) is used to determine the impedance Zx of load 130. In the context of this disclosure, a node is an interconnection of two or more circuits or circuit elements. For example, node 128 is the interconnection between driver circuit 110 and load 130. In the context of this disclosure, a load consists of one or more circuit elements connected to a circuit (e.g., driver circuit 110) and receiving, for example, energy or power from or drawing current from the circuit. This current is referred to as the load current. Impedance Zx is a function (f) of voltage Vx and measured current 142 (IsX), and can be expressed as: Zx = f (Vx, IsX).

[0023] As described herein, this disclosure implements a combination of current sensor 120 and current measurement circuit 140 to achieve panel impedance and / or bandwidth testing of a display panel using minimal hardware. Furthermore, this technique allows the effects of parasitic capacitive loads at the output of driver circuit 110 to be taken into account.

[0024] Figure 2A and 2BThese are schematic diagrams illustrating various aspects of the present invention, including an example of a device 200A for panel impedance sensing via a driver-replicated current, and a corresponding diagram 200B. Device 200A may include the output stage of a transmission (TX) amplifier and utilizes a driver circuit 202 and a current measurement circuit 240. The driver circuit 202 is coupled to the panel 250 at node 232 and provides the pixel current Ipix to the panel 250. A capacitor Cpar is a parasitic capacitor that draws current Ipar. The driver circuit 202 may further include a current sensor (similar to, for example...) Figure 1 The current sensor 120 is included in the driver circuit 202. The driver circuit 202 further includes, but is not limited to, circuits 210, 220, and an output stage 230. Circuit 210 is formed from p-type metal-oxide-semiconductor (PMOS) transistors and provides a current equal to Ip through circuit 220. The circuit also includes a direct current (DC) source Ios and switches S1 and S2. Circuit 220 can be characterized as a replication circuit providing a replicated current (Irep). In this respect, circuit 220 is partially designed to replicate and match the current Ip. The replicated current (Irep) is scaled by a 1 / N ratio but can then be amplified by a factor of N to provide a replicated / matched current. Output stage 230 includes a pair of N-type MOS (NMOS) transistors and switch S3. Output stage 230 provides a path to ground for the alternating current (AC) component of current Ip.

[0025] In the configuration operation, when switches S1 and S2 are closed, the replicated current (Irep) from circuit 220 is provided to current measurement circuit 240. In some embodiments, current measurement circuit 240 is configured to provide a measurable voltage proportional to the measured current. Current measurement circuit 240 may include a transimpedance amplifier (TIA) that generates a voltage based on a feedback loop entering current measurement circuit 240. Furthermore, the DC current source Ios is provided based on the closure of switch S2. Moreover, when switch S3 is open, the current In of output stage 230 is set to zero. In this configuration, if parasitic capacitance Cpar and the corresponding current Ipar are ignored, then current Ipix is ​​given by the following formula:

[0026] Ipix = Ip - Ios (Equation 1)

[0027] Considering that Ios is a DC current with a zero peak-to-peak (ptp) value,

[0028] Ipix (ptp) = Ip (ptp) (Equation 2)

[0029] Since Ip is equal to the replication current (Irep) (or proportional to the replication current), the ptp value associated with the replication current (Irep) (e.g., as shown in curve 260) is equal to the second ptp value associated with the load current (Ipix) (or proportional to the second ptp value).

[0030] Therefore, the admittance Y of panel 250 can be obtained:

[0031] Y = Ip (ptp) / Vtxp (ptp) (Equation 3)

[0032] Where Vtxp is the voltage at node 232, and the ptp value of Ip is the same as the ptp value of the replicated current Irep, which is converted into a sinusoidal voltage with a known frequency at the output node 228 of the current measurement circuit 240. The known frequency is the operating frequency of the TX amplifier. The measured sinusoidal voltage is converted into a digital signal, which is then converted into a ptp voltage value proportional to the ptp value of the replicated current Irep by using known demodulation and Fast Fourier Transform (FFT) operations. The ptp value of Ipix (which is the same as the ptp value of Ip (see Equation 2)) can then be derived from the ptp value of Irep. The DC current source Ios is considered as part of the measurement error in the topology of Figure 2. Figure 7 As shown, the value of Cpar can be de-embedded by performing two measurements: one measurement closes S1, and the other measurement closes both S1 and S2.

[0033] In some embodiments, driver circuitry 202 provides a voltage Vtxp at node 232 of a load (e.g., panel 250). In some embodiments, first circuitry (e.g., circuits 210 and 220) helps determine the load current (e.g., Ipix) at node 232. The load is capacitive, and the first circuitry helps determine the load current by measuring the replication current (e.g., Irep) and using the values ​​of the voltage and replication current to determine the capacitance of the load. In some embodiments, the load comprises at least a portion of a touch display panel, and the load current (Ipix) is the pixel current associated with the touch display panel. In some embodiments, voltage Vtxp is, for example, a periodic voltage (stimulation voltage) having a sinusoidal waveform and a stimulation frequency. Generally, periodic voltages can have various waveforms, such as sinusoidal, square, triangular, or other waveforms. In some embodiments, the first circuitry (e.g., circuits 210 and 220) includes a bias current source (Ios), and circuitry 210 provides the replication current (Irep) to current measurement circuitry 240.

[0034] In some embodiments, the current measurement circuit 240 is a TIA circuit that provides a measurable voltage proportional to the replicated current Irep at the output node 228 of the transimpedance amplifier (TIA). In some embodiments, the current measurement circuit 240 facilitates the extraction (determination) of unipolar RC model parameters associated with the load via measurements at different frequencies (e.g., two stimulation frequencies), as described herein.

[0035] Figure 200B includes curves 260, 262, 264, and 266. Curve 260 shows the simulated time variation of the voltage at node 232. Curves 262, 264, and 266 depict the simulated time variations of the load current Impix, the current Ip, and the replica current Irep, respectively. As can be seen from curve 264, the current load current Impix does not have a DC value (due to the absence of a constant current value), and therefore shows a ptp value. The current Ip has a bias current Ios component. In some embodiments, the bias current is a DC current provided by a current source and used to bias the circuit.

[0036] Figure 3A and 3B These are graphs 300A and 300B illustrating simulated copy current and pixel current according to various aspects of this technology. Graph 300A includes curves 310, 320, and 330. Curves 310 and 320 show the time variations of the copy current Irep and the load current Ipix, respectively, which are generally similar and almost overlap each other. Curve 330 shows the time variation of the error current at different magnified scales. The error current is the difference between curves 310 and 320 and shows an error of approximately 4% to 6% between the measured Ireq and the load current Ipix. This error is caused by the parasitic capacitance Cpar at node 232 (as shown in Figure 2). As described below, this technology is designed to calibrate and counteract the effect of this capacitor.

[0037] Chart 300B includes curves 312, 322, and 332. Curves 312 and 322 show the frequency variations of the replication current Irep and the load current Ipix, respectively, which are generally similar and almost overlap each other. Curve 332 shows the frequency variation of the error current, which is the difference between curves 312 and 322, at magnified scales between 50 kHz and 300 kHz. Charts 300A and 300B indicate that the measured replication current Irep and load current Ipix are well matched.

[0038] Figure 4This is a graph 400 illustrating the estimation of total pixel capacitance according to various aspects of this technique. Graph 400 includes curves 410, 420, and 430 showing the simulated total pixel impedance using a unipolar model (RC), a lumped-pole model, a bipolar model (RC-RC), and a distributed model, respectively. Below 100 kHz (beneficial for capacitance measurements), the three models produce similar results.

[0039] Figure 5A and 5B These are graphs 500A and 500B illustrating simulation results of panel R / C scanning according to various aspects of this technology. Graph 500A includes curves 510 and 520 respectively showing total capacitance and pixel capacitance. Total capacitance (C...) total The conductivity (Y1) is obtained by measuring at a low stimulation frequency ω1 (e.g., 2π × 30 kHz), as follows:

[0040] C total = Y1 / ω1 (Equation 4)

[0041] Curve 510 shows the change in total capacitance value relative to pixel capacitance (in %). As shown in curves 510 and 520, the difference in capacitance value is due to parasitic capacitance (Cpar), which is plotted in curve 530 of graph 500B. The average value of parasitic capacitance (Cpar) appears to be approximately 47 picofarads (pF). Graphs 500A and 500B are results testing the effectiveness of the unipolar approximation measurement. Graph 500A shows the measured value of Cpix increasing as we scan Cpix. Graph 500B shows the value subtracted for a given change in Cpix: Cpar = Ctotal – Cpix.

[0042] In some respects, the parameters of the unipolar RC model can be extracted (determined) from two measurements at two different stimulation frequencies ω1 (e.g., 2π × 100 kHz) and ω2 (e.g., 2π × 300 kHz), as follows:

[0043] α = (Y1 2 ω2 2 ) / (Y2 2 ω1 2 (Equation 5)

[0044] T = RC = ((1-α) / (αω1 2 -ω2 2 )) 1 / 2 (Equation 6)

[0045] C = (Y1 / ω1) (1 +ω1 2 *T 2) 1 / 2 (Equation 7)

[0046] R = T / C (Equation 8)

[0047] The measurement mentioned therein corresponds to Figure 4 Two points on curve 410.

[0048] Figure 6A and 6B These are graphs 600A and 600B illustrating the extraction of total load capacitance using a single measurement according to various aspects of this technology. Graph 600A includes curves 610, 620, and 630, respectively, showing the error (in %) of the values ​​of Cpix, Cpix × Rpix, and Rpix relative to the change (in %) of Cpix. Graph 600B includes curves 612, 622, and 632, respectively, showing the error (in %) of the values ​​of Cpix, Cpix × Rpix, and Rpix relative to the change (in %) of Rpix. Graphs 600A and 600B are simulated results of a single measurement and indicate that the RC accuracy measured by the implemented circuit is within 2% given a variation [-40% to 40%] in R or C from a given manufacturer.

[0049] Figure 7 This is a schematic diagram illustrating an example of a circuit 700 for improved impedance estimation via pixel load reconfiguration according to various aspects of the present technology. In some embodiments, circuit 700 is used to obtain a measured replica current (e.g., Figure 2A Remove the parasitic capacitance Cpar at the output node of the first circuit (e.g., Irep). Figure 2A The load reconfiguration circuit utilizes the effect of Cpar. Circuit 700 includes amplifier 710, switches S1 and S2, and pixel resistor R. pix1 and R pix2 and pixel capacitor C pix1 and C pix2 The parasitic capacitance Cpar is not part of the single-model RC parameters discussed above. Circuit 700 is used to measure the pixel current (I) by eliminating the effect of parasitic capacitance Cpar in three steps. pix1 or I pix2 First, switch S1 is closed while switch S2 is open, and the first measuring current (I) is obtained. m1 ), which is:

[0050] I m1 = I par + I pix1 (Equation 9)

[0051] Second, switches S1 and S2 are closed, and a second measuring current (I) is obtained.m2 ), which is:

[0052] I m2 = I par +I pix1 + I pix2 (Equation 10)

[0053] Third, from I m2 Subtract I m1 To obtain I pix2 :

[0054] I pix2 = I m2 - I m1 (Equation 11)

[0055] Pixel current I can be obtained similarly. pix1 .

[0056] Figure 8A and 8B These are graphs 800A and 800B illustrating simulation results of panel Rpix and Cpix scans according to various aspects of this technology. Graph 800A includes curves 810, 820, and 830 respectively showing the errors (in %) of the values ​​of Rpix, Cpix×Rpix, and Cpix relative to the change in Cpix (in %). Graph 800B includes curves 812, 822, and 832 respectively illustrating the errors (in %) of the values ​​of Rpix, Cpix×Rpix, and Cpix relative to the change in Rpix (in %). Graphs 700A and 700B indicate the measurement error using a two-measurement method. The absolute measurement error at Cpix is ​​improved from 8% (in 600A and 600B) to 0.1% (in 700A and 700B).

[0057] Figure 9 This is a flowchart illustrating an example of a process 900 for panel impedance sensing via a driver, according to various aspects of the present technology. Process 900 includes using a driver (e.g., Figure 2A The driver circuit 202) is in the load (e.g., Figure 2A The nodes of panel 250 (e.g., Figure 2A A voltage is provided at node 232 (box 910). Process 900 also includes using a first circuit (e.g., Figure 2A Circuits 210 and 220) measure the replication current (e.g., Figure 2A The replicated current Irep is used to determine the load current at the node (e.g., Figure 2A The pixel current Ipix) (box 920). Process 900 further includes using the values ​​of voltage and replication current to determine the capacitance of the load (e.g., the pixel current Ipix) (box 920). Figure 5A C pix (Box 930).

[0058] Figure 10 The illustration depicts an example of a wireless communication device 1000, within which some aspects of the present technology are implemented. In one or more embodiments, the wireless communication device 1000 may be a laptop computer, desktop computer, tablet computer, smart TV, smartphone, smartwatch, or other electronic device including one or more health sensing devices. The wireless communication device 1000 may include an RF antenna 1010, a duplexer 1012, a receiver 1020, a transmitter 1030, a baseband processing module 1040, a memory 1050, a processor 1060, and a local oscillator generator (LOGEN) 1070. In various aspects of the present technology, Figure 10 One or more of the boxes indicated herein may be integrated on one or more semiconductor substrates. For example, boxes 1020 to 1070 may be implemented in a single chip, a system-on-a-chip, or a multi-chip chipset.

[0059] Receiver 1020 may include suitable logic circuitry and / or code operable to receive and process signals from RF antenna 1010. Receiver 1020 may be operable, for example, to amplify and / or down-convert the received wireless signal. In various aspects of this technology, receiver 1020 may be operable to eliminate noise in the received signal and may be linear over a wide frequency range. In this way, receiver 1020 may be suitable for receiving signals according to various wireless standards such as Wi-Fi, WiMAX, BT, and various cellular standards. In various aspects of this technology, receiver 1020 may not use any sawtooth acoustic filters and may use few or no off-chip discrete components, such as large capacitors and inductors.

[0060] Transmitter 1030 may include suitable logic circuitry and / or code operable to process and transmit signals from RF antenna 1010. Transmitter 1030 may, for example, be operable to upconvert baseband signals into RF signals and amplify the RF signals. In various aspects of this technology, transmitter 1030 may be operable to upconvert and amplify baseband signals processed according to various wireless standards. Examples of such standards may include Wi-Fi, WiMAX, BT, and various cellular standards. In various aspects of this technology, transmitter 1030 may be operable to provide signals for further amplification by one or more power amplifiers.

[0061] The duplexer 1012 provides isolation in the transmission band to prevent saturation or damage to the receiver 1020's components and relaxes one or more design requirements of the receiver 1020. Furthermore, the duplexer 1012 attenuates noise in the receiver's band. The duplexer 1012 can operate in multiple bands across various wireless standards.

[0062] The baseband processing module 1040 may include suitable logic, circuitry, interfaces, and / or code operable to perform baseband signal processing. The baseband processing module 1040 may, for example, analyze received signals and generate control and / or feedback signals to configure various components of the wireless communication device 1000 (e.g., receiver 1020). The baseband processing module 1040 is operable to encode, decode, transcode, modulate, demodulate, encrypt, decrypt, scramble, descramble, and / or otherwise process data according to one or more wireless standards.

[0063] Processor 1060 may include suitable logic, circuitry, and / or code operable to process data and / or control the operation of wireless communication device 1000. In this regard, processor 1060 may enable the provision of control signals to various other parts of wireless communication device 1000. Processor 1060 may also control data transfer between various parts of wireless communication device 1000. Additionally, processor 1060 may enable the implementation of an operating system, or otherwise the execution of code to manage the operation of wireless communication device 1000. In one or more embodiments, processor 1060 may interface with transducer modules via existing host interface technologies, such as internal integrated circuit (I2C), serial interface protocol (SPI), peripheral component high-speed interconnect (PCIe), universal asynchronous receiver-transmitter (UART), and / or other interface technologies, depending on the data rate required to sample from the transducer module and pipe to processor 1060.

[0064] The memory 1050 may include suitable logic, circuitry, and / or code that enables the storage of various types of information (e.g., received data, generated data, code, and / or configuration information). The memory 1050 may include, for example, RAM, ROM, flash memory, and / or magnetic memory. In various aspects of this technology, the information stored in the memory 1050 may be used to configure the receiver 1020 and / or the baseband processing module 1040.

[0065] LOGEN 1070 may include suitable logic, circuitry, interfaces, and / or code operable to generate one or more oscillation signals at one or more frequencies. LOGEN 1070 is operable to generate digital and / or analog signals. In this way, LOGEN 1070 is operable to generate one or more clock signals and / or sinusoidal signals. The characteristics of the oscillation signals (e.g., frequency and load cycling) may be determined based on one or more control signals from, for example, processor 1060 and / or baseband processing module 1040.

[0066] In operation, processor 1060 can configure various components of wireless communication device 1000 based on wireless standards, according to which processor 1060 is designed to receive signals. Wireless signals can be received via RF antenna 1010 and amplified and down-converted by receiver 1020. Baseband processing module 1040 can perform noise estimation and / or noise cancellation, decoding and / or demodulation of baseband signals. In this way, information in the received signals can be appropriately recovered and utilized. For example, the information may be audio and / or video to be presented to the user of wireless communication device 1000, data to be stored in memory 1050, and / or information affecting and / or enabling the operation of wireless communication device 1000. Baseband processing module 1040 can modulate, encode, and perform other processing on audio, video, and / or control signals to be transmitted by transmitter 1030 according to various wireless standards.

[0067] In some implementations, as discussed above, the technology can be used to replicate current via a driver (e.g., Figure 2A The Irep is used to measure the panel impedance of the touch display panel of the wireless communication device 1000 (for simplicity, in...). Figure 10 (Not shown in the text).

[0068] The predicates “configured to,” “operable to,” and “programmed to” do not imply any particular tangible or intangible modification of an object, but are intended to be used interchangeably. For example, a processor configured to monitor and control an operation or component can also mean a processor programmed to monitor and control said operation or an operable processor to monitor and control said operation. Similarly, a processor configured to execute code can be interpreted as a processor programmed to execute code or an operable processor to execute code.

[0069] For example, the phrase "aspect" does not imply that this aspect is essential to the art or that this aspect applies to all configurations of the art. Disclosures relating to an aspect may apply to all configurations or one or more configurations. For example, the phrase "aspect" may refer to one or more aspects, and vice versa. For example, the phrase "configuration" does not imply that this configuration is essential to the art or that this configuration applies to all configurations of the art. Disclosures relating to configuration may apply to all configurations or one or more configurations. For example, the phrase "configuration" may refer to one or more configurations, and vice versa.

[0070] The term “example” is used in this document to mean “used as an example or illustration.” Any aspect or design described as an “example” in this document is not necessarily to be construed as superior or advantageous to other aspects or designs.

[0071] When an element is referred to herein as "connected" or "coupled" to another element, it should be understood that the element can be directly connected to the other element, or that there are intermediate elements between the elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, it should be understood that there are no intermediate elements in a "direct" connection between the elements. However, the existence of a direct connection does not preclude other connections in which intermediate elements may be present.

[0072] When a quantity is referred to herein as being “equal to” or “proportional to” another quantity, it should be understood that in engineering, the quantity may not have an absolutely accurate value due to several factors that allow for reasonable deviations due to, for example, error ranges, tolerances, interferences and other engineering realities.

[0073] All structural and functional equivalents of the elements of the various aspects described throughout this disclosure, known or subsequently learned by those skilled in the art, are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be public, regardless of whether it is expressly stated in the claims. No claim element will be construed in accordance with 35 USC §112(f) unless the element is expressly stated using the phrase “component for…” or, in the case of a method claim, using the phrase “step for…”. Moreover, with regard to the use of the terms “comprising,” “having,” etc., in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the meaning of the term “comprising” when “comprising” is used as a transitional word in a claim.

[0074] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability between hardware and software, the various illustrative blocks, modules, elements, components, methods, and algorithms have generally been described above in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in varying ways for each specific application. Various components and blocks can be arranged in different ways (e.g., in different orders or in different ways), all without departing from the scope of this art.

Claims

1. An apparatus comprising: A driver circuit configured to provide a voltage at a node of the load, the voltage being based on a first current; A first circuit is configured to generate a second current proportional to the first current; as well as A second circuit is configured to measure the first current in the following manner: Measure the second current; and The capacitance of the load is determined using the values ​​of the voltage and the second current. and A current measurement circuit is configured to provide a measurable voltage proportional to the second current to determine resistance-capacitance RC model parameters associated with the load via measurements at different frequencies, the different frequencies being used to determine the capacitance.

2. The device according to claim 1, wherein: The load includes at least a portion of the touch display panel, and The first current includes the pixel current supplied to the touch display panel.

3. The device of claim 1, wherein the voltage comprises a voltage having a sinusoidal waveform.

4. The device according to claim 1, wherein the voltage includes a peak-to-peak voltage.

5. The device according to claim 1, wherein: The second current includes the first peak-to-peak value, and The first current includes the load current, and the load current includes a second peak-to-peak value equal to the first peak-to-peak value.

6. The device of claim 1, wherein the first circuitry includes a bias current source configured to provide a component to the second current.

7. The device of claim 1, wherein the current measurement circuit includes a transimpedance amplifier circuit configured to provide the measurable voltage.

8. The device of claim 1, further comprising a circuit system configured to remove the effect of parasitic capacitance of the first circuit.

9. A circuit for impedance sensing, the circuit comprising: A driver circuit configured to provide a voltage at a node, the voltage being based on a first circuit configured to generate current. A second circuit, coupled to the node, is configured to: Measure the current; The admittance at the node is determined by using the current and the voltage. and A current measurement circuit is configured to provide a measurable voltage proportional to the current, and to determine the resistance-capacitance RC model parameters associated with the load via measurements at different frequencies, the different frequencies being used to determine the capacitance.

10. The circuit of claim 9, wherein the admittance includes capacitive admittance, and the node is part of a touch display panel.

11. The circuit of claim 9, wherein the second circuit is configured to determine the admittance by using the peak-to-peak values ​​of the current and the voltage.

12. The circuit of claim 9, wherein the first circuit includes a bias current source configured to provide a component to the current.

13. The circuit of claim 12, further comprising a transimpedance amplifier circuit configured to provide a measurable voltage proportional to the current.

14. The circuit according to claim 13, wherein: The voltage includes a stimulation voltage configured to electrically stimulate a third circuit, which is coupled to the driver circuit at the node and operates at a frequency. The admittance is based on the frequency.

15. The circuit of claim 9, further comprising a circuit system configured to remove the parasitic capacitance of the first circuit.

16. An apparatus comprising: Display panel; A first circuit is configured to provide a voltage at a node of the display panel, wherein the voltage is based on a first current, and the first circuit is further configured to generate a second current proportional to the first current. and A second circuit, coupled to the node and configured as follows: Receive a second current that is proportional to the first current; Determine the value of the second current; The capacitance of the display panel is determined by using the peak-to-peak values ​​of the voltage and the second current. and A current measurement circuit is configured to provide a measurable voltage proportional to the second current to determine resistance-capacitance RC model parameters associated with the load via measurements at different frequencies, the different frequencies being used to determine the capacitance.

17. The apparatus according to claim 16, wherein: The first circuit includes a bias current source configured to provide a component to the second current. The current measurement circuit is configured to determine the value of the second current by providing a measurable voltage proportional to the second current.

18. The device of claim 17, wherein the current measurement circuit includes a transimpedance amplifier circuit configured to provide the measurable voltage.

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