Testing and preparation method of superconducting quantum chip, testing structure and preparation method

Abstract

The present invention is applicable to the field of superconducting quantum technology, and in particular, relates to a test and preparation method, test structure and preparation method of a superconducting quantum chip. The test method comprises: providing a superconducting quantum chip; covering the metal conductive film around the edge of the superconducting quantum chip or locally with conductive glue, and the conductive glue is not in contact with a number of Josephson junctions; performing a resistance test of the Josephson junction on the superconducting quantum chip covered with conductive glue by a test device, the test device provides voltage to the superconducting quantum chip covered with conductive glue, the first end of the test device contacts the upper surface of the junction region of a Josephson junction, and the end is electrically connected to the junction region of the Josephson junction, and the second end of the test device is electrically connected to the conductive glue. The present invention realizes low current and high precision testing, and the current level is at the pA or even fA level, which solves the problem of easily damaged or broken junctions in Josephson junction testing.

Description

Technical Field

[0001] The present invention is applicable to the field of superconducting quantum technology, and in particular relates to a test and preparation method, a test structure and a preparation method of a superconducting quantum chip. Background Art

[0002] The Josephson junction is a key structure of superconducting quantum bits, which is related to the computing performance of superconducting quantum chips and even all-solid-state superconducting quantum computers. In order to ensure the performance of superconducting quantum chips, the frequency parameters of superconducting quantum bits must be strictly controlled, and the characterization of the room temperature resistance of the Josephson junction is an important means of reflecting the frequency parameters, so it is necessary to accurately measure the room temperature resistance of the Josephson junction.

[0003] Currently, the resistance measurement of superconducting quantum chips mostly uses a probe to penetrate the pad structure at both ends of the device to make electrical contact. However, the probe test method is easy to damage or even break down the Josephson junction due to the large current. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a method for testing and preparing a superconducting quantum chip, a test structure and a preparation method to solve the problem that the Josephson junction is easily damaged in the existing detection process.

[0005] The present application provides a method for testing a superconducting quantum chip, comprising the following steps:

[0006] A superconducting quantum chip is provided, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions grown on the metal conductive film;

[0007] Covering the conductive glue on the metal conductive film around the edge of the superconducting quantum chip or on a part thereof, and the conductive glue is not in contact with a plurality of Josephson junctions;

[0008] The resistance test of the Josephson junction is performed on the superconducting quantum chip covered with conductive glue by a testing device, wherein the testing device provides voltage to the superconducting quantum chip covered with conductive glue, a first end of the testing device contacts the upper surface of a junction region of a Josephson junction, and the end is electrically connected to the junction region of the Josephson junction, and a second end of the testing device is electrically connected to the conductive glue.

[0009] In addition, the present application also proposes a method for preparing a superconducting quantum chip, including the above-mentioned method for testing the superconducting quantum chip. After the test is completed, the conductive glue is removed by using a glue remover to obtain the superconducting quantum chip.

[0010] Compared with the prior art, the testing method and preparation method of the superconducting quantum chip of the present invention have the following beneficial effects: the present invention conducts the superconducting quantum chip before testing, realizes low current, high precision testing, the current level is at the pA or even fA level, solves the problem of easy damage or breakdown of the Josephson junction test, reduces the damage during the test, and improves the product yield and production efficiency. At the same time, if the conductive glue is covered all around, the electrical environment is balanced, avoiding the problem of uneven global Josephson junction testing during the preparation of large-scale superconducting quantum bit chips.

[0011] Furthermore, the process of covering the metal conductive film around or partially around the edge of the superconducting quantum chip with the conductive glue includes:

[0012] Provide metal gaskets;

[0013] Apply conductive glue on the upper surface of the metal gasket;

[0014] The back side of the superconducting quantum chip is pressed onto the conductive glue, so that the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip or part of it.

[0015] Furthermore, the width of the conductive adhesive covering the metal conductive film is ≥1 mm.

[0016] Furthermore, the testing device is an atomic force microscope, the first end of the atomic force microscope is a conductive probe, the second end of the atomic force microscope is an electromagnetic suction point of the sample carrier, and the resistance of the Josephson junction is determined by testing the bias voltage and the surface current value.

[0017] Furthermore, the conductive adhesive is a mixture of silver paste and photoresist, and the mass ratio of the silver paste to the photoresist is 1:1; or the model of the conductive adhesive is AR-PC5090 and AR-PC5091.

[0018] Furthermore, the open circuit defect of the Josephson junction can be determined based on the surface height map, Z-axis sensor map and amplitude map output by the atomic force microscope.

[0019] In addition, the present application also proposes a test structure of a superconducting quantum chip, including:

[0020] A superconducting quantum chip, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions grown on the metal conductive film;

[0021] and a conductive glue covering the metal conductive film around or partially around the edge of the superconducting quantum chip, wherein the conductive glue is not in contact with a plurality of Josephson junctions;

[0022] Among them, the upper surface of the junction area of ​​the Josephson junction is used to contact the first end of the test equipment, and the end is electrically connected to the junction area of ​​the Josephson junction; the conductive glue is used to electrically connect to the second end of the test equipment, and the test equipment provides voltage to the superconducting quantum chip covered with the conductive glue.

[0023] Furthermore, it also includes: a metal gasket, the upper surface of the metal gasket is fixed to the back surface of the superconducting quantum chip covered with conductive glue through the conductive glue.

[0024] In addition, the present application also proposes a method for preparing a test structure of a superconducting quantum chip, comprising the following steps:

[0025] A superconducting quantum chip is provided, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions grown on the metal conductive film;

[0026] Covering the conductive glue on the metal conductive film around the edge of the superconducting quantum chip or on a part thereof, and the conductive glue is not in contact with a plurality of Josephson junctions;

[0027] Among them, the upper surface of the junction area of ​​the Josephson junction is used to contact the first end of the test equipment, and the end is electrically connected to the junction area of ​​the Josephson junction; the conductive glue is used to electrically connect to the second end of the test equipment, and the test equipment provides voltage to the superconducting quantum chip covered with the conductive glue. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0029] Figure 1 It is a flow chart of the testing method of the superconducting quantum chip of the present invention;

[0030] Figure 2 It is a cross-sectional structural diagram of the superconducting quantum chip of the present invention;

[0031] Figure 3 It is a flow chart of preparing the test structure of the superconducting quantum chip of the present invention;

[0032] Figure 4 is a cross-sectional structural diagram of a test structure of a superconducting quantum chip of the present invention;

[0033] Figure 5 It is a schematic diagram of the placement of the test structure of the superconducting quantum chip of the present invention;

[0034] Figure 6 It is a test connection diagram of the test structure of the superconducting quantum chip of the present invention;

[0035] Figure 7a is a surface height map in the test data of the present invention;

[0036] Figure 7b It is the Z-axis sensor diagram in the test data of the present invention;

[0037] Figure 7c is the surface current diagram in the test data of the present invention;

[0038] Figure 7d is an amplitude diagram in the test data of the present invention;

[0039] Figure 8a is a surface current diagram of the Josephson junction of the present invention;

[0040] Figure 8b is a current curve diagram of a specific position of the Josephson junction of the present invention;

[0041] Figure 9a is a surface height diagram of the Josephson junction of the present invention;

[0042] Figure 9b is a height curve diagram of a specific position of the Josephson junction of the present invention;

[0043] Fig.10a is a surface height diagram of the Josephson junction of the present invention under normal conditions;

[0044] Fig.10b It is the Z-axis sensing diagram of the Josephson junction of the present invention under normal conditions;

[0045] Fig.10c is an amplitude diagram of the Josephson junction of the present invention under normal conditions;

[0046] Fig.11a is a surface height diagram under the condition of a Josephson junction open circuit defect of the present invention;

[0047] Fig.11b It is a Z-axis sensing diagram of the Josephson junction under the condition of a short circuit defect of the present invention;

[0048] Fig.11c is an amplitude diagram of the Josephson junction under the condition of an open circuit defect of the present invention;

[0049] In the figure: 1 is a metal gasket, 2 is a conductive glue, 3 is a superconducting quantum chip, 31 is a metal conductive film, 32 is a Josephson junction, 33 is a substrate, 4 is a conductive probe, 5 is a sample carrier, 6 is a dropper, 7 is a test structure, 8 is a voltage output circuit, and 9 is a voltage input circuit. DETAILED DESCRIPTION

[0050] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present invention. However, it should be clear to those skilled in the art that the present invention may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present invention.

[0051] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0052] It should also be understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0053] As used in the present specification and the appended claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]", depending on the context.

[0054] In addition, in the description of the present specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0055] References to "one embodiment" or "some embodiments" etc. described in the present specification mean that one or more embodiments of the present invention include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0056] It should be understood that the order of execution of the steps in the following embodiments does not imply a precedence of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0057] In order to illustrate the technical solution of the present invention, specific embodiments are provided below for illustration.

[0058] Example of testing method for superconducting quantum chip:

[0059] The main idea of ​​the testing method of the superconducting quantum chip is that in order to avoid the large current that is easy to damage or even break down the Josephson junction during the test, the present invention covers the metal conductive film in the superconducting quantum chip with conductive glue, and the conductive glue does not contact the several Josephson junctions, and then one of the two ends of the test equipment is electrically connected to the Josephson junction, and the other end is electrically connected to the conductive glue, so as to realize the resistance detection of the Josephson junction.

[0060] Specifically, the testing method of superconducting quantum chip, such as Figure 1 As shown, the following steps are included:

[0061] 1) Provide superconducting quantum chips.

[0062] The structure of a superconducting quantum chip is as follows Figure 2 As shown, it includes a substrate 33, a metal conductive film 31 and a plurality of Josephson junctions 32, wherein the plurality of Josephson junctions 32 are grown on the metal conductive film 31. The structure of the superconducting quantum chip is a 10 mm*10 mm die.

[0063] The metal conductive film 31 and the Josephson junction 32 are not in a top-and-bottom structure relationship, but the metal conductive film 31 is a base layer, the Josephson junction 32 grows on the metal conductive film 31 , and the Josephson junction 32 is surrounded by the metal conductive film 31 .

[0064] 2) Prepare test structures for superconducting quantum chips.

[0065] The process of preparing the test structure of the superconducting quantum chip is as follows Figure 3 As shown, the following steps are included:

[0066] S201. Provide a metal gasket 1.

[0067] S202. Use a dropper 6 to drop a conductive glue 2 on the upper surface of the metal gasket 1; the conductive glue 2 is a mixture of silver paste and photoresist, and the mass ratio of the silver paste to the photoresist is 1:1; for example: using high-purity (99.99%) metallic silver particles (micrometer diameter silver particles) at a mass ratio of 1:1 is added to the photoresist S1813, stirred evenly, to prepare the conductive glue 2;

[0068] Or the models of the conductive adhesive 2 are AR-PC5090 and AR-PC5091.

[0069] S203 . Press the back side of the superconducting quantum chip 3 onto the conductive glue 2 , so that the conductive glue 2 spreads to the front side of the superconducting quantum chip 3 and covers the metal conductive film 31 around the edge or part of the superconducting quantum chip 3 .

[0070] S204. Use a heating plate for drying.

[0071] The drying temperature is 80°C and the drying time is 1h.

[0072] Finally, the test structure profile of the superconducting quantum chip 3 is as follows: Figure 4 , the conductive glue 2 covers the metal conductive film 31 around or partially around the edge of the superconducting quantum chip 3 (covering around is to ensure electrical uniformity at all positions during testing, thereby ensuring the same test accuracy), and the conductive glue 2 does not contact the plurality of Josephson junctions 32. The width of the conductive glue 2 covering the metal conductive film 31 is ≥1mm. The upper surface of the metal gasket 1 and the back of the superconducting quantum chip 3 covered with the conductive glue 2 are fixed by the conductive glue 2. It can be seen that the metal conductive film 31 and the metal gasket 1 are conductively connected.

[0073] 3) Set the parameters of the atomic force microscope.

[0074] The parameter setting process is as follows:

[0075] S301. Select the conductive mode (ORCA) of the atomic force microscope, and install a conductive Z-axis scanner and a conductive probe 4, the conductive probe 4 model is ASYELEC.01-R2;

[0076] S302. Turn the stage bias selection knob on the rear side of the atomic force microscope stage to the Bias position;

[0077] S303. Before testing, use a multimeter to test the resistance value of the electromagnetic suction point from the machine holder to the sample carrier 5, and input the measured resistance value into the software interface to adjust the voltage offset (S. Voltage offset) until it returns to zero to offset the influence of the resistance values ​​of other components in the circuit.

[0078] 4) Test preparation.

[0079] Preparation process Figure 5 , Figure 6 As shown:

[0080] S401. Sampling: Place the test structure 7 of the superconducting quantum chip 3 prepared in step 2) on the electromagnetic suction point of the atomic force microscope sample carrier 5 (the electromagnetic suction point is inside the sample carrier 5, not shown in the figure), and control the sample carrier 5 to move the test structure 7 of the superconducting quantum chip 3 prepared to be directly below the conductive probe 4.

[0081] S402. Focusing and positioning: lower the conductive probe 4 to about 1 mm above the upper surface of the test structure 7 of the prepared superconducting quantum chip 3, so that the atomic force microscope can be focused and positioned to the junction area of ​​the Josephson junction 32.

[0082] S403. Set the test bias voltage to 0~5V.

[0083] 5) Scan test.

[0084] This step specifically starts scanning, such as Figure 5 As shown, the atomic force microscope automatically lowers the conductive probe 4 to the upper surface of the junction area of ​​the Josephson junction 32 of the test structure 7 and generates good atomic force contact with it. The contact force between the conductive probe 4 of the atomic force microscope and the test structure 7 is a weak atomic force, about 10 -8 ~10 -11 N, non-destructive testing can be achieved.

[0085] Test circuit such as Figure 6 As shown, it includes a voltage input circuit 9 and a voltage output circuit 8, and the voltage input circuit 9 includes a power supply V bias and resistor R sample One end of the voltage input circuit 9 is connected to the second end of the atomic force microscope, and the other end of the voltage input circuit 9 is grounded Virtual Ground. The voltage output circuit 8 is a common signal amplification circuit. The input end of the voltage output circuit 8 is connected to the first end of the atomic force microscope, and the output end of the voltage output circuit 8 is used to output a voltage signal V out The first end of the atomic force microscope is a conductive probe 4, and the second end of the atomic force microscope is an electromagnetic suction point of the sample carrier 5. The first end contacts the upper surface of the junction area of ​​a Josephson junction 32, and the end is electrically connected to the junction area of ​​the Josephson junction 32. The second end is electrically connected to the conductive glue 2 through the metal gasket 1. After all the connections are made, the circuit is turned on and measurement can be performed.

[0086] During the test, the surface current, morphology and other data of the junction region of the Josephson junction 32 can also be observed in real time, and the test bias voltage can be changed in real time according to the data to adjust the test effect.

[0087] 6) Data analysis.

[0088] When testing, the output is as follows Figure 7a The surface height map (height) shown in Figure 7b The Z-axis sensor diagram (Zsensor) shown in Figure 7c The surface current diagram (current) shown in Figure 7d The test results such as the amplitude diagram shown are analyzed using AsylumResearch software. The surface morphology of the Josephson junction 32 can be observed through the surface height diagram, the Z-axis sensor diagram and the amplitude diagram, and the surface current distribution can be observed through the surface current diagram.

[0089] The specific data analysis is as follows:

[0090] 1. The resistance of the Josephson junction 32 can be calculated and analyzed from the surface current diagram combined with the test bias data.

[0091] Figure 8a is the surface current diagram of the Josephson junction 32, Figure 8b is a current curve diagram of a specific position of the Josephson junction 32. The calculation process of the resistance is: using the Ohm's formula resistance R=V / I, V ​​is the test bias voltage, I is the surface current in the AFM output data diagram, and the resistance R can be obtained by substituting it into the formula.

[0092] For example, the surface current measured at a certain point is 75 pA, and the test bias voltage applied at this time is 0.65 μV. Substituting it into Ohm's formula, it is obtained that the junction resistance of the Josephson junction 32 at this point is 8666 Ω.

[0093] 2. The surface morphology and surface undulation of the Josephson junction 32 can be observed and analyzed by the surface height map, the Z-axis sensor map and the amplitude map, and the open circuit defect of the Josephson junction 32 can be determined based on the surface height map, the Z-axis sensor map and the amplitude map.

[0094] like: Figure 9a is the surface height map of the Josephson junction 32, Figure 9b is a height curve diagram of a specific position of the Josephson junction 32.

[0095] The open circuit defect of the Josephson junction 32 can be determined based on the surface height map, the Z-axis sensor map and the amplitude map, for example: Fig.10a This is a surface height diagram of the Josephson junction 32 under normal conditions; Fig.10b is the Z-axis sensing diagram of the Josephson junction 32 under normal conditions; Fig.10c is the amplitude diagram of the Josephson junction 32 under normal conditions; Fig.11a is the surface height map in the case of Josephson junction 32 open circuit defect (Figure d); Fig.11b It is the Z-axis sensing diagram in the case of the Josephson junction 32 open circuit defect (Figure e in the figure); Fig.11cThis is the amplitude diagram of the Josephson junction 32 with an open circuit defect (Figure f in the figure). It can be seen that the surface height diagram, Z-axis sensing diagram and amplitude diagram of the open circuit defect are significantly different from those of the conventional normal Josephson junction 32.

[0096] 3. The surface height and surface current distribution of the Josephson junction 32 can be compared on the same screen and the specific data can be read out.

[0097] In the above embodiment, the resistance of the Josephson junction 32 is tested by an atomic force microscope, so that the microscopic characteristics of the Josephson junction 32 can be characterized, and the surface current distribution and the microscopic morphology can be output simultaneously, so that the microscopic damage position of the dielectric layer can be located, thereby performing failure analysis, avoiding the step of characterizing the surface morphology of the junction region by means of SEM and the like after the resistance is abnormal, thereby improving the product testing efficiency. As another embodiment, a test device that only performs resistance testing can also be used without the need to perform surface morphology detection.

[0098] In the above embodiment, in order to reduce the test current, the test structure 7 includes a metal gasket 1. Of course, as other implementations, it is only necessary to cover the conductive glue 2 on the metal conductive film 31 around the edge of the superconducting quantum chip 3 or locally, and the conductive glue 2 is not in contact with the Josephson junctions 32. The manufacturing process can also be carried out by directly dropping the dropper 6 on the front side of the superconducting quantum chip 3.

[0099] In the above embodiment, in order to improve the conductive effect, the width of the conductive adhesive 2 covering the metal conductive film 31 is ≥1 mm. As other implementations, the width of the conductive adhesive 2 covering the metal conductive film 31 can also be less than 1 mm, but it is necessary to ensure that the conductive adhesive 2 overlaps the metal conductive film 31.

[0100] The present invention conducts a conductive treatment on the superconducting quantum chip 3 before testing, which not only realizes low current and high precision testing, but also solves the problem of easy damage or breakdown of the Josephson junction 32 test, reduces the damage during the test, and improves the product yield and production efficiency. Moreover, if the conductive glue is covered all around, the electrical environment is balanced, and the junction resistance at each position of the chip is continuously scanned for global testing, which avoids the problem of uneven global Josephson junction 32 testing during the preparation of large-scale superconducting quantum bit chips. At the same time, the conductive glue 2 is water-soluble, and can be easily removed by a common glue remover (deionized water, etc.) at a later stage, without affecting each position of the sample, and realizing non-destructive measurement of the chip.

[0101] Example of test structure of superconducting quantum chip:

[0102] Test structure of superconducting quantum chip, including:

[0103] A superconducting quantum chip 3, the superconducting quantum chip 3 includes a metal conductive film 31 and a plurality of Josephson junctions 32 grown on the metal conductive film 31;

[0104] and a conductive glue 2 covering the metal conductive film 31 around or partially around the edge of the superconducting quantum chip 3, wherein the conductive glue 2 is not in contact with the plurality of Josephson junctions 32;

[0105] Among them, the upper surface of the junction area of ​​the Josephson junction 32 is used to contact the first end of the test equipment, and the end is electrically connected to the junction area of ​​the Josephson junction 32; the conductive glue 2 is used to electrically connect to the second end of the test equipment, and the test equipment provides voltage to the superconducting quantum chip 3 covered with the conductive glue 2.

[0106] Also includes:

[0107] A metal gasket 1 , the upper surface of the metal gasket 1 and the back surface of the superconducting quantum chip 3 covered with the conductive glue 2 are fixed by the conductive glue 2 .

[0108] The specific structure of the test structure 7 of the superconducting quantum chip 3 has been introduced in detail in the above-mentioned embodiment of the test method for superconducting quantum chip, and will not be described in detail here.

[0109] Example of a method for preparing a test structure of a superconducting quantum chip:

[0110] A method for preparing a test structure of a superconducting quantum chip comprises the following steps:

[0111] A superconducting quantum chip 3 is provided, wherein the superconducting quantum chip 3 comprises a metal conductive film 31 and a plurality of Josephson junctions 32 grown on the metal conductive film 31;

[0112] The conductive glue 2 is covered on the metal conductive film 31 around the edge of the superconducting quantum chip 3 or locally, and the conductive glue 2 is not in contact with the plurality of Josephson junctions 32;

[0113] Among them, the upper surface of the junction area of ​​the Josephson junction 32 is used to contact the first end of the test equipment, and the end is electrically connected to the junction area of ​​the Josephson junction 32; the conductive glue 2 is used to electrically connect to the second end of the test equipment, and the test equipment provides voltage to the superconducting quantum chip 3 covered with the conductive glue 2.

[0114] The method for preparing the test structure of the superconducting quantum chip has been introduced in detail in the above-mentioned embodiment of the test method of the superconducting quantum chip, and will not be described in detail here.

[0115] Example of a method for preparing a superconducting quantum chip:

[0116] The preparation method of the superconducting quantum chip includes a testing method of the superconducting quantum chip. After the test is completed, the conductive glue 2 is removed by using a glue remover to obtain the superconducting quantum chip 3.

[0117] The testing method of the superconducting quantum chip has been introduced in detail in the above-mentioned embodiment of the testing method of the superconducting quantum chip, and will not be described in detail here.

[0118] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention.

Claims

1. A method for testing a superconducting quantum chip, characterized in that: The following steps are involved: A superconducting quantum chip is provided, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions grown on the metal conductive film; Covering the conductive glue on the metal conductive film around the edge of the superconducting quantum chip, or covering the conductive glue on the metal conductive film at a local edge of the superconducting quantum chip, and the conductive glue does not contact with a plurality of Josephson junctions; The resistance test of the Josephson junction is performed on the superconducting quantum chip covered with the conductive glue by using a testing device, wherein the testing device provides a voltage to the superconducting quantum chip covered with the conductive glue, a first end of the testing device contacts an upper surface of a junction region of a Josephson junction, and the end is electrically connected to the junction region of the Josephson junction, and a second end of the testing device is electrically connected to the conductive glue; The process of covering the metal conductive film around the edge of the superconducting quantum chip with the conductive glue, or covering the metal conductive film locally at the edge of the superconducting quantum chip with the conductive glue includes: Provide metal gaskets; Apply conductive glue on the upper surface of the metal gasket; The back side of the superconducting quantum chip is pressed onto the conductive glue, so that the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip, or the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film at the local edge of the superconducting quantum chip.

2. The method for testing a superconducting quantum chip according to claim 1, characterized in that: The width of the conductive adhesive covering the metal conductive film is ≥1mm.

3. The method for testing a superconducting quantum chip according to claim 1, characterized in that: The testing device is an atomic force microscope, the first end of which is a conductive probe, and the second end of which is an electromagnetic suction point of a sample carrier. The resistance of the Josephson junction is determined by testing bias voltage and surface current value.

4. The method for testing a superconducting quantum chip according to claim 1, characterized in that: The conductive adhesive is a mixture of silver paste and photoresist, and the mass ratio of the silver paste to the photoresist is 1:1; or the model of the conductive adhesive is AR-PC5090 and AR-PC5091.

5. The method for testing a superconducting quantum chip according to claim 3, characterized in that: The open circuit defect of the Josephson junction is determined based on the surface height map, Z-axis sensor map and amplitude map output by the atomic force microscope.

6. A test structure for a superconducting quantum chip, characterized in that: include: A superconducting quantum chip, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions grown on the metal conductive film; and a conductive glue covering the metal conductive film around the edge of the superconducting quantum chip, or a conductive glue covering the metal conductive film locally at the edge of the superconducting quantum chip, wherein the conductive glue does not contact the plurality of Josephson junctions; The upper surface of the junction region of the Josephson junction is used to contact the first end of the test device, and the first end is electrically connected to the junction region of the Josephson junction; the conductive glue is used to electrically connect to the second end of the test device, and the test device provides voltage to the superconducting quantum chip covered with the conductive glue; A metal gasket is provided, and conductive glue is dripped on the upper surface of the metal gasket; the back side of the superconducting quantum chip is pressed on the conductive glue, so that the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip, or the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film at the edge of the superconducting quantum chip; the upper surface of the metal gasket and the back side of the superconducting quantum chip covered with the conductive glue are fixed by the conductive glue.

7. A method for preparing a test structure of a superconducting quantum chip, characterized in that: The following steps are involved: A superconducting quantum chip is provided, wherein the superconducting quantum chip comprises a metal conductive film and a plurality of Josephson junctions grown on the metal conductive film; Covering the conductive glue on the metal conductive film around the edge of the superconducting quantum chip, or covering the conductive glue on the metal conductive film at a local edge of the superconducting quantum chip, and the conductive glue does not contact with a plurality of Josephson junctions; The upper surface of the junction region of the Josephson junction is used to contact the first end of the test device, and the first end is electrically connected to the junction region of the Josephson junction; the conductive glue is used to electrically connect to the second end of the test device, and the test device provides voltage to the superconducting quantum chip covered with the conductive glue; The process of covering the metal conductive film around the edge of the superconducting quantum chip with the conductive glue, or covering the metal conductive film locally at the edge of the superconducting quantum chip with the conductive glue includes: Provide metal gaskets; Apply conductive glue on the upper surface of the metal gasket; The back side of the superconducting quantum chip is pressed onto the conductive glue, so that the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film around the edge of the superconducting quantum chip, or the conductive glue spreads to the front side of the superconducting quantum chip and covers the metal conductive film at the local edge of the superconducting quantum chip.

8. A method for preparing a superconducting quantum chip, characterized in that: A method for testing a superconducting quantum chip according to any one of claims 1 to 5, wherein after the test is completed, the conductive glue is removed by using a glue remover to obtain the superconducting quantum chip.

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