Semiconductor device and manufacturing method, power module, power conversion circuit and vehicle

Abstract

The present application discloses a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, belonging to the field of semiconductor technology. The semiconductor device includes a silicon carbide substrate and a drift layer, a well region, a JFET region and a first region, a gate, a source and a drain, wherein the JFET region includes a first part close to the silicon carbide substrate and a second part away from the silicon carbide substrate, and the area of ​​the orthographic projection of the first part on the silicon carbide substrate is smaller than the area of ​​the orthographic projection of the second part on the silicon carbide substrate. The technical solution of the present application aims to increase the carrier concentration of the semiconductor device while reducing the path of the reverse current, thereby improving the safety and reliability of the semiconductor.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Semiconductor devices play a vital role in the field of semiconductor technology. In the manufacturing process of existing semiconductor devices, in order to achieve high-dose P+ and N+ regions, multiple high-energy ion implantations are required to form JFET regions. The JFET region formed by such ion implantation increases the carrier concentration while also increasing the reverse current path, making the semiconductor device susceptible to breakdown and short circuit, thereby affecting the performance of the semiconductor device.

[0003] Based on this, how to increase the carrier concentration of semiconductor devices while reducing the path of reverse current has become an urgent problem to be solved in this field. Summary of the invention

[0004] The present application proposes a semiconductor device and a preparation method, a power module, a power conversion circuit and a vehicle, which are used to increase the carrier concentration of the semiconductor device while reducing the path of the reverse current.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] On the one hand, a semiconductor device is provided, which includes a silicon carbide substrate, a drift layer, a well region, a JFET region and a first region, as well as a gate, a source and a drain. The silicon carbide substrate includes a first surface and a second surface opposite to each other, the drift layer is arranged on the first surface, the well region, the JFET region and the first region are arranged on a side of the drift layer away from the silicon carbide substrate, the gate is arranged on a side of the well region and the JFET region away from the silicon carbide substrate, the source is arranged on a side of the gate away from the silicon carbide substrate and is electrically connected to the first region, and the drain is arranged on the second surface.

[0007] The JFET region includes a first portion close to the silicon carbide substrate and a second portion far from the silicon carbide substrate, and an area of ​​an orthographic projection of the first portion on the silicon carbide substrate is smaller than an area of ​​an orthographic projection of the second portion on the silicon carbide substrate.

[0008] In the above-mentioned semiconductor device, when the semiconductor device is forward-conducted, the reverse current first flows through the first part of the JFET region close to the silicon carbide substrate, and then flows through the second part of the JFET region away from the silicon carbide substrate. Since the area of ​​the positive projection of the first part of the JFET region on the silicon carbide substrate is smaller than the area of ​​the positive projection of the second part of the JFET region on the silicon carbide substrate, the flow path of the reverse current is reduced, resulting in a certain current limiting effect, thereby avoiding damage to the semiconductor device due to excessive reverse current, thereby improving the safety and reliability of the semiconductor device.

[0009] In some embodiments, an orthographic projection of the first portion on the silicon carbide substrate is located within a range of an orthographic projection of the second portion on the silicon carbide substrate.

[0010] In some embodiments, the cross-section shape of the JFET region along the reference plane is an inverted boss, the reference plane is perpendicular to the first surface, the cross-section shape of the well region along the reference plane is a positive boss, and the JFET region and the well region are embedded in each other along a direction parallel to the first surface.

[0011] In some embodiments, the semiconductor device further comprises a second region, the second region comprises a third portion close to the silicon carbide substrate, and a fourth portion away from the silicon carbide substrate, the area of ​​the orthographic projection of the third portion on the silicon carbide substrate is smaller than the area of ​​the orthographic projection of the fourth portion on the silicon carbide substrate. On the other hand, a method for preparing a semiconductor device is provided, the method comprising forming a drift layer on a silicon carbide substrate, the silicon carbide substrate comprising a first surface and a second surface opposite to each other, the drift layer being located on the first surface; forming a well region, a JFET region and a first region, the well region, the JFET region and the first region being located on a side of the drift layer away from the silicon carbide substrate; forming a gate and a source, the gate being located on a side of the well region and the JFET region away from the silicon carbide substrate, the source being located on a side of the gate away from the silicon carbide substrate; forming a drain, the drain being located on the second surface.

[0012] The JFET region includes a first portion close to the silicon carbide substrate and a second portion far from the silicon carbide substrate, and an area of ​​an orthographic projection of the first portion on the silicon carbide substrate is smaller than an area of ​​an orthographic projection of the second portion on the silicon carbide substrate.

[0013] In the process of forming the JFET region in the above-mentioned method for preparing the semiconductor device, a first part of the JFET region is formed which is close to the silicon carbide substrate and a second part of the JFET region which is far from the silicon carbide substrate, and the area of ​​the orthographic projection of the first part on the silicon carbide substrate is smaller than the area of ​​the orthographic projection of the second part on the silicon carbide substrate. The JFET region formed by this preparation method enables the reverse current to first flow through the first part which has a smaller orthographic projection area on the silicon carbide substrate, and then flow through the second part which has a larger orthographic projection area on the silicon carbide substrate when the semiconductor device is forward-conducted. Since the path for the reverse current to flow is reduced, the reverse current is limited, thereby reducing the risk of short circuit and improving the reliability of the semiconductor device.

[0014] In some embodiments, a first ion implantation is performed on the drift layer through a first opening of a first mask plate, and then a sidewall is formed on a sidewall of the first opening, and a second opening is provided inside the sidewall, and a second ion implantation is performed on the drift layer through the second opening to form a well region, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation.

[0015] In some embodiments, a third ion implantation is performed on the drift layer through the third opening of the second mask plate, a sidewall is formed on the sidewall of the third opening, a fourth opening is provided inside the sidewall, and a fourth ion implantation is performed on the drift layer through the fourth opening to form a JFET region. The energy of the third ion implantation is less than the energy of the fourth ion implantation.

[0016] On the other hand, a power module is provided. The power module includes a substrate and a semiconductor device according to any one of the above embodiments. The substrate is used for carrying the semiconductor device.

[0017] In another aspect, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as described in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0018] On the other hand, a vehicle is provided, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0019] The power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above embodiments, which will not be described in detail here. Additional aspects and advantages of the present application will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present application, the actual process of the method, etc.

[0021] Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application;

[0022] Figure 2 A method flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0023] Figure 3 A flow chart of a method for forming a well region provided in an embodiment of the present application;

[0024] Figure 4A to Figure 4F It is a diagram of each step of forming a well region in an embodiment of the present application;

[0025] Figure 5 A flow chart of a method for forming a JFET region provided in an embodiment of the present application;

[0026] Figure 6A to Figure 6F It is a diagram of each step of forming a JFET region in an embodiment of the present application;

[0027] Figure 7 A schematic diagram of the existing JFET region ion implantation;

[0028] Figure 8 A structural diagram of a power module provided in an embodiment of the present application;

[0029] Fig. 9 A structural diagram of a power conversion circuit provided in an embodiment of the present application;

[0030] Fig.10 A structural diagram of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0032] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0033] In the description of the present application, “plurality” means two or more.

[0034] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0035] An embodiment of the present application provides a semiconductor device, which is a silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET). Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0036] See also Figure 1 The semiconductor device 1 includes a silicon carbide substrate 10, a drift layer 11, a well region 12, a JFET region 13, a first region 14, a second region 15, a gate 16, a source 17 and a drain 18. The silicon carbide substrate 10 includes a first surface 100 and a second surface 101 opposite to each other. The drift layer 11 is arranged on the first surface 100. The well region 12, the JFET region 13 and the first region 14 are all arranged on a side of the drift layer 11 away from the silicon carbide substrate 10. The gate 16 is arranged on a side of the well region 12 and the JFET region 13 away from the silicon carbide substrate 10. The source 14 is arranged on a side of the gate 16 away from the silicon carbide substrate 10, and the source 17 is electrically connected to the first region 14. The drain 18 is arranged on the second surface 101 of the silicon carbide substrate 10.

[0037] The above-mentioned well region 12 and the second region 15 have the same conductivity type, and are both of the first conductivity type. The silicon carbide substrate 10, the drift layer 11, the JFET region 13 and the first region 14 have the same conductivity type, and are all of the second conductivity type. For example, P-type ions are injected into both the well region 12 and the second region 15, and the conductivity types of both are P-type. The well region 12 can also be called a "P-type well region (P-well)", and the second region 15 can also be called a "P + The conductivity types of the silicon carbide substrate 10, the drift layer 11, the JFET region 13 and the first region 14 are all N-type. N-type ions are implanted into the first region 14. The first region 14 may also be referred to as “N + contact area".

[0038] The semiconductor device 1 further includes a gate oxide layer 161, a dielectric layer 171 and an ohmic contact layer 19. The gate oxide layer 161 and the ohmic contact layer 19 are arranged on the side of the drift layer 11 away from the silicon carbide substrate 10, and on the side of the gate 16 close to the silicon carbide substrate 10. The gate oxide layer 161 is used to isolate the gate 16 from the drift layer 11 to prevent the semiconductor device 1 from short circuiting. The ohmic contact layer 19 is used to form a low-resistance contact interface, thereby effectively promoting the input and output of current. The dielectric layer 171 is arranged between the gate 16 and the source 17 to isolate the gate 16 from the source 17.

[0039] By transmitting the turn-on voltage to the gate 16 , when the semiconductor device 1 is forward-conducting and the operating current is small, the operating current flows from the source 17 through the ohmic contact layer 19 , the first region 14 , the well region 12 , the JFET region 13 , the drift layer 11 and the silicon carbide substrate 10 to the drain 18 .

[0040] Since the P-type ion concentration in the second region 15 is higher than that in the well region 12, more PN junctions are formed between the second region 15 and the drift layer 11. When the working current is large, the working current flows from the source 17 through the ohmic contact layer 19, the second region 15, the drift layer 11 and the silicon carbide substrate 10 to the drain 18, thereby preventing the large working current from flowing through the well region 12 and protecting the channel in the well region 12.

[0041] Continue to see Figure 1 The JFET region 13 includes a first portion 130 close to the silicon carbide substrate 10 and a second portion 131 away from the silicon carbide substrate 10 , and an area of ​​a positive projection of the first portion 130 on the silicon carbide substrate 10 is smaller than an area of ​​a positive projection of the second portion 131 on the silicon carbide substrate 10 .

[0042] When the semiconductor device 1 is forward-conducted, the reverse current first flows through the first part 130 with a smaller forward projection area, and then flows through the second part 131 with a larger forward projection area, thereby reducing the flow path of the reverse current and limiting the magnitude of the reverse current, thereby reducing the risk of electrical breakdown of the semiconductor device 1 due to excessive reverse current and improving the reliability and safety of the semiconductor device 1.

[0043] In some embodiments, see Figure 1 The orthographic projection of the first part 130 of the JFET region on the silicon carbide substrate 10 is located within the range of the orthographic projection of the second part 131 on the silicon carbide substrate 10, that is, the carrier flow path of the first part 130 completely falls within the range of the carrier flow path of the second part 131, ensuring the maximization of the minimum cross-sectional area of ​​the carrier flow path. The minimum cross-sectional area of ​​the carrier flow path is the cross-sectional area of ​​the first part 130.

[0044] In some embodiments, see Figure 1 , assuming that plane XZ is a reference plane, the reference plane is perpendicular to the first surface 100, the cross-section of the JFET region 13 along the reference plane is an inverted convex platform, the cross-section of the well region 12 along the reference plane is a positive convex platform, and the JFET region 13 and the well region 12 are mutually embedded in a direction parallel to the first surface 100. By mutually embedding the convex platform structures of the JFET region 13 and the well region 12, the contact area of ​​the JFET region 13 and the well region 12 under the same positive projection area is increased, which can effectively reduce the on-resistance of the semiconductor device 1 when it is forward-conducted, thereby enhancing the conductive performance of the semiconductor device 1.

[0045] In some embodiments, see Figure 1 The second region 15 includes a third portion 150 close to the silicon carbide substrate 10 and a fourth portion 151 far from the silicon carbide substrate 10. The area of ​​the orthographic projection of the third portion 150 on the silicon carbide substrate 10 is smaller than the area of ​​the orthographic projection of the fourth portion 151 on the silicon carbide substrate 10. The second region 15 also presents a boss structure because it is mutually embedded with the well region 12 of the boss structure. It is arranged around the JFET region 13, and while improving the contact performance of the semiconductor device 1, it isolates two adjacently arranged semiconductor devices 1.

[0046] The present application also provides a method for preparing a semiconductor device. Figure 2 For a method flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, see Figure 2 , the preparation method comprises the following steps S1 to S4:

[0047] Step S1 : forming a drift layer 11 on a silicon carbide substrate 10 . The silicon carbide substrate 10 includes a first surface 100 and a second surface 101 opposite to each other. The drift layer 11 is located on the first surface 100 .

[0048] Step S2 : forming a well region 12 , a JFET region 13 , a first region 14 and a second region 15 . The well region 12 , the JFET region 13 , the first region 14 and the second region 15 are located on a side of the drift layer 11 away from the silicon carbide substrate 10 .

[0049] Step S3: forming a gate oxide layer 161, a gate 16, a dielectric layer 171, a source 17 and an ohmic contact layer 19. The gate oxide layer 161 and the ohmic contact layer 19 are arranged on the side of the drift layer 11 away from the silicon carbide substrate 10, and on the side of the gate 16 close to the silicon carbide substrate 10. The gate oxide layer 161 is used to isolate the gate 16 from the drift layer 11 to prevent the semiconductor device 1 from short circuiting. The ohmic contact layer 19 is used to form a low-resistance contact interface, thereby effectively promoting the input and output of current. The dielectric layer 171 is arranged between the gate 16 and the source 17 to isolate the gate 16 from the source 17.

[0050] Step S4 : forming a drain 18 , wherein the drain 18 is located on the second surface 101 of the silicon carbide substrate 10 .

[0051] The JFET region 13 includes a first portion 130 close to the silicon carbide substrate 10 and a second portion 131 away from the silicon carbide substrate 10. The area of ​​the orthographic projection of the first portion 130 on the silicon carbide substrate 10 is smaller than the area of ​​the orthographic projection of the second portion 131 on the silicon carbide substrate 10, that is, the JFET region 13 has a boss structure. When the semiconductor device 1 is forward-conducted, the reverse current first flows through the first portion 130 with a smaller orthographic projection area on the silicon carbide substrate 10, and then flows through the second portion 131 with a larger orthographic projection area on the silicon carbide substrate 10. Since the path of the reverse current is reduced, the reverse current is limited, thereby reducing the risk of short circuit and improving the reliability of the semiconductor device 1.

[0052] Figure 3 A flow chart of a method for forming a well region provided in an embodiment of the present application, Figure 4A to Figure 4F Schematic diagram of various steps of forming a well region in an embodiment of the present application.

[0053] For example, in Figure 2 In step S2 shown in FIG. 1 , ion implantation is first performed on a side of the drift layer 11 away from the silicon carbide substrate 10 to form a second region 15, and then a well region 12 is formed. The process of forming the well region 12 is shown in FIG. Figure 3 , comprising the following steps S1 to S4:

[0054] Step S1: Figure 4AAs shown, a first mask plate 20 is formed on a side of the drift layer 11 away from the silicon carbide substrate 10, and a first opening 21 is formed on the first mask plate 20. The process of forming the first opening 21 adopts a mask technology, a layer of mask material is deposited on the first mask plate 20, and a photoresist is coated on the surface of the deposited mask material. After defining the photolithography pattern, photolithography, exposure, and development processes are performed, and the mask material is first etched through the photoresist blocking to form the first opening 21. Exemplarily, the mask material can be silicon dioxide.

[0055] Step S2: Figure 4B As shown, the drift layer 11 is first ion-implanted through the first opening 21 of the first mask plate 20 to obtain the first portion 120 of the target well region 12, wherein the ion implantation is performed vertically to the first surface 100, and illustratively, the implanted ions may be aluminum (Al) or boron (B).

[0056] Step S3: forming a side wall on the side wall of the first opening 21 to form a second opening 22, such as Figure 4C As shown, the process of forming the second opening 22 adopts a multi-tower technology, firstly depositing a layer of mask material on the first opening 21, and then Figure 4D As shown, the mask material at the bottom of the first opening 21 is etched a second time using the anisotropy of the etching process until the mask material at the bottom of the first opening 21 is completely etched away, thereby forming a sidewall on the sidewall of the first opening 21, and a second opening 22 is provided inside the sidewall.

[0057] Step S4: Figure 4E As shown, a second ion implantation is performed on the drift layer 11 through the second opening 22, wherein the ion implantation is performed vertically to the first surface 100. For example, the implanted ion type is the same as the first ion implantation type, and may also be aluminum (Al) or boron (B), to obtain a second portion 121 of the target well region 12, as shown in FIG. Figure 4F As shown, after the second ion implantation is completed, the mask material is etched away to form a complete well region 12 .

[0058] In the above ion implantation process, the energy of the first ion implantation is greater than the energy of the second ion implantation, so that the depth of the first ion implantation is greater than the depth of the second ion implantation. Since the second opening 22 is formed by etching after depositing the mask material on the first opening 21, and Figure 4D It can be obtained that the width of the second opening 22 is smaller than the width of the first opening 21, so the area of ​​the positive projection of the second part 121 formed by the second ion implantation on the silicon carbide substrate 10 is smaller than the area of ​​the positive projection of the first part 120 formed by the first ion implantation on the silicon carbide substrate 10, forming a positive boss-type well region 12.

[0059] Figure 5 A flow chart of a method for forming a JFET region provided in an embodiment of the present application, Figure 6A to Figure 6F Schematic diagram of the steps of forming a JFET region in an embodiment of the present application.

[0060] Exemplarily, after forming the well region 12 in the drift layer 11, ion implantation is performed on a side of the drift layer 11 away from the silicon carbide substrate 10 to form the JFET region 13. The process of forming the JFET region 13 is described in detail in detail. Figure 5 , comprising the following steps S1 to S4:

[0061] Step S1: Fig. 6A As shown, a second mask plate 30 is formed on the side of the drift layer 11 away from the silicon carbide substrate 10, and a third opening 31 is formed on the second mask plate 30. The process of forming the third opening 31 adopts a mask technology, a layer of mask material is deposited on the second mask plate 30, and a photoresist is coated on the surface of the deposited mask material. After defining the photolithography pattern, photolithography, exposure, and development processes are performed. Through the photoresist blocking, the mask material is etched for the third time to form the third opening 31. Exemplarily, the mask material can be silicon dioxide.

[0062] Step S2: Figure 6B As shown, the drift layer 11 is subjected to a third ion implantation through the second opening 31 of the second mask plate 30 to obtain a second portion 131 of the target JFET region 13, wherein the ion implantation is vertical to the first surface 100, and the implanted ion type is N-type. Exemplarily, the implanted ions may be boron (B), phosphorus (P) or arsenic (As).

[0063] Step S3: forming a sidewall on the sidewall of the third opening 31, thereby forming a fourth opening 32, such as Figure 6C As shown, the process of forming the fourth opening 32 adopts a multi-tower technology, firstly depositing a layer of mask material on the third opening 31, and then Fig.6D As shown, the mask material at the bottom of the third opening 31 is etched for the fourth time by utilizing the anisotropy of the etching process until the mask material at the bottom of the third opening 31 is completely etched away, thereby forming a sidewall on the sidewall of the third opening 31, and a fourth opening 32 is formed inside the sidewall.

[0064] Step S4: Fig. 6E As shown, the drift layer 11 is implanted with ions for the fourth time through the fourth opening 32, wherein the ion implantation is performed vertically to the first surface 100, and the implanted ions are of N type. Exemplarily, the implanted ions are the same as the ions of the first ion implantation, and may also be boron (B), phosphorus (P) or arsenic (As), to obtain the first portion 130 of the target JFET region 13, as shown in FIG. Fig. 6FAs shown, after the fourth ion implantation is completed, the mask material is removed by etching to form a complete JFET region 13 .

[0065] In the above ion implantation process, the energy of the third ion implantation is less than that of the fourth ion implantation, that is, the depth of the third ion implantation is less than that of the fourth ion implantation. Fig.6D It can be obtained that the width of the fourth opening 32 is smaller than the width of the third opening 31, and the area of ​​the positive projection of the first part 130 formed by the fourth ion implantation on the silicon carbide substrate 10 is smaller than the area of ​​the positive projection of the second part 131 formed by the third ion implantation on the silicon carbide substrate 10, forming an inverted convex platform type JFET region 13.

[0066] like Figure 3 and Figure 5 The process of forming the well region 12 and the JFET region 13 shown in the figure forms an injection window by means of a mask and a multi-tower double mask, thereby realizing the precise injection of the well region 12 and the JFET region 13, and the well region 12 and the JFET region 13 formed by the injection are mutually embedded, and the contact area between the well region 12 and the JFET region 13 is increased without changing the total area of ​​the well region 12 and the JFET region 13, thereby reducing the resistance of the semiconductor device 1 during forward conduction and improving the overall conductive efficiency of the semiconductor device 1. After the well region 12 and the JFET region 13 are formed, ion implantation is continued on the side of the drift layer 11 away from the silicon carbide substrate 10 to form a first region 14, so as to complete all ion implantations on the side of the drift layer 11 away from the silicon carbide substrate 10, and finally form a second region 15 also having a boss structure. The second region 15 includes a third portion 150 close to the silicon carbide substrate 10 and a fourth portion 151 away from the silicon carbide substrate 10. The area of ​​the orthographic projection of the third portion 150 on the silicon carbide substrate 10 is smaller than the area of ​​the orthographic projection of the fourth portion 151 on the silicon carbide substrate 10. The second region 15 is arranged around the JFET region 13 to isolate two adjacently arranged semiconductor devices 1 while improving the contact performance of the semiconductor device 1.

[0067] Figure 7 Schematic diagram of the existing JFET region ion implantation.

[0068] See also Figure 7 The existing ion implantation in the JFET region adopts direct implantation without using a mask. The implantation window under this implantation method is large, making it difficult to control the edge area of ​​the JFET region 13. The formation method of the JFET region 13 provided in the embodiment of the present application performs ion implantation through the blocking of a mask plate, and only implants ions into the opening part, which solves the above problem well.

[0069] Table 1 is a data table of existing JFET region ion implantation. As shown in Table 1, the ion types of the four implantations are all N-type, the implantation temperature is all 500°C, and the implantation angle is all 0°, that is, the implantation is perpendicular to the first surface. The data in the dosage takes "1.1E+12" as an example, which means that 1.1 times 10 to the power of 12 ions are injected per square centimeter of area.

[0070] Furthermore, the existing implantation scheme uses four ion implantations with high temperature, high dose and high energy to form the JFET region. The ion implantation process for forming the JFET region 13 provided in the embodiment of the present application only requires two ion implantations, which not only reduces the manufacturing cost but also simplifies the operation.

[0071]

[0072] Table 1

[0073] The embodiment of the present application further provides a power module, Figure 8 A structural diagram of a power module provided in an embodiment of the present application.

[0074] See also Figure 8 The power module 4 includes a substrate 41 and the semiconductor device 1 in any of the above embodiments, and the substrate 41 is used to carry the semiconductor device 1 .

[0075] Exemplarily, the power module 4 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0076] The embodiment of the present application also provides a power conversion circuit, Fig. 9 A structural diagram of a power conversion circuit provided in an embodiment of the present application.

[0077] See also Fig. 9 The power conversion circuit 5 includes a circuit board 51 and a semiconductor device 1 in any of the above embodiments. The semiconductor device 1 is electrically connected to the circuit board 51. The power conversion circuit 5 can be used for current conversion, voltage conversion or power factor correction.

[0078] Exemplarily, the power conversion circuit 5 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0079] An embodiment of the present application further provides a vehicle, Fig.10 A structural diagram of a vehicle provided in an embodiment of the present application.

[0080] See also Fig.10 The vehicle 6 includes a load 61 and the power conversion circuit 5 in the above embodiment, and the power conversion circuit 5 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 61 to power the load 61.

[0081] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: A silicon carbide substrate including a first surface and a second surface opposite to each other; A drift layer is disposed on the first surface; The well region, the JFET region, the first region and the second region are arranged on a side of the drift layer away from the silicon carbide substrate; A gate is arranged on a side of the well region and the JFET region away from the silicon carbide substrate; A source electrode, disposed on a side of the gate away from the silicon carbide substrate and electrically connected to the first region; A drain electrode is disposed on the second surface; The JFET region includes a first portion close to the silicon carbide substrate and a second portion away from the silicon carbide substrate, and an area of ​​an orthographic projection of the first portion on the silicon carbide substrate is smaller than an area of ​​an orthographic projection of the second portion on the silicon carbide substrate; The second region includes a third portion close to the silicon carbide substrate and a fourth portion far from the silicon carbide substrate, and an area of ​​an orthographic projection of the third portion on the silicon carbide substrate is smaller than an area of ​​an orthographic projection of the fourth portion on the silicon carbide substrate.

2. The semiconductor device according to claim 1, wherein: An orthographic projection of the first portion on the silicon carbide substrate is located within a range of an orthographic projection of the second portion on the silicon carbide substrate.

3. The semiconductor device according to claim 1, wherein: The cross-section of the JFET region along a reference plane is in the shape of an inverted convex platform, and the reference plane is perpendicular to the first surface; The shape of the cross section of the well region along the reference plane is a positive convex platform; Along a direction parallel to the first surface, the JFET region and the well region are embedded with each other.

4. A method for preparing a semiconductor device, characterized in that: For preparing a semiconductor device according to any one of claims 1 to 3, the preparation method comprises: forming a drift layer on a silicon carbide substrate, wherein the silicon carbide substrate comprises a first surface and a second surface opposite to each other, and the drift layer is located on the first surface; forming a well region, a JFET region, a first region, and a second region, wherein the well region, the JFET region, and the first region are located on a side of the drift layer away from the silicon carbide substrate; forming a gate and a source, wherein the gate is located on a side of the well region and the JFET region away from the silicon carbide substrate; and the source is located on a side of the gate away from the silicon carbide substrate; forming a drain electrode, wherein the drain electrode is located on the second surface; The JFET region includes a first portion close to the silicon carbide substrate and a second portion away from the silicon carbide substrate, and an area of ​​an orthographic projection of the first portion on the silicon carbide substrate is smaller than an area of ​​an orthographic projection of the second portion on the silicon carbide substrate; The second region includes a third portion close to the silicon carbide substrate and a fourth portion far from the silicon carbide substrate, and an area of ​​an orthographic projection of the third portion on the silicon carbide substrate is smaller than an area of ​​an orthographic projection of the fourth portion on the silicon carbide substrate.

5. The preparation method according to claim 4, characterized in that: The forming of the well region comprises: forming a first mask plate on a side of the drift layer away from the silicon carbide substrate, wherein the first mask plate has a first opening; Performing a first ion implantation into the drift layer through the first opening; A side wall is formed on the side wall of the first opening, and a second opening is formed on the inner side of the side wall; performing a second ion implantation into the drift layer through the second opening to form the well region; Wherein, the energy of the first ion implantation is greater than the energy of the second ion implantation.

6. The preparation method according to claim 4, characterized in that: The JFET region is formed, comprising: forming a second mask plate on a side of the drift layer away from the silicon carbide substrate, wherein the second mask plate has a third opening; Performing a third ion implantation on the drift layer through the third opening to obtain the second portion; A side wall is formed on the side wall of the third opening, and a fourth opening is formed on the inner side of the side wall; Performing a fourth ion implantation on the drift layer through the fourth opening to obtain the first portion to form the JFET region; Wherein, the energy of the third ion implantation is less than the energy of the fourth ion implantation.

7. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 3, wherein the substrate is used to carry the semiconductor device.

8. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is electrically connected to the circuit board.

9. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 8, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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