Micro-led, micro-led array panel and manufacturing method thereof

Abstract

A micro-LED includes a first-type semiconductor layer (110), a first-type cap layer (114), a light-emitting layer (130), a second-type cap layer (124), and a second-type semiconductor layer (120), wherein the first-type semiconductor layer (110) includes a mesa structure (111), a trench (112) extending upward into at least a portion of the first-type cap layer (114) and formed around the mesa structure (111), and an ion implantation fence (113) separated from the mesa structure (111), and the ion implantation fence (113) is formed around the trench (112). The ion implantation fence (113) has a higher electrical resistance than the mesa structure (111), and the ion implantation fence (113) can absorb light from the mesa structure (111).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a light emitting diode, and more particularly to a micro light emitting diode (LED), a micro LED array panel, and a method of manufacturing the same. BACKGROUND

[0002] Inorganic micro-pixel light emitting diodes (also referred to as micro light emitting diodes, micro-LEDs, or p-LEDs) are increasingly important due to their use in various applications including self-emissive micro-displays, visible light communication, and optogenetics. Micro-LEDs exhibit higher output performance than conventional LEDs due to better strain relaxation, improved light extraction efficiency, and uniform current spreading. Micro-LEDs also exhibit improved thermal effects, fast response rates, greater operating temperature range, higher resolution, color gamut, and contrast, and lower power consumption and can operate at higher current densities compared to conventional LEDs.

[0003] Inorganic micro-LEDs are typically III-V epitaxial layers formed into multiple mesas. Spaces are formed between adjacent micro-LEDs in conventional micro-LED structures to avoid diffusion of carriers in the epitaxial layer from one mesa to an adjacent mesa. However, the spaces formed between adjacent micro-LEDs can reduce the effective light emitting area and lower light extraction efficiency. If no spaces are formed between adjacent micro-LEDs, the effective light emitting area will increase and carriers in the epitaxial layer will laterally diffuse to adjacent mesas, which reduces the light emitting efficiency of the micro-LEDs. Furthermore, if no spaces are formed between adjacent mesas, cross-talk between adjacent micro-LEDs will occur, which will interfere with the operation of the LEDs.

[0004] However, smaller micro-LEDs with higher current densities will experience red-shift, lower maximum efficiency, and non-uniform emission at high current densities due to manufacturing process damage that causes degraded electrical injection. Furthermore, peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) are greatly reduced as chip size is reduced. Reduced EQE occurs due to non-radiative recombination caused by etch damage, while reduced IQE is due to poor current injection and electron leakage current of the micro-LEDs.

[0005] The above discussion is merely provided for help of understanding technical problems overcome by the present disclosure and does not constitute an acknowledgement that the above is prior art. SUMMARY

[0006] Embodiments of the present disclosure provide a micro-LED. The micro-LED includes: a first type semiconductor layer; and a light emitting layer formed on the first type semiconductor layer; a first type cap layer formed at a bottom surface of the light emitting layer and between the first type semiconductor layer and the light emitting layer; wherein the first type semiconductor layer includes a mesa structure, a trench extending upward through the first type semiconductor layer and upward into at least a portion of the first type cap layer, and an ion implantation fence separated from the mesa structure; and the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; wherein a resistance of the ion implantation fence is higher than a resistance of the mesa structure.

[0007] Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method includes: providing an epitaxial structure, wherein the epitaxial structure includes, in order from top to bottom, a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a bottom contact on the mesa structure; and performing an ion implantation process into the fence to form an ion implantation fence.

[0008] Embodiments of the present disclosure provide a micro-LED. The micro-LED includes: a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light emitting layer formed on the first type cap layer; a second type cap layer formed on the light emitting layer; a second type semiconductor layer formed on the second type cap layer; and an integrated circuit (IC) backplane formed at a bottom surface of the first type semiconductor layer; wherein the second type semiconductor layer includes a mesa structure, a trench extending downward through the second type semiconductor layer and downward into at least a portion of the second type cap layer, and an ion implantation fence separated from the mesa structure; the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; wherein a resistance of the ion implantation fence is higher than a resistance of the mesa structure; wherein a conductivity type of the first type semiconductor layer is different from a conductivity type of the second type semiconductor layer.

[0009] Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method comprises: providing an epitaxial structure, wherein the epitaxial structure comprises, in order from top to bottom, a first-type semiconductor layer, a first-type cap layer, a light-emitting layer, a second-type cap layer, and a second-type semiconductor layer; bonding the epitaxial structure with an integrated circuit (IC) backplane; patterning the second-type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a top contact on the mesa structure; performing an ion implantation process into the fence; and depositing a top conductive layer on a top surface of the second-type semiconductor layer, on the top contact, and in the trench.

[0010] Embodiments of the present disclosure provide a micro-LED. The micro-LED comprises: a first-type semiconductor layer; a first-type cap layer formed on the first-type semiconductor layer; a light-emitting layer formed on the first-type cap layer; a second-type cap layer formed on the light-emitting layer; and a second-type semiconductor layer formed on the second-type cap layer; wherein the first-type semiconductor layer comprises a first mesa structure, a first trench extending upwardly through the first-type semiconductor layer and upwardly into at least a portion of the first-type cap layer, and a first ion-implanted fence separated from the first mesa structure and formed around the first trench, and the first trench is formed around the first mesa structure; and the first ion-implanted fence has a higher electrical resistance than the first mesa structure; and the second-type semiconductor layer comprises a second mesa structure, a second trench, and a second ion-implanted fence separated from the second mesa structure and formed around the second trench, and the second trench is formed around the second mesa structure; and the second ion-implanted fence has a higher electrical resistance than the second mesa structure; wherein a conductive type of the first-type semiconductor layer is different from a conductive type of the second-type semiconductor layer.

[0011] Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method comprises: process I comprising patterning a first-type semiconductor layer and implanting first ions into the first-type semiconductor layer; and process II comprising patterning a second-type semiconductor layer and implanting second ions into the second-type semiconductor layer.

[0012] Embodiments of the present disclosure provide a micro-LED array panel. The micro-LED array panel comprises a plurality of the above-described micro-LEDs. BRIEF DESCRIPTION OF DRAWINGS

[0013] Embodiments and various aspects of the present disclosure are illustrated in the detailed description and drawings below. Various features shown in the drawings are not drawn to scale.

[0014] FIGS. 1A-1F is a structural diagram illustrating a side cross-sectional view of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0015] FIG. 2 is a structural diagram illustrating a bottom view of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0016] FIG. 3 is a structural diagram illustrating a side cross-sectional view of another variant of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0017] FIG. 4 is a structural diagram illustrating a side cross-sectional view of another variant of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0018] FIG. 5 is a flowchart illustrating a method for manufacturing a first exemplary micro-LED according to some embodiments of the present disclosure.

[0019] FIGS. 6A-6J is a structural diagram illustrating a side cross-sectional view of a micro-LED manufacturing process at each step of the method shown in FIG. 5

[0020] FIG. 7 is a structural diagram illustrating a side cross-sectional view of a micro-LED of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0021] FIG. 8 is a structural diagram illustrating a bottom view of a micro-LED of a first exemplary micro-LED according to some embodiments of the present disclosure. FIG. 7

[0022] FIG. 9 is a structural diagram illustrating a side cross-sectional view of a micro-LED of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0023] FIGS. 10A-10F is a structural diagram illustrating a side cross-sectional view of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0024] FIG. 11 is a structural diagram illustrating a top view of a second exemplary micro-LED according to some embodiments of the present disclosure.

[0025] FIG. 12A and FIG. 12B ​​is a structural diagram illustrating a side cross-sectional view of another variant of the second exemplary micro-LED according to some embodiments of the present disclosure.

[0026] FIG. 13 is a structural diagram illustrating a side cross-sectional view of another variant of the second exemplary micro-LED according to some embodiments of the present disclosure.

[0027] FIG. 14 is a flowchart illustrating a method for fabricating the second exemplary micro-LED according to some embodiments of the present disclosure.

[0028] FIGS. 15A-15F is a structural diagram illustrating a side cross-sectional view of the micro-LED fabrication process at step 2105 of the method shown in FIG. 14

[0029] FIG. 16 is a structural diagram illustrating a side cross-sectional view of the micro-LED fabrication process at step 2110 of the method shown in

[0030] FIG. 17 is a structural diagram illustrating a top view of the micro-LEDs in FIG. 16

[0031] FIG. 18 is a structural diagram illustrating a side cross-sectional view of the micro-LED fabrication process at step 2113 of the method shown in FIG. 12B

[0032] FIGS. 19A-19F is a structural diagram illustrating a side cross-sectional view of various different variants of the third exemplary micro-LED according to some embodiments of the present disclosure.

[0033] FIG. 20 is a structural diagram illustrating a side cross-sectional view of another variant of the third exemplary micro-LED according to some embodiments of the present disclosure.

[0034] FIG. 21 is a flowchart illustrating a method for fabricating the third exemplary micro-LED according to some embodiments of the present disclosure.

[0035] FIGS. 22A-22D is a structural diagram illustrating a side cross-sectional view of the micro-LED fabrication process at step 2105 of the method shown in FIG. 21

[0036] FIG. 23A and FIG. 23B ​​​​is a structural diagram illustrating a side cross-sectional view of another variant of a third exemplary micro-LED according to some embodiments of the present disclosure.

[0037] FIG. 24 is a structural diagram illustrating a side cross-sectional view of a micro-LED adjacent to the micro-LED in FIG. 23A DETAILED DESCRIPTION

[0038] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers represent the same or similar elements between the several drawings. The implementation set forth in the following description of exemplary embodiments does not represent all of the implementations consistent with the present disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects set forth in the appended claims. Certain aspects of the present disclosure are described in more detail below. If there is a contradiction between the claims and the

[0039] The present disclosure provides a micro-LED which can avoid non-radiative recombination at the sidewall of a mesa according to the structure of a semiconductor layer and a light-emitting layer formed continuously. In addition, the space between adjacent mesas can be greatly reduced due to ion implantation fences compared to conventional micro-LEDs. Therefore, the integration of micro-LEDs in a chip is increased, and the effective light-emitting efficiency is improved. In addition, the micro-LED provided by the present disclosure can also increase the effective light-emitting area and improve the image quality.

[0040] Embodiment 1

[0041] FIGS. 1A-1F is a structural diagram illustrating a side cross-sectional view of various different variants of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0042] Reference FIGS. 1A-1F The micro-LED includes a first-type semiconductor layer 110, a first-type cap layer 114, a light-emitting layer 130, a second-type cap layer 124, and a second-type semiconductor layer 120. The light-emitting layer 130 is formed on the first-type cap layer 114 above the first-type semiconductor layer 110, and the second-type semiconductor layer 120 is formed on the second-type cap layer 124 above the light-emitting layer 130. The thickness of the first-type semiconductor layer 110 is greater than the thickness of the second-type semiconductor layer 120.

[0043] ​The first type semiconductor layer 110 has a different conductivity type than the second type semiconductor layer 120. In some embodiments, the first type semiconductor layer 110 has a P-type conductivity and the second type semiconductor layer 120 has an N-type conductivity. In some embodiments, the second type semiconductor layer 120 has a P-type conductivity and the first type semiconductor layer 110 has an N-type conductivity. For example, the material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The first type cap layer 114 has the same conductivity type as the first type semiconductor layer 110 and the second type cap layer 124 has the same conductivity type as the second type semiconductor layer 120.

[0044] The first type semiconductor layer 110 includes a mesa structure 111, a trench 112, and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are annular around the mesa structure 111.

[0045] The ion implantation fence 113 includes a light absorbing material for absorbing light from the mesa structure 111. The light absorbing material has the same conductivity type as the first type semiconductor layer 110. Preferably, the light absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. Additionally, the ion implantation fence 113 is formed at least by implanting ions into a fence formed by the first type semiconductor layer 110. Preferably, the type of ions implanted into the fence is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0046] Furthermore, the width of the ion implantation fence 113 is no more than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is no more than 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is no more than 200 nm, the diameter of the mesa structure 111 is no more than 2500 nm, and the thickness of the first type semiconductor layer 110 is no more than 300 nm.

[0047] In some embodiments, the width of the trench 112 is no more than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the trench 112 is no more than 10% of the diameter of the mesa structure 111. Preferably, the width of the first trench 112 is no more than 200 nm.

[0048] In some embodiments, the top surface of the ion implantation fence 113 is lower than or aligned with the top surface of the first type semiconductor layer 110. Thus, the ion implantation fence 113 can contact the first type cap layer 114, but cannot contact the light emitting layer 130. The top surface of the ion implantation fence 113 can be formed at any position within the first type semiconductor layer 110. As shown in FIG. 1A , the trench 112 extends upward through the first type semiconductor layer 110 and into the interior of the first type cap layer 114. The top surface of the trench 112 is higher than the top surface of the first type semiconductor layer 110. The top surface of the ion implantation fence 113 is lower than the top surface of the trench 112. FIG. 2 is a structural diagram showing a bottom view of a first exemplary micro-LED as shown in FIG. 1A . FIG. 2 shows a bottom view of the first type semiconductor layer 110, in which the ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The ion implantation fence 113 is formed around the trench, and the trench is formed around the mesa structure 111. Since the trench extends upward through the first type semiconductor layer 110 and into the interior of the first type cap layer 114, the first type cap layer 114 can be seen through the trench in the bottom view.

[0049] In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110 and the first type cap layer 114 and reaches the light emitting layer 130. In some embodiments, with reference to FIG. 1B , the trench 112 extends upward through the first type semiconductor layer 110 and the first type cap layer 114, and also extends into the interior of the light emitting layer 130. In some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, and the light emitting layer 130. Furthermore, in some embodiments, the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, and the light emitting layer 130, and also extends upward into the interior of the second type cap layer 124. Furthermore, in some embodiments, with reference to FIG. 1C , the trench 112 extends upward through the first type semiconductor layer 110, the first type cap layer 114, the light emitting layer 130, and the second type cap layer 124, and also extends upward into the interior of the second type semiconductor layer 120.

[0050] With reference toFIG. 1C In some embodiments, the top surface of the ion implantation fence 113 is aligned with the top surface of the first-type semiconductor layer 110.

[0051] In addition, the bottom surface of the ion implantation fence 113 can be formed at any position. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first-type semiconductor layer 110. Referring to FIG. 1D In some embodiments, the bottom surface of the ion implantation fence 113 is higher than the bottom surface of the first-type semiconductor layer 110. Referring to FIG. 1E In some embodiments, the bottom surface of the ion implantation fence 113 is lower than the bottom surface of the first-type semiconductor layer 110.

[0052] In some embodiments, as FIG. 1F shown, the mesa structure 111 includes a stepped structure 111a. In some embodiments, the mesa structure 111 can have one or more stepped structures.

[0053] FIG. 3 is a structural diagram showing a side cross-sectional view of another variant of a first exemplary micro-LED according to some embodiments of the present disclosure. As FIG. 3 shown, the micro-LED further includes a bottom isolation layer 140 filled in the trench 112. Preferably, the material of the bottom isolation layer 140 is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

[0054] In the present embodiment, an integrated circuit (IC) backplane 190 is formed underneath the first-type semiconductor layer 110 and is electrically connected with the first-type semiconductor layer 110 via a connection structure 150. As FIG. 3 shown, the connection structure 150 is a connection pillar.

[0055] The micro-LED further includes a bottom contact 160. The bottom contact 160 is formed at the bottom of the first-type semiconductor layer 110. The upper surface of the connection structure 150 is connected with the bottom contact 160, and the bottom surface of the connection structure 150 is connected with the IC backplane 190.

[0056] Referring to FIG. 3In some embodiments, the micro-LED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on top of the second-type semiconductor layer 120. The top conductive layer 170 is formed on top of the second-type semiconductor layer 120 and the top contact 180. The conductive type of the top contact 180 is the same as the conductive type of the second-type semiconductor layer 120. For example, in some embodiments, the conductive type of the second-type semiconductor layer 120 is N-type, and the conductive type of the top contact 180 is N-type. In some embodiments, the conductive type of the second-type semiconductor layer 120 is P-type, and the conductive type of the top contact 180 is P-type. The top contact 180 is made of a metal or a metal alloy, such as AuGe, AuGeNi, etc. The top contact 180 is used to form an ohmic contact between the top conductive layer 170 and the second-type semiconductor layer 120 to optimize the electrical properties of the micro-LED. The diameter of the top contact 180 is about 20-50 nm, and the thickness of the top contact 180 is about 10-20 nm.

[0057] FIG. 4 is a structural diagram showing a side cross-sectional view of another variant of the first exemplary micro-LED according to some embodiments of the present disclosure. As shown, the connecting structure 150 is a metal bonding layer for bonding the micro-LED with an IC backplane 190. In addition, in this variant, the bottom contact 160 is a bottom contact layer. FIG. 4

[0058] FIG. 5 is a flowchart showing a method 500 for fabricating the first exemplary micro-LED (e.g., the micro-LED shown in FIG. 3 The method 500 for fabricating the micro-LED includes steps 501-510. FIGS. 6A-6J is a structural diagram showing a side cross-sectional view of the micro-LED fabrication process at each step (i.e., steps 501-510) corresponding to the method 500 shown in FIG. 5

[0059] Referring to FIG. 5 and FIGS. 6A-6J In step 501, an epitaxial structure is provided. As shown in FIG. 6A The epitaxial structure includes, in order from top to bottom, a first-type semiconductor layer 610, a first-type cap layer 614, a light-emitting layer 630, a second-type cap layer 624, and a second-type semiconductor layer 620. The epitaxial structure is grown on a substrate 600. The substrate 600 can be GaN, GaAs, etc.

[0060] In step 502: referring to FIG. 6B ​​, the first-type semiconductor layer 610 is patterned to form the mesa structure 611, the trench 613, and the fence 613'.

[0061] Step 502 can further include etching the first-type semiconductor layer 610, the first-type cap layer 614, and the light-emitting layer 630 in sequence, and stopping etching on the second-type cap layer 624. As shown, the bottom surface of the first trench 612 contacts and is located on the second-type cap layer 624. The first-type semiconductor layer 610 is etched by a conventional dry etching process, such as a plasma etching process, which can be understood by those skilled in the art. FIG. 6B

[0062] In some embodiments, step 502 can include etching the first-type semiconductor layer, the first-type cap layer, and the light-emitting layer in sequence, and stopping etching in the light-emitting layer. For example, referring back to FIG. 1B , the top surface of the trench 121 contacts and is located in the light-emitting layer 130.

[0063] In some embodiments, step 502 can include etching the first-type semiconductor layer, the first-type cap layer, the light-emitting layer, the second-type cap layer, and the second-type semiconductor layer in sequence, and stopping etching in the second-type semiconductor layer. For example, referring back to FIG. 1C , the top surface of the trench 121 contacts and is located in the second-type semiconductor layer 120.

[0064] Referring back to FIG. 1A , the first-type semiconductor layer 110 is etched, and etching is stopped in the first-type cap layer 114 to avoid the light-emitting layer 130 being etched in the patterning process. The bottom of the trench 112 does not reach the light-emitting layer 130. The first-type semiconductor layer 110 is etched by a conventional dry etching process, such as a plasma etching process, which can be understood by those skilled in the art.

[0065] In step 503: referring back to FIG. 6C , a bottom contact 660 is deposited on the mesa structure 611.

[0066] Before depositing the bottom contact 660, a first protection mask (not shown) is used to protect the area where the bottom contact 660 will not be formed. Then, the material of the bottom contact 660 is deposited on the first protection mask and on the first-type semiconductor layer 610 by a conventional vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. After the deposition process, the first protection mask is removed from the first-type semiconductor layer 610, and the material on the first protection mask is also removed together with the first protection mask to form the bottom contact 660 on the mesa structure 611. ​

[0067] In step 504: referring to FIG. 6D , an ion implantation process is performed into the fence 613'. The arrow shows the direction of the ion implantation process.

[0068] In combination FIG. 6C , ions are implanted into the fence 613' (as shown in FIG. 6C ) by an ion implantation process to form an ion implanted fence 613 (as shown in FIG. 6D ), as shown in FIG. 6D . Before the ion implantation process, a second protective mask (not shown) is formed on the area to be implanted with ions. Then, ions are implanted into the exposed fence 613'. Subsequently, the second protective mask is removed by a conventional chemical etching process, which can be understood by those skilled in the art. Preferably, the implantation energy is 0 Kev to 500 Kev, and the implantation dose is 1E10 to 9E17.

[0069] In step 505: referring to FIG. 6E , a bottom isolation layer 640 is deposited on the entire substrate 600. That is, the bottom isolation layer 640 is deposited on the first type semiconductor layer 610. The first type semiconductor layer 610 and the bottom contact 660 are covered by the bottom isolation layer 640, and the trench 612 is filled with the bottom isolation layer 640. The bottom isolation layer 640 is deposited by a conventional chemical vapor deposition process.

[0070] As shown in FIG. 6E , the bottom isolation layer 640 fills into the trench 612. Therefore, the bottom isolation layer 640 is formed on the sidewalls and the bottom of the trench 612. The bottom isolation layer 640 is also formed in the first trench 612 at the sidewalls of the first mesa structure 611, the first type semiconductor layer 610, the first type cap layer 614, and the light emitting layer 630, and on the surface of the second type cap layer 624 in the first trench 612. In some embodiments, referring back to FIG. 1A , the bottom isolation layer can be formed at the sidewalls of the mesa structure 111, the first type semiconductor layer 110, and the ion implanted fence 113, and at the surface of the first type cap layer 114 in the trench 112. In some embodiments, referring back to FIG. 1B , the bottom isolation layer can be formed in the first trench 112 at the sidewalls of the mesa structure 111, the first type semiconductor layer 110, the ion implanted fence 113, and the first type cap layer 114, and at the surface within the light emitting layer 130 in the first trench 112. In some embodiments, referring back to FIG. 1CA bottom isolation layer can be formed in the trench 112 at the sidewalls of the mesa structure 111, the ion implantation fence 113, the first-type cap layer 114, the light emitting layer 130, and the second-type cap layer 124, and at the surface within the second-type semiconductor layer 120 in the trench 112.

[0071] In step 506: referring to FIG. 6F The bottom isolation layer 640 is patterned to expose the bottom contact 660. The bottom isolation layer 640 is etched by a photo-etching process and a dry etching process.

[0072] In step 507: referring to FIG. 6G A metal material 650' is deposited over the entire substrate 600. That is, the metal material 650' is deposited on the bottom isolation layer 640 and the bottom contact 660. The metal material is deposited by a conventional physical vapor deposition method.

[0073] In step 508: referring to FIG. 6H A top of the metal material is ground to a top of the bottom isolation layer 640 to form a connection structure 650, such as a connection pillar. In some embodiments, the metal material is ground by a chemical mechanical polishing (CMP) process.

[0074] In step 509: referring to FIG. 6I The connection pillar 650 is bonded with an IC backplane 690. First, the epitaxial structure is flipped. Then, the connection pillar 650 is bonded with a contact pad of the IC backplane 690 by a metal bonding process. Then, the substrate 600 is removed by a conventional separation method, such as a laser lift-off method, or a chemical etching method. The arrow shows a removal direction of the substrate 600.

[0075] In step 510: referring to FIG. 6J The top contact 680 and the top conductive layer 670 can be sequentially deposited on the second-type semiconductor layer 620 by a conventional vapor deposition method.

[0076] Some embodiments of the present disclosure further provide a micro LED array panel. The micro LED array panel includes a plurality of micro LEDs as described above and shown in FIGS. 1A-1F 、 FIG. 3 and FIG. 4 These micro LEDs can be arranged into an array in the micro LED array panel.

[0077] FIG. 7 is a structural diagram showing a side cross-sectional view of adjacent micro LEDs of a first exemplary micro LED according to some embodiments of the present disclosure. As FIG. 7As shown, the micro LED array panel includes a first type semiconductor layer 710 formed continuously in the micro LED array panel, a first type cap layer 714 formed continuously on the first type semiconductor layer 710, a light emitting layer 730 formed continuously on the first type cap layer 714, a second type cap layer 724 formed continuously on the light emitting layer 730, and a second type semiconductor layer 720 formed continuously on the second type cap layer 724.

[0078] The first type semiconductor layer 710 has a different conductivity type than the second type semiconductor layer 720. For example, in some embodiments, the first type semiconductor layer 710 has a P-type conductivity and the second type semiconductor layer 720 has an N-type conductivity. In some embodiments, the second type semiconductor layer 720 has a P-type conductivity and the first type semiconductor layer 710 has an N-type conductivity. The first type semiconductor layer 710 has a greater thickness than the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The first type cap layer 714 has the same conductivity type as the first type semiconductor layer 710 and the second type cap layer 724 has the same conductivity type as the second type semiconductor layer 720.

[0079] The first type semiconductor layer 710 includes a plurality of mesa structures 711, a plurality of trenches 712, and a plurality of ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fence 713 is aligned with or lower than the top surface of the first type semiconductor layer 710. Thus, the ion implantation fence 713 cannot reach the light emitting layer 730. The top of the ion implantation fence 713 can be formed at any location. In addition, the bottom surface of the ion implantation fence 713 can be formed at any location. The relationship of the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, and the top surface of the trench 712 can be seen in the micro LED shown in FIG. 1F, which will not be further described here. In addition, the relationship of the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be seen in the micro LED shown in FIG. 1G, which will not be further described here. FIGS. 1A-1E The relationship of the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, and the top surface of the trench 712 can be seen in the micro LED shown in FIG. 1F, which will not be further described here. In addition, the relationship of the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be seen in the micro LED shown in FIG. 1G, which will not be further described here. FIG. 1E The relationship of the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, and the top surface of the trench 712 can be seen in the micro LED shown in FIG. 1F, which will not be further described here. In addition, the relationship of the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be seen in the micro LED shown in FIG. 1G, which will not be further described here.

[0080] FIG. 8 This illustrates some embodiments according to this disclosure. FIG. 7 A structural diagram of the bottom view of adjacent micro-LEDs. (See diagram below.) FIG. 8 As shown, an ion implantation fence 713 is formed around a trench 712 and between adjacent mesa structures 711. Furthermore, in each micro-LED, an ion implantation fence 713 is formed around a trench 712, and the trench 712 is formed around a mesa structure 711. The resistance of the ion implantation fence 713 is higher than the resistance of the mesa structure 711. Since the trench extends upward through the first type semiconductor layer 710 and through the first type cap layer 714, the light-emitting layer 730 can be seen through the trench in the bottom view.

[0081] In some embodiments, the space between adjacent sidewalls of adjacent mesa structures of mesa structure 711 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of mesa structure 711 is no greater than 50% of the diameter of mesa structure 711. In some embodiments, the space between adjacent sidewalls of mesa structure 711 is no greater than 30% of the diameter of mesa structure 711. Preferably, the space between adjacent sidewalls of mesa structure 711 is no greater than 600 nm. Additionally, in some embodiments, the width of ion implantation fence 713 can be adjusted. For example, the width of ion implantation fence 713 may be no greater than 50% of the diameter of mesa structure 711. In some embodiments, the width of ion implantation fence 713 may be no greater than 10% of the diameter of mesa structure 711. Preferably, in a micro-LED array panel, the width of ion implantation fence 713 is no greater than 200 nm.

[0082] FIG. 9 This is a structural diagram showing a side cross-sectional view of adjacent microLEDs of a first example microLED in a microLED array panel according to some embodiments of this disclosure. FIG. 9 As shown, the micro-LED array panel further includes a bottom isolation layer 940 formed on a first-type semiconductor layer 910 and filled in a trench 912. Preferably, in some embodiments, the material of the bottom isolation layer 940 is SiO2 or SiN. x Alternatively, it may contain one or more of Al2O3, AlN, HfO2, TiO2, or ZrO2. Furthermore, the IC backplane 990 is continuously formed beneath the first type semiconductor layer 910 and electrically connected to the first type semiconductor layer 910 via a connection structure 950. The micro-LED array panel further includes a bottom contact 960 formed at the bottom of the first type semiconductor layer 910. Further details of the bottom isolation layer 940, IC backplane 990, bottom contact 960, and connection structure 950 are provided in [details omitted]. FIG. 3 and FIG. 4The micro-LEDs in the micro-LED array panel are shown as corresponding to the isolation layer 140, the IC backplane 190, the bottom contact 160, and the connection structure 150, which will not be further described.

[0083] In the present embodiment, the micro-LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on top of the second-type semiconductor layer 920. The top conductive layer 970 is formed on top of the second-type semiconductor layer 920 and the top contact 980. The conductive type of the top contact 980 is the same as the conductive type of the second-type semiconductor layer 920. For example, in some embodiments, the conductive type of the second-type semiconductor layer 920 is N-type, and the conductive type of the top contact 980 is N-type. In some embodiments, the conductive type of the second-type semiconductor layer 920 is P-type, and the conductive type of the top contact 980 is P-type. The top contact 980 is made of a metal or a metal alloy, such as AuGe, AuGeNi, etc. The top contact 980 is used to form an ohmic contact between the top conductive layer 970 and the second-type semiconductor layer 920 to optimize the electrical properties of the micro-LED. The diameter of the top contact 980 is about 20 nm to 50 nm, and the thickness of the top contact 980 is about 10 nm to 20 nm.

[0084] The micro-LED array panel can be manufactured by the method 500 as shown in FIG. 5 , which will not be further described.

[0085] Embodiment 2

[0086] FIGS. 10A-10F is a structural diagram showing side cross-sectional views of various different variants of a second exemplary micro-LED according to some embodiments of the present disclosure. As FIG. 10AAs shown, the micro-LED includes a first-type semiconductor layer 1010, a first-type cap layer 1014, a light-emitting layer 1030, a second-type cap layer 1024, and a second-type semiconductor layer 1020. The conduction type of the first-type semiconductor 1010 is different from the conduction type of the second-type semiconductor layer 1020. For example, the conduction type of the first-type semiconductor 1010 is P-type, and the conduction type of the second-type semiconductor layer 1020 is N-type. The thickness of the first-type semiconductor layer 1010 is greater than the thickness of the second-type semiconductor layer 1020. The material of the first-type semiconductor layer 1010 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second-type semiconductor layer 1020 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The conduction type of the first-type cap layer 1014 is the same as the conduction type of the first-type semiconductor layer 1010, and the conduction type of the second-type cap layer 1024 is the same as the second-type semiconductor layer 1020.

[0087] The second-type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is aligned with or higher than the bottom surface of the second-type semiconductor layer 1020. Therefore, the ion implantation fence 1023 can reach the second-type cap layer 1024, but cannot reach the light-emitting layer 1030. The bottom surface of the ion implantation fence 1023 can be formed at any position. In addition, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.

[0088] The ion implantation fence 1023 includes a light-absorbing material for absorbing light from the mesa structure 1021. The conduction type of the light-absorbing material is the same as the conduction type of the second-type semiconductor layer 1020. Preferably, the light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN. In addition, the ion implantation fence 1023 is formed at least by implanting ions into the second-type semiconductor layer 1020. Preferably, the type of ions implanted into the second-type semiconductor layer 1020 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0089] Furthermore, the width of the ion implantation fence 1023 can be adjusted. For example, in some embodiments, the width of the ion implantation fence 1023 is no greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is no greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is no greater than 200 nm. The diameter of the mesa structure 1021 is no greater than 2500 nm. The thickness of the second type semiconductor layer 1020 is no greater than 100 nm.

[0090] In some embodiments, the width of the trench 1022 is no greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the trench 1022 is no greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the trench 1022 is no greater than 200 nm.

[0091] There is no limitation on the depth of trench 1022. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and into the interior of the second type cap layer 1024. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and the second type cap layer 1024 and reach the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and the second type cap layer 1024 and into the interior of the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020, the second type cap layer 1024, and the light-emitting layer 1030. Furthermore, in some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020, the second type cap layer 1024, and the light-emitting layer 1030 and into the interior of the first type cap layer 1014. Furthermore, in some embodiments, the trench 1022 may extend downward through the second type semiconductor layer 1020, the second type cap layer 1024, the light-emitting layer 1030 and the first type cap layer 1014 and extend downward into the interior of the first type semiconductor layer 1010.

[0092] In some implementation schemes, such as FIG. 10A As shown, trench 1022 extends downward through the bottom surface of the second type semiconductor layer 1020 and into the interior of the second type cap layer 1024. The bottom surface of trench 1022 is lower than the bottom surface of the second type semiconductor layer 1020. Furthermore, the bottom surface of the second ion implantation fence 1023 is higher than the bottom surface of the second trench 1022. FIG. 11 It is shown FIG. 10A The top view structural diagram of the second exemplary microLED is shown. FIG. 11A top view of the second type semiconductor layer 1020 is shown, wherein an ion implantation fence 1023 is separated from the mesa structure 1021 by a trench 1022. Here, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. Since the trench 1022 extends downward through the bottom surface of the second type semiconductor layer 1020 and into the interior of the second type cap layer 1024, the second type cap layer 1024 is visible through the trench 1022 in the top view.

[0093] In some implementation schemes, such as FIG. 10B As shown, trench 1022 extends downward through the bottom surface of the second type semiconductor layer 1020 and the second type cap layer 1024. The bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the second trench 1022. In some embodiments, such as FIG. 10C As shown, the bottom surface of the ion implantation fence 1023 is aligned with the bottom surface of the second type semiconductor layer 1020.

[0094] Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any location. In some embodiments, such as FIG. 10D As shown, the top surface of the ion implantation fence 1023 is higher than the top surface of the second type semiconductor layer 1020. In some embodiments, such as FIG. 10E As shown, the top surface of the ion implantation fence 1023 is lower than the top surface of the second type semiconductor layer 1020.

[0095] In some implementation schemes, such as FIG. 10F As shown, the platform structure 1021 includes a stepped structure 1021a. In some embodiments, the platform structure 1021 may have multiple stepped structures.

[0096] FIG. 12A and FIG. 12B This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure. FIG. 12A As shown, the micro-LED further includes a bottom isolation layer 1040 formed beneath the first type of semiconductor layer 1010. Preferably, the material of the bottom isolation layer 1040 is selected from SiO2 and SiN. xor one or more of Al2O3. An integrated circuit (IC) backplane 1090 is formed underneath the first type semiconductor layer 1010 and is electrically connected with the first type semiconductor layer 1010 via a connection structure 1050. The connection structure 1050 is a connection pillar. The micro-LED further includes a bottom contact 1060 formed at the bottom of the first type semiconductor layer 1010. The upper surface of the connection structure 1050 is connected with the bottom contact 1060, and the bottom of the connection structure 1050 is connected with the IC backplane 1090. In the present embodiment, the bottom contact 1060 protrudes from the first type semiconductor layer 1010 as a bottom contact of the micro-LED.

[0097] In addition, in some embodiments, the micro-LED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on the top of the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020 and the top surface of the top contact 1080, and covers the sidewall of the second trench 1022. Preferably, a dielectric layer 1071 is formed on the sidewall and bottom surface of the trench 1022. The conductive type of the top contact 1080 is the same as the conductive type of the second type semiconductor layer 1020. For example, the conductive type of the second type semiconductor layer 1020 is N-type, and the conductive type of the top contact 1080 is N-type. The top contact 1080 is made of a metal or a metal alloy, such as AuGe, AuGeNi, etc. The top contact 1080 is used to form an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020 to optimize the electrical properties of the micro-LED. The diameter of the top contact 1080 is about 20-50 nm, and the thickness of the top contact 1080 is about 10-20 nm.

[0098] Reference is made to FIG. 12B , the connection structure 1050 can be a metal bonding layer for bonding the micro-LED with the IC backplane 1090. In addition, in the present embodiment, the bottom contact 1060 is a bottom contact layer.

[0099] FIG. 13 is a structural diagram showing a side cross-sectional view of another variant of a second exemplary micro-LED according to some embodiments of the present disclosure. As FIG. 13 shown, the dielectric layer 1071 can be completely filled in the second trench 1022. The conductive layer 1070 is formed on the entire substrate. In some embodiments, the dielectric layer 1071 can be formed on the top surface of the second type semiconductor layer 1020. In some embodiments, the dielectric layer can be a multi-layer structure, and the material for the first portion of the dielectric layer in the trench and the material for the second portion of the dielectric layer can be different.

[0100] FIG. 14A flowchart of a method 1400 for fabricating a second exemplary micro-LED (e.g., FIG. 13 is shown in accordance with some embodiments of the present disclosure. As FIG. 14 shown, the method for fabricating a micro-LED includes steps 1401-1406. FIGS. 15A-15F is shown in accordance with some embodiments of the present disclosure. As FIG. 14 is shown, a side cross-sectional view of the micro-LED fabrication process at each step of the method 1400 (i.e., steps 1401-1406).

[0101] Referring to FIG. 14 and FIGS. 15A-15F , in step 1401: an epitaxial structure is provided. As FIG. 15A shown, the epitaxial structure includes, in order from top to bottom, a first-type semiconductor layer 1510, a first-type cap layer 1514, a light-emitting layer 1530, a second-type cap layer 1524, and a second-type semiconductor layer 1520. The epitaxial structure is grown on a substrate 1500. The substrate 1500 can be GaN, GaAs, etc.

[0102] Preferably, a bottom contact layer 1560, which serves as a bottom contact, is deposited on the top surface of the first-type semiconductor layer 1510 before flipping the epitaxial structure. Then, a metal bonding layer, which serves as a connection structure 1550, is deposited on the top surface of the bottom contact layer 1560.

[0103] In step 1402: referring to FIG. 15B , the epitaxial structure is bonded with an IC backplane 1590. First, the epitaxial structure is flipped. Subsequently, the connection structure 1550 is bonded with a contact pad of the IC backplane 1590 by a metal bonding process. Finally, the substrate 1500 is removed by a conventional separation method, such as a laser lift-off method, or a chemical etching method. The arrow shows the removal direction of the substrate 1500.

[0104] In step 1403: referring to FIG. 15C , the second-type semiconductor layer 1520 is patterned to form mesa structures 1521, trenches 1522, and fences 1523'.

[0105] In some embodiments, step 1403 further includes: etching the second-type semiconductor layer and the second-type cap layer and stopping the etching on the top surface of the light-emitting layer 1030 to avoid the light-emitting layer from being etched in the patterning process. As FIG. 15C shown, the bottom surface of the trench 1522 contacts the light-emitting layer 1530.

[0106] In some embodiments, step 1403 further comprises: etching the second-type semiconductor layer and the light-emitting layer sequentially, and stopping etching in the light-emitting layer 1030. Referring back to FIG. 10B , the bottom surface of the trench 1022 contacts the light-emitting layer 1030 and is located in the light-emitting layer 1030.

[0107] In some embodiments, step 1403 further comprises: etching the second-type semiconductor layer, the light-emitting layer and the first-type semiconductor layer sequentially, and stopping etching in the first-type semiconductor layer. Referring back to FIG. 10C , the bottom of the trench 1022 contacts the first-type semiconductor layer 1010 and is located in the first-type semiconductor layer 1010.

[0108] It is understood by those skilled in the art that the second-type semiconductor layer 1520 is etched by a conventional dry etching process, such as a plasma etching process.

[0109] In step 1404: referring back to FIG. 15D , a top contact 1580 is deposited on the mesa structure 1521. Before depositing the top contact 1580, a first protective mask (not shown) is used to protect the area where the top contact 1580 will not be formed. Then, the material of the top contact 1580 is deposited on the first protective mask and on the second-type semiconductor layer 1520 by a conventional vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. After the deposition process, the first protective mask is removed from the second-type semiconductor layer 1520, and the material on the first protective mask is also removed together with the first protective mask to form the top contact 1580 on the mesa structure 1521.

[0110] In step 1405: referring back to FIG. 15E , an ion implantation process is performed into the fence 1523'. Also referring back to FIG. 15D , ions are implanted into the fence 1523' by the ion implantation process (as shown in FIG. 15D ) to form an ion implanted fence 1523 (as shown in FIG. 15E ). The arrows show the direction of the ion implantation process. Before the ion implantation process, a second protective mask (not shown) is formed on the area to be implanted with ions. Then, ions are implanted into the exposed fence 1523' (as shown in FIG. 15D ). Subsequently, the second protective mask is removed by a conventional chemical etching process, which is understood by those skilled in the art. Preferably, the implantation energy is 0 KeV to 500 KeV, and the implantation dose is 1E10 to 9E17.

[0111] In step 1406: referring back to FIG. 15FThe top conductive layer 1570 is deposited on top of the second-type semiconductor layer 1520 and on top of the top contact 1580 and covers the sidewalls of the trench 1522. The top conductive layer 1570 is deposited by a conventional physical vapor deposition process.

[0112] Before the top conductive layer 1570 is formed, a dielectric layer 1571 is formed on the sidewalls and bottom surface of the trench 1522. As shown in FIG. 15B, FIG. 15F the dielectric layer 1571 is formed in the trench 1522 on the sidewalls of the second-type semiconductor layer 1520, the mesa structure 1521, and the second-type cap layer 1524 and on the surface of the light emitting layer 1530 in the trench 1522. In some embodiments, referring back to FIG. 10B the dielectric layer can be formed in the trench 1022 on the sidewalls of the second-type semiconductor layer 1020, the mesa structure 1021, and the light emitting layer 1030 and on the surface of the light emitting layer 1030 in the trench 1022. In some embodiments, referring back to FIG. 10C the dielectric layer can be formed on the sidewalls of the mesa structure 1021, the second-type cap layer 1024, the light emitting layer 1030, the first-type cap layer 1014, and on the sidewalls and surface of the first-type semiconductor layer 1010 in the trench 1022.

[0113] Referring back to FIG. 15F the top conductive layer 1570 is formed on the surface of the dielectric layer 1571 and covers the sidewalls and bottom of the trench 1522, on the top surface of the second mesa structure 1521, and on the top surface of the ion implantation fence 1523. In addition, in some embodiments, referring back to FIG. 13 the dielectric layer 1071 can completely fill in the second trench 1022. A microlens can be further formed on the top conductive layer, as can be appreciated by one skilled in the art.

[0114] According to some embodiments of the disclosure, a micro LED array panel is further provided. The micro LED array panel includes a plurality of micro LEDs, as described above and shown in FIG. 10A FIG. 10H, FIG. 12A , FIG. 12B and FIG. 13 . These micro LEDs can be arranged into an array in the micro LED array panel.

[0115] FIG. 16 is a structural diagram showing a side cross-sectional view of adjacent micro LEDs of a second exemplary micro LED according to some embodiments of the disclosure. As shown in FIG. 10H, FIG. 16As shown, the micro LED array panel includes a first type semiconductor layer 1610 continuously formed in the micro LED array panel, a first type capping layer 1614 continuously formed on the first type semiconductor layer 1610, a light-emitting layer 1630 continuously formed on the first type semiconductor layer 1610, a second type capping layer 1624 continuously formed on the light-emitting layer 1630, and a second type semiconductor layer 1620 continuously formed on the second type capping layer 1624.

[0116] The second type semiconductor layer 1620 includes a plurality of mesa structures 1621, a plurality of trenches 1622, and a plurality of ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. The bottom surface of the ion implantation fences 1623 is not lower than the bottom surface of the second type semiconductor layer 1620.

[0117] FIG. 17 This illustrates some embodiments according to this disclosure. FIG. 16 A top-view structural diagram of adjacent micro-LEDs. FIG. 17 In the top view, an ion implantation fence 1623 is formed around a trench 1622 and between adjacent mesa structures 1621. The resistance of the ion implantation fence 1623 is higher than the resistance of the mesa structures 1621. The ion implantation fence 1623 is formed around the trench 1622, and the trench 1622 is formed around the mesa structures 1621.

[0118] The variation in the relationship between the bottom surface of the ion implantation fence 1623, the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 generally corresponds to FIGS. 10A-10E The variations shown for micro-LEDs will not be described further here. Additionally, in some embodiments, variations in the relationship between the top surface of the ion-implanted fence 1623 and the top surface of the second type semiconductor layer 1620 generally correspond to... FIG. 10E The variation shown in Figure 10G for micro-LEDs will not be described further here. In some embodiments, the mesa structure may have one or more stepped structures, as shown in Figure 10H.

[0119] In some embodiments, the space between adjacent sidewalls of adjacent mesa structures of mesa structure 1621 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of mesa structure 1621 is no greater than 50% of the diameter of mesa structure 1621. In some embodiments, the space between adjacent sidewalls of mesa structure 1621 is no greater than 30% of the diameter of mesa structure 1621. Preferably, the space between adjacent sidewalls of mesa structure 1621 is no greater than 600 nm. Additionally, in some embodiments, the width of ion implantation fence 1623 can be adjusted. For example, the width of ion implantation fence 1623 may be no greater than 50% of the diameter of mesa structure 1621. In some embodiments, the width of ion implantation fence 1623 may be no greater than 10% of the diameter of mesa structure 1621. Preferably, in a micro-LED array panel, the width of ion implantation fence 1623 is no greater than 200 nm.

[0120] Bottom contact 1660 is formed at the bottom of the first type semiconductor layer 1610. Connection structure 1650 is a metal bonding layer used to bond the microLED to the IC backplane 1690. Details of the bottom contact 1660, connection structure 1650, and IC backplane 1690 can be found in [reference needed]. FIG. 12A and FIG. 12B The aforementioned micro-LEDs were found.

[0121] FIG. 18 This illustrates some embodiments of a micro LED array panel according to this disclosure. FIG. 12B A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) FIG. 18 As shown, the micro LED array panel further includes a top contact 1880, a dielectric layer 1871, and a top conductive layer 1870. Further details of the top contact 1880, dielectric layer 1871, and top conductive layer 1870 can be found by referring to [reference also provided]. FIGS. 10A-10F , FIG. 12A and FIG. 12B as well as FIG. 13 The micro-LEDs shown are used for understanding, and will not be described further here.

[0122] In addition, return to reference FIG. 18IC backplane 1890 is formed underneath the first-type semiconductor layer 1810 and is electrically connected with the first-type semiconductor layer 1810 via the connection structure 1850. The micro LED array panel further includes a bottom contact 1860 formed at the bottom of the first-type semiconductor layer 1810. The connection structure 1850 can be a metal bonding layer for bonding the micro LED with the IC backplane 1890. In addition, in some embodiments, the bottom contact 1860 is a bottom contact layer. Further details of the bottom isolation layer 1840, the IC backplane 1890, the bottom contact 1860, and the connection structure 1850 can be understood by also referring to FIG. 12B FIG. 10H, which will not be further described here.

[0123] In addition, further details regarding the features of the micro LED and the ion implantation fence in the micro LED array panel can be understood by also referring to FIG. 10A FIG. 10H, which will not be further described here.

[0124] FIG. 18 The micro LED array panel shown can be fabricated by a method 1400 of fabricating a micro LED as shown in FIG. 14 FIG. 10H, which will not be further described here.

[0125] Embodiment 3

[0126] FIGS. 19A-19F is a structural diagram showing various different variants of a third exemplary micro LED according to some embodiments of the present disclosure. As FIG. 19AIn some embodiments, the micro-LED includes at least a first type semiconductor layer 1910, a first type cap layer 1914, a light emitting layer 1930, a second type cap layer 1924, and a second type semiconductor layer 1920. The first type semiconductor layer 1910 has a different conductivity type than the second type semiconductor layer 1920. For example, in some embodiments, the first type semiconductor layer 1910 has a P-type conductivity and the second type semiconductor layer 1920 has an N-type conductivity. In some embodiments, the second type semiconductor layer 1920 has a P-type conductivity and the first type semiconductor layer 1910 has an N-type conductivity. The first type semiconductor layer 1910 has a greater thickness than the second type semiconductor layer 1920. The first type semiconductor layer 1910 can have a thinner thickness than the second type semiconductor layer 1920. In some embodiments, the first type semiconductor layer 1910 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the second type semiconductor layer 1920 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN. The first type cap layer 1914 has the same conductivity type as the first type semiconductor layer 1910, and the second type cap layer 1924 has the same conductivity type as the second type semiconductor layer 1920.

[0127] The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913 that is separated from the first mesa structure 1911. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 that is separated from the second mesa structure 1921.

[0128] In combination FIG. 1A , the first trench can extend upward through the top of the first type semiconductor layer and into the interior of the first type cap layer. In combination FIG. 1B , the first trench can extend upward through the first type semiconductor layer and the first type cap layer and contact the light emitting layer. Further, the first trench can extend into the interior of the light emitting layer. In some embodiments, the first trench can extend upward through the first type semiconductor layer, the first type cap layer, and the light emitting layer. Further, the first trench can extend upward into the interior of the second type cap layer. In some embodiments, in combination FIG. 1C, the first trench can extend upward through the first-type semiconductor layer, the first-type cap layer, and the light emitting layer, and into the second-type cap layer. Also, the first trench can extend upward into the interior of the second-type semiconductor layer. In addition, the first trench can extend upward through the first-type semiconductor layer, the first-type cap layer, the light emitting layer, the second-type cap layer, and the second-type semiconductor layer.

[0129] In conjunction with FIG. 10A , the second trench can extend downward through the second-type semiconductor layer and into the interior of the second-type cap layer. In addition, in conjunction with FIG. 10B , the second trench can extend downward through the second-type semiconductor layer and through the second-type cap layer and can reach the light emitting layer. Also, the second trench can extend into the interior of the light emitting layer. In some embodiments, the second trench can extend downward through the second-type semiconductor layer, the second-type cap layer, and the light emitting layer. Also, the second trench can extend downward into the interior of the first-type cap layer. In some embodiments, in conjunction with FIG. 10C , the second trench can extend downward through the second-type semiconductor layer, the second-type cap layer, the light emitting layer, and the first-type cap layer and downward into the interior of the first-type semiconductor layer. In addition, the second trench can extend downward through the second-type semiconductor layer, the second-type cap layer, the light emitting layer, the first-type cap layer, and the first-type semiconductor layer.

[0130] Referring back to FIGS. 19A-19D , the top of the first trench 1912 does not contact the bottom of the second trench 1922 in the horizontal direction or the vertical direction. A portion of the light emitting layer 1930 is disposed between the top surface of the first trench 1912 and the bottom surface of the second trench 1922. In addition, in some embodiments, referring to FIG. 19E and FIG. 19F , the top surface of the first trench 1912 is directly connected with the bottom of the second trench 1922 in the horizontal direction and the vertical direction. In some embodiments, as shown in FIG. 19E , there is no light emitting layer between the top of the first trench 1912 and the bottom of the second trench 1922. That is, when the first trench 1912 and the second trench 1922 extend through each other in the vertical direction, the first trench 1912 and the second trench 1922 are interconnected. The center of the first trench 1912 can be aligned with or deviated from the center of the second trench 1922. In some embodiments, as shown in FIG. 19D and FIG. 19F , the first trench 1912 and the second trench 1922 do not correspond to each other in the vertical direction. In addition, in some embodiments, the diameter of the first trench 1912 from the top side downward can be the same or different. The diameter of the second trench 1922 from the top side downward can be the same or different. The diameter of the first trench 1912 can be the same or different from the diameter of the second trench 1922.

[0131] In some embodiments, the center of the first mezzanine structure 1911 is aligned with the center of the second mezzanine structure 1921, the center of the first trench 1912 is aligned with the center of the second trench 1922, and the center of the first ion implantation fence 1913 is aligned with the center of the second ion implantation fence 1923.

[0132] The relationship between the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912, and the top surface of the first type semiconductor layer 1910 and FIGS. 1A-1D The relationships of the variant of the microLED shown in Embodiment 1 are the same and will not be described further here. The relationships of the bottom of the first ion implantation fence 1913, the bottom of the first trench 1912, and the bottom of the first type semiconductor layer 1910 are the same as in Embodiment 1. FIG. 1D The relationship is the same as that of the variant of the micro-LED in embodiment 1 shown in Figure 1G, and will not be described further here. Furthermore, in some embodiments, the first mesa structure 1911 may have one or more stepped structures, as shown in Figure 1H.

[0133] The relationship between the bottom of the second ion implantation fence 1923, the bottom of the second trench 1922, and the bottom of the second type semiconductor layer 1920 is as follows: FIGS. 10A-10E The relationships between the variants of the microLED shown in Embodiment 2 are the same and will not be described further here. The relationships between the top surface of the second ion implantation fence 1923, the top surface of the second trench 1922, and the top surface of the second type semiconductor layer 1920 are as follows: FIG. 10E The relationship to the microLEDs in embodiment 2 shown in Figure 10G is the same and will not be described further here. Furthermore, in some embodiments, the second mezzanine structure 1921 may have one or more stepped structures, as shown in Figure 10H.

[0134] FIG. 20 This is a structural diagram showing a side cross-sectional view of another variant of a third exemplary microLED according to some embodiments of this disclosure. FIG. 20 As shown, the micro-LED further includes a bottom insulating layer 2040 filled in the first trench 2012. Preferably, the bottom insulating layer 2040 is made of SiO2 or SiN. xOr one or more of Al2O3. An IC backplane 2090 is formed beneath the first type semiconductor layer 2010 and electrically connected to the first type semiconductor layer 2010 via a connection structure 2050. Here, the connection structure 2050 is a connection pillar. The micro-LED further includes a bottom contact 2060 formed at the bottom of the first type semiconductor layer 2010. Further details of the bottom isolation layer 2040, IC backplane 2090, connection structure 2050, and bottom contact 2060 can be found in the description of Embodiment 1, and will not be described further here.

[0135] The microLED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on top of the second type semiconductor layer 2020. The top conductive layer 2070 is formed on top of the second type semiconductor layer 2020 and the top contact 2080, and covers the sidewalls and bottom of the second trench 2022. Further details regarding the top contact 2080 and the top conductive layer 2070 can be found by referring to the description of embodiment 2, and will not be described further here.

[0136] In addition, regarding FIG. 20 Further details of the micro-LEDs shown (including the first ion implantation fence 2013 and the second ion implantation fence 2023) can be found by referring to the descriptions of embodiments 1 and 2, and will not be described further here.

[0137] FIG. 21 A flowchart of a method 2100 for manufacturing a third exemplary microLED according to some embodiments of this disclosure is shown. Method 2100 includes at least process I and process II.

[0138] In process I: a first type semiconductor layer is patterned, and then ions are implanted into the first type semiconductor layer to form a first ion implantation fence.

[0139] In process II: a second type semiconductor layer is patterned, and then ions are implanted into the second type semiconductor layer to form a second ion implantation fence.

[0140] refer to FIG. 21 Process I includes at least steps 2101 to 2109, and process II includes at least steps 2110 to 2113.

[0141] For process I, steps 2101 to 2109 are as follows: FIG. 5 Steps 501 to 509 of method 500 shown are similar. The side cross-sectional view of the microLED fabricated according to steps 2101 to 2109 is similar. FIGS. 6A-6I The view shown is similar. (Reference)FIG. 21 and FIGS. 6A-6I In step 2101: referring to FIG. 6A , an epitaxial structure is provided. The epitaxial structure includes, in order from top to bottom, a first-type semiconductor layer 610, a first-type cap layer 614, a light-emitting layer 630, a second-type cap layer 624, and a second-type semiconductor layer 620. In step 2102: referring to FIG. 6B , the first-type semiconductor layer 610 is patterned to form mesa structures 611, trenches 612, and fences 613'.

[0142] In step 2103: referring to FIG. 6C , a bottom contact 660 is deposited on the mesa structures 611.

[0143] In step 2104: referring to FIG. 6D , an ion implantation process is performed into the fences 613'.

[0144] In step 2105: referring to FIG. 6E , an isolation layer 640 is deposited on the entire substrate 600.

[0145] The bottom isolation layer can fill into the first trenches. In some embodiments, the bottom isolation layer can be formed on the sidewalls of the first-type semiconductor layer, the first-type cap layer, the light-emitting layer, and the second-type semiconductor layer of the first mesa structure, the second mesa structure, the second-type cap layer, and the second-type ion implantation fence in the first trenches, depending on the depth of the first trenches.

[0146] In step 2106: referring to FIG. 6F , the isolation layer 640 is patterned to expose the bottom contact 660.

[0147] In step 2107: referring to FIG. 6G , a metal material 650' is deposited on the entire substrate 600.

[0148] In step 2108: referring to FIG. 6H , a top of the metal material 650' is ground to a top of the isolation layer 640 to form a connection pillar 650.

[0149] In step 2109: referring to FIG. 6I , the connection pillar 650 is bonded with an IC backplate 690, and the substrate 600 is removed.

[0150] FIGS. 22A-22D is a structural diagram showing a side cross-sectional view of a micro-LED manufacturing process at steps 2110-2113 of the method 2100 shown in FIG. 21 . Referring to FIG. 21 andFIGS. 22A-22D In step 2110: Referring to FIG. 22A The second-type semiconductor layer 2220 is patterned to form mesa structures 2221, trenches 2222, and fences 2223'.

[0151] In step 2111: Referring to FIG. 22B A top contact 2280 is deposited on the mesa structures 2221.

[0152] In step 2112: Referring to FIG. 22C An ion implantation process is performed into the fences 2223' to form ion-implanted fences 2223. FIG. 22B The arrow in the figure shows the direction of the ion implantation process.

[0153] In step 2113: Referring to FIG. 22D A top conductive layer 2270 is deposited on top of the second-type semiconductor layer 2220 and on the top contact 2280, and in the trenches 2222. In some implementations, the top conductive layer 2270 can be formed directly on top of the second-type semiconductor layer 2220 and on the top contact 2280, and on the sidewalls and bottom of the trenches 2222.

[0154] FIG. 23A and FIG. 23B is a structural diagram showing a side cross-sectional view of other variants of a third exemplary micro-LED according to some embodiments of the present disclosure. As shown in FIG. 23A The bottom isolation layer 2340 is filled in the first trenches 2312 and formed on the sidewalls of the first mesa structures 2311, the first ion-implanted fences 2313, the first-type cap layer 2314, and the light-emitting layer 2330 in the first trenches 2312. Before the top conductive layer 2370 is formed, a dielectric layer 2371 is formed extending into the second trenches 2322. The dielectric layer 2371 is formed on the sidewalls and bottom of the second trenches 2322. In addition, the dielectric layer 2371 is formed on the sidewalls of the second mesa structures 2321, the second-type semiconductor layer 2320, the second ion-implanted fences 2323, the second-type cap layer 2324, and the light-emitting layer 2330 in the second trenches 2322. Then, the top conductive layer 2370 is formed on the surface of the dielectric layer 2371 extending into the second trenches 2322, and on top of the second mesa structures 2321 and the second ion-implanted fences 2323.

[0155] In some implementations, as FIG. 23BAs shown, the bottom isolation layer 2340 fills in the first trench 2312 and forms on the sidewalls of the first mesa structure 2311, the first ion implantation fence 2313, and the first type semiconductor layer 2310. The top conductive layer 2370 can be formed to extend into the second trench 2322. In addition, the dielectric layer 2371 is formed to extend into the second trench 2322. The dielectric layer 2371 forms on the sidewalls of the second mesa structure 2321, the second type semiconductor layer 2320, the second ion implantation fence 2323, the second type cap layer 2324, the light emitting layer 2330, the first mesa structure 2311, the first type cap layer 2314, the first ion implantation fence 2313, the first type semiconductor layer 2310 in the second trench 2322.

[0156] The bottom isolation layer 2340 forms on the sidewalls and the top of the first trench 2312, and the dielectric layer 2371 forms on the sidewalls and the bottom of the second trench 2322. The thickness of the bottom isolation layer extending into the first trench 2312 depends on the position of the bottom of the second trench 2322 and the position of the top of the first trench 2312. The thickness of the dielectric layer 2371 extending into the second trench 2322 depends on the position of the bottom of the second trench 2322 and the position of the top of the first trench 2312.

[0157] According to some embodiments of the present disclosure, a top contact and a bottom contact can be formed on the micro-LED, which will not be further described here.

[0158] Further details of the process I can be found by referring to the description of steps 501 to 509 of embodiment 1. Further details of the process II can be found by referring to the description of steps 1403 to 1406 of embodiment 2, which will not be further described here.

[0159] According to some embodiments of the present disclosure, further provided is a micro-LED array panel. The micro-LED array panel comprises a plurality of micro-LEDs as described above and in FIGS. 19A-19E 、 FIG. 20 and FIG. 23A and FIG. 23B embodiments of the present disclosure. These micro-LEDs can be arranged into an array in the micro-LED array panel.

[0160] FIG. 24 is a structural diagram showing a side cross-sectional view of adjacent micro-LEDs of a micro-LED in FIG. 23A according to some embodiments of the present disclosure. As FIG. 24As shown, the micro-LED array panel includes at least a first type semiconductor layer 2410 formed continuously in the micro-LED array panel, a first type cap layer 2414 formed continuously on the first type semiconductor layer 2410, a light emitting layer 2430 formed continuously on the first type cap layer 2414, a second type cap layer 2424 formed continuously on the light emitting layer 2330, and a second type semiconductor layer 2420 formed on the second type cap layer 2324.

[0161] The first type semiconductor layer 2410 includes a plurality of first mesa structures 2411, a plurality of first trenches 2412, and a plurality of first ion implantation fences 2413 separated from the first mesa structures via the first trenches 2412. The top surface of the first ion implantation fences 2413 is lower than the top surface of the first type semiconductor layer 2410. Referring back to FIG. 8 The bottom view of the micro-LED array panel without the IC backplane is similar to FIG. 8 As shown, the bottom view is similar to that of the micro-LED array panel with the IC backplane. The first ion implantation fences 2413 are formed around the first trenches 2412 and between adjacent first type mesa structures 2411. The electrical resistance of the first ion implantation fences 2413 is higher than that of the first mesa structures 2411. In addition, the first ion implantation fences 2413 are formed around the first trenches 2412, and the first trenches 2412 are formed around the first mesa structures 2411.

[0162] The second type semiconductor layer 2420 includes a plurality of second mesa structures 2421, a plurality of second trenches 2422, and a plurality of second ion implantation fences 2423 separated from the second mesa structures 2421 via the second trenches 2422. The bottom surface of the second ion implantation fences 2423 is higher than the bottom surface of the second type semiconductor layer 2420. The top view of the micro-LED array panel is similar to FIG. 17 As shown, the top view is similar to that of the micro-LED array panel with the IC backplane. The second ion implantation fences 2423 are formed around the second trenches 2422 and between adjacent second mesa structures 2421. The electrical resistance of the second ion implantation fences 2423 is higher than that of the second mesa structures 2421. The second ion implantation fences 2323 are formed around the second trenches 2422, and the second trenches 2422 are formed around the second mesa structures 2421.

[0163] In some embodiments, the space between adjacent sidewalls of the first mesa structure 2411 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of the first mesa structure 2411 is no more than 50% of the diameter of the first mesa structure 2411. In some embodiments, the space between adjacent sidewalls of the first mesa structure 2411 is no more than 30% of the diameter of the first mesa structure 2411. Preferably, the space between adjacent sidewalls of the first mesa structure 2411 is no more than 600 nm. In addition, in some embodiments, the width of the first ion implantation fence 2413 can be adjusted. For example, in some embodiments, the width of the first ion implantation fence 2413 is no more than 50% of the diameter of the first mesa structure 2411. In some embodiments, the width of the first ion implantation fence 2313 is no more than 10% of the diameter of the first mesa structure 2311. Preferably, in some embodiments, the width of the first ion implantation fence 2413 is no more than 200 nm in the micro LED array panel. The space between adjacent sidewalls of the second mesa structure 2421 is no more than 50% of the diameter of the second mesa structure 2421. In some embodiments, the space between adjacent sidewalls of the second mesa structure 2421 is no more than 30% of the diameter of the second mesa structure 2421. Preferably, the space between adjacent sidewalls of the second mesa structure 2421 is no more than 600 nm. In addition, the width of the second ion implantation fence 2423 is no more than 50% of the diameter of the second mesa structure 2421. In some embodiments, the width of the second ion implantation fence 2423 is no more than 10% of the diameter of the second mesa structure 2421. Preferably, the width of the second ion implantation fence 2423 is no more than 200 nm in the micro LED array panel.

[0164] The micro LED array panel further includes a bottom isolation layer 2440 filled in the first trench 2412. Preferably, the material of the bottom isolation layer 2440 is one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2. In addition, an IC back plate 2490 is formed below the first type semiconductor layer 2410 and is electrically connected with the first type semiconductor layer 2410 via a connection structure 2450. The micro LED array panel further includes a bottom contact 2460 formed at the bottom of the first type semiconductor layer 2410. The upper surface of the connection structure 2450 is connected with the bottom contact 2460, and the bottom of the connection structure 2450 is connected with the IC back plate 2490. The bottom contact 2460 is a protruding contact. In some embodiments, referring to FIG. 4 , the connection structure 2450 can be a metal bonding layer for bonding the micro LED with the IC back plate 2490. In addition, in some embodiments, the bottom contact 2460 is a bottom contact layer.

[0165] Reference is made back to FIG. 24 The micro LED array panel further includes a top contact 2480 and a top conductive layer 2470. The top contact 2480 is formed on top of the second-type semiconductor layer 2420. The top conductive layer 2470 is formed on top of the second-type semiconductor layer 2420 and the top contact 2480 and covers the sidewalls and the bottom of the second trench 2422. The top contact 2480 is of the same conductive type as the second-type semiconductor layer 2420. For example, the second-type semiconductor layer 2420 is of N-type and the top contact 2480 is of N-type. The top contact 2480 is made of a metal or a metal alloy, such as AuGe, AuGeNi, etc. The top contact 2480 is used to form an ohmic contact between the top conductive layer 2470 and the second-type semiconductor layer 2420 to optimize the electrical properties of the micro LED. The diameter of the top contact 2480 is about 20-50 nm and the thickness of the top contact 2480 is about 10-20 nm.

[0166] In addition, a dielectric layer 2471 is formed under the top conductive layer 2470 on the sidewalls and the bottom of the second trench 2422.

[0167] Further detailed properties of the micro LED in the micro LED array panel can be found by referring to the above micro LED, which will not be further described here.

[0168] The method of manufacturing the micro LED array panel at least includes manufacturing the micro LED. Details of manufacturing the micro LED can refer to the description of steps 501-509 in Embodiment 1 and the description of steps 1403-1406 in Embodiment 2, which will not be further described here.

[0169] In Embodiments 1-3, a micro-lens can be further formed on or above the top of the second-type semiconductor layer, such as on the top surface of the top conductive layer, which can be understood by those skilled in the art.

[0170] The micro-LED has a very small volume. The micro-LED can be an organic LED or an inorganic LED. The micro-LED can be applied in a micro-LED array panel. The micro-LED array panel has a very small light emitting area, such as 1 mm x 1 mm, 3 mm x 5 mm. In some embodiments, the light emitting area is the area of a micro-LED array in the micro-LED array panel. The micro-LED array panel includes one or more micro-LED arrays forming a pixel array, such as a 1600 x 1200, 680 x 480, or 1920 x 1080 pixel array, where the micro-LEDs are the pixels. The diameter of the micro-LED is in a range from about 200 nm to 2 pm. An IC backplane is formed at the back surface of the micro-LED array and is electrically connected with the micro-LED array. The IC backplane obtains signals such as image data from the outside via signal lines to control the corresponding micro-LEDs to emit light or not to emit light.

[0171] It should be noted that relational terms herein, such as“first” and“second”, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the words“comprising”,“having”,“containing” and“including” and other similar forms are intended to be equivalent in meaning and are open-ended, in that an item or items following any one of these words are not meant to be an exhaustive listing of possible items, or are meant to be limited to only the items specifically listed.

[0172] As used herein, the term“or” encompasses all possible combinations, unless otherwise indicated by context. For example, if a database is stated to include A or B, then unless otherwise indicated or infeasible, the database can include A, or B, or A and B. As a second example, if a database is stated to include A, B, or C, then unless otherwise indicated or infeasible, the database can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0173] In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain modifications and changes can be made thereto, and it is intended to embrace all such modifications and changes as fall within the scope of the application disclosed herein. The specification and examples given are intended as illustrative only and are not intended to limit the true scope and spirit of the application, which is indicated by the following claims. The sequence of steps shown in the drawings is also intended to be illustrative only and is not intended to limit the application to any particular sequence of steps. Thus, those skilled in the art will appreciate that these steps can be performed in different orders while still implementing the same method.

[0174] In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Therefore, it is to be understood that no limitation of the scope of the application is intended by the disclosure. The disclosure is intended to cover any and all modifications within the scope of the following claims.

Claims

1. A micro-LED, comprising: a first-type semiconductor layer; a first-type cap layer formed on the first-type semiconductor layer; and a light-emitting layer formed on the first-type cap layer; wherein the first-type semiconductor layer comprises a mesa structure, a trench extending upward through the first-type semiconductor layer and upward into at least a portion of the first-type cap layer, and an ion-implanted fence separated from the mesa structure; and the ion-implanted fence is formed around the trench and the trench is formed around the mesa structure, wherein the ion-implanted fence has a higher electrical resistance than the mesa structure, wherein the mesa structure comprises one or more stepped structures. a top surface of the ion-implanted fence is lower than or aligned with a top surface of the first-type semiconductor layer.

2. The micro-LED of claim 1, wherein, a bottom surface of the ion-implanted fence is aligned with, higher than, or lower than a bottom surface of the first-type semiconductor layer.

3. The micro-LED of claim 1, wherein, a top surface of the ion-implanted fence is lower than a top surface of the trench.

4. The micro-LED of claim 1, wherein, the trench extends upward through the first-type cap layer.

5. The micro-LED of claim 1, wherein, the trench extends upward into at least a portion of the light-emitting layer.

6. The micro-LED of claim 5, wherein, a conductive type of the second-type semiconductor layer is different from a conductive type of the first-type semiconductor layer.

7. The micro-LED of claim 1, further comprising a second type cap layer formed on a top surface of the light emitting layer; and a second type semiconductor layer formed on the second type cap layer, wherein, the trench further extends upward through the first-type cap layer, the light-emitting layer, and into an interior of the second-type cap layer.

8. The micro-LED of claim 7, wherein, the trench further extends upward through the second-type cap layer and into an interior of the second-type semiconductor layer.

9. The micro-LED of claim 8, wherein, the trench further extends upward through the second-type semiconductor layer.

10. The micro-LED of claim 9, wherein, a width of the trench is no more than 50% of a width of the mesa structure.

11. The micro-LED of claim 1, wherein, a width of the trench is no more than 200 nm.

12. The micro-LED of claim 11, wherein, the ion-implanted fence comprises a light-absorbing material, and the light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

13. The micro-LED of claim 1, wherein, a thickness of the first-type semiconductor layer is greater than a thickness of the light-emitting layer.

14. The micro-LED of claim 1, wherein, 15. The micro-LED of claim 1, further comprising a bottom isolation layer filling in the trench. a material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2, or ZrO2.

16. The micro-LED of claim 15, wherein, the ion-implanted fence is formed by implanting ions into at least the first-type semiconductor layer.

17. The micro-LED of claim 1, wherein, the ions implanted into the ion-implanted fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

18. The micro-LED of claim 17, wherein, a width of the ion-implanted fence is no more than 50% of a diameter of the mesa structure.

19. The micro-LED of claim 1, wherein, a width of the ion-implanted fence is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the first-type semiconductor layer is no more than 100 nm.

20. The micro-LED of claim 19, wherein, ​ 21. The micro-LED of claim 7, wherein, The material of the first type semiconductor layer is one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN, and the material of the second type semiconductor layer is one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, and AlGaN.

22. The micro-LED of claim 1, further comprising an integrated circuit (IC) backplane formed underneath the first type semiconductor layer; and a connection structure electrically connecting the integrated circuit (IC) backplane with the first type semiconductor layer.

23. The micro-LED of claim 22, wherein, The connection structure is a connection pillar or a metal bonding layer.

24. The micro-LED of claim 22, further comprising a bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure is connected with the bottom contact, and a bottom surface of the connection structure is connected with the integrated circuit (IC) backplane.

25. A micro-LED array panel comprising a plurality of micro-LEDs according to any one of claims 1 to 24.

26. A method for fabricating a micro-LED, the method comprising: providing an epitaxial structure, wherein the epitaxial structure comprises, in order from top to bottom, a first type semiconductor layer, a first type cap layer, a light emitting layer, a second type cap layer, and a second type semiconductor layer; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence, wherein the mesa structure comprises one or more stepped structures; depositing a bottom contact on the mesa structure; and performing an ion implantation process into the fence to form an ion implanted fence.

27. The method of claim 26, wherein, After patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, the method further comprises: depositing a bottom isolation layer on the first type semiconductor layer and the bottom contact; patterning the bottom isolation layer to expose the bottom contact; depositing a metal material on the bottom isolation layer and the bottom contact; polishing the metal material to a top surface of the bottom isolation layer to form a connection structure; and flipping the epitaxial structure and bonding the connection structure with an integrated circuit (IC) backplane.

28. The method of claim 27, wherein, When depositing the bottom isolation layer on the bottom contact, the material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2or ZrO2.

29. The method of claim 27, wherein, When providing the epitaxial structure, the epitaxial structure is grown on a substrate.

30. The method of claim 29, wherein, Flipping the epitaxial structure and bonding the connection structure with the integrated circuit (IC) backplane further comprises: removing the substrate.

31. The method of claim 29, wherein, After flipping the epitaxial structure and bonding the connection structure with the integrated circuit (IC) backplane, the method further comprises: forming a top contact and a top conductive layer on a top surface of the mesa structure.

32. The method of claim 26, wherein, Patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the first type semiconductor layer to a surface of the light emitting layer.

33. The method of claim 26, wherein, Patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the first type semiconductor layer and the light emitting layer in order, and stopping the etching in the light emitting layer.

34. The method of claim 26, wherein, patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: sequentially etching the first type semiconductor layer, the light emitting layer, and the second type semiconductor layer, and stopping the etching in the second type semiconductor layer.

35. The method of claim 26, wherein, depositing the bottom contact on the mesa structure further comprises: forming a protective mask to protect areas where the bottom contact is not deposited; depositing a material of the bottom contact on the protective mask and on the first type semiconductor layer; and removing the protective mask from the first type semiconductor layer and removing the material on the protective mask to form the bottom contact on the mesa structure.

36. The method of claim 26, wherein, performing the ion implantation process into the fence to form the ion implanted fence further comprises: forming a protective mask on areas not to be ion implanted while exposing the fence; implanting ions into the fence; and removing the protective mask.

37. The method of claim 36, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, implanting at an energy of 0 Kev to 500 Kev.

38. The method of claim 36, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, implanting a dose of 1E10 to 9E17.

39. The method of claim 36, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, the ions implanted into the fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

40. The method of claim 36, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, a width of the ion implanted fence is no more than 50% of a diameter of the mesa structure.

41. The method of claim 36, wherein, when performing the ion implantation process into the fence to form the ion implanted fence, a width of the ion implanted fence is no more than 200 nm, a diameter of the mesa structure is no more than 2500 nm, and a thickness of the first type semiconductor layer is no more than 300 nm.

42. The method of claim 26, wherein, when patterning the first type semiconductor layer to form the mesa structure, the trench, and the fence, a width of the trench is no more than 50% of a diameter of the mesa structure.

43. The method of claim 26, wherein, the first type semiconductor layer is of a P-type conductivity and the second type semiconductor layer is of an N-type conductivity, wherein a material of the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and a material of the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

44. The method of claim 43, wherein, the ion implanted fence comprises a light absorbing material.

45. The method of claim 44, wherein, the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

46. A micro-LED comprising: a first type semiconductor layer; a first-type cap layer formed on the first-type semiconductor layer; a light-emitting layer formed on the first-type cap layer; a second-type cap layer formed on the light-emitting layer; a second-type semiconductor layer formed on the second-type cap layer; and an integrated circuit (IC) backplane formed at a bottom surface of the first-type semiconductor layer; wherein the second-type semiconductor layer comprises a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending downward through the second-type semiconductor layer and into at least a portion of the second-type cap layer; and the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure, wherein an electrical resistance of the ion implantation fence is higher than an electrical resistance of the mesa structure; wherein a conductivity type of the first-type semiconductor layer is different from a conductivity type of the second-type semiconductor layer, wherein the mesa structure comprises one or more step structures. a bottom surface of the ion implantation fence is higher than or aligned with a bottom surface of the second-type semiconductor layer.

47. The micro-LED of claim 46, wherein, a top surface of the ion implantation fence is aligned with, higher than, or lower than a top surface of the second-type semiconductor layer.

48. The micro-LED of claim 46, wherein, a bottom surface of the ion implantation fence is higher than a bottom surface of the trench.

49. The micro-LED of claim 46, wherein, the trench extends downward through the second-type cap layer.

50. The micro-LED of claim 46, wherein, the trench further extends downward into at least a portion of the light-emitting layer.

51. The micro-LED of claim 50, wherein, the trench further extends downward through the light-emitting layer and into an interior of the first-type cap layer; or the trench further extends downward through the light-emitting layer and the first-type cap layer and into an interior of the first-type semiconductor layer.

52. The micro-LED of claim 51, wherein, the trench further extends downward through the first-type semiconductor layer.

53. The micro-LED of claim 52, wherein, a width of the trench is no greater than 50% of a width of the mesa structure.

54. The micro-LED of claim 46, wherein, a width of the trench is no greater than 200 nm.

55. The micro-LED of claim 54, wherein, the ion implantation fence comprises a light-absorbing material, and the light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

56. The micro-LED of claim 46, wherein, a thickness of the second-type semiconductor layer is greater than a thickness of the light-emitting layer.

57. The micro-LED of claim 46, wherein, 58. The micro-LED of claim 46, further comprising a bottom isolation layer formed between a bottom surface of the first-type semiconductor layer and a top surface of the integrated circuit (IC) backplane. the ion implantation fence is formed by implanting ions into at least the second-type semiconductor layer.

59. The micro-LED of claim 58, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

60. The micro-LED of claim 46, wherein, the ions implanted into the second-type semiconductor layer are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

61. The micro-LED of claim 60, wherein, a width of the ion implantation fence is no greater than 50% of a diameter of the mesa structure.

62. The micro-LED of claim 46, wherein, a width of the ion implantation fence is no greater than 200 nm, a diameter of the mesa structure is no greater than 2500 nm, and a thickness of the first-type semiconductor layer is no greater than 300 nm.

63. The micro-LED of claim 60, wherein, ​ 64. The micro-LED of claim 46, wherein, The material of the first-type semiconductor layer is one or more of GaAs, GaP, AlInP, GaN, InGaN, AlGaN, and the material of the second-type semiconductor layer is one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, and AlGaN.

65. The micro-LED of claim 46, further comprising a connection structure that electrically connects the integrated circuit (IC) backplane with the first-type semiconductor layer.

66. The micro-LED of claim 65, wherein, The connection structure is a connection pillar or a metal bonding layer.

67. The micro-LED of claim 65, further comprising a bottom contact formed on a bottom surface of the first-type semiconductor layer, an upper surface of the connection structure is connected with the bottom contact, and a bottom surface of the connection structure is connected with the integrated circuit (IC) backplane.

68. A micro-LED array panel comprising a plurality of micro-LEDs according to any one of claims 46-67.

69. A method for fabricating a micro-LED, the method comprising: providing an epitaxial structure, wherein the epitaxial structure comprises, in order from top to bottom, a first-type semiconductor layer, a first-type cap layer, a light-emitting layer, a second-type cap layer, and a second-type semiconductor layer; bonding the epitaxial structure with an integrated circuit (IC) backplane; patterning the second-type semiconductor layer to form a mesa structure, a trench, and a fence, the mesa structure comprising one or more staircase structures; depositing a top contact on the mesa structure; performing an ion implantation process into the fence; and depositing a top conductive layer on a top surface of the second-type semiconductor layer, on the top contact, and in the trench.

70. The method of claim 69, wherein, providing the epitaxial structure further comprises: depositing a bottom contact layer on a top surface of the first-type semiconductor layer; and depositing a metal bonding layer on a top surface of the bottom contact layer.

71. The method of claim 70, wherein, bonding the epitaxial structure with the integrated circuit (IC) backplane further comprises: flipping the epitaxial structure; and bonding the metal bonding layer with a contact pad of the integrated circuit (IC) backplane.

72. The method of claim 71, wherein, when providing the epitaxial structure, the epitaxial structure is grown on a substrate.

73. The method of claim 72, wherein, bonding the epitaxial structure with the integrated circuit (IC) backplane further comprises: removing the substrate.

74. The method of claim 69, wherein, patterning the second-type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the second-type semiconductor layer to a surface of the light-emitting layer.

75. The method of claim 69, wherein, patterning the second-type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the second-type semiconductor layer and the light-emitting layer in order, and stopping the etching in the light-emitting layer.

76. The method of claim 69, wherein, patterning the second-type semiconductor layer to form the mesa structure, the trench, and the fence further comprises: etching the second-type semiconductor layer, the light-emitting layer, and the first-type semiconductor layer in order, and stopping the etching in the first-type semiconductor layer.

77. The method of claim 69, wherein, depositing the top contact further comprises: forming a protective mask to protect areas where a bottom contact is not deposited; depositing a material for the top contact on the protective mask; removing the protective mask from the second type semiconductor layer and removing the material for the top contact on the protective mask to form the top contact on the mesa structure.

78. The method of claim 69, wherein, performing the ion implantation process into the fence further comprises: forming a protective mask on areas not to be ion implanted while exposing the fence; implanting ions into the fence; and removing the protective mask.

79. The method of claim 78, wherein, implanting at an energy of 0 KeV to 500 KeV when performing the ion implantation process into the fence.

80. The method of claim 78, wherein, implanting a dose of 1E10 to 9E17 when performing the ion implantation process into the fence.

81. The method of claim 78, wherein, implanting ions into the fence selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F when performing the ion implantation process into the fence.

82. The method of claim 78, wherein, the fence has a width no greater than 50% of a diameter of the mesa structure when performing the ion implantation process into the fence.

83. The method of claim 78, wherein, the fence has a width no greater than 200 nm, the mesa structure has a diameter no greater than 2500 nm, and the second type semiconductor layer has a thickness no greater than 100 nm when performing the ion implantation process into the fence.

84. The method of claim 69, wherein, the first type semiconductor layer has a P-type conductivity and the second type semiconductor layer has an N-type conductivity; wherein the first type semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the second type semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

85. The method of claim 84, wherein, the fence comprises a light absorbing material.

86. The method of claim 85, wherein, the light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

87. A micro-LED comprising: a first type semiconductor layer; a first type cap layer formed on the first type semiconductor layer; a light emitting layer formed on the first type cap layer; a second type cap layer formed on the light emitting layer; and a second type semiconductor layer formed on the second type cap layer; wherein the first type semiconductor layer comprises a first mesa structure, a first trench extending upward through the first type semiconductor layer and upward into at least a portion of the first type cap layer, and a first ion implanted fence separated from the first mesa structure; and the first ion implanted fence is formed around the first trench and the first trench is formed around the first mesa structure; and the first ion implanted fence has a higher electrical resistance than the first mesa structure; and the first type cap layer is formed on the first type semiconductor layer; the light emitting layer is formed on the first type cap layer; the second type cap layer is formed on the light emitting layer; and the second type semiconductor layer is formed on the second type cap layer. the first type semiconductor layer comprises a first mesa structure, a first trench extending upward through the first type semiconductor layer and upward into at least a portion of the first type cap layer, and a first ion implanted fence separated from the first mesa structure; and the first ion implanted fence is formed around the first trench and the first trench is formed around the first mesa structure; and the first ion implanted fence has a higher electrical resistance than the first mesa structure; and the first type cap layer is formed on the first type semiconductor layer; the light emitting layer is formed on the first type cap layer; the second type cap layer is formed on the light emitting layer; and the second type semiconductor layer is formed on the second type cap layer. the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure; and the second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure; and the electrical resistance of the second ion implantation fence is higher than the electrical resistance of the second mesa structure; wherein the first type semiconductor layer and the second type semiconductor layer are of different conductivity types, wherein the first mesa structure comprises one or more step structures, and the second mesa structure comprises one or more step structures.

88. The micro-LED of claim 87, wherein, a top surface of the first trench does not contact a bottom of the second trench; and a portion of the light emitting layer is disposed between the top surface of the first trench and the bottom surface of the second trench.

89. The micro-LED of claim 88, wherein, a top surface of the first ion implantation fence is lower than or aligned with a top surface of the first type semiconductor layer; and a bottom surface of the second ion implantation fence is higher than or aligned with a bottom surface of the second type semiconductor layer.

90. The micro-LED of claim 87, wherein, a bottom surface of the first ion implantation fence is aligned with, higher than, or lower than a bottom surface of the first type semiconductor layer; and a top surface of the second ion implantation fence is aligned with, higher than, or lower than a top surface of the second type semiconductor layer.

91. The micro-LED of claim 87, wherein, a top surface of the first ion implantation fence is lower than a top surface of the first trench.

92. The micro-LED of claim 87, wherein, the second trench does not extend downward through the second type semiconductor layer.

93. The micro-LED of claim 92, wherein, the second trench extends downward through the second type semiconductor layer and into at least a portion of the second type cap layer, or extends downward through the second type cap layer and into at least a portion of the light emitting layer.

94. The micro-LED of claim 93, wherein, a bottom surface of the second ion implantation fence is higher than a bottom surface of the second trench.

95. The micro-LED of claim 87, wherein, a top surface of the first trench is directly connected with a bottom surface of the second trench without disposing the light emitting layer between the first trench and the second trench.

96. The micro-LED of claim 87, wherein, a width of the first trench is no more than 50% of a width of the first mesa structure; and / or, a width of the second trench is no more than 50% of a width of the second mesa structure.

97. The micro-LED of claim 96, wherein, a width of the first trench is no more than 200 nm; and / or, a width of the second trench is no more than 200 nm.

98. The micro-LED of claim 87, wherein, the first ion implantation fence comprises a first light absorbing material, and the second ion implantation fence comprises a second light absorbing material; wherein the first light absorbing material is of the same conductivity type as the first type semiconductor layer, and the second light absorbing material is of the same conductivity type as the second type semiconductor layer.

99. The micro-LED of claim 98, wherein, the first light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN; and / or the second light absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

100. The micro-LED of claim 87, wherein, The first type semiconductor layer has a thickness greater than a thickness of the light emitting layer, the second type semiconductor layer has a thickness greater than a thickness of the light emitting layer, and the first type semiconductor layer has a thickness greater than a thickness of the second type semiconductor layer.

101. The micro-LED of claim 87, further comprising a bottom isolation layer formed between a bottom surface of the first type semiconductor layer and a top surface of an integrated circuit (IC) backplane.

102. The micro-LED of claim 101, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

103. The micro-LED of claim 87, wherein, The first ion implantation fence is formed by implanting ions into at least the first type semiconductor layer, and the second ion implantation fence is formed by implanting ions into at least the second type semiconductor layer.

104. The micro-LED of claim 102, wherein, The ions implanted into the first type semiconductor layer are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and the ions implanted into the second type semiconductor layer are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

105. The micro-LED of claim 87, wherein, The first ion implantation fence has a width no greater than 50% of a diameter of the first mesa structure, and the second ion implantation fence has a width no greater than 50% of a diameter of the second mesa structure.

106. The micro-LED of claim 105, wherein, The first ion implantation fence has a width no greater than 200 nm, the first mesa structure has a diameter no greater than 2500 nm, and the first type semiconductor layer has a thickness no greater than 100 nm; and The second ion implantation fence has a width no greater than 200 nm, the second mesa structure has a diameter no greater than 2500 nm, and the second type semiconductor layer has a thickness no greater than 300 nm.

107. The micro-LED of claim 87, wherein, The first type semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN; and the second type semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

108. The micro-LED of claim 87, further comprising an integrated circuit (IC) backplane formed below the first type semiconductor layer; and a connection structure electrically connecting the IC backplane and the first type semiconductor layer.

109. The micro-LED of claim 108, wherein, The connection structure is a connection pillar or a metal bonding layer.

110. The micro-LED of claim 108, further comprising: A bottom contact formed on a bottom surface of the first type semiconductor layer, an upper surface of the connection structure is connected with the bottom contact, and a bottom surface of the connection structure is connected with the IC backplane.

111. A micro-LED array panel comprising a plurality of micro-LEDs according to any one of claims 87-110.

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