Micro-led, micro-led array panel and manufacturing method thereof

Abstract

A micro-LED includes: a first type semiconductor layer; and a light emitting layer formed on the first type semiconductor layer; wherein the first type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure; the trench extends upward through the first type semiconductor layer and upward into at least a portion of the light emitting layer; and a first ion implantation fence is formed around the trench, and the trench is formed around the mesa structure; wherein the electrical resistance of the ion implantation fence is higher than the electrical resistance of the mesa structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a light emitting diode, and more particularly to a micro light emitting diode (LED), a micro LED array panel, and a manufacturing method thereof. BACKGROUND

[0002] Inorganic micro-pixel light emitting diodes (also referred to as micro light emitting diodes, micro-LEDs, or μ-LEDs) are increasingly important due to their use in various applications including self-emissive micro-displays, visible light communication, and optogenetics. Micro-LEDs exhibit higher output performance than conventional LEDs due to better strain relaxation, improved light extraction efficiency, and uniform current spreading. Micro-LEDs also exhibit improved thermal effects, fast response rates, greater operating temperature ranges, higher resolution, color gamut, and contrast, and lower power consumption and can operate at higher current densities compared to conventional LEDs.

[0003] Inorganic micro-LEDs are typically III-V epitaxial layers formed into multiple mesas. Spaces are formed between adjacent micro-LEDs in conventional micro-LED structures to avoid diffusion of carriers in the epitaxial layer from one mesa to an adjacent mesa. However, the spaces formed between adjacent micro-LEDs can reduce the effective light emitting area and lower light extraction efficiency. If there are no spaces between adjacent micro-LEDs, the effective light emitting area will increase and carriers in the epitaxial layer will laterally diffuse to adjacent mesas, which reduces the light emitting efficiency of the micro-LEDs. Furthermore, if no spaces are formed between adjacent mesas, crosstalk will occur between adjacent micro-LEDs, which will interfere with the operation of the micro-LEDs.

[0004] However, smaller micro-LEDs with higher current densities will experience redshift, lower maximum efficiency, and non-uniform emission at high current densities due to manufacturing process damage that causes degraded electrical injection. Furthermore, peak external quantum efficiency (EQE) and internal quantum efficiency (IQE) are greatly reduced as chip size decreases. Reduced EQE occurs due to non-radiative recombination caused by etching damage, while reduced IQE is due to poor current injection and electron leakage current of the micro-LEDs.

[0005] The above discussion merely provides a help for understanding the technical problems overcome by the present disclosure and does not constitute an acknowledgement that the above is prior art. SUMMARY

[0006] Embodiments of the present disclosure provide a micro-LED. The micro-LED includes: a first type semiconductor layer; and a light emitting layer formed on the first type semiconductor layer; wherein the first type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extends upward through the first type semiconductor layer and extends upward into at least a portion of the light emitting layer; and the ion implantation fence is formed around the trench; and the trench is formed around the mesa structure; wherein the resistance of the ion implantation fence is higher than the resistance of the mesa structure.

[0007] Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method includes: providing an epitaxial structure, wherein the epitaxial structure includes, in order from top to bottom, a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer; patterning the first type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a bottom contact on the mesa structure; and performing an ion implantation process into the fence to form a first ion implantation fence.

[0008] Embodiments of the present disclosure provide a micro-LED. The micro-LED includes: a first type semiconductor layer; and a light emitting layer formed on the first type semiconductor layer; a second type semiconductor layer formed on the light emitting layer; an integrated circuit (IC) backplane formed at a bottom surface of the first type semiconductor layer; wherein the second type semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extends downward through the second type semiconductor layer and extends downward into at least a portion of the light emitting layer; and the ion implantation fence is formed around the trench, and the trench is formed around the mesa structure, wherein the resistance of the ion implantation fence is higher than the resistance of the mesa structure.

[0009] Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method includes: providing an epitaxial structure, wherein the epitaxial structure includes, in order from top to bottom, a first type semiconductor layer, a light emitting layer, and a second type semiconductor layer; bonding the epitaxial structure with an integrated circuit (IC) backplane; patterning the second type semiconductor layer to form a mesa structure, a trench, and a fence; depositing a top contact on the mesa structure; performing an ion implantation process into the fence; depositing a top conductive layer on a top surface of the second type semiconductor layer, on the top contact, and in the trench.

[0010] Embodiments of the present disclosure provide a micro-LED. The micro-LED comprises: a first type semiconductor layer; a light emitting layer formed on the first type semiconductor layer; and a second type semiconductor layer formed on the light emitting layer; wherein the first type semiconductor layer comprises a first mesa structure, a first trench, and a first ion implantation fence separated from the first mesa structure, the first trench extends upward through the first type semiconductor layer and upward into at least a portion of the light emitting layer; the first ion implantation fence is formed around the first trench, and the first trench is formed around the first mesa structure; wherein the electrical resistance of the first ion implantation fence is higher than the electrical resistance of the first mesa structure; and the second type semiconductor layer comprises a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure, the second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure; wherein the electrical resistance of the second ion implantation fence is higher than the electrical resistance of the second mesa structure.

[0011] Embodiments of the present disclosure provide a method for manufacturing a micro-LED. The method comprises: process I comprising patterning a first type semiconductor layer and implanting first ions into the first type semiconductor layer; and process II comprising patterning a second type semiconductor layer and implanting second ions into the second type semiconductor layer.

[0012] Embodiments of the present disclosure provide a micro-LED array panel. The micro-LED array panel comprises a plurality of the above micro-LEDs. BRIEF DESCRIPTION OF DRAWINGS

[0013] Embodiments and various aspects of the present disclosure are illustrated in the following detailed description and in the accompanying drawings. Various features shown in the drawings are not drawn to scale.

[0014] FIGS. 1A-1F is a structural diagram showing a side cross-sectional view of various different variants of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0015] FIG. 2 is a structural diagram showing a bottom view of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0016] FIG. 3 is a structural diagram showing a side cross-sectional view of another variant of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0017] FIG. 4 is a structural diagram showing a side cross-sectional view of another variant of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0018] FIG. 5 A flowchart is shown of a method for manufacturing a first exemplary microLED according to some embodiments of this disclosure.

[0019] FIGS. 6A-6J This illustrates some embodiments according to this disclosure. FIG. 5 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at each step of the method shown.

[0020] FIG. 7 This illustrates some embodiments according to this disclosure. FIG. 1A A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0021] FIG. 8 This illustrates some embodiments according to this disclosure. FIG. 7 The structural diagram of the bottom view of adjacent micro-LEDs.

[0022] FIG. 9 This illustrates some embodiments according to this disclosure. FIG. 3 A structural diagram showing a side cross-sectional view of an adjacent microLED within a microLED.

[0023] FIGS. 10A-10F This is a structural diagram showing a side cross-sectional view of various different variants of a second exemplary microLED according to some embodiments of this disclosure.

[0024] FIG. 11 This is a top view structural diagram showing a second exemplary microLED according to some embodiments of this disclosure.

[0025] FIG. 12A and FIG. 12B This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure.

[0026] FIG. 13 This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure.

[0027] FIG. 14 A flowchart is shown of a method for manufacturing a second exemplary microLED according to some embodiments of this disclosure.

[0028] FIGS. 15A-15F This illustrates some embodiments according to this disclosure. FIG. 14 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at each step of the method shown.

[0029] FIG. 16 is a structural diagram illustrating a top view of adjacent micro-LEDs in the third exemplary micro-LED according to some embodiments of the present disclosure. FIG. 10C is a structural diagram illustrating a side cross-sectional view of adjacent micro-LEDs of the micro-LED in the third exemplary micro-LED according to some embodiments of the present disclosure.

[0030] FIG. 17 is a structural diagram illustrating a top view of adjacent micro-LEDs in the third exemplary micro-LED according to some embodiments of the present disclosure. FIG. 16 is a structural diagram illustrating a side cross-sectional view of adjacent micro-LEDs of the micro-LED in the third exemplary micro-LED according to some embodiments of the present disclosure.

[0031] FIG. 18 is a structural diagram illustrating a top view of adjacent micro-LEDs in the third exemplary micro-LED according to some embodiments of the present disclosure. FIG. 12B is a structural diagram illustrating a side cross-sectional view of adjacent micro-LEDs of the micro-LED in the third exemplary micro-LED according to some embodiments of the present disclosure.

[0032] FIGS. 19A-19F is a structural diagram illustrating a side cross-sectional view of various different variants of the third exemplary micro-LED according to some embodiments of the present disclosure.

[0033] FIG. 20 is a structural diagram illustrating a side cross-sectional view of another variant of the third exemplary micro-LED according to some embodiments of the present disclosure.

[0034] FIG. 21 is a flowchart illustrating a method for manufacturing the third exemplary micro-LED according to some embodiments of the present disclosure.

[0035] FIGS. 22A-22D is a structural diagram illustrating a top view of adjacent micro-LEDs in the third exemplary micro-LED according to some embodiments of the present disclosure. FIG. 21 is a structural diagram illustrating a side cross-sectional view of the micro-LED fabrication process at steps 2110 to 2113 of the method shown in FIG. 21.

[0036] FIG. 23A and FIG. 23B is a structural diagram illustrating a side cross-sectional view of other variants of the third exemplary micro-LED according to some embodiments of the present disclosure.

[0037] FIG. 24 is a structural diagram illustrating a top view of adjacent micro-LEDs in the third exemplary micro-LED according to some embodiments of the present disclosure. FIG. 23A is a structural diagram illustrating a side cross-sectional view of adjacent micro-LEDs of the micro-LED in the third exemplary micro-LED according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to the example embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers represent the same or similar elements between the several drawings. The implementation set forth in the following description of example embodiments does not represent all of the implementations consistent with the present disclosure. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the present disclosure as recited in the appended claims. Specific aspects of the present disclosure are described in further detail below. To the extent not inconsistent with the text of this document, the terminology used herein merges with terminology used in the documents incorporated by reference.

[0039] The present disclosure provides a micro-LED which can avoid non-radiative recombination at the sidewall of the mesa according to the structure of the semiconductor layer and the continuously formed light emitting layer. In addition, compared with the conventional micro-LED, the space between adjacent mesas can be greatly reduced due to the ion implantation fence. Therefore, the integration of the micro-LED in the chip is increased, and the effective light emitting efficiency is improved. In addition, the micro-LED provided by the present disclosure can also increase the effective light emitting area and improve the image quality.

[0040] Embodiment 1

[0041] FIGS. 1A-1F is a structural diagram showing side cross-sectional views of various different variants of a first exemplary micro-LED according to some embodiments of the present disclosure.

[0042] Referring to FIGS. 1A-1F The micro-LED includes a first type semiconductor layer 110, a light emitting layer 130, and a second type semiconductor layer 120. The light emitting layer 130 is formed on the first type semiconductor layer 110, and the second type semiconductor layer 120 is formed on the light emitting layer 130. The thickness of the first type semiconductor layer 110 is greater than the thickness of the second type semiconductor layer 120.

[0043] The conduction type of the first type semiconductor layer 110 is different from the conduction type of the second type semiconductor layer 120. In some embodiments, the conduction type of the first type semiconductor layer 110 is P-type, and the conduction type of the second type semiconductor layer 120 is N-type. In some embodiments, the conduction type of the second type semiconductor layer 120 is P-type, and the conduction type of the first type semiconductor layer 110 is N-type. For example, the material of the first type semiconductor layer 110 can be selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 120 can be selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0044] The first-type semiconductor layer 110 includes a mesa structure 111, a trench 112, and an ion implantation fence 113. The ion implantation fence 113 is separated from the mesa structure 111 by the trench 112. The trench 112 and the ion implantation fence 113 are annular around the mesa structure 111.

[0045] The ion implantation fence 113 includes a light-absorbing material for absorbing light from the mesa structure 111. The light-absorbing material has the same conductivity type as the first-type semiconductor layer 110. Preferably, the light-absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. In addition, the ion implantation fence 113 is formed at least by implanting ions into the first-type semiconductor layer 110. Preferably, the ions implanted into the first-type semiconductor layer 110 to form the ion implantation fence 113 are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0046] Furthermore, the width of the ion implantation fence 113 is no greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is no greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the ion implantation fence 113 is no greater than 200 nm, the diameter of the mesa structure 111 is no greater than 2500 nm, and the thickness of the first-type semiconductor layer 110 is no greater than 300 nm.

[0047] In some embodiments, the width of the trench 112 is no greater than 50% of the diameter of the mesa structure 111. In some embodiments, the width of the ion implantation fence 113 is no greater than 10% of the diameter of the mesa structure 111. Preferably, the width of the trench 112 is no greater than 200 nm.

[0048] As shown in FIG. 1A, in some embodiments, the trench 112 extends upward through the first-type semiconductor layer 110 and reaches the light-emitting layer 130. FIG. 1A As shown in FIG. 1A, in some embodiments, the trench 112 extends upward through the first-type semiconductor layer 110 and reaches the light-emitting layer 130. FIG. 2 is a structural diagram showing a bottom view of a first exemplary micro-LED according to some embodiments of the present disclosure. FIG. 1A is a structural diagram showing a bottom view of a first exemplary micro-LED according to some embodiments of the present disclosure. FIG. 2 is a structural diagram showing a bottom view of a first-type semiconductor layer 110, in which an ion implantation fence 113 is separated from a mesa structure 111 by a trench. The ion implantation fence 113 is formed around the trench, and the trench is formed around the mesa structure 111. Since the trench extends upward through the first-type semiconductor layer 110 and reaches a light-emitting layer 130, the light-emitting layer 130 can be seen through the trench in the bottom view.

[0049] There is no limitation on the depth of the trench 112. The trench 112 can extend upward through the first-type semiconductor layer 110, the light-emitting layer 130, and even into the second-type semiconductor layer 120. In FIG. 1B the variant shown in FIG. 1C, the trench 112 extends upward through the first-type semiconductor layer 110 and into the interior of the light-emitting layer 130. In some embodiments, the trench 112 can extend upward through the first-type semiconductor layer 110 and the light-emitting layer 130. In FIG. 1C the variant shown in FIG. 1D, the trench 112 extends upward through the first-type semiconductor layer 110 and the light-emitting layer 130, and further extends upward into the interior of the second-type semiconductor layer 120. Thus, in some embodiments, the trench 112 can extend upward through the first-type semiconductor layer 110, the light-emitting layer 130, and into the second-type semiconductor layer 120.

[0050] In the first exemplary micro-LED, the top surface of the ion implantation fence 113 is lower than the top surface of the first-type semiconductor layer 110. Thus, the ion implantation fence 113 cannot reach the light-emitting layer 130. The top surface of the ion implantation fence 113 can be formed at any position within the first-type semiconductor layer 110. Preferably, as shown in FIG. 1A the top surface of the ion implantation fence 113 is lower than the top surface of the trench 112.

[0051] In addition, the bottom surface of the ion implantation fence 113 can be formed at any position higher or lower than the bottom surface of the first-type semiconductor layer 110. Preferably, the bottom surface of the ion implantation fence 113 is aligned with the bottom surface of the first-type semiconductor layer 110. As FIG. 1D shown in FIG. 1E, in some embodiments, the bottom surface of the ion implantation fence 113 is higher than the bottom surface of the first-type semiconductor layer 110. As FIG. 1E shown in FIG. 1F, in some embodiments, the bottom surface of the ion implantation fence 113 is lower than the bottom surface of the first-type semiconductor layer 110.

[0052] In some embodiments, as FIG. 1F shown in FIG. 1G, the mesa structure 111 includes a stepped structure 111a. The mesa structure 111 can have one or more stepped structures.

[0053] FIG. 3 is a structural diagram showing another variant of the first exemplary micro-LED according to some embodiments of the present disclosure. As FIG. 3 shown in FIG. 1H, the micro-LED further includes a bottom isolation layer 140 filled in the trench 112. Preferably, the material of the bottom isolation layer 140 is selected from one or more of SiO2, SiN x , Al2O3, AIN, HfO2, TiO2, or ZrO2.

[0054] In the present embodiment, an integrated circuit (IC) backplane 190 is formed underneath the first-type semiconductor layer 110 and is electrically connected with the first-type semiconductor layer 110 via the connection structure 150. As shown, the connection structure 150 is a connection pillar. FIG. 3

[0055] The micro-LED further includes a bottom contact 160. The bottom contact 160 is formed at the bottom of the first-type semiconductor layer 110. The upper surface of the connection structure 150 is connected with the bottom contact 160, and the bottom surface of the connection structure 150 is connected with the IC backplane 190. As shown, the bottom contact 160 protrudes from the first-type semiconductor layer 110 as a bottom contact of the micro-LED. FIG. 3

[0056] In some embodiments, the micro-LED further includes a top contact 180 and a top conductive layer 170. The top contact 180 is formed on the top of the second-type semiconductor layer 120. The top conductive layer 170 is formed on the top of the second-type semiconductor layer 120 and the top contact 180. The conductive type of the top contact 180 is the same as the conductive type of the second-type semiconductor layer 120. For example, in some embodiments, the conductive type of the second-type semiconductor layer 120 is N-type, and the conductive type of the top contact 180 is N-type. In some embodiments, the conductive type of the second-type semiconductor layer 120 is P-type, and the conductive type of the top contact 180 is P-type. The top contact 180 is made of a metal or a metal alloy, such as AuGe, AuGeNi, etc. The top contact 180 is used to form an ohmic contact between the top conductive layer 170 and the second-type semiconductor layer 120 to optimize the electrical properties of the micro-LED. The diameter of the top contact 180 is about 20 nm to 50 nm, and the thickness of the top contact 180 is about 10 nm to 20 nm.

[0057] FIG. 4 is a structural diagram showing a side cross-sectional view of another variant of the first exemplary micro-LED according to some embodiments of the present disclosure. As shown, the connection structure 150 is a metal bonding layer for bonding the micro-LED with the IC backplane 190. In addition, in this variant, the bottom contact 160 is a bottom contact layer. FIG. 4

[0058] FIG. 5 is a flowchart showing a method 500 for fabricating the first exemplary micro-LED (e.g., the micro-LED shown in FIG. 3 is a flowchart showing a method 500 for fabricating the first exemplary micro-LED (e.g., the micro-LED shown in FIGS. 6A-6J is a flowchart showing a method 500 for fabricating the first exemplary micro-LED (e.g., the micro-LED shown in​​​FIG. 5 The method 500 is shown in a structure diagram of a side cross-sectional view of the micro-LED manufacturing process at each step (i.e., steps 501-510) of the method 500.

[0059] Referring to FIG. 5 and FIGS. 6A-6J In step 501, an epitaxial structure is provided. As shown in FIG. 6A , the epitaxial structure includes, in order from top to bottom, a first-type semiconductor layer 610, a light-emitting layer 630, and a second-type semiconductor layer 620. The epitaxial structure is grown on a substrate 600. The substrate 600 can be GaN, GaAs, or the like.

[0060] In step 502: referring to FIG. 6B , the first-type semiconductor layer 610 is patterned to form mesa structures 611, trenches 613, and fences 613'.

[0061] As shown in FIG. 6B , the first-type semiconductor layer 610, the light-emitting layer 630, and the second-type semiconductor layer 620 are etched. The etching stops in the second-type semiconductor layer 620. Thus, the top surface of the trench 612 is located within the second-type semiconductor layer 620.

[0062] In some embodiments, the first-type semiconductor layer 610 is etched and the etching stops on the light-emitting layer 630 to avoid etching the light-emitting layer 630 in the patterning process. Referring back to FIG. 1A , the top of the trench 112 contacts the bottom surface of the light-emitting layer 130, and the light-emitting layer 130 is not etched in this variant.

[0063] In some embodiments, step 502 further includes etching the first-type semiconductor layer and the light-emitting layer in order and stopping the etching in the light-emitting layer. Referring back to FIG. 1B , the top surface of the trench 112 can be at any location within the light-emitting layer 130.

[0064] In some embodiments, step 502 further includes etching the first-type semiconductor layer 610, the light-emitting layer 630, and the second-type semiconductor layer 620 in order and stopping the etching in the second-type semiconductor layer 620. Referring back to FIG. 1C , the trench 112 extends upward through the light-emitting layer 130, and the top surface of the trench 121 can be at any location within the second-type semiconductor layer 120.

[0065] The first-type semiconductor layer 610, the light-emitting layer 630, and the second-type semiconductor layer 620 are etched by a conventional dry etching process, such as a plasma etching process, as can be appreciated by those skilled in the art.

[0066] In step 503: referring toFIG. 6C A bottom contact 660 is deposited on the mesa structure 611.

[0067] Before depositing the bottom contact 660, a first protective mask (not shown) is used to protect the area where the bottom contact 660 will not be formed. Then, the material of the bottom contact 660 is deposited on the first protective mask and on the first type semiconductor layer 610 by a conventional vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. After the deposition process, the first protective mask is removed from the first type semiconductor layer 610, and the material on the first protective mask is also removed with the first protective mask to form the bottom contact 660 on the mesa structure 611.

[0068] In step 504: referring to FIG. 6D , an ion implantation process is performed into the fence 613'. The arrow shows the direction of the ion implantation process.

[0069] In combination FIG. 6C , ions are implanted into the fence 613' (as shown in FIG. 6C ) by the ion implantation process to form an ion implanted fence 613 (as shown in FIG. 6D ), as shown in FIG. 6D . Before the ion implantation process, a second protective mask (not shown) is formed on the area where the ions are to be implanted. Then, the ions are implanted into the exposed fence 613'. Subsequently, the second protective mask is removed by a conventional chemical etching process, which can be understood by those skilled in the art. Preferably, the implantation energy is 0 Kev to 500 Kev, and the implantation dose is 1E10 to 9E17.

[0070] In step 505: referring to FIG. 6E , a bottom isolation layer 640 is deposited on the entire substrate 600. That is, the first type semiconductor layer 610 and the bottom contact 660 are covered by the bottom isolation layer 640, and the trench 612 is filled by the bottom isolation layer 640. The bottom isolation layer 640 is deposited by a conventional chemical vapor deposition process.

[0071] The bottom isolation layer 640 is formed on the sidewall and the bottom surface of the trench 612. As shown in FIG. 6E , the bottom isolation layer 640 is filled into the trench 612. Therefore, the bottom isolation layer 640 is formed on the sidewall of the first type semiconductor layer 610, the mesa structure 611, the light emitting layer 630, and the second type semiconductor layer 620 in the trench 612. In some embodiments, referring back to FIG. 1AThe bottom isolation layer is formed on the sidewalls of the mesa structure 111, the first-type semiconductor layer 110, and the ion implantation fence 113, and on the surface of the light-emitting layer 130 in the trench 112. In some embodiments, referring back to FIG. 1B The bottom isolation layer is formed on the sidewalls of the mesa structure 111, the first-type semiconductor layer 110, and the ion implantation fence 113, and on the surface of the light-emitting layer 130 in the trench 112. In some embodiments, referring back to

[0072] In step 506: referring back to FIG. 6F The bottom isolation layer 640 is patterned to expose the bottom contact 660. The bottom isolation layer 640 is etched by a photo-etching process and a dry etching process.

[0073] In step 507: referring back to FIG. 6G A metal material 650’ is deposited on the entire substrate 600. That is, the metal material 650’ is deposited on the bottom isolation layer 640 and the bottom contact 660. The metal material is deposited by a conventional physical vapor deposition method.

[0074] In step 508: referring back to FIG. 6H A top portion of the metal material 650’ is ground to a top portion of the bottom isolation layer 640 to form a connection structure 650 such as a connection pillar. In some embodiments, the metal material is ground by a chemical mechanical polishing (CMP) process.

[0075] In step 509: referring back to FIG. 6I The connection pillar 650 is bonded with an IC backplate 690. First, the epitaxial structure is flipped. Then, the connection pillar 650 is bonded with a contact pad of the IC backplate 690 by a metal bonding process. Then, the substrate 600 is removed by a conventional separation method such as a laser lift-off method or a chemical etching method. The arrow shows the removal direction of the substrate 600.

[0076] In step 510: referring back to FIG. 6J The top contact 680 and the top conductive layer 670 can be sequentially deposited on the second-type semiconductor layer 620 by a conventional vapor deposition method.

[0077] Some embodiments of the present disclosure further provide a micro-LED array panel. The micro-LED array panel includes a plurality of micro-LEDs as described above and shown in FIGS. 1A-1F 、 FIG. 3 and FIG. 4 The micro-LEDs can be arranged into an array in the micro-LED array panel.

[0078] FIG. 7 is a diagram showing a micro-LED array panel in some embodiments according to the present disclosure.FIG. 1C A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) FIG. 7 As shown, the micro LED array panel includes a first type semiconductor layer 710 continuously formed in the micro LED array panel, a light-emitting layer 730 continuously formed on the first type semiconductor layer 710, and a second type semiconductor layer 720 continuously formed on the light-emitting layer 730.

[0079] The conductivity type of the first type semiconductor layer 710 is different from that of the second type semiconductor layer 720. For example, in some embodiments, the conductivity type of the first type semiconductor layer 710 is P-type, and the conductivity type of the second type semiconductor layer 720 is N-type. In some embodiments, the conductivity type of the second type semiconductor layer 720 is P-type, and the conductivity type of the first type semiconductor layer 710 is N-type. The thickness of the first type semiconductor layer 710 is greater than the thickness of the second type semiconductor layer 720. In some embodiments, the material of the first type semiconductor layer 710 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type semiconductor layer 720 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0080] The first type semiconductor layer 710 includes multiple mesa structures 711, multiple trenches 712, and multiple ion implantation fences 713 separated from the mesa structures 711 by the trenches 712. The top surface of the ion implantation fence 713 is lower than the top surface of the first type semiconductor layer 710. Therefore, the top surface of the trenches 712 does not contact the light-emitting layer 730. The relationship between the top surface of the ion implantation fence 713, the top surface of the first type semiconductor layer 710, and the top surface of the trenches 712 can be referenced. FIGS. 1B-1D The micro-LED shown will not be described further here. Additionally, the relationship between the bottom surface of the ion implantation fence 713 and the bottom surface of the first type semiconductor layer 710 can be found in [reference needed]. FIGS. 1D-1E The micro-LEDs shown will not be described further here. In another embodiment, the mesa structure may have one or more stepped structures, such as... FIG. 1F This is what you see in the tabletop structure shown.

[0081] FIG. 8 This illustrates some embodiments according to this disclosure. FIG. 7 A structural diagram of the bottom view of adjacent micro-LEDs. (See diagram below.) FIG. 8As shown, an ion implantation fence 713 is formed around a trench 712 and between adjacent mesa structures 711. Furthermore, in each micro-LED, an ion implantation fence 713 is formed around a trench 712, and the trench 712 is formed around a mesa structure 711. The resistance of the ion implantation fence 713 is higher than the resistance of the mesa structure 711.

[0082] In some embodiments, the space between adjacent sidewalls of adjacent mesa structures of mesa structure 711 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of mesa structure 711 is no greater than 50% of the diameter of mesa structure 711. In some embodiments, the space between adjacent sidewalls of mesa structure 711 is no greater than 30% of the diameter of mesa structure 711. Preferably, the space between adjacent sidewalls of mesa structure 711 is no greater than 600 nm. Additionally, in some embodiments, the width of ion implantation fence 713 can be adjusted. For example, the width of ion implantation fence 713 may be no greater than 50% of the diameter of mesa structure 711. In some embodiments, the width of ion implantation fence 713 may be no greater than 10% of the diameter of mesa structure 711. Preferably, in a micro-LED array panel, the width of ion implantation fence 713 is no greater than 200 nm.

[0083] FIG. 9 This illustrates some embodiments of a micro LED array panel according to this disclosure. FIG. 3 A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) FIG. 9 As shown, the micro-LED array panel further includes a bottom isolation layer 940 formed on the first type semiconductor layer 910 and filled in a trench 912. Preferably, in some embodiments, the material of the bottom isolation layer 940 is one or more of SiO2, SiNx, or Al2O3, AlN, HfO2, TiO2, or ZrO2. Additionally, an IC backplane 990 is continuously formed under the first type semiconductor layer 910 and electrically connected to the first type semiconductor layer 910 via a connection structure 950. The micro-LED array panel further includes a bottom contact 960 formed at the bottom of the first type semiconductor layer 910. Further details of the bottom isolation layer 940, IC backplane 990, bottom contact 960, and connection structure 950 are provided in [details omitted]. FIG. 3 and FIG. 4 The micro-LED is shown as corresponding to the bottom isolation layer 140, IC backplane 190, bottom contact 160 and connection structure 150, which will not be described further.

[0084] In the present embodiment, the micro LED array panel further includes a top contact 980 and a top conductive layer 970. The top contact 980 is formed on top of the second type semiconductor layer 920. The top conductive layer 970 is formed on top of the second type semiconductor layer 920 and the top contact 980. The conductive type of the top contact 980 is the same as the conductive type of the second type semiconductor layer 920. For example, in some embodiments, the conductive type of the second type semiconductor layer 920 is N-type, and the conductive type of the top contact 980 is N-type. In some embodiments, the conductive type of the second type semiconductor layer 920 is P-type, and the conductive type of the top contact 980 is P-type. The top contact 980 is made of a metal or a metal alloy such as AuGe, AuGeNi, etc. The top contact 980 is used to form an ohmic contact between the top conductive layer 970 and the second type semiconductor layer 920 to optimize the electrical characteristics of the micro LED. The diameter of the top contact 980 is about 20-50 nm, and the thickness of the top contact 980 is about 10-20 nm.

[0085] The micro LED array panel can be manufactured by the method 500 as shown, which will not be further described. FIG. 5

[0086] Embodiment 2

[0087] FIGS. 10A-10F is a structural diagram showing side cross-sectional views of various different variants of a second exemplary micro LED according to some embodiments of the present disclosure. As shown in FIG. 10A The micro LED includes a first type semiconductor layer 1010, a light emitting layer 1030, and a second type semiconductor layer 1020. The conductive type of the first type semiconductor 1010 is different from the conductive type of the second type semiconductor layer 1020. For example, the conductive type of the first type semiconductor 1010 is P-type, and the conductive type of the second type semiconductor layer 1020 is N-type.

[0088] The second type semiconductor layer 1020 includes a mesa structure 1021, a trench 1022, and an ion implantation fence 1023 separated from the mesa structure 1021. The bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the second type semiconductor layer 1020. In addition, the ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021. The electrical resistance of the ion implantation fence 1023 is higher than the electrical resistance of the mesa structure 1021.

[0089] ​The ion implantation fence 1023 includes a light absorbing material for absorbing light from the mesa structure 1021. The light absorbing material is of the same conductivity type as the second type semiconductor layer 1020. Preferably, the light absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or p-AlGaN. In addition, the ion implantation fence 1023 is formed at least by implanting ions into the second type semiconductor layer 1020. Preferably, the ion type implanted into the second type semiconductor layer 1020 is selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

[0090] In addition, the width of the ion implantation fence 1023 is no greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the ion implantation fence 1023 is no greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the ion implantation fence 1023 is no greater than 200 nm. The diameter of the mesa structure 1021 is no greater than 2500 nm. The thickness of the second type semiconductor layer 1020 is no greater than 100 nm.

[0091] In some embodiments, the width of the trench 1022 is no greater than 50% of the diameter of the mesa structure 1021. In some embodiments, the width of the trench 1022 is no greater than 10% of the diameter of the mesa structure 1021. Preferably, the width of the second trench 1022 is no greater than 200 nm.

[0092] FIG. 11 is a structural diagram showing a top view of a second exemplary micro-LED according to some embodiments of the present disclosure. FIG. 10A is a structural diagram showing a top view of a second exemplary micro-LED according to some embodiments of the present disclosure. FIG. 11 is a top view showing the second type semiconductor layer 1020, in which the ion implantation fence 1023 is separated from the mesa structure 1021 by the trench 1022. FIG. 11 is a top view showing the light emitting layer 1030 at the bottom of the trench 1022. The ion implantation fence 1023 is formed around the trench 1022, and the trench 1022 is formed around the mesa structure 1021.

[0093] There is no limitation on the depth of trench 1022. In some embodiments, trench 1022 may extend downward through the bottom surface of the second type semiconductor layer 1020, but not reach the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and reach the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through the second type semiconductor layer 1020 and extend into the interior of the light-emitting layer 1030. In some embodiments, trench 1022 may extend downward through both the second type semiconductor layer 1020 and the light-emitting layer 1030. Furthermore, trench 1022 may extend downward through both the second type semiconductor layer 1020 and the light-emitting layer 1030, and extend downward into the interior of the first type semiconductor layer 1010.

[0094] In some implementation schemes, such as FIG. 10A As shown, trench 1022 extends downward through the bottom surface of the second type semiconductor layer 1020 and reaches the light-emitting layer 1030. The bottom surface of trench 1022 is aligned with the bottom of the second type semiconductor layer 1020. Therefore, the bottom surface of trench 1022 exposes the light-emitting layer 1030.

[0095] In some implementation schemes, such as FIG. 10B As shown, trench 1022 extends downward through the second type semiconductor layer 1020 and into the interior of the light-emitting layer 1030. In some embodiments, such as FIG. 10C As shown, the trench 1022 extends downward through the second type semiconductor layer 1020 and the light-emitting layer 1030, and extends downward into the interior of the first type semiconductor layer 1010.

[0096] In some embodiments, the bottom surface of the ion implantation fence 1023 is higher than the bottom surface of the trench 1022. The bottom surface of the ion implantation fence 1023 can be formed at any location within the first type semiconductor layer 1010.

[0097] Additionally, in some embodiments, the top surface of the ion implantation fence 1023 can be formed at any location. Preferably, the top surface of the ion implantation fence 1023 is aligned with the top surface of the second type semiconductor layer 1020. In some embodiments, such as FIG. 10D As shown, the top surface of the ion implantation fence 1023 is higher than the top surface of the second type semiconductor layer 1020. In some embodiments, such as FIG. 10E As shown, the top surface of the ion implantation fence 1023 is lower than the top surface of the second type semiconductor layer 1020.

[0098] In some implementation schemes, such as FIG. 10FAs shown, the platform structure 1021 includes a stepped structure 1021a. In some embodiments, the platform structure 1021 may have multiple stepped structures.

[0099] FIG. 12A and FIG. 12B This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure. FIG. 12A As shown, the micro-LED further includes a bottom isolation layer 1040 formed beneath the first type of semiconductor layer 1010. Preferably, the material of the bottom isolation layer 1040 is selected from SiO2 and SiN. x Or one or more of Al2O3.

[0100] In this embodiment, an integrated circuit (IC) backplane 1090 is formed beneath a first type semiconductor layer 1010 and is electrically connected to the first type semiconductor layer 1010 via an interconnect structure 1050. For example... FIG. 12A As shown, the connection structure 1050 serves as a connection pillar. The micro-LED further includes a bottom contact 1060 formed at the bottom of the first type semiconductor layer 1010. The upper surface of the connection structure 1050 is connected to the bottom contact 1060, and the bottom of the connection structure 1050 is connected to the IC backplane 1090. In this embodiment, the bottom contact 1060 protrudes from the first type semiconductor layer 1010, serving as the bottom contact of the micro-LED.

[0101] In some embodiments, the microLED further includes a top contact 1080 and a top conductive layer 1070. The top contact 1080 is formed on top of the second type semiconductor layer 1020. The top conductive layer 1070 is formed on the top surface of the second type semiconductor layer 1020 and the top surface of the top contact 1080, and covers the sidewalls and bottom of the trench 1022. Preferably, a dielectric layer 1071 is formed on the sidewalls and bottom surface of the trench 1022. The conductivity type of the top contact 1080 is the same as that of the second type semiconductor layer 1020. For example, the conductivity type of the second type semiconductor layer 1020 is N-type, and the conductivity type of the top contact 1080 is also N-type. The top contact 1080 is made of metal or a metal alloy (such as AuGe, AuGeNi, etc.). The top contact 1080 is used to form an ohmic contact between the top conductive layer 1070 and the second type semiconductor layer 1020 to optimize the electrical properties of the microLED. The diameter of the top contact 1080 is approximately 20 nm to 50 nm, and the thickness of the top contact 1080 is approximately 10 nm to 20 nm.

[0102] refer to FIG. 12BThe connection structure 1050 may be a metal bonding layer for bonding the micro-LED to the IC backplane 1090. Additionally, in this embodiment, the bottom contact 1060 is a bottom contact layer.

[0103] FIG. 13 This is a structural diagram showing a side cross-sectional view of another variant of a second exemplary microLED according to some embodiments of this disclosure. FIG. 13 As shown, dielectric layer 1071 fills the second trench 1022. Top conductive layer 1070 is formed on top of the second type semiconductor layer 1020, on top of the top contact 1080, and on the top surface of dielectric layer 1071. In some embodiments, dielectric layer 1071 may be formed on the top surface of the second type semiconductor layer.

[0104] FIG. 14 Some embodiments of the present disclosure are shown for manufacturing a second exemplary microLED (e.g., FIG. 12B The flowchart of method 1400 (shown for miniature LEDs) is shown. FIG. 14 As shown, the method for manufacturing micro LEDs includes steps 1401 to 1406. FIGS. 15A-15F This illustrates some embodiments according to this disclosure. FIG. 14 A structural diagram of a side cross-sectional view of the micro-LED manufacturing process at each step (i.e., steps 1401 to 1406) of the method 1400 shown.

[0105] refer to FIG. 14 and FIGS. 15A-15F In step 1401: an epitaxial structure is provided. For example... FIG. 15A As shown, the epitaxial structure, from top to bottom, includes a first type semiconductor layer 1510, a light-emitting layer 1530, and a second type semiconductor layer 1520. The epitaxial structure is grown on a substrate 1500. The substrate 1500 can be GaN, GaAs, etc.

[0106] Preferably, before flipping the epitaxial structure, a bottom contact layer 1560, serving as a bottom contact, is deposited on the top surface of the first type semiconductor layer 1510. Then, a metal bonding layer, serving as a connection structure 1550, is deposited on the top surface of the bottom contact layer 1560.

[0107] In step 1402: Reference FIG. 15B The epitaxial structure is bonded to the IC backplane 1590. First, the epitaxial structure is flipped. Then, the connection structure 1550 is bonded to the contact pads of the IC backplane 1590 using a metal bonding process. Finally, the substrate 1500 is removed using a conventional separation method (such as laser lift-off) or a chemical etching method. The arrows indicate the removal direction of the substrate 1500.

[0108] In step 1403: referring to FIG. 15C , the second-type semiconductor layer 1520 is patterned to form the mesa structure 1521, the trench 1522, and the fence 1523'.

[0109] In some embodiments, the second-type semiconductor layer 1520 is etched down to the surface of the light-emitting layer 1530 to avoid the light-emitting layer 1530 being etched in the patterning process. For example, referring back to FIG. 10A , the bottom surface of the trench 1022 exposes the light-emitting layer 1030.

[0110] In some embodiments, step 1403 further comprises: etching the second-type semiconductor layer 1520 and the light-emitting layer 1530 sequentially, and stopping the etching process in the light-emitting layer 1530. For example, referring back to FIG. 10B , the bottom of the trench 1022 contacts the light-emitting layer 1030 and is disposed within the light-emitting layer 1030.

[0111] In some embodiments, step 1403 further comprises: etching the second-type semiconductor layer, the light-emitting layer, and the first-type semiconductor layer 1510 sequentially, and stopping the etching process in the first-type semiconductor layer. Referring back to FIG. 15C , the bottom of the trench 1522 contacts the first-type semiconductor layer 1510 and is disposed within the first-type semiconductor layer 1510.

[0112] The second-type semiconductor layer 1520 is etched by a conventional dry etching process, such as a plasma etching process, which can be understood by those skilled in the art.

[0113] In step 1404: referring to FIG. 15D , a top contact 1580 is deposited on the mesa structure 1521. Before depositing the top contact 1580, a first protective mask (not shown) is used to protect the area where the top contact 1580 will not be formed. Then, the material of the top contact 1580 is deposited on the first protective mask and on the second-type semiconductor layer 1520 by a conventional vapor deposition process, such as a physical vapor deposition process or a chemical vapor deposition process. After the deposition process, the first protective mask is removed from the second-type semiconductor layer 1520, and the material on the first protective mask is also removed together with the first protective mask to form the top contact 1580 on the mesa structure 1521.

[0114] In step 1405: referring to FIG. 15E , an ion implantation process is performed into the fence 1523'. Also referring to FIG. 15D , ions are implanted into the fence 1523' by the ion implantation process (as shown in FIG. 15D ) to form an ion-implanted fence 1523 (as shown in FIG. 15EThe direction of the ion implantation process is shown by the arrow. FIG. 15E The second protective mask (not shown) is formed on the region to be implanted with ions before the ion implantation process. Then, ions are implanted into the exposed fence 1523' (as shown) in the ion implantation process. Subsequently, the second protective mask is removed by a conventional chemical etching process, which is understood by those skilled in the art. Preferably, the implantation energy is 0 Kev to 500 Kev, and the implantation dose is 1E10 to 9E17. FIG. 15D

[0115] In some embodiments, the top contact 1580 can be formed after the ion implantation process.

[0116] In step 1406: Referring to FIG. 15F , the top conductive layer 1570 is deposited on top of the second type semiconductor layer 1520 and on the top contact 1580, and covers the sidewalls and the bottom of the trench 1522. The top conductive layer 1570 is deposited by a conventional physical vapor deposition process.

[0117] Alternatively, a dielectric layer can be formed on the sidewalls and the bottom of the trench 1522 before the deposition of the top conductive layer 1570. More specifically, a dielectric layer 1571 is formed on the sidewalls and the bottom of the trench 1522 before the formation of the top conductive layer 1570. In addition, the dielectric layer 1571 is formed in the trench 1522 on the sidewalls of the first type semiconductor layer 1510, the light emitting layer 1530, and the mesa structure 1521. The top conductive layer 1570 is formed on the surface of the dielectric layer 1571 extending into the trench 1522, on top of the mesa structure 1521, and on top of the ion implantation fence 1523. Referring back to FIG. 13 , the dielectric layer 1071 can completely fill the trench 1022. Referring back to FIG. 10A , the dielectric layer can be formed in the trench 1022 on the sidewalls of the second type semiconductor layer 1020, the mesa structure 1021, and on the surface of the light emitting layer 1030 in the trench 1022. Referring back to FIG. 10B , the dielectric layer can be formed in the trench 1022 on the sidewalls of the second type semiconductor layer 1020 and the mesa structure 1021, and on the surface of the light emitting layer 1030 in the trench 1022.

[0118] Referring back to FIG. 15F , a microlens can be further formed on the top conductive layer 1570, which is understood by those skilled in the art.

[0119] ​When the connection structure 1550 is a connection pillar, step 1402 can be replaced by the following step 1402': depositing a bottom contact on the first-type semiconductor layer; depositing a bottom isolation layer over the entire substrate; patterning the bottom isolation layer to expose the bottom contact; depositing a metal material over the entire substrate; polishing a top portion of the metal material to a top portion of the bottom isolation layer to form the connection pillar; and bonding the connection pillar with a contact pad of an IC backplane. Flip the epitaxial structure, and bond the connection pillar with the contact pad of the IC backplane by a metal bonding process. Step 1402' can be further understood by referring to the description of step 1402 in Embodiment 1, which will not be further described here. FIG. 6C and FIGS. 6E-6I .

[0120] According to some embodiments of the present disclosure, further provided is a micro-LED array panel. The micro-LED array panel includes a plurality of micro-LEDs as described above with reference to FIGS. 10A-10F , FIG. 12A and FIG. 12B . These micro-LEDs can be arranged into an array in the micro-LED array panel.

[0121] FIG. 16 is a structural diagram showing a side cross-sectional view of adjacent micro-LEDs of a micro-LED in FIG. 10C according to some embodiments of the present disclosure. As shown in FIG. 16 , the micro-LED array panel includes a first-type semiconductor layer 1610 formed continuously in the micro-LED array panel, a light-emitting layer 1630 formed continuously on the first-type semiconductor layer 1610, and a second-type semiconductor layer 1620 formed continuously on the light-emitting layer 1630.

[0122] The second-type semiconductor layer 1620 includes a plurality of mesa structures 1621, a plurality of trenches 1622, and a plurality of ion implantation fences 1623 separated from the mesa structures 1621 by the trenches 1622. A bottom surface of the ion implantation fence 1623 is higher than a bottom surface of the second-type semiconductor layer 1620.

[0123] FIG. 17 is a structural diagram showing a top view of adjacent micro-LEDs in FIG. 16 according to some embodiments of the present disclosure. FIG. 17 shows a top view of the second-type semiconductor layer 1620, in which the ion implantation fence 1623 is formed around the trench 1622 and between adjacent mesa structures 1621. The ion implantation fence 1623 has a higher electrical resistance than the mesa structure 1621. The ion implantation fence 1623 is formed around the trench 1622, and the trench 1622 is formed around the mesa structure 1621.

[0124] Furthermore, in some implementation schemes, such as FIG. 16 As shown, trench 1622 can extend downward through the second type semiconductor layer 1620 and the light-emitting layer 1630, and downward into the interior of the first type semiconductor layer 1610. In some embodiments, refer back to the previous section. FIG. 10A The trench 1022 extends downward through the second type semiconductor layer 1020 and reaches the light-emitting layer 1030. In some embodiments, refer back to the previous section. FIG. 10B The trench 1022 extends downward through the second type semiconductor layer 1020 and into the interior of the light-emitting layer 1030. Variations in the relationship between the bottom surface of the ion implantation fence 1623, the bottom surface of the second type semiconductor layer 1620, and the bottom of the trench 1622 can generally correspond to... FIGS. 10A-10C The variations shown for the micro-LED will not be described further here. Additionally, in some embodiments, variations in the relationship between the top surface of the ion-implanted fence 1623 and the top surface of the second type semiconductor layer 1620 can generally correspond to... FIGS. 10C-10E The variations shown for micro-LEDs will not be described further here. In some embodiments, the mesa structure may have one or more stepped structures, such as... FIG. 10F As shown.

[0125] In some embodiments, the space between adjacent sidewalls of adjacent mesa structures of mesa structure 1621 can be adjusted. For example, in some embodiments, the space between adjacent sidewalls of mesa structure 1621 is no greater than 50% of the diameter of mesa structure 1621. In some embodiments, the space between adjacent sidewalls of mesa structure 1621 is no greater than 30% of the diameter of mesa structure 1621. Preferably, the space between adjacent sidewalls of mesa structure 1621 is no greater than 600 nm. Additionally, in some embodiments, the width of ion implantation fence 1623 can be adjusted. For example, in some embodiments, the width of ion implantation fence 1623 is no greater than 50% of the diameter of mesa structure 1621. In some embodiments, the width of ion implantation fence 1623 is no greater than 10% of the diameter of mesa structure 1621. Preferably, in a micro-LED array panel, the width of ion implantation fence 1623 is no greater than 200 nm.

[0126] FIG. 18 This illustrates some embodiments of a micro LED array panel according to this disclosure. FIG. 12B A structural diagram showing a side cross-sectional view of adjacent microLEDs within a microLED. (See diagram below.) FIG. 18As shown, the micro-LED array panel further includes a top contact 1880 and a top conductive layer 1870. Further details of the top contact 1880 and the top conductive layer 1870 can be understood by also referring to the micro-LED shown in FIGS. 10A-10F , FIG. 12, and FIG. 13 , which will not be further described here.

[0127] Further, referring back to FIG. 18 , the IC backplane 1890 is formed underneath the first-type semiconductor layer 1810 and is electrically connected with the first-type semiconductor layer 1810 via a connection structure 1850. The micro-LED array panel further includes a bottom contact 1860 formed at the bottom of the first-type semiconductor layer 1810. The connection structure 1850 can be a metal bonding layer for bonding the micro-LED with the IC backplane 1890. In addition, in some embodiments, the bottom contact 1860 is a bottom contact layer. Further details of the IC backplane 1890, the bottom contact 1860, and the connection structure 1850 can be understood by also referring to FIG. 12A , FIG. 12B , and FIG. 13 , which will not be further described here.

[0128] In addition, further details regarding the features of the ion implantation fences in the micro-LED and the micro-LED array panel can be understood by also referring to the micro-LED shown in FIGS. 10A-10F , which will not be further described here.

[0129] FIG. 18 The micro-LED array panel shown can be fabricated by a method 1400 of fabricating a micro-LED as shown in FIG. 14 , which will not be further described here.

[0130] Embodiment 3

[0131] FIGS. 19A-19E is a structural diagram showing various different variants of a third exemplary micro-LED according to some embodiments of the present disclosure. As FIG. 19AAs shown, in some embodiments, the micro-LED includes at least a first type semiconductor layer 1910, a light emitting layer 1930, and a second type semiconductor layer 1920. The first type semiconductor layer 1910 has a different conductivity type than the second type semiconductor layer 1920. For example, in some embodiments, the first type semiconductor layer 1910 has a P-type conductivity type, and the second type semiconductor layer 1920 has an N-type conductivity type. In some embodiments, the second type semiconductor layer 1920 has a P-type conductivity type, and the first type semiconductor layer 1910 has an N-type conductivity type. The first type semiconductor layer 1910 has a greater thickness than the second type semiconductor layer 1920. In some embodiments, the first type semiconductor layer 1910 is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the second type semiconductor layer 1920 is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

[0132] The first type semiconductor layer 1910 includes a first mesa structure 1911, a first trench 1912, and a first ion implantation fence 1913. The first trench 1912 extends upward through a top surface of the first type semiconductor layer 1910. The second type semiconductor layer 1920 includes a second mesa structure 1921, a second trench 1922, and a second ion implantation fence 1923 that is separated from the second mesa structure 1921.

[0133] In some embodiments, referring back to FIG. 1A , the first trench extends upward through the first type semiconductor layer and contacts the light emitting layer. Referring back to FIG. 1B , in some embodiments, the first trench extends upward through the first type semiconductor layer and extends into an interior of the light emitting layer. Referring back to FIG. 1C , in some embodiments, the first trench extends upward through the first type semiconductor layer and the light emitting layer, and upward into an interior of the second type semiconductor layer. Additionally, the first trench can extend upward through the first type semiconductor layer and the light emitting layer and the second type semiconductor layer.

[0134] Further, in some embodiments, the second trench 1922 extends downward through a bottom of the second type semiconductor layer 1920, and the bottom of the second trench 1922 is lower than the bottom of the second type semiconductor layer 1920. Thus, the bottom of the second trench 1922 is in contact with the light emitting layer 1930. Referring back to FIG. 10A , in some embodiments, the second trench extends downward to the bottom of the second type semiconductor layer and contacts the light emitting layer. Referring back toFIG. 10B In some embodiments, the second trench extends downward through the second-type semiconductor layer and into an interior of the light-emitting layer. Referring back to FIG. 10C , the second trench extends downward through the second-type semiconductor layer and the light-emitting layer, and further extends downward into an interior of the first-type semiconductor layer. Also, in some embodiments, the second trench can extend downward through the second-type semiconductor layer, the light-emitting layer, and the first-type semiconductor layer.

[0135] Referring back to FIGS. 19A-19D , in some embodiments, a top surface of the first trench 1912 does not contact a bottom surface of the second trench 1922 in a horizontal direction or a vertical direction. A portion of the light-emitting layer 1930 is disposed between the top surface of the first trench 1912 and the bottom surface of the second trench 1922. Also, in some embodiments, referring back to FIG. 19E and FIG. 19F , a top portion of the first trench 1912 directly connects with a bottom portion of the second trench 1922 in a horizontal direction or a vertical direction. Thus, there is no light-emitting layer 1930 between the top portion of the first trench 1911 and the bottom portion of the second trench 1922. For example, as shown in FIG. 19E , when the first trench 1912 and the second trench 1922 extend through each other in a vertical direction, the first trench 1912 and the second trench 1922 can act as one trench structure. In some embodiments, a center of the first trench 1912 can be aligned with or offset from a center of the second trench 1922. In some embodiments, as shown in FIG. 19D and 19F , the first trench 1912 and the second trench 1022 are not aligned with each other in a vertical direction. Also, a diameter of the first trench 1912 can be the same or different from top to bottom. A diameter of the second trench 1922 can be the same or different from top to bottom. The diameter of the first trench 1912 can be the same or different from the diameter of the second trench 1922.

[0136] In some embodiments, a center of the first mesa structure 1911 is aligned with a center of the second mesa structure 1921. A center of the first trench 1912 is aligned with a center of the second trench 1922, and a center of the first ion implantation fence 1913 is aligned with a center of the second ion implantation fence 1923.

[0137] A bottom view of the first-type semiconductor layer 1910 is similar to the bottom view shown in FIG. 2 . The first ion implantation fence 1913 is separated from the first mesa structure 1911 by the first trench 1912. The first ion implantation fence 1913 is formed around the first trench 1912, and the first trench 1912 is formed around the first mesa structure 1911. A top view of the second-type semiconductor layer 1920 is similar to the top view shown in FIG. 11Similar to the top view shown, the second ion implantation fence 1923 is separated from the second mesa structure 1921 by a second trench 1922. The second ion implantation fence 1923 is formed around the second trench 1922, and the second trench 1922 is formed around the second mesa structure 1921.

[0138] The relationship between the top surface of the first ion implantation fence 1913, the top surface of the first trench 1912, and the top surface of the first type semiconductor layer 1910 and FIGS. 1A-1C The relationships of the variant of the microLED shown in Embodiment 1 are the same and will not be described further here. The relationships of the bottom of the first ion implantation fence 1913, the bottom of the first trench 1912, and the bottom of the first type semiconductor layer 1910 are the same as in Embodiment 1. FIGS. 1C-1E The variations of the microLEDs shown in Embodiment 1 have the same relationship and will not be described further here. Furthermore, in some embodiments, the first mesa structure 1911 may have one or more stepped structures, such as... FIG. 1F As shown.

[0139] The relationship between the bottom of the second ion implantation fence 1923, the bottom of the second trench 1922, and the bottom of the second type semiconductor layer 1920 is as follows: FIGS. 10A-10C The relationships between the variants of the microLED shown in Embodiment 2 are the same and will not be described further here. The relationships between the top surface of the second ion implantation fence 1923, the top surface of the second trench 1922, and the top surface of the second type semiconductor layer 1920 are as follows: FIGS. 10C-10E The variations of the microLEDs shown in embodiment 2 have the same relationship and will not be described further here. Furthermore, in some embodiments, the second mezzanine structure 1921 may have one or more stepped structures, such as... FIG. 10F As shown.

[0140] FIG. 20 This is a structural diagram showing a side cross-sectional view of another variant of a third exemplary microLED according to some embodiments of this disclosure. FIG. 20 As shown, the micro-LED further includes a bottom insulating layer 2040 filled in the first trench 2012. Preferably, the bottom insulating layer 2040 is made of SiO2 or SiN. xor one or more of Al2O3. The IC backplane 2090 is formed underneath the first-type semiconductor layer 2010 and is electrically connected with the first-type semiconductor layer 2010 via the connection structure 2050. Here, the connection structure 2050 is a connection pillar. The micro-LED further includes a bottom contact 2060 formed at the bottom of the first-type semiconductor layer 2010. Further details of the bottom isolation layer 2040, the IC backplane 2090, the connection structure 2050, and the bottom contact 2060 can be found by referring to the description of Embodiment 1, which will not be further described here.

[0141] The micro-LED further includes a top contact 2080 and a top conductive layer 2070. The top contact 2080 is formed on top of the second-type semiconductor layer 2020, and the top conductive layer 2070 is formed on top of the second-type semiconductor layer 2020. The top conductive layer 2070 covers the top contact 2080 and covers the sidewall of the second trench 2022. Further details about the top contact 2080 and the top conductive layer 2070 can be found by referring to the description of Embodiment 2, which will not be further described here.

[0142] In addition, further details about the micro-LED, the first ion implantation fence 2013, and the second ion implantation fence 2023 can be found by referring to the description of Embodiment 1 and Embodiment 2, which will not be further described here.

[0143] FIG. 21 A flowchart of a method 2100 for fabricating a third exemplary micro-LED is shown, according to some embodiments of the present disclosure. The method 2100 includes at least process I and process II.

[0144] In process I: the first-type semiconductor layer is patterned, and then ions are implanted into the first-type semiconductor layer to form a first ion implantation fence.

[0145] In process II: the second-type semiconductor layer is patterned, and then ions are implanted into the second-type semiconductor layer to form a second ion implantation fence.

[0146] Reference is made to FIG. 21 , process I includes at least steps 2101-2109, and process II includes at least steps 2110-2113.

[0147] For process I, steps 2101-2109 are similar to steps 501-509 of the method 500 as shown in FIG. 5 . The side cross-sectional view of the micro-LED fabricated according to steps 2101-2109 is similar to the view as shown in FIGS. 6A-6I . Reference is made to FIG. 21and FIGS. 6A-6I In step 2101 : referring to FIG. 6A An epitaxial structure is provided.

[0148] In step 2102: referring to FIG. 6B The first-type semiconductor layer 610 is patterned to form mesa structures 611, trenches 612, and fences 613'.

[0149] In step 2103: referring to FIG. 6C A bottom contact 660 is deposited on the mesa structures 611.

[0150] In step 2104: referring to FIG. 6D An ion implantation process is performed into the fences 613'.

[0151] In step 2105: referring to FIG. 6E A bottom isolation layer 640 is deposited on the entire substrate 600.

[0152] In some embodiments, referring to FIG. 20 The bottom isolation layer 2040 fills the first trenches 2012. Furthermore, when the first trenches 2012 extend through the first-type semiconductor layer 2010 and the light-emitting layer 2030, and extend into the second-type semiconductor layer 2020, the bottom isolation layer 2040 is further formed on the sidewalls of the first mesa structures 2011, the first ion implantation fences 2013, the first-type semiconductor layer 2010, the light-emitting layer 2030, the second-type semiconductor layer 2020, the second mesa structures 2021, and the second ion implantation fences 2023 in the first trenches 2012.

[0153] In step 2106: referring to FIG. 6F The bottom isolation layer 640 is patterned to expose the bottom contact 660.

[0154] In step 2107: referring to FIG. 6G A metal material 650' is deposited on the entire substrate 600.

[0155] In step 2108: referring to FIG. 6H A top of the metal material 650' is ground to a top of the isolation layer 640 to form a connection pillar 650.

[0156] In step 2109: referring to FIG. 6I The connection pillar 650 is bonded with an IC backplate 690, and the substrate 600 is removed.

[0157] FIGS. 22A-22D is a flowchart illustrating a method of fabricating a semiconductor light emitting device according to some embodiments of the present disclosure. FIG. 21The structure diagram of the side cross-sectional view of the micro-LED fabrication process at step 2110 to step 2113 of the method 2100 shown. Refer to FIG. 21 and FIGS. 22A-22D In step 2110: refer to FIG. 22A , the second type semiconductor layer 2220 is patterned to form a second mesa structure 2221, a second trench 2222, and a second fence 2223. The central axis of the second trench 2222 is aligned with the central axis of the first trench 2212. In some embodiments, the central axis of the second trench 2222 is not aligned with the central axis of the first trench 2212. As FIG. 22A shown, the second trench 2222 is etched to connect with the first trench 2212. That is, the second trench 2222 is etched to the surface of the bottom isolation layer 2240 filled in the first trench 2212.

[0158] In step 2111: refer to FIG. 22B , a top contact 2280 is deposited on the mesa structure 2221.

[0159] In step 2112: refer to FIG. 22C , an ion implantation process is performed into the fence 2223'. The arrow shows the direction of the ion implantation process.

[0160] In step 2113: refer to FIG. 22D , a top conductive layer 2270 is deposited on top of the second type semiconductor layer 2220 and on the top contact 2280, and on the sidewall of the trench 2222. The top conductive layer 2270 can be formed directly on top of the second type semiconductor layer 2220 and on the top contact 2280, and on the sidewall of the trench 2222.

[0161] FIG. 23A and FIG. 23B are structure diagrams showing side cross-sectional views of other variants of the third exemplary micro-LED according to some embodiments of the present disclosure. As FIG. 23AAs shown, a bottom insulating layer 2340 fills the first trench 2312 and is formed in the first trench 2312 on the sidewalls of the first mesa structure 2311, the first ion implantation fence 2313, and the light-emitting layer 2330. Before forming the top conductive layer 2370, a dielectric layer 2371 is deposited and extends into the second trench 2322. Sidewall dielectric layers 2371 are formed on the sidewalls and bottom of the second trench 2322. The second trench 2322 extends downward through the second type semiconductor layer 2320 and into the light-emitting layer 2330. Therefore, a dielectric layer 2371 is formed in the second trench 2322 on the sidewalls of the second mesa structure 2321, the second type semiconductor layer 2320, the second ion implantation fence 2323, and the light-emitting layer 2330. Then, a top conductive layer 2370 is formed on the surface of the dielectric layer 2371 extending into the second trench 2322, and is formed on top of the second mesa structure 2321 and on top of the second ion implantation fence 2323.

[0162] In some implementation schemes, such as FIG. 23B As shown, a bottom isolation layer 2340 fills the first trench 2312 and is formed on the sidewalls of the first mesa structure 2311, the first ion implantation fence 2313, and the first type semiconductor layer 2310. A top conductive layer 2370 extending into the second trench 2322 can be formed. Furthermore, a dielectric layer 2371 extending into the second trench 2322 is formed. The second trench 2322 extends downward through the second type semiconductor layer 2320, the light-emitting layer 2330, and into the first type semiconductor layer 2310. Therefore, the dielectric layer 2371 is formed in the second trench 2322 on the sidewalls of the second mesa structure 2321, the second type semiconductor layer 2320, the second ion implantation fence 2323, the light-emitting layer 2330, the first mesa structure 2311, the first ion implantation fence 2313, and the first type semiconductor layer 2310.

[0163] A bottom insulating layer 2340 is formed on the sidewalls and top of the first trench 2312, and a dielectric layer 2371 is formed on the sidewalls and bottom of the second trench 2322. The thickness of the bottom insulating layer extending into the first trench 2312 depends on the location of the bottom of the second trench 2322 and the location of the top of the first trench 2312. The thickness of the dielectric layer 2371 extending into the second trench 2322 depends on the location of the bottom of the second trench 2322 and the location of the top of the first trench 2312.

[0164] Top and bottom contacts may be formed in a miniature LED according to some embodiments of this disclosure, which will not be described further herein.

[0165] Further details of process I can be found by referring to the description of steps 501-509 of embodiment 1. Further details of process II can be found by referring to the description of steps 1403-1406 of embodiment 2, which will not be further described here.

[0166] According to some embodiments of the present disclosure, further provided is a micro-LED array panel. The micro-LED array panel includes a plurality of micro-LEDs as described above and illustrated in FIGS. 19A-19E 、 FIG. 20 and 23A and FIG. 23B The micro-LEDs can be arranged into an array in the micro-LED array panel.

[0167] FIG. 24 is a structural diagram illustrating a side cross-sectional view of adjacent micro-LEDs of a micro-LED in FIG. 23A according to some embodiments of the present disclosure. As shown in FIG. 24 , the micro-LED array panel includes at least a first type semiconductor layer 2410 continuously formed in the micro-LED array panel, a light emitting layer 2430 continuously formed on the first type semiconductor layer 2410, and a second type semiconductor layer 2420 formed on the light emitting layer 2330.

[0168] The first type semiconductor layer 2410 includes a plurality of first mesa structures 2311, a plurality of first trenches 2412, and a plurality of first ion implantation fences 2413 separated from the first mesa structures via the first trenches 2412. The top surface of the first ion implantation fence 2413 is lower than the top surface of the first type semiconductor layer 2410. Referring back to FIG. 8 , the bottom view of the micro-LED array panel without IC backplane is similar to the bottom view shown in FIG. 8 . The first ion implantation fence 2413 is formed around the first trench 2412 between adjacent first type mesa structures 2411. The electrical resistance of the first ion implantation fence 2413 is higher than that of the first mesa structure. In addition, the first ion implantation fence 2313 is formed around the first trench 2412, and the first trench 2412 is formed around the first mesa structure.

[0169] The second type semiconductor layer 2420 includes a plurality of second mesa structures 2421, a plurality of second trenches 2422, and a plurality of second ion implantation fences 2423 separated from the second mesa structures 2421 by the second trenches 2422. The bottom surface of the second ion implantation fence 2423 is higher than the bottom surface of the second type semiconductor layer 2420. The top view of the micro-LED array panel is similar to the top view shown in FIG. 17Similar to the top view shown, a second ion implantation fence 2423 is formed around the second trenches 2422 between the adjacent second mesa structures 2421. The resistance of the second ion implantation fence 2423 is higher than the resistance of the second mesa structure 2421. The second ion implantation fence 2323 is formed around the second trenches 2422, and the second trenches 2422 are formed around the second mesa structure 2421.

[0170] In some embodiments, the space between the adjacent sidewalls of the first mesa structure 2411 can be adjusted. For example, in some embodiments, the space between the adjacent sidewalls of the first mesa structure 2411 is no more than 50% of the diameter of the first mesa structure 2411. In some embodiments, the space between the adjacent sidewalls of the first mesa structure 2411 is no more than 30% of the diameter of the first mesa structure 2411. Preferably, the space between the adjacent sidewalls of the first mesa structure 2411 is no more than 600 nm. In addition, in some embodiments, the width of the first ion implantation fence 2413 can be adjusted. For example, in some embodiments, the width of the first ion implantation fence 2413 is no more than 50% of the diameter of the first mesa structure 2411. In some embodiments, the width of the first ion implantation fence 2413 is no more than 10% of the diameter of the first mesa structure 2411. Preferably, in some embodiments, the width of the first ion implantation fence 2413 is no more than 200 nm in the micro-LED array panel. The space between the adjacent sidewalls of the second mesa structure 2421 is no more than 50% of the diameter of the second mesa structure 2421. In some embodiments, the space between the adjacent sidewalls of the second mesa structure 2421 is no more than 30% of the diameter of the second mesa structure 2421. Preferably, the space between the adjacent sidewalls of the second mesa structure 2421 is no more than 600 nm. In addition, the width of the second ion implantation fence 2423 is no more than 50% of the diameter of the second mesa structure 2421. In some embodiments, the width of the second ion implantation fence 2423 is no more than 10% of the diameter of the second mesa structure 2421. Preferably, the width of the second ion implantation fence 2423 is no more than 200 nm in the micro-LED array panel.

[0171] As to FIG. 24 , the micro-LED array panel further comprises a bottom isolation layer 2440 filled in the first trenches 2412. Preferably, the material of the bottom isolation layer 2440 is SiO2, SiN xone or more of Al2O3, AlN, HfO2, TiO2, or ZrO2. In addition, the IC backplane 2490 is formed underneath the first-type semiconductor layer 2410 and is electrically connected with the first-type semiconductor layer 2410 via the connection structure 2450. The micro LED array panel further includes a bottom contact 2460 formed at the bottom of the first-type semiconductor layer 2410. The upper surface of the connection structure 2450 is connected with the bottom contact 2460, and the bottom of the connection structure 2450 is connected with the IC backplane 2490. The bottom contact 2460 is a protruding contact. In some embodiments, reference is made to FIG. 4 The connection structure can be a metal bonding layer for bonding the micro LED with the IC backplane 2490. In addition, in some embodiments, the bottom contact 2460 is a bottom contact layer.

[0172] Referring back to FIG. 24 The micro LED array panel further includes a top contact 2480 and a top conductive layer 2470. The top contact 2480 is formed on the top of the second-type semiconductor layer 2420 of each micro LED. In addition, a dielectric layer 2471 is formed on the sidewall and the bottom of the second trench 2422. The top conductive layer 2470 is formed on the top of the second-type semiconductor layer 2420 and on the top contact 2480, and covers the sidewall of the second trench 2422. The conductive type of the top contact 2480 is the same as the conductive type of the second-type semiconductor layer 2420. For example, the conductive type of the second-type semiconductor layer 2420 is N-type, and the conductive type of the top contact 2480 is N-type. The top contact 2480 is made of a metal or a metal alloy, such as AuGe, AuGeNi, etc. The top contact 2480 is used to form an ohmic contact between the top conductive layer 2470 and the second-type semiconductor layer 2420 to optimize the electrical properties of the micro LED. The diameter of the top contact 2480 is about 20 nm to 50 nm, and the thickness of the top contact 2480 is about 10 nm to 20 nm.

[0173] Further detailed properties of the micro LED in the micro LED array panel can be found by referring to the micro LED described above, which will not be further described here.

[0174] The method of manufacturing the micro LED array panel at least includes manufacturing the micro LED. Details of manufacturing the micro LED can refer to the description of steps 501 to 509 in Embodiment 1 and the description of steps 1403 to 1406 in Embodiment 2, which will not be further described here.

[0175] In Embodiments 1 to 3, a micro-lens can be further formed on or above the top of the second-type semiconductor layer, such as on the top surface of the top conductive layer, which can be understood by those skilled in the art.

[0176] The micro-LED has a very small volume. The micro-LED can be an organic LED or an inorganic LED. The micro-LED can be applied in a micro-LED array panel. The micro-LED array panel has a small light emitting area, such as 1 mm x 1 mm, 3 mm x 5 mm. In some embodiments, the light emitting area is the area of a micro-LED array in the micro-LED array panel. The micro-LED array panel includes one or more micro-LED arrays forming a pixel array, such as a 1600 x 1200, 680 x 480, or 1920 x 1080 pixel array, where the micro-LED is a pixel. The diameter of the micro-LED is in a range from about 200 nm to 2 pm. An IC backplane is formed at the back surface of the micro-LED array and is electrically connected with the micro-LED array. The IC backplane obtains signals such as image data from the outside via signal lines to control the corresponding micro-LED to emit light or not to emit light.

[0177] It should be noted that relational terms herein, such as“first” and“second”, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the words“comprising”,“having”,“containing” and“including” and other similar forms are intended to be equivalent in meaning and are open-ended, in that an item or items following any one of these words are not meant to be an exhaustive listing of possible items, or are meant to be limited to only the items specifically listed.

[0178] As used herein, the term“or” encompasses all possible combinations, unless otherwise indicated by context. For example, if a database is stated to include A or B, then unless otherwise indicated or infeasible, the database can include A, or B, or A and B. As a second example, if a database is stated to include A, B, or C, then unless otherwise indicated or infeasible, the database can include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0179] In the foregoing specification, embodiments have been described with reference to numerous specific details that can vary from implementation to implementation. Certain modifications and changes can be made thereto, and it is intended to embrace all such modifications and changes as fall within the scope of the application disclosed herein. The specification and examples given are intended as illustrative only and are not intended to limit the true scope and spirit of the application, which is indicated by the following claims. The sequence of steps shown in the drawings is also intended to be illustrative only and is not intended to limit the application to any particular sequence of steps. Accordingly, those skilled in the art will recognize that the steps could be performed in other sequences while still implementing the same method.

[0180] In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Accordingly, while specific terminology has been employed, they are used in the generic and descriptive sense only and not for purposes of limitation.

Claims

1. A miniature LED, comprising: Type 1 semiconductor layer; as well as Emissive layer; It is formed on the first type of semiconductor layer; wherein, The first type of semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending upward through the first type of semiconductor layer and extending upward into at least a portion of the light-emitting layer; and The ion implantation fence is formed around the trench, and the trench is formed around the mesa structure, wherein the resistance of the ion implantation fence is higher than the resistance of the mesa structure, wherein the mesa structure includes one or more stepped structures.

2. The micro LED according to claim 1, wherein, The top surface of the ion implantation fence is lower than the top surface of the first type of semiconductor layer.

3. The micro LED according to claim 1, wherein, The bottom surface of the ion implantation fence is aligned with, or is higher than or lower than, the bottom surface of the first type of semiconductor layer.

4. The micro LED according to claim 1, wherein, The top surface of the ion implantation fence is lower than the top surface of the trench.

5. The micro LED according to claim 1, wherein, The groove extends upward through the light-emitting layer.

6. The microLED of claim 1, further comprising a second type of semiconductor layer formed on the light-emitting layer, wherein, The conductivity type of the second type of semiconductor layer is different from that of the first type of semiconductor layer.

7. The micro LED according to claim 6, wherein, The trench extends upward through the light-emitting layer and further upward into the interior of the second type of semiconductor layer.

8. The micro LED according to claim 6, wherein, The trench extends upward through the light-emitting layer and further upward through the second type of semiconductor layer.

9. The micro LED according to claim 1, wherein, The width of the groove is no more than 50% of the diameter of the platform structure.

10. The micro LED according to claim 9, wherein, The width of the trench is no greater than 200 nm.

11. The micro LED according to claim 1, wherein, The ion implantation fence includes a light-absorbing material, and the light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

12. The micro LED according to claim 1, wherein, The thickness of the first type of semiconductor layer is greater than the thickness of the light-emitting layer.

13. The micro LED of claim 1, further comprising a bottom insulating layer filling the trench.

14. The micro LED according to claim 13, wherein, The material of the bottom insulating layer is selected from SiO2 and SiN. x One or more of Al2O3, AlN, HfO2, TiO2 or ZrO2.

15. The micro LED according to claim 1, wherein, The ion implantation fence is formed by implanting ions into at least the first type of semiconductor layer.

16. The micro LED according to claim 15, wherein, The ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

17. The micro LED according to claim 1, wherein, The width of the ion implantation fence is no more than 50% of the diameter of the platform structure.

18. The micro LED according to claim 17, wherein, The width of the ion implantation fence is no greater than 200 nm, the diameter of the mesa structure is no greater than 2500 nm, and the thickness of the first type of semiconductor layer is no greater than 100 nm.

19. The micro LED according to claim 6, wherein, The material of the first type of semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and the material of the second type of semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

20. The micro LED of claim 1, further comprising an integrated circuit (IC) backplane formed beneath the first type of semiconductor layer; and a connection structure electrically connecting the IC backplane to the first type of semiconductor layer via the connection structure.

21. The micro LED according to claim 20, wherein, The connection structure is a connecting pillar or a metal bonding layer.

22. The micro LED of claim 20, further comprising a bottom contact formed on the bottom surface of the first type of semiconductor layer, the upper surface of the connection structure being connected to the bottom contact, and the bottom surface of the connection structure being connected to the backplane of the integrated circuit (IC).

23. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 1 to 22.

24. A method for manufacturing a micro LED, the method comprising: An epitaxial structure is provided, wherein the epitaxial structure comprises, from top to bottom, a first type of semiconductor layer, a light-emitting layer, and a second type of semiconductor layer; The first type of semiconductor layer is patterned to form mesa structures, trenches, and fences, wherein the mesa structures include one or more stepped structures; The bottom contact is deposited on the platform structure; and An ion implantation process is performed into the fence to form an ion implantation fence.

25. The method according to claim 24, wherein, After patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence, the method further includes: A bottom isolation layer is deposited on the first type of semiconductor layer and the bottom contact; Pattern the bottom isolation layer to expose the bottom contacts; Metallic material is deposited on the bottom insulating layer and the bottom contacts; The metal material is ground to the top surface of the bottom insulating layer to form a connection structure; and The epitaxial structure is flipped and the connection structure is bonded to the backplane of the integrated circuit (IC).

26. The method of claim 25, wherein, When the bottom insulating layer is deposited on the insulating layer and the bottom contact, the material of the bottom insulating layer is selected from SiO2 and SiN. x One or more of Al2O3, AlN, HfO2, TiO2 or ZrO2.

27. The method according to claim 25, wherein, When providing the epitaxial structure, the epitaxial structure is grown on a substrate.

28. The method according to claim 27, wherein, Flipping the epitaxial structure and bonding the connection structure to the backplane of the integrated circuit (IC) further includes: Remove the substrate.

29. The method according to claim 27, wherein, After flipping the epitaxial structure and bonding the connection structure to the backplane of the integrated circuit (IC), the method further includes: A top contact and a top conductive layer are formed on the top surface of the second type of semiconductor layer.

30. The method according to claim 24, wherein, Patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The first type of semiconductor layer is etched onto the surface of the light-emitting layer.

31. The method according to claim 24, wherein, Patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The first type of semiconductor layer and the light-emitting layer are etched sequentially, and The etching is stopped in the light-emitting layer.

32. The method according to claim 24, wherein, Patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The first type of semiconductor layer, the light-emitting layer, and the second type of semiconductor layer are etched sequentially. The etching is stopped in the second type of semiconductor layer.

33. The method according to claim 24, wherein, Depositing the bottom contact on the mesa structure further includes: A protective mask is formed to protect the area where the bottom contact is not deposited; Material for the bottom contact is deposited on the protective mask and on the first type of semiconductor layer; and The protective mask is removed from the first type of semiconductor layer, and the material on the protective mask is removed to form the bottom contact on the mesa structure.

34. The method according to claim 24, wherein, Performing an ion implantation process into the fence to form an ion implantation fence further includes: A protective mask is formed on the area not implanted with ions, while the fence is exposed; Injecting ions into the fence; and Remove the protective mask.

35. The method according to claim 34, wherein, When performing the ion implantation process into the fence to form the ion implantation fence, the implantation is performed at an energy of 0 keV to 500 keV.

36. The method according to claim 34, wherein, When performing the ion implantation process into the fence to form the ion implantation fence, a dose of 1E10 to 9E17 is injected.

37. The method of claim 34, wherein, When the ion implantation process is performed in the fence to form the ion implantation fence, the ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl or F.

38. The method according to claim 34, wherein, When performing the ion implantation process into the enclosure to form the ion implantation enclosure, the width of the ion implantation enclosure is not greater than 50% of the diameter of the platform structure.

39. The method according to claim 34, wherein, When performing the ion implantation process into the fence to form the ion implantation fence, the width of the ion implantation fence is no greater than 200 nm, the diameter of the mesa structure is no greater than 2500 nm, and the thickness of the first type of semiconductor layer is no greater than 300 nm.

40. The method of claim 24, wherein, When patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence, the width of the trench is no greater than 50% of the diameter of the mesa structure.

41. The method according to claim 24, wherein, The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity. The material of the first type of semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN, and the material of the second type of semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

42. The method according to claim 41, wherein, The ion implantation fence includes a light-absorbing material.

43. The method according to claim 42, wherein, The light-absorbing material is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN.

44. A miniature LED, comprising: Type 1 semiconductor layer; A light-emitting layer is formed on the first type of semiconductor layer; A second type of semiconductor layer is formed on the light-emitting layer; as well as An integrated circuit (IC) backplane is formed on the bottom surface of the first type of semiconductor layer; wherein... The second type of semiconductor layer includes a mesa structure, a trench, and an ion implantation fence separated from the mesa structure, the trench extending downward through the second type of semiconductor layer and downward into at least a portion of the light-emitting layer; and The ion implantation fence is formed around the trench, and the trench is formed around the mesa structure, wherein the resistance of the ion implantation fence is higher than the resistance of the mesa structure; The conductivity type of the second type of semiconductor layer differs from that of the first type of semiconductor layer. The platform structure includes one or more stepped structures.

45. The micro LED according to claim 44, wherein, The bottom surface of the ion implantation fence is higher than the bottom surface of the second type of semiconductor layer.

46. ​​The micro LED according to claim 44, wherein, The top surface of the ion implantation fence is aligned with, or is higher than or lower than, the top surface of the second type of semiconductor layer.

47. The micro LED according to claim 44, wherein, The bottom surface of the ion implantation fence is higher than the bottom surface of the trench.

48. The micro LED according to claim 44, wherein, The groove extends downward through the light-emitting layer.

49. The micro LED according to claim 44, wherein, The trench extends downward through the light-emitting layer and further downward into the interior of the first type of semiconductor layer.

50. The micro LED according to claim 44, wherein, The trench extends downward through the light-emitting layer and further downward through the first type of semiconductor layer.

51. The micro LED according to claim 44, wherein, The width of the groove is no more than 50% of the diameter of the platform structure.

52. The micro LED according to claim 51, wherein, The width of the trench is no greater than 200 nm.

53. The micro LED according to claim 44, wherein, The ion implantation fence includes a light-absorbing material, wherein the light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

54. The micro LED according to claim 44, wherein, The thickness of the second type of semiconductor layer is greater than the thickness of the light-emitting layer.

55. The microLED of claim 44, further comprising a bottom isolation layer formed on the bottom surface of the first type of semiconductor layer and the top surface of the integrated circuit IC backplane.

56. The micro LED according to claim 55, wherein, The material of the bottom isolation layer is selected from one or more of SiO2, SiNx, Al2O3, AlN, HfO2, TiO2 or ZrO2.

57. The micro LED according to claim 44, wherein, The ion implantation fence is formed by implanting ions into at least the second type of semiconductor layer.

58. The micro LED according to claim 57, wherein, The ions implanted into the ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

59. The micro LED according to claim 44, wherein, The width of the ion implantation fence is no more than 50% of the diameter of the platform structure.

60. The micro LED according to claim 59, wherein, The width of the ion implantation fence is no greater than 200 nm, the diameter of the mesa structure is no greater than 2500 nm, and the thickness of the first type of semiconductor layer is no greater than 300 nm.

61. The micro LED according to claim 44, wherein, The material of the first type of semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and the material of the second type of semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

62. The micro LED of claim 44, further comprising a connection structure via which the integrated circuit IC backplane is electrically connected to the first type of semiconductor layer.

63. The micro LED according to claim 62, wherein, The connection structure is a connecting pillar or a metal bonding layer.

64. The micro LED according to claim 62, further comprising: A bottom contact is formed on the bottom surface of the first type of semiconductor layer; and the upper surface of the connection structure is connected to the bottom contact, and the bottom surface of the connection structure is connected to the backplane of the integrated circuit (IC).

65. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 44 to 64.

66. A method for manufacturing a micro LED, the method comprising: An epitaxial structure is provided, wherein the epitaxial structure comprises, from top to bottom, a first type of semiconductor layer, a light-emitting layer, and a second type of semiconductor layer; The epitaxial structure is bonded to the backplane of the integrated circuit (IC). The second type of semiconductor layer is patterned to form mesa structures, trenches, and fences, wherein the mesa structures include one or more stepped structures; Deposit the top contact on the mezzanine structure; Perform an ion implantation process into the fence; and A top conductive layer is deposited on the top surface of the second type of semiconductor layer, on the top contact, and in the trench.

67. The method according to claim 66, wherein, The epitaxial structure further includes: Deposit a bottom contact layer on the top surface of the first type of semiconductor layer; and A metal bonding layer is deposited on the top surface of the bottom contact layer.

68. The method according to claim 67, wherein, Bonding the epitaxial structure to the backplane of the integrated circuit (IC) further includes: Flip the epitaxial structure; and The metal bonding layer is bonded to the contact pads of the integrated circuit (IC) backplane.

69. The method according to claim 68, wherein, When providing the epitaxial structure, the epitaxial structure is grown on a substrate.

70. The method according to claim 69, wherein, Bonding the epitaxial structure to the backplane of the integrated circuit (IC) further includes: Remove the substrate.

71. The method according to claim 66, wherein, Patterning the second type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The second type of semiconductor layer is etched onto the surface of the light-emitting layer.

72. The method according to claim 66, wherein, Patterning the second type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The second type of semiconductor layer and the light-emitting layer are etched sequentially; and The etching is stopped in the light-emitting layer.

73. The method according to claim 66, wherein, Patterning the second type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The second type of semiconductor layer, the light-emitting layer, and the first type of semiconductor layer are sequentially etched; and The etching is stopped in the first type of semiconductor layer.

74. The method according to claim 66, wherein, Depositing the top contact on the mesa structure further includes: Form a protective mask; Depositing the material of the top contact on the protective mask; and The protective mask is removed from the second type of semiconductor layer, and the material of the top contact on the protective mask is removed to form the top contact on the mesa structure.

75. The method according to claim 66, wherein, Performing the ion implantation process into the fence further includes: A protective mask is formed on the area not implanted with ions, while the fence is exposed; Injecting ions into the fence; and Remove the protective mask.

76. The method according to claim 75, wherein, When performing the ion implantation process into the enclosure, implantation is carried out at an energy of 0 keV to 500 keV.

77. The method according to claim 75, wherein, When performing the ion implantation process into the enclosure, a dose of 1E10 to 9E17 is injected.

78. The method according to claim 75, wherein, When performing the ion implantation process into the enclosure, the ions implanted into the enclosure are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

79. The method according to claim 75, wherein, When performing the ion implantation process into the enclosure, the width of the enclosure is no greater than 50% of the diameter of the platform structure.

80. The method according to claim 75, wherein, When performing the ion implantation process into the fence, the width of the fence is no greater than 200 nm, the diameter of the mesa structure is no greater than 2500 nm, and the thickness of the second type of semiconductor layer is no greater than 100 nm.

81. The method according to claim 66, wherein, The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity. The material of the first type of semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN. The material of the second type of semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

82. The method according to claim 81, wherein, The ion implantation fence includes a light-absorbing material.

83. The method according to claim 82, wherein, The light-absorbing material is selected from one or more of n-GaAs, n-GaP, n-AlInP, n-GaN, n-InGaN, or n-AlGaN.

84. A miniature LED, comprising: Type 1 semiconductor layer; A light-emitting layer is formed on the first type of semiconductor layer; as well as A second type of semiconductor layer is formed on the light-emitting layer; wherein the first type of semiconductor layer includes a first mesa structure, a first trench and a first ion implantation fence separated from the first mesa structure, the first trench extending upward through the first type of semiconductor layer and extending upward into at least a portion of the light-emitting layer; The first ion implantation fence is formed around the first trench, and the first trench is formed around the first mesa structure; the resistance of the first ion implantation fence is higher than the resistance of the first mesa structure. The second type of semiconductor layer includes a second mesa structure, a second trench, and a second ion implantation fence separated from the second mesa structure. The second ion implantation fence is formed around the second trench, and the second trench is formed around the second mesa structure, wherein the resistance of the second ion implantation fence is higher than the resistance of the second mesa structure; The conductivity type of the second type of semiconductor layer differs from that of the first type of semiconductor layer. The first tabletop structure includes one or more stepped structures, and the second tabletop structure includes one or more stepped structures.

85. The micro LED according to claim 84, wherein, The top surface of the first trench does not contact the bottom surface of the second trench, and a portion of the light-emitting layer is disposed between the top surface of the first trench and the bottom surface of the second trench.

86. The micro LED according to claim 85, wherein, The top surface of the first ion implantation fence is lower than the top surface of the first type of semiconductor layer, and the bottom surface of the second ion implantation fence is higher than the bottom surface of the second type of semiconductor layer.

87. The micro LED according to claim 84, wherein, The bottom surface of the first ion implantation fence is aligned with, or is higher than, or lower than, the bottom surface of the first type of semiconductor layer; and The top surface of the second ion implantation fence is aligned with or above or below the top surface of the second type of semiconductor layer.

88. The micro LED according to claim 84, wherein, The top surface of the first ion implantation fence is lower than the top surface of the first trench.

89. The micro LED according to claim 84, wherein, The second trench extends downward into the second type of semiconductor layer.

90. The micro LED according to claim 89, wherein, The second trench extends downward through the second type of semiconductor layer and downward into at least a portion of the light-emitting layer.

91. The micro LED according to claim 90, wherein, The bottom surface of the second ion implantation fence is higher than the bottom of the first trench.

92. The micro LED according to claim 84, wherein, The first trench is directly connected to the second trench, without the need to arrange the light-emitting layer between the first trench and the second trench.

93. The micro LED according to claim 84, wherein, The width of the first groove is not greater than 50% of the diameter of the first countertop structure; and / or, the width of the second groove is not greater than 50% of the diameter of the second countertop structure.

94. The micro LED according to claim 93, wherein, The width of the first trench is no greater than 200 nm; and / or the width of the second trench is no greater than 200 nm.

95. The micro LED according to claim 84, wherein, The first ion implantation fence includes a first light-absorbing material, and the second ion implantation fence includes a second light-absorbing material; wherein the conductivity type of the first light-absorbing material is the same as the conductivity type of the first type of semiconductor layer, and the conductivity type of the second light-absorbing material is the same as the conductivity type of the second type of semiconductor layer.

96. The micro LED according to claim 95, wherein, The first light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN; and / or the second light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

97. The micro LED according to claim 84, wherein, The thickness of the first type of semiconductor layer is greater than the thickness of the light-emitting layer, the thickness of the second type of semiconductor layer is greater than the thickness of the light-emitting layer, and the thickness of the first type of semiconductor layer is greater than the thickness of the second type of semiconductor layer.

98. The micro LED of claim 84, further comprising a bottom isolation layer formed between the bottom surface of the first type of semiconductor layer and the top surface of the integrated circuit IC backplane.

99. The micro LED according to claim 98, wherein, The material of the bottom insulating layer is selected from SiO2 and SiN. x One or more of Al2O3, AlN, HfO2, TiO2 or ZrO2.

100. The micro LED according to claim 84, wherein, The first ion implantation fence is formed by implanting a first ion into at least the first type of semiconductor layer; and the second ion implantation fence is formed by implanting a second ion into at least the second type of semiconductor layer.

101. The micro LED according to claim 100, wherein, The ions implanted into the first ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F; and the ions implanted into the second ion implantation fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

102. The micro LED according to claim 84, wherein, The width of the first ion implantation fence is no greater than 50% of the diameter of the first platform structure; and the width of the second ion implantation fence is no greater than 50% of the diameter of the second platform structure.

103. The micro LED according to claim 102, wherein, The width of the first ion implantation fence is no greater than 200 nm, the diameter of the first mesa structure is no greater than 2500 nm, and the thickness of the first type of semiconductor layer is no greater than 100 nm; and The width of the second ion implantation fence is no greater than 200 nm, the diameter of the second mesa structure is no greater than 2500 nm, and the thickness of the first type of semiconductor layer is no greater than 300 nm.

104. The micro LED according to claim 84, wherein, The material of the first type of semiconductor layer is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN, and the material of the second type of semiconductor layer is selected from one or more of GaAs, AlInP, GaInP, AlGaAs, AlGaInP, GaN, InGaN, or AlGaN.

105. The micro LED according to claim 84, further comprising: An integrated circuit (IC) backplane, wherein the integrated circuit (IC) backplane is formed beneath the first type of semiconductor layer; The connection structure electrically connects the integrated circuit (IC) backplane to the first type of semiconductor layer.

106. The micro LED according to claim 105, wherein, The connection structure is a connecting pillar or a metal bonding layer.

107. The micro LED according to claim 105, further comprising: A bottom contact is formed on the bottom surface of the first type of semiconductor layer, the upper surface of the connection structure is connected to the bottom contact, and the bottom surface of the connection structure is connected to the backplane of the integrated circuit (IC).

108. A micro LED array panel comprising a plurality of micro LEDs according to any one of claims 84 to 107.

109. A method for manufacturing a micro LED, the method comprising: Process I includes patterning a first type of semiconductor layer and implanting first ions into the first type of semiconductor layer; as well as Process II includes patterning a second type of semiconductor layer and implanting second ions into the second type of semiconductor layer, wherein process I further includes: An epitaxial structure is provided, wherein the epitaxial structure comprises, from top to bottom, a first type of semiconductor layer, a light-emitting layer, and a second type of semiconductor layer; The first type of semiconductor layer is patterned to form a first mesa structure, a first trench, and a first fence; Deposit the bottom contact on the first mezzanine structure; An ion implantation process is performed into the first fence to form an ion implantation fence; A bottom isolation layer is deposited on the first type of semiconductor layer and the bottom contact; Pattern the bottom isolation layer to expose the bottom contacts; Metallic material is deposited on the bottom insulating layer and the bottom contacts; The metal material is ground to the top surface of the bottom insulating layer to form a connection structure; and The epitaxial structure is flipped and the connection structure is bonded to the backplane of the integrated circuit (IC). Wherein, process II further includes: The second type of semiconductor layer is patterned to form a second mesa structure, a second trench, and a second fence; Deposit the top contact on the second mezzanine structure; Perform an ion implantation process into the second enclosure; and A top conductive layer is deposited on the top surface of the second type of semiconductor layer, on the top contact, and in the second trench. The first tabletop structure includes one or more stepped structures, and the second tabletop structure includes one or more stepped structures.

110. The method according to claim 109, wherein, Patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The first type of semiconductor layer is etched onto the surface of the light-emitting layer.

111. The method according to claim 109, wherein, Patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The first type of semiconductor layer and the light-emitting layer are etched sequentially; and The etching is stopped in the light-emitting layer.

112. The method according to claim 109, wherein, Patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence further includes: The first type of semiconductor layer, the light-emitting layer, and the second type of semiconductor layer are sequentially etched; and The etching is stopped in the second type of semiconductor layer.

113. The method according to claim 109, wherein, Depositing the bottom contact on the mesa structure further includes: A protective mask is formed to protect the area where the bottom contact is not deposited; The material of the bottom contact is deposited on the protective mask and on the first type of semiconductor layer; and The protective mask is removed from the first type of semiconductor layer, and the material on the protective mask is removed to form the bottom contact on the mesa structure.

114. The method according to claim 109, in, Performing the ion implantation process into the fence to form the ion implantation fence further includes: A protective mask is formed on the area not implanted with ions, while the fence is exposed; Injecting ions into the fence; and Remove the protective mask.

115. The method according to claim 114, wherein, When performing the ion implantation process into the fence to form the ion implantation fence, the implantation is performed at an energy of 0 keV to 500 keV and a dose of 1E10 to 9E17 is injected.

116. The method according to claim 114, wherein, When the ion implantation process is performed in the fence to form the ion implantation fence, the ions implanted into the fence are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl or F.

117. The method according to claim 114, wherein, When performing an ion implantation process into the fence to form the ion implantation fence, the width of the ion implantation fence is not greater than 50% of the diameter of the mesa structure, the width of the ion implantation fence is not greater than 200 nm, the diameter of the mesa structure is not greater than 2500 nm, and the thickness of the first type of semiconductor layer is not greater than 300 nm.

118. The method according to claim 109, wherein, When patterning the first type of semiconductor layer to form the mesa structure, the trench, and the fence, the width of the trench is no greater than 50% of the diameter of the mesa structure.

119. The method according to claim 109, wherein, Patterning the second type of semiconductor layer to form the second mesa structure, the second trench, and the second fence further includes: The second type of semiconductor layer is etched onto the surface of the light-emitting layer.

120. The method according to claim 109, wherein, Patterning the second type of semiconductor layer to form the second mesa structure, the second trench, and the second fence further includes: The second type of semiconductor layer and the light-emitting layer are etched sequentially, and The etching is stopped in the light-emitting layer.

121. The method according to claim 109, wherein, Patterning the second type of semiconductor layer to form the second mesa structure, the second trench, and the second fence further includes: The second type semiconductor layer, the light-emitting layer, and the first type semiconductor layer are etched sequentially. The etching is stopped in the first type of semiconductor layer.

122. The method according to claim 109, wherein, Depositing the top contact on the second mezzanine structure further includes: Form a protective mask; Deposit the material of the top contact onto the protective mask; The protective mask is removed from the second type of semiconductor layer, and the material of the top contact on the protective mask is removed to form the top contact on the second mesa structure.

123. The method according to claim 109, wherein, Performing the ion implantation process into the second enclosure further includes: A protective mask is formed on the uninjected area, while exposing the second fence; Ions are implanted into the second fence; and Remove the protective mask.

124. The method according to claim 109, wherein, When performing the ion implantation process into the second enclosure, implantation is performed at an energy of 0 keV to 500 keV, and a dose of 1E10 to 9E17 is injected.

125. The method according to claim 109, wherein, When performing the ion implantation process into the second enclosure, the ions implanted into the second enclosure are selected from one or more of H, N, Ar, Kr, Xe, As, O, C, P, B, Si, S, Cl, or F.

126. The method according to claim 109, wherein, The ion implantation process is performed in the second fence to form a second ion implantation fence, wherein the width of the second ion implantation fence is not greater than 50% of the diameter of the second mesa structure, the width of the second ion implantation fence is not greater than 200 nm, the diameter of the second mesa structure is not greater than 2500 nm, and the thickness of the second type semiconductor layer is not greater than 100 nm.

127. The method according to claim 109, wherein, When providing the epitaxial structure, the epitaxial structure is grown on a substrate; and the step of flipping the epitaxial structure and bonding the interconnect structure to the backplane of the integrated circuit (IC) further includes: Remove the substrate.

128. The method according to claim 109, wherein, When the bottom isolation layer is deposited on the first type of semiconductor layer and the bottom contact, the material of the bottom isolation layer is selected from SiO2 and SiN. x One or more of Al2O3, AlN, HfO2, TiO2 or ZrO2.

129. The method according to claim 109, wherein, The first ion implantation fence includes a light-absorbing material.

130. The method according to claim 129, wherein, The light-absorbing material is selected from one or more of GaAs, GaP, AlInP, GaN, InGaN, or AlGaN.

131. The method according to claim 109, wherein, The first type of semiconductor layer has a P-type conductivity, and the second type of semiconductor layer has an N-type conductivity; the material of the first type of semiconductor layer is selected from one or more of p-GaAs, p-GaP, p-AlInP, p-GaN, p-InGaN, or p-AlGaN; and the material of the second type of semiconductor layer is selected from one or more of n-GaAs, n-AlInP, n-GaInP, n-AlGaAs, n-AlGaInP, n-GaN, n-InGaN, or n-AlGaN.

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