Display panel, driving method thereof, and display device

Abstract

Embodiments of the present application provide a display panel, a driving method thereof and a display device, and relate to the display field, and optimize the performance of a pixel circuit. The display panel comprises a pixel circuit, which comprises: a driving module; a gate reset module connected with a first scan line, a first reset line and a control end of the driving module; a threshold compensation module connected with a second scan line, a second end of the driving module and the control end of the driving module; and a data writing module connected with a third scan line, a data line and a first end of the driving module. In one frame of time, the first scan line outputs a first effective level and a second effective level, the second scan line outputs a third effective level and a fourth effective level, and the third scan line outputs a fifth effective level. The third effective level is at least partially located between the first effective level and the second effective level, the second effective level is at least partially located between the third effective level and the fourth effective level, and the fifth effective level overlaps with the fourth effective level.

Description

[Technical Field]

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. [Background Technology]

[0002] The display panel includes pixel circuitry and light-emitting elements. The pixel circuitry provides driving current to the light-emitting elements to drive them to emit light.

[0003] Pixel circuits typically consist of a driving transistor and multiple switching transistors. The characteristics of the driving transistor significantly influence the performance of the pixel circuit, and consequently, the light-emitting effect of the light-emitting element. Therefore, optimizing the characteristics of the driving transistor has become a pressing technical problem. [Summary of the Invention]

[0004] In view of this, embodiments of the present invention provide a display panel and its driving method and display device, for optimizing the circuit performance of pixel circuits.

[0005] On one hand, embodiments of the present invention provide a display panel, including a pixel circuit, the pixel circuit comprising:

[0006] The drive module has its control terminal electrically connected to the first node, its first terminal electrically connected to the second node, and its second terminal electrically connected to the third node.

[0007] A gate reset module, wherein the control terminal of the gate reset module is electrically connected to the first scan line, the first terminal is electrically connected to the first reset line, and the second terminal is electrically connected to the first node;

[0008] A threshold compensation module, wherein the control terminal of the threshold compensation module is electrically connected to the second scan line, the first terminal is electrically connected to the third node, and the second terminal is electrically connected to the first node;

[0009] The data writing module has a control terminal electrically connected to the third scan line, a first terminal electrically connected to the data line, and a second terminal electrically connected to the second node.

[0010] Specifically, for the first scan line, the second scan line, and the third scan line electrically connected to the same pixel circuit, within one frame, the first scan line outputs a first effective level and a second effective level, the second scan line outputs a third effective level and a fourth effective level, and the third scan line outputs a fifth effective level. Furthermore, at least a portion of the third effective level is located between the first effective level and the second effective level, at least a portion of the second effective level is located between the third effective level and the fourth effective level, and the fifth effective level overlaps with the fourth effective level.

[0011] On the other hand, embodiments of the present invention provide a driving method for a display panel.

[0012] The display panel includes a pixel circuit, the pixel circuit comprising:

[0013] The drive module has its control terminal electrically connected to the first node, its first terminal electrically connected to the second node, and its second terminal electrically connected to the third node.

[0014] A gate reset module, wherein the control terminal of the gate reset module is electrically connected to the first scan line, the first terminal is electrically connected to the first reset line, and the second terminal is electrically connected to the first node;

[0015] A threshold compensation module, wherein the control terminal of the threshold compensation module is electrically connected to the second scan line, the first terminal is electrically connected to the third node, and the second terminal is electrically connected to the first node;

[0016] The data writing module has a control terminal electrically connected to the third scan line, a first terminal electrically connected to the data line, and a second terminal electrically connected to the second node.

[0017] Specifically, for the first scan line, the second scan line, and the third scan line electrically connected to the same pixel circuit, within one frame, the first scan line outputs a first effective level and a second effective level, the second scan line outputs a third effective level and a fourth effective level, and the third scan line outputs a fifth effective level. Furthermore, at least a portion of the third effective level is located between the first effective level and the second effective level, at least a portion of the second effective level is located between the third effective level and the fourth effective level, and the fifth effective level overlaps with the fourth effective level.

[0018] The driving cycle of the pixel circuit includes a first time period, a second time period, a third time period, and a fourth time period;

[0019] The driving method includes:

[0020] During the first time period, the gate reset module is turned on in response to the first valid level, and the first reset voltage provided by the first reset line is written to the first node;

[0021] During the second time period, the threshold compensation module is activated in response to the third valid level;

[0022] During the third time period, the gate reset module turns on in response to the second valid level, and the first reset voltage provided by the first reset line is written to the first node;

[0023] During the fourth time period, the data writing module responds to the fifth valid level to turn on, the threshold compensation module responds to the fourth valid level to turn on, and the data voltage on the data line is written to the first node and threshold compensation is performed.

[0024] In another aspect, embodiments of the present invention provide a display device including the aforementioned display panel.

[0025] One of the above technical solutions has the following beneficial effects:

[0026] In the technical solution provided by this invention, before charging, the pixel circuit performs a three-terminal reset operation on the driving module: In the first time period, by controlling the first scan line to provide a first effective level, a first reset voltage can be written to the first node, controlling the driving module to turn on. Then, in the second time period, by controlling the second scan line to provide a third effective level, the threshold compensation module can be turned on, thereby forming a conductive signal path between the first node, the third node, and the second node. This allows the voltage on the first node to be further written to the third and second nodes, or the voltage on the second node to be further written to the third and first nodes. For example, during this time period, the first reset voltage on the first node can be transmitted to the third node via the turned-on threshold compensation module, and then to the second node via the turned-on driving module, thus achieving a three-terminal reset of the driving module. In this way, before charging, the device characteristics of the driving modules in different pixel circuits are set to the same initial state, effectively solving the problem of inconsistent device characteristics of the driving modules caused by different gray levels displayed by different sub-pixels in the previous frame.

[0027] Furthermore, in this embodiment of the invention, after the driving module is reset at three terminals and before charging, the first scan line will provide a second effective level to control the gate reset module to turn on again, reset the first node again, compensate for potential changes that may occur in the first node during the second time period, and ensure the consistency of charging effect of different pixel circuits. [Attached Image Description]

[0028] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0030] Figure 2This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0031] Figure 3 for Figure 2 A corresponding timing diagram;

[0032] Figure 4 This is a schematic diagram illustrating a connection between a scan line and a shift register provided in an embodiment of the present invention;

[0033] Figure 5 for Figure 4 A schematic diagram of a connection between the scan line corresponding to the i-th circuit row and the shift register;

[0034] Figure 6 for Figure 5 A corresponding timing diagram;

[0035] Figure 7 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0036] Figure 8 This is a schematic diagram illustrating another connection between the scan line and the shift register provided in an embodiment of the present invention;

[0037] Figure 9 for Figure 8 Another schematic diagram showing the connection between the scan line corresponding to the i-th circuit row and the shift register;

[0038] Figure 10 for Figure 9 A corresponding timing diagram;

[0039] Figure 11 This is a schematic diagram illustrating another connection between the scan line and the shift register provided in an embodiment of the present invention;

[0040] Figure 12 for Figure 11 A schematic diagram of a connection between the scan line corresponding to the i-th circuit row and the shift register;

[0041] Figure 13 for Figure 12 A corresponding timing diagram;

[0042] Figure 14 for Figure 12 Another corresponding timing diagram;

[0043] Figure 15 for Figure 12 Another corresponding timing diagram;

[0044] Figure 16 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0045] Figure 17 This is another schematic diagram showing the connection between the scan line and the shift register provided in an embodiment of the present invention;

[0046] Figure 18 for Figure 17 A schematic diagram of a connection between the scan line corresponding to the i-th circuit row and the shift register;

[0047] Figure 19 for Figure 18 A corresponding timing diagram;

[0048] Figure 20 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0049] Figure 21 This is another schematic diagram showing the connection between the scan line and the shift register provided in an embodiment of the present invention;

[0050] Figure 22 for Figure 21 A schematic diagram of a connection between the scan line corresponding to the i-th circuit row and the shift register;

[0051] Figure 23 for Figure 22 A corresponding timing diagram;

[0052] Figure 24 This is another schematic diagram showing the connection between the scan line and the shift register provided in an embodiment of the present invention;

[0053] Figure 25 Figure 24 A schematic diagram of a connection between the scan line corresponding to the i-th circuit row and the shift register;

[0054] Figure 26 for Figure 25 A corresponding timing diagram;

[0055] Figure 27 for Figure 25 Another corresponding timing diagram;

[0056] Figure 28 This is a timing diagram corresponding to the shift register provided in an embodiment of the present invention;

[0057] Figure 29 This is a timing diagram corresponding to the shift register provided in an embodiment of the present invention;

[0058] Figure 30 This is another schematic diagram showing the connection between the scan line and the shift register provided in an embodiment of the present invention;

[0059] Figure 31 for Figure 30A schematic diagram of a connection between the scan line corresponding to the i-th circuit row and the shift register;

[0060] Figure 32 for Figure 31 A corresponding timing diagram;

[0061] Figure 33 This is another schematic diagram showing the connection between the scan line corresponding to the i-th circuit row and the shift register provided in an embodiment of the present invention;

[0062] Figure 34 This is another schematic diagram showing the connection between the scan line corresponding to the i-th circuit row and the shift register provided in an embodiment of the present invention;

[0063] Figure 35 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0064] Figure 36 This is a schematic diagram of another structure of the pixel circuit provided in an embodiment of the present invention;

[0065] Figure 37 This is a schematic diagram of a display device provided in an embodiment of the present invention.

Detailed Implementation Methods

[0066] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0067] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0068] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0069] It should be understood that although the terms "first" and "second" may be used to describe scan lines in embodiments of the present invention, these scan lines should not be limited to these terms. These terms are only used to distinguish scan lines from each other. For example, without departing from the scope of embodiments of the present invention, a first scan line may also be referred to as a second scan line, and similarly, a second scan line may also be referred to as a first scan line.

[0070] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0071] This invention provides a display panel, such as an organic light-emitting diode (OLED) display panel.

[0072] like Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a pixel circuit 1.

[0073] like Figure 2 and Figure 3 As shown, Figure 2 This is a schematic diagram of a pixel circuit 1 provided in an embodiment of the present invention. Figure 3 for Figure 2 One corresponding timing diagram shows that the pixel circuit 1 includes a driving module 2, a gate reset module 3, a threshold compensation module 4, and a data writing module 5.

[0074] Specifically, the control terminal of the drive module 2 is electrically connected to the first node N1, the first terminal is electrically connected to the second node N2, and the second terminal is electrically connected to the third node N3. The control terminal of the gate reset module 3 is electrically connected to the first scan line S1, the first terminal is electrically connected to the first reset line Ref1, and the second terminal is electrically connected to the first node N1. The control terminal of the threshold compensation module 4 is electrically connected to the second scan line S2, the first terminal is electrically connected to the third node N3, and the second terminal is electrically connected to the first node N1. The control terminal of the data writing module 5 is electrically connected to the third scan line S3, the first terminal is electrically connected to the data line Data, and the second terminal is electrically connected to the second node N2.

[0075] For the first scan line S1, the second scan line S2, and the third scan line S3 electrically connected to the same pixel circuit 1: within one frame, the first scan line S1 outputs a first effective level el1 and a second effective level el2, the second scan line S2 outputs a third effective level el3 and a fourth effective level el4, and the third scan line S3 outputs a fifth effective level el5. At least a portion of the third effective level el3 is located between the first effective level el1 and the second effective level el2, at least a portion of the second effective level el2 is located between the third effective level el3 and the fourth effective level el4, and the fifth effective level el5 overlaps with the fourth effective level el4.

[0076] Corresponding to the above structure, the driving cycle of pixel circuit 1 includes a first time period T1, a second time period T2, a third time period T3, and a fourth time period T4.

[0077] During the first time period T1, the gate reset module 3 responds to the first valid level el1 and turns on, writing the first reset voltage provided by the first reset line Ref1 into the first node N1.

[0078] During the second time period T2, the threshold compensation module 4 responds to the third valid level el3 and is turned on.

[0079] During the third time period T3, the gate reset module 3 responds to the second effective level el2 and turns on, writing the first reset voltage provided by the first reset line Ref1 back into the first node N1.

[0080] During the fourth time period T4, the data writing module 5 responds to the fifth valid level el5 and turns on, and the threshold compensation module 4 responds to the fourth valid level el4 and turns on, writing the data voltage provided by the data line Data to the first node N1 and performing threshold compensation on the drive module 2.

[0081] The inventors discovered that within a single frame, different sub-pixels may display different grayscale levels, meaning that the data voltages written to different pixel circuits may differ. Consequently, after a frame ends, inconsistencies in the residual potentials at different terminals of the driving module 2 in different pixel circuits 1 can occur.

[0082] In related technologies, within one frame, the control terminal of the driving module is reset only once before charging. However, the driving modules in different pixel circuits will still have inconsistent device characteristics of transistors in the driving module due to the different residual potentials at the first and second terminals, which in turn affects subsequent charging.

[0083] The technical solution provided by the embodiments of the present invention can effectively solve this problem. In the technical solution provided by the embodiments of the present invention, before charging, the pixel circuit 1 performs a three-terminal reset operation on the driving module 2: In the first time period T1, the first scan line S1 provides a first effective level e1, which can control the gate reset module 3 to turn on, thereby writing a first reset voltage to the first node N1, so that the driving module 2 turns on. Then, in the second time period T2, the second scan line S2 provides a third effective level e13, which can control the threshold compensation module 4 to turn on, thereby forming a conductive signal path between the first node N1, the third node N3 and the second node N2. For example, the voltage on the first node N1 can be further written to the third node N3 and the second node N2, or the voltage on the second node N2 can be further written to the third node N3 and the first node N1. For example, during this time period, the first reset voltage on the first node N1 can be transmitted to the third node N3 through the turned-on threshold compensation module 4, and then transmitted to the second node N2 through the turned-on driving module 2, thereby realizing the three-terminal reset of the driving module 2. In this way, before charging, the device characteristics of the driving module 2 in different pixel circuits 1 will be set to the same initial state, which can effectively solve the problem of inconsistent device characteristics of the driving module 2 caused by different sub-pixels displaying different gray levels in the previous frame.

[0084] Furthermore, in this embodiment of the invention, after the three-terminal reset of the driving module 2 is completed, before entering the charging period, the first scan line S1 will also provide a second effective level e12 to control the gate reset module 3 to turn on again and reset the first node N1 again. This can compensate for the potential changes that may occur in the first node N1 during the second period T2, and ensure that the potential of the first node N1 of different pixel circuits 1 is consistent before charging.

[0085] In one feasible implementation, see Figures 4-6 , Figures 11-15 , Figures 17-19 The display panel also includes a first shift register 9, which includes a plurality of first sub-shift registers 10 cascaded together. Within one frame, the first sub-shift registers 10 output at least two valid levels.

[0086] Specifically, for the same pixel circuit 1, at least two of its corresponding first scan line S1, second scan line S2, and third scan line S3 are electrically connected to the first sub-shift register 10. This means that the scan signals provided by at least two of the first scan line S1, second scan line S2, and third scan line S3 are borrowed signals from different levels within the same shift register. In this way, these three scan lines require at most two shift registers to drive, reducing the number of shift registers in the display panel and helping to narrow the bezel.

[0087] Furthermore, in this embodiment of the invention, all three of the first scan line S1, the second scan line S2, and the third scan line S3 may be electrically connected to the first shift register 9, or only two of the first scan line S1, the second scan line S2, and the third scan line S3 may be electrically connected to the first shift register 9.

[0088] When the first scan line S1, the second scan line S2, and the third scan line S3 are all electrically connected to the first shift register 9, combined with Figure 2 , Figures 4-6 , Figure 4 This is a schematic diagram illustrating a connection between a scan line and a shift register provided in an embodiment of the present invention. Figure 5 for Figure 4 A schematic diagram showing one connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 6 for Figure 5 In a corresponding timing diagram, the display panel also includes a plurality of circuit rows 11 arranged along a first direction x, and the circuit rows 11 include a plurality of pixel circuits 1 arranged along a second direction y, wherein the first direction x and the second direction y intersect.

[0089] For the i-th circuit row 11_i, its corresponding first scan line S1, second scan line S2, and third scan line S3 are electrically connected to the m-th level first sub-shift register 10_m, the (m+1)-th level first sub-shift register 10_m+1, and the (m+3)-th level first sub-shift register 10_m+3 in the first shift register 9, respectively. i is an integer greater than or equal to 1, and m is an integer greater than or equal to 1.

[0090] In one embodiment, m = i. That is, the first scan line S1, the second scan line S2, and the third scan line S3 corresponding to the first circuit row 11_1 are electrically connected to the first sub-shift register 10 of the first stage, the second stage, and the fourth stage, respectively; the first scan line S1, the second scan line S2, and the third scan line S3 corresponding to the second circuit row 11_2 are electrically connected to the first sub-shift register 10 of the second stage, the third stage, and the fifth stage, respectively; and so on.

[0091] Based on the operating characteristics of shift registers, when multiple sub-shift registers within the same shift register output valid levels sequentially, the valid levels output by adjacent sub-shift registers do not overlap. When all three scan lines are electrically connected to the first shift register 9, the first valid level el1, the second valid level el2, the third valid level el3, the fourth valid level el4, and the fifth valid level el5 satisfy the following: the third valid level el3 is located between the first valid level el1 and the second valid level el2, and the time interval between the third valid level el3 and the first valid level el1 and the second valid level el2 is equal; the second valid level el2 is located between the third valid level el3 and the fourth valid level el4, and the time interval between the second valid level el2 and the third valid level el3 and the fourth valid level el4 is equal; the time intervals of the fifth valid level el5 and the fourth valid level el4 overlap.

[0092] This enables the following: in the first time period T1, the gate reset module 3 is turned on to reset the first node N1; in the second time period T2, the threshold compensation module 4 is turned on to reset the drive module 2; in the third time period T3, the gate reset module 3 is turned on to reset the first node N1 again; and in the fourth time period T4, the data writing module 5 and the threshold compensation module 4 are turned on to charge and compensate the first node N1.

[0093] Furthermore, when the third scan line S3 is connected to the first shift register 9, after outputting the fifth valid level el5, the third scan line S3 will also output a sixth valid level el6. For further details, see [link to relevant documentation]. Figure 6 The driving cycle of pixel circuit 1 also includes the fifth time period T5 and the sixth time period T6. In the sixth time period T6, the data writing module 5 responds to the sixth effective level el6 and turns on, writing the voltage on the data line Data to the second node N2, thereby refreshing the potential of the second node N2 after charging, adjusting the bias state of the driving transistor M0, preventing the characteristics of the driving transistor M0 from drifting, improving the hysteresis effect of the driving transistor M0, and weakening the afterimage.

[0094] In the above structure, the signals required for the first scan line S1, the second scan line S2, and the third scan line S3 are provided by the same set of shift registers, which greatly reduces the number of shift registers that need to be set in the display panel. This technical solution is more suitable for display panel designs with extremely narrow bezels.

[0095] Furthermore, such as Figures 7-10 As shown, Figure 7 This is a schematic diagram of another structure of the pixel circuit 1 provided in an embodiment of the present invention. Figure 8This is a schematic diagram illustrating another connection between the scan line and the shift register provided in an embodiment of the present invention. Figure 9 for Figure 8 Another schematic diagram showing the connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 10 for Figure 9 In a corresponding timing diagram, the pixel circuit 1 also includes an anode reset module 12. The control terminal of the anode reset module 12 is electrically connected to the fourth scan line S4, the first terminal is electrically connected to the second reset line Ref2, and the second terminal is electrically connected to the light-emitting element 14.

[0096] Specifically, for the i-th circuit row 11_i, its corresponding fourth scan line S4 is electrically connected to the first sub-shift register 10_m+2 of the m+2-th stage in the first shift register 9.

[0097] Based on the above structure, see Figure 10 During the third time period T3 and the fifth time period T5, the anode reset module 12 is activated, and the second reset voltage on the second reset line Ref2 is written to the anode of the light-emitting element 14 to reset the anode of the light-emitting element 14. In this structure, the signal required for the fourth scan line S4 is also provided by the first shift register 9, eliminating the need to configure other shift registers for the fourth scan line S4, resulting in a more optimized structural design for the display panel.

[0098] When only two of the first scan line S1, the second scan line S2, and the third scan line S3 are electrically connected to the first shift register 9, see [reference needed]. Figures 11-15 , Figures 17-19 The display panel also includes a second shift register 15, which includes a plurality of cascaded second sub-shift registers 16. The first shift register 9 and the second shift register 15 can be located on opposite sides of the circuit row 11 in the second direction y.

[0099] In this configuration, the first scan line S1 is electrically connected to the second sub-shift register 16, and the second scan line S2 and the third scan line S3 are electrically connected to the first sub-shift register 10. Alternatively, the first scan line S1 and the second scan line S2 are electrically connected to the first sub-shift register 10, and the third scan line S3 is electrically connected to the second sub-shift register 16.

[0100] When the signals provided by the first scan line S1, the second scan line S2, and the third scan line S3 come from two shift registers, by differentiating the types of these two shift registers, the time when the frame start signal is received, and the pulse width and frequency of the received clock signal, the parameters of the effective level output by the above scan lines can be controlled in a variety of ways, making the driving of the pixel circuit more flexible.

[0101] When the display panel includes a second shift register 15, in one feasible implementation, it is combined with Figure 2 , Figures 11-13 , Figure 11 This is a schematic diagram illustrating another connection between the scan line and the shift register provided in an embodiment of the present invention. Figure 12 for Figure 11 A schematic diagram showing one connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 13 for Figure 12 In one corresponding timing diagram, the second sub-shift register 16 outputs at least two valid levels within one frame.

[0102] The display panel also includes a plurality of circuit rows 11 arranged along a first direction x, the circuit rows 11 including a plurality of pixel circuits 1 arranged along a second direction y, the first direction x and the second direction y intersecting.

[0103] For the i-th circuit row 11_i, its corresponding first scan line S1 is electrically connected to the n-th stage second sub-shift register 16_n in the second shift register 15, and its corresponding second scan line S2 and third scan line S3 are electrically connected to the m-th stage first sub-shift register 10_m and the (m+2)-th stage first sub-shift register 10_m+2 in the first shift register 9, respectively. i is an integer greater than or equal to 1, m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1.

[0104] In one embodiment, m = i, n = i. That is, for the first circuit row 11_1, its corresponding first scan line S1 is electrically connected to the first-stage second sub-shift register 16_1, and its corresponding second scan line S2 and third scan line S3 are electrically connected to the first-stage first sub-shift register 10_1 and the third-stage first sub-shift register 10_3, respectively; for the second circuit row 11_2, its corresponding first scan line S1 is electrically connected to the second-stage second sub-shift register 16_2, and its corresponding second scan line S2 and third scan line S3 are electrically connected to the second-stage first sub-shift register 10_2 and the fourth-stage first sub-shift register 10_4, respectively; ...; and so on.

[0105] And see also Figure 13The time interval between the moment when the nth-stage second sub-shift register 16_n stops outputting the first valid level el1 and the moment when the mth-stage first sub-shift register 10_m starts outputting the third valid level el3 is t1. The time interval between the moment when the mth-stage first sub-shift register 10_m stops outputting the third valid level el3 and the moment when the nth-stage second sub-shift register 16_n starts outputting the second valid level el2 is t2, where t1 ≠ t2. Furthermore, the second valid level el2 output by the nth-stage second sub-shift register 16_n does not overlap with the fifth valid level el5 output by the (m+2)th-stage first sub-shift register 10_m+2.

[0106] In this structure, the second scan line S2 and the third scan line S3 are electrically connected to the first shift register 9, while the first scan line S1 is electrically connected to the second shift register 15 alone. By adjusting the timing of the first shift register 9 receiving the frame start signal, the timing of the effective output levels of the second scan line S2 and the third scan line S3 can be adjusted. For example, the interval between the third effective level el3 output by the second scan line S2 and the first effective level el1 output by the first scan line S1 can be shortened or lengthened, thereby enabling more flexible driving of the pixel circuit 1 when performing various operations.

[0107] Furthermore, the above configuration further limits the overlap between the second effective level el2 and the fifth effective level el5. That is, during the time period when the fourth effective level el4 and the fifth effective level el5 overlap, the output of the first scan line S1 is an ineffective level. This can prevent the gate reset module 3, the data writing module 5 and the threshold compensation module 4 from being turned on at the same time, and from writing the first reset voltage and the data voltage to the first node N1 at the same time, which would cause the signal of the first node N1 to be disordered.

[0108] Furthermore, see again Figure 13 Since t1 < t2, the time when the third effective level el3 output by the second scan line S2 is adjusted forward. Correspondingly, the time when the third scan line S3 stops outputting the sixth enable level el6 is also adjusted forward. This can compress the overall time required for the first scan line S1, the second scan line S2, and the third scan line S3 to output effective levels within one frame, reduce the non-light emission time, and increase the proportion of light emission time.

[0109] Of course, in other optional embodiments of the present invention, such as Figure 14 and Figure 15 As shown, Figure 14 for Figure 12 Another corresponding timing diagram, Figure 15 for Figure 12 Another possible time series diagram is t1 > t2.

[0110] It should be noted that when t1 > t2, provided that the second effective level el2 and the fifth effective level el5 do not overlap, see [reference needed]. Figure 15 The third effective level el3 can overlap with the second effective level el2. At this time, the moment when the first sub-shift register 10_m of the m-th stage stops outputting the third effective level el3 is later than the moment when the second sub-shift register 16_n of the n-th stage starts outputting the second effective level el2.

[0111] When the display panel includes a second shift register 15, in another feasible implementation, such as Figures 16-19 As shown, Figure 16 This is a schematic diagram of another structure of the pixel circuit 1 provided in an embodiment of the present invention. Figure 17 This is another schematic diagram illustrating the connection between the scan line and the shift register provided in an embodiment of the present invention. Figure 18 for Figure 17 A schematic diagram showing one connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 19 for Figure 18 In one corresponding timing diagram, within one frame, the second sub-shift register 16 outputs at least one valid level, and the valid level output by the second sub-shift register 16 is at a different potential than the valid level output by the first sub-shift register 10.

[0112] The display panel also includes a plurality of circuit rows 11 arranged along a first direction x, the circuit rows 11 including a plurality of pixel circuits 1 arranged along a second direction y, the first direction x and the second direction y intersecting.

[0113] Specifically, for the i-th circuit row 11_i, its corresponding first scan line S1 and second scan line S2 are electrically connected to the m-th level first sub-shift register 10_m and the (m+1)-th level first sub-shift register 10_m+1 in the first shift register 9, respectively, and its corresponding third scan line S3 is electrically connected to the n1-th level second sub-shift register 16_n1 in the second shift register 15. i is an integer greater than or equal to 1, m is an integer greater than or equal to 1, and n1 is an integer greater than or equal to 1.

[0114] The effective level output by the second sub-shift register 16 is opposite to the effective level output by the first sub-shift register 10, meaning that the data writing transistor M3 in the data writing module 5, the gate reset transistor M1 in the gate reset module 3, and the threshold compensation transistor M2 in the threshold compensation module 4 are of opposite transistor types. In this embodiment of the invention, the data writing transistor M3 can be designed as a P-type low-temperature polysilicon (LTPS) transistor, and the gate reset transistor M1 and the threshold compensation transistor M2 can be designed as N-type indium gallium zinc oxide (IGZO) transistors with lower leakage current. In this case, the effective level output by the second sub-shift register 16 is low, while the effective level output by the first sub-shift register 10 is high.

[0115] In this configuration, the transistors in pixel circuit 1 do not need to be limited to the same type. For example, some IGZO transistors can be used to reduce the leakage current of the driving transistor M0. In addition, in this structure, the third scan line S3 is driven separately by the second shift register 15. Therefore, the number of effective levels output by the third scan line S3 within one frame can be differentiated from the number of effective levels output by the first scan line S1 and the second scan line S2. For example, the third scan line S3 can be controlled to output only one effective level (the fifth effective level el5) within one frame.

[0116] In one feasible implementation, such as Figures 20-23 As shown, Figure 20 This is a schematic diagram of another structure of the pixel circuit 1 provided in an embodiment of the present invention. Figure 21 This is another schematic diagram illustrating the connection between the scan line and the shift register provided in an embodiment of the present invention. Figure 22 for Figure 21 A schematic diagram showing one connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 23 for Figure 22 In a corresponding timing diagram, the display panel also includes a bias adjustment module 17. The control terminal of the bias adjustment module 17 is electrically connected to the fifth scan line S5, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the second node N2.

[0117] For the i-th circuit row 11_i, its corresponding fifth scan line S5 is electrically connected to the n2-th sub-shift register 16_n2 in the second shift register 15, where n2 is an integer greater than or equal to 1 and n2 ≠ n1.

[0118] Based on the above structure, before or after charging, the bias adjustment module 17 is turned on, writing the bias voltage on the bias signal line DVH into the second node N2, refreshing the potential of the second node N2, adjusting the bias state of the driving transistor M0, preventing the characteristics of the driving transistor M0 from drifting, and improving the hysteresis effect of the driving transistor M0. Furthermore, the fifth scan line S5 and the third scan line S3 are connected to the same shift register, eliminating the need for an additional shift register for the fifth scan line S5.

[0119] For n2, in one feasible implementation, see again... Figures 21-23 n2 = n1 + 1. In one embodiment, n1 = i, n2 = i + 1.

[0120] This structure adjusts the bias state of the driving transistor M0 using the bias drive module 2 after charging is complete, thereby maintaining the driving transistor M0 with better characteristics during the period from charging to light emission.

[0121] Furthermore, when n2 = n1 + 1, see again... Figure 23 The time interval between the effective level output by the second sub-shift register 16_n2 of the n2nd stage and the effective level output by the second sub-shift register 16_n1 of the n1st stage is . Where F is the duration of one frame, and X is the number of circuit lines 11. It is also commonly referred to as a line time H.

[0122] When the fifth scan line S5 outputs an effective level later than the third scan line S3, by making the effective levels output sequentially by the second shift register 15 have a small time interval, the overall time required for the first scan line S1, the second scan line S2, the third scan line S3 and the fifth scan line S5 to output effective levels within one frame can be compressed, thereby reducing the non-light emission time.

[0123] Or, such as Figures 24-26 As shown, Figure 24 This is another schematic diagram illustrating the connection between the scan line and the shift register provided in an embodiment of the present invention. Figure 25 Figure 24 A schematic diagram showing one connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 26 for Figure 25 In one corresponding timing diagram, n1 is an integer greater than or equal to 2, and n2 = n1 - 1. In one embodiment, n2 = i, and n1 = i + 1. This structure adjusts the bias state of the driving transistor M0 using the bias drive module 2 before charging.

[0124] Furthermore, such as Figure 27 As shown,Figure 27 for Figure 25 In another timing diagram, for the i-th circuit row 11_i, the effective level output by the second sub-shift register 16_n2 of the n2-th stage overlaps with the third effective level el3 output by the first sub-shift register 10_m+1 of the m+1-th stage.

[0125] Typically, the bias voltage is much greater than the reset voltage. In this embodiment of the invention, the bias adjustment module 17 is turned on during the second time period T2. During the second time period T2, both the threshold compensation module 4 and the bias adjustment module 17 are turned on. Since the second node N2 will be continuously written with bias voltage, the bias voltage of the second node N2 will be further written to the third node N3 and the first node N1, so that the driver module 2 can be reset using only the bias voltage, which can avoid the potential difference between the two ends of the driver module 2 being too large.

[0126] In one feasible implementation, such as Figure 28 As shown, Figure 28 The timing diagram corresponding to the shift register provided in the embodiment of the present invention is such that the pulse width of the effective level output by the first sub-shift register 10 is greater than the pulse width of the effective level output by the second sub-shift register 16.

[0127] Currently, shift registers that output high active levels and shift registers that output low active levels are of different types. Generally, shift registers that output high active levels can output a larger pulse width for the active level. Therefore, in this embodiment of the invention, the pulse widths of the active levels output by the first shift register 9 and the second shift register 15 can be differentiated, allowing the first sub-shift register 10 to output a high active level with a larger pulse width. From another perspective, the larger the pulse width of the active level output by the first sub-shift register 10, the longer the three-terminal reset time of the drive module 2, and the better the reset effect.

[0128] In one feasible implementation, such as Figure 29 As shown, Figure 29 The timing diagram corresponding to the shift register provided in the embodiment of the present invention is shown in a display panel having a first mode. In the first mode, a frame time F includes a write frame F1 and a hold frame F2. In at least one hold frame F2, the second sub-shift register 16 outputs an effective level.

[0129] The first mode can be a low-frequency mode. Because a frame in low-frequency mode is longer, the offset of the driving transistor M0 is greater. Therefore, by making the second sub-shift register 16 also output an effective level in at least one holding frame F2, the bias state of the driving transistor M0 can be adjusted in the holding frame F2, thereby improving device performance.

[0130] In one feasible implementation, combined withFigure 15 ,like Figures 30-32 As shown, Figure 30 This is another schematic diagram illustrating the connection between the scan line and the shift register provided in an embodiment of the present invention. Figure 31 for Figure 30 A schematic diagram showing one connection between the scan line corresponding to the i-th circuit row and the shift register. Figure 32 for Figure 31 In a corresponding timing diagram, the display panel also includes a bias adjustment module 17. The control terminal of the bias adjustment module 17 is electrically connected to the fifth scan line S5, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the second node N2.

[0131] The display panel also includes a third shift register 19, which includes a plurality of cascaded third sub-shift registers 20, and the third sub-shift registers 20 output at least one valid level within one frame.

[0132] The fifth scan line S5 is electrically connected to the third sub-shift register 20, and the effective levels output by the second sub-shift register 16 and the third sub-shift register 20 connected to the same pixel circuit 1 do not overlap.

[0133] Specifically, see Figure 31 For the i-th circuit row 11_i, its corresponding fifth scan line S5 is electrically connected to the k-th stage third sub-shift register 20 in the third shift register 19. In one embodiment, k = i.

[0134] In this structure, the data writing module 5 and the bias adjustment module 17 in the pixel circuit 1 are driven by two different shift registers, allowing for independent control of the on-time and on-frequency of the data writing module 5 and the bias adjustment module 17. For example, see... Figure 32 In hold frame F2, only the third shift register 19 can output an effective level, while the second sub-shift register 16 does not output an effective level.

[0135] In one feasible implementation, combined with Figure 7 The pixel circuit 1 also includes an anode reset module 12. The control terminal of the anode reset module 12 is electrically connected to the fourth scan line S4, the first terminal is electrically connected to the second reset line Ref2, and the second terminal is electrically connected to the light-emitting element 14.

[0136] Among them, such as Figure 33 As shown, Figure 33This is another schematic diagram showing the connection between the scan line corresponding to the i-th circuit row and the shift register provided in an embodiment of the present invention. The fourth scan line S4 is electrically connected to the first sub-shift register 10. For example, for the i-th circuit row 11_i, when its corresponding first scan line S1 is the n-th level second sub-shift register 16_n in the second shift register 15, and its corresponding second scan line S2 and third scan line S3 are the m-th level first sub-shift register 10_m and the (m+2)-th level first sub-shift register 10_m+1 in the first shift register 9, its corresponding fourth scan line S4 is the (m+1)-th level first sub-shift register 10_m+1 in the first shift register 9.

[0137] When the first sub-shift register 10 of the (m+1)th stage outputs an effective level, the anode reset module 12 is turned on, and the anode of the light-emitting element 14 is reset using the second reset voltage.

[0138] Or, such as Figure 34 As shown, Figure 34 This is another schematic diagram of the connection between the scan line corresponding to the i-th circuit row and the shift register provided in the embodiment of the present invention. Alternatively, the fourth scan line S4 is electrically connected to the second sub-shift register 16. For example, for the i-th circuit row 11_i, when its corresponding first scan line S1 is electrically connected to the n-th level second sub-shift register 16_n in the second shift register 15, and its corresponding second scan line S2 and third scan line S3 are electrically connected to the m-th level first sub-shift register 10_m and the (m+2)-th level first sub-shift register 10_m+2 in the first shift register 9, its corresponding fourth scan line S4 can be electrically connected to the (n+1)-th level second sub-shift register 16_n+1 in the second shift register 15.

[0139] When the output of the second sub-shift register 16_n+1 of the n+1 stage is valid, the anode reset module 12 is turned on, and the anode of the light-emitting element 14 is reset using the second reset voltage.

[0140] In the above structure, the fourth scan line S3 can share a shift register with other scan lines, eliminating the need to configure an additional shift register for the fourth scan line S4, thus simplifying the structural design.

[0141] In one feasible implementation, such as Figure 35 and Figure 36 As shown, Figure 35 This is a schematic diagram of another structure of the pixel circuit 1 provided in an embodiment of the present invention. Figure 36 This is another schematic diagram of the pixel circuit 1 provided in an embodiment of the present invention. The display panel also includes a bias adjustment module 17. The control terminal of the bias adjustment module 17 is electrically connected to the first scan line S1, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the second node N2.

[0142] With this configuration, the bias adjustment module 17 and the gate reset module 3 share the same scan line. In the first time period T1 and the third time period T3, the bias adjustment module 17 is turned on and writes the bias voltage to the second node N2.

[0143] It should be noted that during the first time period T1, after the bias voltage is written to the second node N2, the bias voltage of the second node N2 will be further written to the third node N3 via the driver module 2 because the driver module 2 is turned on. During the second time period T2, although the threshold compensation module 4 is turned on, since there is no external signal continuously written to the first node N1 and the third node N3 during this time period, the first node N1 maintains the first reset voltage written in the first time period T1, and the second node N2 and the third node N3 maintain the bias voltage written in the first time period T1. The driver module 2 is then reset using the first reset voltage and the bias voltage.

[0144] In one feasible implementation, see again Figure 2 The pixel circuit 1 also includes an anode reset module 12. The control terminal of the anode reset module 12 is electrically connected to one of the first scan line S1, the second scan line S2 and the third scan line S3, the first terminal is electrically connected to the second reset line Ref2, and the second terminal is electrically connected to the light-emitting element 14, so that no additional scan lines and shift registers are required for the anode reset module 12.

[0145] The specific circuit structure of pixel circuit 1 is described below.

[0146] The pixel circuit 1 may specifically include a driving module 2, a gate reset module 3, a threshold compensation module 4, a data writing module 5, an anode reset module 12, a first light emission control module 21, a second light emission control module 22, a bias adjustment module 17, and a storage capacitor Cst.

[0147] The driving module 2 includes a driving transistor M0, whose gate is electrically connected to the first node N1, its first electrode is electrically connected to the second node N2, and its second electrode is electrically connected to the third node N3.

[0148] The gate reset module 3 includes a gate reset transistor M1. The gate of the gate reset transistor M1 is electrically connected to the first scan line S1, the first electrode is electrically connected to the first reset line Ref1, and the second electrode is electrically connected to the first node N1.

[0149] The threshold compensation module 4 includes a threshold compensation transistor M2. The gate of the threshold compensation transistor M2 is electrically connected to the second scan line S2, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first node N1.

[0150] The data writing module 5 includes a data writing transistor M3. The gate of the data writing transistor M3 is electrically connected to the third scan line S3, the first electrode is electrically connected to the data line Data, and the second electrode is electrically connected to the second node N2.

[0151] The anode reset module 12 includes an anode reset transistor M4. The gate of the anode reset transistor M4 is electrically connected to the first scan line S1, the second scan line S2, the third scan line S3 or the fourth scan line S4, the first electrode is electrically connected to the second reset line Ref2, and the second electrode is electrically connected to the light-emitting element 14.

[0152] The first light-emitting control module 21 includes a first light-emitting control transistor M5. The gate of the first light-emitting control transistor M5 is electrically connected to the light-emitting control signal line Emit, the first electrode is electrically connected to the first power supply line PVDD, and the second electrode is electrically connected to the second node N2.

[0153] The second light-emitting control module 22 includes a second light-emitting control transistor M6. The gate of the second light-emitting control transistor M6 is electrically connected to the light-emitting control signal line Emit, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the light-emitting element 14.

[0154] The bias adjustment module 17 includes a bias adjustment transistor M7. The gate of the bias adjustment transistor M7 is electrically connected to the fifth scan line S5 or the first scan line S1, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the second node N2.

[0155] The first plate of the storage capacitor Cst is electrically connected to the first power line PVDD, and the second substrate is electrically connected to the first node N1.

[0156] The driving cycle of pixel circuit 1 also includes a seventh time period T7. During the seventh time period T7, the light emission control signal line Emit provides an effective level, the first light emission control module 21 and the second light emission control module 22 are turned on, and the driving current converted by the driving module 2 flows into the light emission element 14, driving the light emission element 14 to emit light.

[0157] Based on the same inventive concept, embodiments of the present invention also provide a driving method for a display panel, which is applied to the aforementioned display panel.

[0158] Combination Figures 1-3 The display panel includes a pixel circuit 1. The pixel circuit 1 includes a driving module 2, a gate reset module 3, a threshold compensation module 4, and a data writing module 5.

[0159] Specifically, the control terminal of the drive module 2 is electrically connected to the first node N1, the first terminal is electrically connected to the second node N2, and the second terminal is electrically connected to the third node N3. The control terminal of the gate reset module 3 is electrically connected to the first scan line S1, the first terminal is electrically connected to the first reset line Ref1, and the second terminal is electrically connected to the first node N1. The control terminal of the threshold compensation module 4 is electrically connected to the second scan line S2, the first terminal is electrically connected to the third node N3, and the second terminal is electrically connected to the first node N1. The control terminal of the data writing module 5 is electrically connected to the third scan line S3, the first terminal is electrically connected to the data line Data, and the second terminal is electrically connected to the second node N2.

[0160] For the first scan line S1, the second scan line S2, and the third scan line S3 electrically connected to the same pixel circuit 1, within one frame, the first scan line S1 outputs a first effective level el1 and a second effective level el2, the second scan line S2 outputs a third effective level el3 and a fourth effective level el4, and the third scan line S3 outputs a fifth effective level el5. At least a portion of the third effective level el3 is located between the first effective level el1 and the second effective level el2, at least a portion of the second effective level el2 is located between the third effective level el3 and the fourth effective level el4, and the fifth effective level el5 overlaps with the fourth effective level el4.

[0161] The driving cycle of pixel circuit 1 includes a first time period T1, a second time period T2, a third time period T3, and a fourth time period T4.

[0162] The driving methods include:

[0163] During the first time period T1, the gate reset module 3 is turned on in response to the first valid level el1, and the first reset voltage provided by the first reset line Ref1 is written to the first node N1.

[0164] During the second time period T2, the threshold compensation module 4 responds to the third valid level el3 and is turned on.

[0165] During the third time period T3, the gate reset module 3 is turned on in response to the second effective level el2, and the first reset voltage provided by the first reset line Ref1 is written to the first node N1.

[0166] During the fourth time period T4, the data writing module 5 responds to the fifth valid level el5 and turns on, and the threshold compensation module 4 responds to the fourth valid level el4 and turns on. The data voltage on the data line Data is written to the first node N1 and threshold compensation is performed.

[0167] Based on the foregoing analysis, using this driving method, the pixel circuit 1 will perform a three-terminal reset operation on the driving module 2 before charging, so that the device characteristics of the driving module 2 in different pixel circuits 1 will be set to the same initial state. This can effectively solve the problem of inconsistent device characteristics of the driving module 2 caused by different sub-pixels displaying different gray levels in the previous frame.

[0168] In one feasible implementation, combined with Figures 4-6 During the second time period T2, the threshold compensation module 4 responds to the third effective level el3 and turns on. The first reset voltage on the first node N1 is written to the third node N3 via the threshold compensation module 4, and then to the second node N2 via the drive module 2, so that the drive module 2 is reset using only the first reset voltage.

[0169] Alternatively, in another feasible implementation, combined with Figure 35 and Figure 3 The display panel also includes a bias adjustment module 17, the control terminal of which is electrically connected to the first scan line S1, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the second node N2.

[0170] During the first time period T1, the gate reset module 3 and the bias adjustment module 17 are turned on in response to the first valid level e1. The bias voltage on the bias signal line DVH is written to the second node N2, and then to the third node N3 via the drive module 2. During the second time period T2, the threshold compensation module 4 is turned on in response to the third valid level e13. The first node N1 maintains the first reset voltage, and the third node N3 maintains the bias voltage, thereby using the first reset voltage and the bias voltage to perform a three-terminal reset on the drive module 2.

[0171] Alternatively, in another feasible implementation, combined with Figure 2 , Figures 4-6 Within one frame, the third scan line S3 also outputs the sixth active level el6.

[0172] The driving cycle of pixel circuit 1 also includes the fifth time period T5 and the sixth time period T6. For pixel circuit 1 in the i-th circuit row 11, the driving method also includes: in the sixth time period T6, the data writing module 5 responds to the sixth effective level el6 and turns on, writing the voltage on the data line Data to the second node N2, thereby refreshing the potential of the second node N2 again after charging, adjusting the bias state of the driving transistor M0, preventing the characteristics of the driving transistor M0 from drifting, improving the hysteresis effect of the driving transistor M0, and thus helping to optimize the display effect, such as improving image retention.

[0173] In one feasible implementation, see again Figures 20-23The display panel also includes a plurality of circuit rows 11 arranged along a first direction x, and the circuit rows 11 include a plurality of pixel circuits 1 arranged along a second direction y, wherein the first direction x and the second direction y intersect.

[0174] The display panel also includes a first shift register 9 and a second shift register 15. The first shift register 9 includes a plurality of first sub-shift registers 10 cascaded together, and the second shift register 15 includes a plurality of second sub-shift registers 16 cascaded together. Within one frame, the first sub-shift register 10 outputs at least two valid levels, and the second sub-shift register 16 outputs at least one valid level. Furthermore, the valid levels output by the first sub-shift register 10 and the valid levels output by the second sub-shift register 16 are at opposite potentials.

[0175] Specifically, for the i-th circuit row 11_i, its corresponding first scan line S1 and second scan line S2 are respectively connected to the m-th level first sub-shift register 10_m and the (m+1)-th level first sub-shift register 10_m+1 in the first shift register 9, and its corresponding third scan line S3 is connected to the n1-th level second sub-shift register 16_n1 in the second shift register 15. i is an integer greater than or equal to 1, m is an integer greater than or equal to 1, and n1 is an integer greater than or equal to 1.

[0176] The display panel also includes a bias adjustment module 17, the control terminal of which is electrically connected to the fifth scan line S5, the first terminal is electrically connected to the bias signal line DVH, and the second terminal is electrically connected to the second node N2.

[0177] For the i-th circuit row 11_i, its corresponding fifth scan line S5 is electrically connected to the n2-th sub-shift register 16 in the second shift register 15, where n2 is an integer greater than or equal to 1 and n2≠n1.

[0178] For the i-th circuit row 11_i, before or after the fourth time period T4, the driving method further includes: the bias adjustment module 17 responds to the effective level output of the second sub-shift register 16 of the n2-th stage, the bias voltage on the bias signal line DVH is written to the second node N2, the potential of the second node N2 is refreshed, the bias state of the driving transistor M0 is adjusted, the characteristics of the driving transistor M0 are prevented from drifting, the hysteresis effect of the driving transistor M0 is improved, and thus the display effect is optimized, such as improving the afterimage.

[0179] Further, see Figure 24 , Figure 25 and Figure 27, n2 = n1 - 1, where n1 is an integer greater than or equal to 2. Furthermore, for pixel circuit 1 in the i-th circuit row, the effective level output by its corresponding n2-level second sub-shift register 16 overlaps with the third effective level output by its corresponding m+1-level first sub-shift register 10.

[0180] For the i-th circuit row 11_i, in the second time period T2, after the voltage on the bias signal line DVH is written to the second node N2, it is written to the third node N3 via the turned-on drive module 2, and then to the first node N1 via the turned-on threshold compensation module 4.

[0181] Typically, the bias voltage is much greater than the reset voltage. In this embodiment of the invention, the bias adjustment module 17 is activated during the second time period T2. During the second time period T2, both the threshold compensation module 4 and the bias adjustment module 17 are activated. Since the second node N2 will continuously receive a bias voltage, the bias voltage of the second node N2 will be further written to the third node N3 and the first node N1, so that the drive module 2 is reset using only the bias voltage, thus avoiding excessive potential difference between the two ends of the drive module 2.

[0182] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 37 As shown, Figure 37 This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the aforementioned display panel 100. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Figure 37 The display device shown is for illustrative purposes only. The display device can be any electronic device with display function, such as a mobile phone, tablet computer, laptop computer, e-reader or television.

[0183] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Includes a pixel circuit, the pixel circuit comprising: The drive module has its control terminal electrically connected to the first node, its first terminal electrically connected to the second node, and its second terminal electrically connected to the third node. A gate reset module, wherein the control terminal of the gate reset module is electrically connected to the first scan line, the first terminal is electrically connected to the first reset line, and the second terminal is electrically connected to the first node; A threshold compensation module, wherein the control terminal of the threshold compensation module is electrically connected to the second scan line, the first terminal is electrically connected to the third node, and the second terminal is electrically connected to the first node; The data writing module has a control terminal electrically connected to the third scan line, a first terminal electrically connected to the data line, and a second terminal electrically connected to the second node. Specifically, for the first scan line, the second scan line, and the third scan line electrically connected to the same pixel circuit, within one frame, the first scan line outputs a first effective level and a second effective level, the second scan line outputs a third effective level and a fourth effective level, and the third scan line outputs a fifth effective level. Furthermore, at least a portion of the third effective level is located between the first effective level and the second effective level, at least a portion of the second effective level is located between the third effective level and the fourth effective level, and the fifth effective level overlaps with the fourth effective level. The display panel further includes a first shift register, which includes a plurality of cascaded first sub-shift registers. Within one frame, the first sub-shift registers output at least two valid levels. The display panel further includes a second shift register, which includes a plurality of cascaded second sub-shift registers; The display panel further includes a plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; Within one frame, the second sub-shift register outputs at least two valid levels. For the i-th circuit row, its corresponding first scan line is electrically connected to the n-th stage second sub-shift register in the second shift register, and its corresponding second scan line and third scan line are electrically connected to the m-th and (m+2)-th stage first sub-shift registers in the first shift register, respectively. i is an integer greater than or equal to 1, m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1. Furthermore, the time interval between the moment when the n-th stage second sub-shift register stops outputting the first valid level and the moment when the m-th stage first sub-shift register starts outputting the third valid level is t1, and the time interval between the moment when the m-th stage first sub-shift register stops outputting the third valid level and the moment when the n-th stage second sub-shift register starts outputting the second valid level is t2, where t1 ≠ t2. The second valid level output by the n-th stage second sub-shift register does not overlap with the fifth valid level output by the (m+2)-th stage first sub-shift register. Alternatively, within one frame, the second sub-shift register outputs at least one valid level, and the valid level output by the second sub-shift register is at a potential opposite to the valid level output by the first sub-shift register; for the i-th circuit row, its corresponding first scan line and second scan line are electrically connected to the m-th and m+1-th level first sub-shift registers in the first shift register, respectively, and its corresponding third scan line is electrically connected to the n1-th level second sub-shift register in the second shift register; i is an integer greater than or equal to 1, m is an integer greater than or equal to 1, and n1 is an integer greater than or equal to 1.

2. The display panel according to claim 1, characterized in that, t1 < t2.

3. The display panel according to claim 1, characterized in that, The display panel also includes a bias adjustment module, wherein the control terminal of the bias adjustment module is electrically connected to the fifth scan line, the first terminal is electrically connected to the bias signal line, and the second terminal is electrically connected to the second node; Specifically, for the i-th circuit row, the corresponding fifth scan line is electrically connected to the n2-th sub-shift register in the second shift register, where n2 is an integer greater than or equal to 1 and n2 ≠ n1.

4. The display panel according to claim 3, characterized in that, n2 = n1 + 1.

5. The display panel according to claim 4, characterized in that, The time interval between the effective level output by the second sub-shift register of the n2th stage and the effective level output by the second sub-shift register of the n1th stage is t3, where t3 < Where F is the duration of a frame and X is the number of circuit lines.

6. The display panel according to claim 3, characterized in that, n2 = n1 - 1, where n1 is an integer greater than or equal to 2.

7. The display panel according to claim 6, characterized in that, The effective level output by the second sub-shift register of the n2th stage overlaps with the third effective level output by the first sub-shift register of the m+1th stage.

8. The display panel according to claim 1, characterized in that, The pulse width of the effective level output by the first sub-shift register is greater than the pulse width of the effective level output by the second sub-shift register.

9. The display panel according to claim 1, characterized in that, The display panel has a first mode, in which a frame time includes a write frame and a hold frame, and in at least one of the hold frames, the second sub-shift register outputs an active level.

10. The display panel according to claim 1, characterized in that, The display panel also includes a bias adjustment module, wherein the control terminal of the bias adjustment module is electrically connected to the fifth scan line, the first terminal is electrically connected to the bias signal line, and the second terminal is electrically connected to the second node; The display panel also includes a third shift register, which includes multiple cascaded third sub-shift registers. Within one frame, the third sub-shift register outputs at least one valid level. The fifth scan line is electrically connected to the third sub-shift register, and the effective levels output by the second sub-shift register and the third sub-shift register connected to the same pixel circuit do not overlap.

11. The display panel according to claim 1, characterized in that, The pixel circuit also includes an anode reset module, wherein the control terminal of the anode reset module is electrically connected to the fourth scan line, the first terminal is electrically connected to the second reset line, and the second terminal is electrically connected to the light-emitting element; The fourth scan line is electrically connected to the first sub-shift register, or the fourth scan line is electrically connected to the second sub-shift register.

12. The display panel according to claim 1, characterized in that, The display panel also includes a bias adjustment module, wherein the control terminal of the bias adjustment module is electrically connected to the first scan line, the first terminal is electrically connected to the bias signal line, and the second terminal is electrically connected to the second node.

13. The display panel according to claim 1, characterized in that, The pixel circuit further includes an anode reset module. The control terminal of the anode reset module is electrically connected to one of the first scan line, the second scan line, and the third scan line. The first terminal of the anode reset module is electrically connected to the second reset line, and the second terminal is electrically connected to the light-emitting element.

14. A driving method for a display panel, characterized in that, The display panel includes a pixel circuit, the pixel circuit comprising: The drive module has its control terminal electrically connected to the first node, its first terminal electrically connected to the second node, and its second terminal electrically connected to the third node. A gate reset module, wherein the control terminal of the gate reset module is electrically connected to the first scan line, the first terminal is electrically connected to the first reset line, and the second terminal is electrically connected to the first node; A threshold compensation module, wherein the control terminal of the threshold compensation module is electrically connected to the second scan line, the first terminal is electrically connected to the third node, and the second terminal is electrically connected to the first node; The data writing module has a control terminal electrically connected to the third scan line, a first terminal electrically connected to the data line, and a second terminal electrically connected to the second node. Specifically, for the first scan line, the second scan line, and the third scan line electrically connected to the same pixel circuit, within one frame, the first scan line outputs a first effective level and a second effective level, the second scan line outputs a third effective level and a fourth effective level, and the third scan line outputs a fifth effective level. Furthermore, at least a portion of the third effective level is located between the first effective level and the second effective level, at least a portion of the second effective level is located between the third effective level and the fourth effective level, and the fifth effective level overlaps with the fourth effective level. The driving cycle of the pixel circuit includes a first time period, a second time period, a third time period, and a fourth time period; The driving method includes: During the first time period, the gate reset module is turned on in response to the first valid level, and the first reset voltage provided by the first reset line is written to the first node; During the second time period, the threshold compensation module is activated in response to the third valid level; During the third time period, the gate reset module turns on in response to the second valid level, and the first reset voltage provided by the first reset line is written to the first node; In the fourth time period, the data writing module responds to the fifth valid level to turn on, the threshold compensation module responds to the fourth valid level to turn on, and the data voltage on the data line is written to the first node and threshold compensation is performed; The display panel further includes a plurality of circuit rows arranged along a first direction, the circuit rows including a plurality of pixel circuits arranged along a second direction, the first direction intersecting the second direction; The display panel further includes a first shift register and a second shift register. The first shift register includes a plurality of first sub-shift registers cascaded together, and the second shift register includes a plurality of second sub-shift registers cascaded together. Within one frame, the first sub-shift register outputs at least two valid levels, and the second sub-shift register outputs at least one valid level. Furthermore, the valid levels output by the first sub-shift register and the valid levels output by the second sub-shift register are at opposite potentials. Wherein, for the i-th circuit row, its corresponding first scan line and second scan line are electrically connected to the m-th and m+1-th first sub-shift registers in the first shift register, respectively, and its corresponding third scan line is electrically connected to the n1-th second sub-shift register in the second shift register; i is an integer greater than or equal to 1, m is an integer greater than or equal to 1, and n1 is an integer greater than or equal to 1; The display panel also includes a bias adjustment module, wherein the control terminal of the bias adjustment module is electrically connected to the fifth scan line, the first terminal is electrically connected to the bias signal line, and the second terminal is electrically connected to the second node; Wherein, for the i-th circuit row, the corresponding fifth scan line is electrically connected to the n2-th sub-shift register in the second shift register, where n2 is an integer greater than or equal to 1, and n2 ≠ n1; For the pixel circuit of the i-th circuit row, before or after the fourth time period, the driving method further includes: the bias adjustment module turns on in response to the effective level output of the second sub-shift register of the n2-th stage, and the bias voltage on the bias signal line is written to the second node.

15. The driving method for a display panel according to claim 14, characterized in that, During the second time period, the threshold compensation module turns on in response to the third valid level, and the first reset voltage on the first node is written to the third node via the threshold compensation module and then to the second node via the drive module.

16. The driving method for a display panel according to claim 14, characterized in that, Within one frame, the third scan line also outputs a sixth active level; The driving cycle of the pixel circuit further includes a fifth time period and a sixth time period. The driving method further includes: during the sixth time period, the data writing module responds to the sixth valid level and writes the voltage on the data line into the second node.

17. The driving method for a display panel according to claim 14, characterized in that, n2 = n1 - 1, where n1 is an integer greater than or equal to 2, and the effective level output by the second sub-shift register of the n2th stage overlaps with the third effective level output by the first sub-shift register of the m+1th stage; For the i-th circuit row, during the second time period, after the voltage on the bias signal line is written to the second node, it is written to the third node via the activated drive module, and then to the first node via the activated threshold compensation module.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 13.

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