A display screen common voltage regulation method and system

Abstract

The present invention discloses a method and system for adjusting the common voltage of a display screen, and relates to the field of liquid crystal display technology, including: establishing a charging effect distance model for a single gate line, and establishing a resistance and capacitance delay model for a single gate line; obtaining the voltage maintenance time of the pixel electrode of the gate line; obtaining the output positive voltage and the output negative voltage of the gate line; obtaining the first real-time output positive voltage and the first real-time output negative voltage of the pixel electrode of the sampling liquid crystal molecule corresponding to the sampling point; calculating the delay effect of the resistance and capacitance on the pixel electrode of the gate line; calculating the display value of the common voltage at the time mark point; at the time mark point, adjusting the value of the common voltage to the display value. By setting a model building module, a data calculation module and a voltage adjustment module, the degree of picture flickering on the same gate line is as low as possible, thereby effectively improving the imaging stability of the display screen.

Description

Technical Field

[0001] The present invention relates to the field of liquid crystal display technology, and in particular to a display screen common voltage regulation method and system. Background Art

[0002] In recent years, liquid crystal display screens have gradually spread throughout people's lives. As an important component of liquid crystal display screens, the liquid crystal display panel mainly includes an array substrate, a color filter substrate, and liquid crystal molecules located between the array substrate and the color filter substrate. The liquid crystal display panel controls the orientation of the liquid crystal molecules through an electric field to change the transmittance of the liquid crystal display panel, thereby realizing the display function. In the liquid crystal display panel, the electric field that controls the liquid crystal molecules is determined by the voltage difference between the pixel electrode and the common electrode. However, due to the presence of parasitic capacitance, when the gate signal is turned off, the voltage of the pixel electrode will have a deviation of ΔVP before and after the jump (feed-through effect). In order to ensure the display quality of the liquid crystal display panel, the voltage deviation ΔVP of all pixel electrodes before and after the jump should remain consistent.

[0003] However, in a liquid crystal display panel, due to the delay of resistance and capacitance, the gate signal transmitted on a gate line will be distorted along the transmission direction, causing the voltage of the pixel electrode to be delayed along the transmission direction of the gate signal on the gate line. Generally, the voltage loaded on the common electrode is the same, which leads to inconsistent voltage deviation ΔVP on each pixel unit in the entire liquid crystal display panel, and the liquid crystal display panel then has problems such as screen flickering. This phenomenon is more obvious in large-size LCDs.

[0004] Nowadays, the common solution is to adjust the common electrode voltage, i.e., the VCOM voltage, to satisfy the positive voltage - VCOM = VCOM - negative voltage, so that the flicker can be minimized, but this increases the man-hours and difficulty of LCM (LCD Module) operation. In addition, since the charging effect of the middle area and the two side areas of the screen is different (that is, the charging effect of the pixel unit at the far end of the gate line is different from that of the pixel unit at the near end), the feed-through effect is also different. Since there is only one VCOM voltage, the display effect of the middle area is often guaranteed at the expense of the display effect of the two side areas, which results in a situation where the flicker in the middle area is lower, while the flicker on the two sides is still more serious. Summary of the invention

[0005] In order to solve the above technical problems, a method and system for adjusting the common voltage of a display screen are provided. This technical solution solves the problems raised in the above background technology.

[0006] In order to achieve the above purpose, the technical solution adopted by the present invention is:

[0007] A display screen common voltage regulation method, comprising:

[0008] Acquire at least one gate line in the display screen, and acquire at least one liquid crystal molecule to which a pixel voltage is provided by the gate line;

[0009] Dividing a single gate line at equal intervals to obtain at least one sampling point;

[0010] Acquire the liquid crystal molecule corresponding to the sampling point as the sampling liquid crystal molecule;

[0011] Performing coordinate modeling on a single gate line to obtain the coordinates of a sampling point;

[0012] A charging effect distance model is established for a single gate line, and a resistance and capacitance delay model is established for a single gate line. When the charging effect distance model and the resistance and capacitance delay model are established, the positive voltage outputted by the single gate line is a characteristic positive voltage, and the negative voltage outputted by the single gate line is a characteristic negative voltage;

[0013] The holding time of the voltage of the pixel electrode of the gate line is obtained as the voltage switching time, and the voltage of the pixel electrode of the gate line is converted once every the voltage switching time;

[0014] During the voltage switching time, the positive output voltage and the negative output voltage of the gate line are obtained;

[0015] Using a charging effect distance model, calculating the blocking effect of the distance on the pixel electrodes at different positions of the gate line, and obtaining a first real-time output positive voltage and a first real-time output negative voltage of the pixel electrode corresponding to the sampling point sampling liquid crystal molecules;

[0016] Using a resistance-capacitance delay model, the delay effect of the resistance and capacitance on the pixel electrode of the gate line is calculated to obtain a second real-time output positive voltage and a second real-time output negative voltage of the pixel electrode of the sampling liquid crystal molecule corresponding to the sampling point;

[0017] Divide the voltage switching time into equal intervals to obtain at least one time mark point;

[0018] At a single time mark point, a third real-time output positive voltage and a third real-time output negative voltage of a pixel electrode of a sampled liquid crystal molecule corresponding to each sampling point are obtained;

[0019] Calculating a display value of the common voltage at the time mark point according to the third real-time output positive voltage and the third real-time output negative voltage;

[0020] At the time mark point, the value of the common voltage of the point on the gate line whose distance from the sampling point is less than the preset distance is adjusted to the display value.

[0021] Preferably, the coordinate modeling of a single gate line to obtain the coordinates of a sampling point comprises the following steps:

[0022] Taking the left end point of the single gate line as the coordinate origin, the single gate line as the horizontal axis, and the straight line perpendicularly passing through the left end point of the single gate line as the vertical axis, an xy coordinate system is obtained;

[0023] In the xy coordinate system, get the coordinates of the sampling point, where the ordinate of the sampling point is 0.

[0024] Preferably, establishing a charging effect distance model for a single gate line comprises the following steps:

[0025] providing a voltage in a single gate line according to a characteristic positive voltage and a characteristic negative voltage;

[0026] Acquire a first display positive voltage and a first display negative voltage corresponding to at least one sampling point;

[0027] Fitting at least one sampling point and the first displayed positive voltage to obtain a first positive voltage fitting function, wherein the abscissa and ordinate of the sampling point are independent variables, and the first displayed positive voltage is a dependent variable;

[0028] At least one sampling point and the first displayed negative voltage are fitted to obtain a first negative voltage fitting function, wherein the abscissa and ordinate of the sampling point are independent variables, and the first displayed negative voltage is a dependent variable.

[0029] Preferably, establishing a resistance-capacitance delay model for a single gate line comprises the following steps:

[0030] Select at least one of the sampling points as a target sampling point;

[0031] providing a voltage in a single gate line according to a characteristic positive voltage and a characteristic negative voltage;

[0032] At the target sampling point, obtaining a second display positive voltage and a second display negative voltage corresponding to at least one time mark point;

[0033] Fitting at least one time mark point and the second displayed positive voltage to obtain a second positive voltage fitting function, wherein the value of the time mark point is an independent variable and the second displayed positive voltage is a dependent variable;

[0034] At least one time mark point and the second displayed negative voltage are fitted to obtain a second negative voltage fitting function, wherein the value of the time mark point is an independent variable and the second displayed negative voltage is a dependent variable.

[0035] Preferably, the calculation of the obstruction effect of the distance on the pixel electrodes at different positions of the gate line comprises the following steps:

[0036] The positive voltage of the output of the gate line is divided by the characteristic positive voltage, the characteristic positive ratio;

[0037] The negative voltage of the output of the gate line is divided by the characteristic negative voltage, the characteristic negative ratio;

[0038] Substituting the coordinates of the sampling point into the first positive voltage fitting function to obtain a first pre-output positive voltage;

[0039] The characteristic positive ratio is multiplied by the first pre-output positive voltage to obtain a first real-time output positive voltage;

[0040] Substituting the coordinates of the sampling point into the first negative voltage fitting function to obtain a first pre-output negative voltage;

[0041] The characteristic negative ratio is multiplied by the first pre-output negative voltage to obtain the first real-time output negative voltage.

[0042] Preferably, the calculation of the delay effect of the resistance and capacitance on the pixel electrode of the gate line comprises the following steps:

[0043] Divide the first real-time output positive voltage by the characteristic positive voltage, with a target positive ratio;

[0044] Divide the first real-time output negative voltage by the characteristic negative voltage, a target negative ratio;

[0045] Substituting the coordinates of the sampling point into the second positive voltage fitting function to obtain a second pre-output positive voltage;

[0046] The target positive ratio is multiplied by the second pre-output positive voltage to obtain a second real-time output positive voltage;

[0047] Substituting the coordinates of the sampling point into the second negative voltage fitting function to obtain a second pre-output negative voltage;

[0048] The target negative ratio is multiplied by the second pre-output negative voltage to obtain the second real-time output negative voltage.

[0049] Preferably, obtaining the third real-time output positive voltage and the third real-time output negative voltage of the pixel electrode corresponding to the sampled liquid crystal molecule at each sampling point comprises the following steps:

[0050] Using the value of the second real-time positive output voltage corresponding to the same time mark point and sampling point as the third real-time positive output voltage as the third real-time positive output voltage;

[0051] The value of the second real-time negative output voltage corresponding to the same time mark point and sampling point as the third real-time negative output voltage is used as the third real-time negative output voltage.

[0052] Preferably, the calculation to obtain the display value of the common voltage at the time mark point comprises the following steps:

[0053] Solve the common voltage as an unknown variable and record the common voltage as the voltage unknown variable;

[0054] For each sampling point, subtract the difference between the third real-time output positive voltage and the voltage unknown from the difference between the voltage unknown and the third real-time output negative voltage to obtain an unknown difference function;

[0055] After squaring the unknown difference function of each sampling point, the conditional objective function is accumulated;

[0056] The Lagrange multiplier method is used to obtain the value of the voltage unknown corresponding to the minimum value of the conditional objective function, which is used as the displayed value of the common voltage at the time mark point.

[0057] A display screen common voltage regulation system, used to implement the above display screen common voltage regulation method, comprising:

[0058] A sampling acquisition module, wherein the sampling acquisition module acquires at least one gate line in the display screen, acquires at least one liquid crystal molecule to which a pixel voltage is provided by the gate line, obtains at least one sampling point, and acquires the liquid crystal molecule corresponding to the sampling point;

[0059] A coordinate modeling module, wherein the coordinate modeling module performs coordinate modeling on a single gate line to obtain the coordinates of a sampling point;

[0060] A model building module, wherein the model building module builds a charging effect distance model for a single gate line and a resistance and capacitance delay model for a single gate line;

[0061] A data acquisition module, wherein the data acquisition module acquires the holding time of the voltage of the pixel electrode of the gate line, and acquires the output positive voltage and the output negative voltage of the gate line;

[0062] A data calculation module, which calculates the blocking effect of the distance on the pixel electrodes at different positions of the gate line, calculates the delay effect of the resistor and capacitor on the pixel electrodes of the gate line, and calculates the display value of the common voltage at the time mark point;

[0063] A voltage adjustment module adjusts the value of the common voltage of a point on the gate line whose distance from the sampling point is less than a preset distance to a display value at a time mark point.

[0064] Compared with the prior art, the present invention has the following beneficial effects:

[0065] By setting up a model building module, a data calculation module and a voltage adjustment module, the delay effect of the resistor and capacitor on the voltage of the pixel electrode along the gate signal and the different charging effects of the middle area and the two side areas of the screen are comprehensively considered, and the common voltage is adjusted in a targeted manner, so that the difference between the positive voltage minus the common voltage and the common voltage minus the negative voltage calculated by the common voltage is as small as possible, so that on the same gate line, the degree of picture flickering is as low as possible, thereby effectively improving the imaging stability of the display screen. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] Figure 1 It is a schematic diagram of the flow chart of the display screen common voltage regulation method of the present invention;

[0067] Figure 2 A schematic diagram of the coordinate flow of obtaining a sampling point by performing coordinate modeling on a single gate line according to the present invention;

[0068] Figure 3 A schematic diagram of the process of establishing a charging effect distance model for a single gate line according to the present invention;

[0069] Figure 4 A schematic diagram of a process of establishing a resistance and capacitance delay model for a single gate line according to the present invention;

[0070] Figure 5 It is a schematic diagram of the flow of calculating the blocking effect of distance on pixel electrodes at different positions of the gate line according to the present invention;

[0071] Figure 6 It is a schematic diagram of the process of calculating the delay effect of the resistance and capacitance on the pixel electrode of the gate line of the present invention;

[0072] Figure 7 It is a schematic diagram of a process of obtaining a third real-time output positive voltage and a third real-time output negative voltage of a pixel electrode of a sampled liquid crystal molecule corresponding to each sampling point according to the present invention;

[0073] Figure 8 The figure is a schematic diagram of a flow chart of calculating and obtaining a display value of a common voltage at a time mark point according to the present invention. DETAILED DESCRIPTION

[0074] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art may think of other obvious variations.

[0075] Reference Figure 1 As shown, a display screen common voltage regulation method includes:

[0076] Acquire at least one gate line in the display screen, and acquire at least one liquid crystal molecule to which a pixel voltage is provided by the gate line;

[0077] Dividing a single gate line at equal intervals to obtain at least one sampling point;

[0078] Acquire the liquid crystal molecule corresponding to the sampling point as the sampling liquid crystal molecule;

[0079] Performing coordinate modeling on a single gate line to obtain the coordinates of a sampling point;

[0080] A charging effect distance model is established for a single gate line, and a resistance and capacitance delay model is established for a single gate line. When the charging effect distance model and the resistance and capacitance delay model are established, the positive voltage outputted by the single gate line is a characteristic positive voltage, and the negative voltage outputted by the single gate line is a characteristic negative voltage;

[0081] The holding time of the voltage of the pixel electrode of the gate line is obtained as the voltage switching time, and the voltage of the pixel electrode of the gate line is converted once every the voltage switching time;

[0082] During the voltage switching time, the positive output voltage and the negative output voltage of the gate line are obtained;

[0083] Using a charging effect distance model, calculating the blocking effect of the distance on the pixel electrodes at different positions of the gate line, and obtaining a first real-time output positive voltage and a first real-time output negative voltage of the pixel electrode corresponding to the sampling point sampling liquid crystal molecules;

[0084] Using a resistance-capacitance delay model, the delay effect of the resistance and capacitance on the pixel electrode of the gate line is calculated to obtain a second real-time output positive voltage and a second real-time output negative voltage of the pixel electrode of the sampling liquid crystal molecule corresponding to the sampling point;

[0085] Divide the voltage switching time into equal intervals to obtain at least one time mark point;

[0086] At a single time mark point, a third real-time output positive voltage and a third real-time output negative voltage of a pixel electrode of a sampled liquid crystal molecule corresponding to each sampling point are obtained;

[0087] Calculating a display value of the common voltage at the time mark point according to the third real-time output positive voltage and the third real-time output negative voltage;

[0088] At the time mark point, the value of the common voltage of the point on the gate line whose distance from the sampling point is less than the preset distance is adjusted to the display value.

[0089] Reference Figure 2 As shown, coordinate modeling is performed on a single gate line to obtain the coordinates of the sampling point, including the following steps:

[0090] Taking the left end point of the single gate line as the coordinate origin, the single gate line as the horizontal axis, and the straight line perpendicularly passing through the left end point of the single gate line as the vertical axis, an xy coordinate system is obtained;

[0091] In the xy coordinate system, get the coordinates of the sampling point, where the ordinate of the sampling point is 0.

[0092] Reference Figure 3 As shown, establishing a charging effect distance model for a single gate line includes the following steps:

[0093] providing a voltage in a single gate line according to a characteristic positive voltage and a characteristic negative voltage;

[0094] Acquire a first display positive voltage and a first display negative voltage corresponding to at least one sampling point;

[0095] Fitting at least one sampling point and the first displayed positive voltage to obtain a first positive voltage fitting function, wherein the abscissa and ordinate of the sampling point are independent variables, and the first displayed positive voltage is a dependent variable;

[0096] Fitting at least one sampling point and the first displayed negative voltage to obtain a first negative voltage fitting function, wherein the abscissa and ordinate of the sampling point are independent variables, and the first displayed negative voltage is a dependent variable;

[0097] When a single gate line is charged, voltage is transmitted along the single gate line. The effect of voltage transmission varies with the distance. Therefore, it is necessary to make a quantitative analysis of the differences. Since the effects of different voltage transmissions are consistent, the corresponding transmission effect is obtained only under the conditions of characteristic positive voltage and characteristic negative voltage. According to the proportional conversion, the transmission effect of voltage at different positions in all cases can be calculated.

[0098] Reference Figure 4 As shown, establishing a resistance-capacitance delay model for a single gate line includes the following steps:

[0099] Select at least one of the sampling points as a target sampling point;

[0100] providing a voltage in a single gate line according to a characteristic positive voltage and a characteristic negative voltage;

[0101] At the target sampling point, obtaining a second display positive voltage and a second display negative voltage corresponding to at least one time mark point;

[0102] Fitting at least one time mark point and the second displayed positive voltage to obtain a second positive voltage fitting function, wherein the value of the time mark point is an independent variable and the second displayed positive voltage is a dependent variable;

[0103] Fitting at least one time mark point and the second displayed negative voltage to obtain a second negative voltage fitting function, wherein the value of the time mark point is an independent variable and the second displayed negative voltage is a dependent variable;

[0104] Resistor and capacitor delay means that the voltage of resistors and capacitors does not change instantly, but changes gradually over time. That is, if the input voltage is 5V, it takes a certain reaction time for the voltage of the pixel electrode to become 5V. During the reaction time, the voltage of the pixel electrode is not 5V. Therefore, it affects the flickering effect of the display screen. It is necessary to predict the voltage of the pixel electrode within the reaction time and adjust the common voltage in real time so that the difference between the positive voltage of the pixel electrode and the common voltage on the same gate line and the difference between the common voltage and the negative voltage of the pixel electrode are as close as possible, thereby reducing the flicker on the gate line as much as possible.

[0105] Reference Figure 5 As shown, calculating the blocking effect of the distance on the pixel electrodes at different positions of the gate line includes the following steps:

[0106] The positive voltage of the output of the gate line is divided by the characteristic positive voltage, the characteristic positive ratio;

[0107] The negative voltage of the output of the gate line is divided by the characteristic negative voltage, the characteristic negative ratio;

[0108] Substituting the coordinates of the sampling point into the first positive voltage fitting function to obtain a first pre-output positive voltage;

[0109] The characteristic positive ratio is multiplied by the first pre-output positive voltage to obtain a first real-time output positive voltage;

[0110] Substituting the coordinates of the sampling point into the first negative voltage fitting function to obtain a first pre-output negative voltage;

[0111] The characteristic negative ratio is multiplied by the first pre-output negative voltage to obtain a first real-time output negative voltage;

[0112] Since the charging effect distance model is established under the conditions of characteristic positive voltage and characteristic negative voltage, it is necessary to perform proportional conversion in actual calculation to obtain the actual results under the conditions of positive voltage and negative voltage of the output of the gate line.

[0113] Reference Figure 6 As shown, calculating the delay effect of the resistor and capacitor on the pixel electrode of the gate line includes the following steps:

[0114] Divide the first real-time output positive voltage by the characteristic positive voltage, with a target positive ratio;

[0115] Divide the first real-time output negative voltage by the characteristic negative voltage, a target negative ratio;

[0116] Substituting the coordinates of the sampling point into the second positive voltage fitting function to obtain a second pre-output positive voltage;

[0117] The target positive ratio is multiplied by the second pre-output positive voltage to obtain a second real-time output positive voltage;

[0118] Substituting the coordinates of the sampling point into the second negative voltage fitting function to obtain a second pre-output negative voltage;

[0119] The target negative ratio is multiplied by the second pre-output negative voltage to obtain a second real-time output negative voltage;

[0120] Since the resistance-capacitance delay model is established under the conditions of characteristic positive voltage and characteristic negative voltage, it is necessary to perform proportional conversion in actual calculation to obtain the actual results under the conditions of positive output voltage and negative output voltage of the gate line.

[0121] Reference Figure 7 As shown, obtaining the third real-time output positive voltage and the third real-time output negative voltage of the pixel electrode corresponding to the sampled liquid crystal molecule at each sampling point includes the following steps:

[0122] Using the value of the second real-time positive output voltage corresponding to the same time mark point and sampling point as the third real-time positive output voltage as the third real-time positive output voltage;

[0123] The value of the second real-time negative output voltage corresponding to the same time mark point and sampling point as the third real-time negative output voltage is used as the third real-time negative output voltage.

[0124] Reference Figure 8 As shown, calculating the display value of the common voltage at the time mark point includes the following steps:

[0125] Solve the common voltage as an unknown variable and record the common voltage as the voltage unknown variable;

[0126] For each sampling point, subtract the difference between the third real-time output positive voltage and the voltage unknown from the difference between the voltage unknown and the third real-time output negative voltage to obtain an unknown difference function;

[0127] After squaring the unknown difference function of each sampling point, the conditional objective function is accumulated;

[0128] Use the Lagrange multiplier method to find the value of the voltage unknown corresponding to the minimum value of the conditional objective function, and use it as the display value of the common voltage at the time mark point;

[0129] Sampling points are used to approximate the gate lines. When the number of sampling points is sufficient, the accuracy of the adjustment results based on the sampling points can meet the usage requirements. When the conditional objective function takes the minimum value, it means that at each moment, the difference between the result of the positive voltage of the pixel electrode minus the common voltage and the result of the common voltage minus the negative voltage of the pixel electrode at most points on the gate line is within the allowable accuracy range. Therefore, the flicker degree of the display screen can be reduced to meet the usage requirements.

[0130] A display screen common voltage regulation system, used to implement the above display screen common voltage regulation method, comprising:

[0131] A sampling acquisition module, wherein the sampling acquisition module acquires at least one gate line in the display screen, acquires at least one liquid crystal molecule to which a pixel voltage is provided by the gate line, obtains at least one sampling point, and acquires the liquid crystal molecule corresponding to the sampling point;

[0132] A coordinate modeling module, wherein the coordinate modeling module performs coordinate modeling on a single gate line to obtain the coordinates of a sampling point;

[0133] A model building module, wherein the model building module builds a charging effect distance model for a single gate line and a resistance and capacitance delay model for a single gate line;

[0134] A data acquisition module, wherein the data acquisition module acquires the holding time of the voltage of the pixel electrode of the gate line, and acquires the output positive voltage and the output negative voltage of the gate line;

[0135] A data calculation module, which calculates the blocking effect of the distance on the pixel electrodes at different positions of the gate line, calculates the delay effect of the resistor and capacitor on the pixel electrodes of the gate line, and calculates the display value of the common voltage at the time mark point;

[0136] A voltage adjustment module adjusts the value of the common voltage of a point on the gate line whose distance from the sampling point is less than a preset distance to a display value at a time mark point.

[0137] The working process of the above display screen common voltage regulation system is as follows:

[0138] Step 1: The sampling and acquisition module acquires at least one gate line in the display screen, and acquires at least one liquid crystal molecule to which a pixel voltage is provided by the gate line;

[0139] Step 2: The sampling acquisition module divides a single gate line at equal intervals to obtain at least one sampling point;

[0140] Step 3: The sampling acquisition module acquires the liquid crystal molecules corresponding to the sampling points as sampling liquid crystal molecules;

[0141] Step 4: The coordinate modeling module performs coordinate modeling on a single gate line to obtain the coordinates of a sampling point;

[0142] Step 5: The model building module builds a charging effect distance model for a single gate line, and a resistance and capacitance delay model for a single gate line. When the charging effect distance model and the resistance and capacitance delay model are built, the positive voltage outputted by the single gate line is a characteristic positive voltage, and the negative voltage outputted by the single gate line is a characteristic negative voltage.

[0143] Step 6: The data acquisition module acquires the maintenance time of the voltage of the pixel electrode of the gate line as the voltage switching time, and the voltage of the pixel electrode of the gate line is converted once every voltage switching time;

[0144] Step 7: During the voltage switching time, the data acquisition module acquires the output positive voltage and the output negative voltage of the gate line;

[0145] Step 8: The data calculation module uses the charging effect distance model to calculate the hindering effect of the distance on the pixel electrodes at different positions of the gate line, and obtains the first real-time output positive voltage and the first real-time output negative voltage of the pixel electrode corresponding to the sampling point sampling liquid crystal molecule;

[0146] Step 9: The data calculation module uses the resistance and capacitance delay model to calculate the delay effect of the resistance and capacitance on the pixel electrode of the gate line, and obtains the second real-time output positive voltage and the second real-time output negative voltage of the pixel electrode of the sampling point corresponding to the sampling liquid crystal molecule;

[0147] Step 10: Divide the voltage switching time into equal intervals to obtain at least one time mark point;

[0148] Step 11: at a single time mark point, obtaining a third real-time output positive voltage and a third real-time output negative voltage of the pixel electrode of the sampled liquid crystal molecule corresponding to each sampling point;

[0149] Step 12: The data calculation module calculates the display value of the common voltage at the time mark point according to the third real-time output positive voltage and the third real-time output negative voltage;

[0150] Step 13: At the time mark point, the voltage adjustment module adjusts the value of the common voltage of the point on the gate line whose distance from the sampling point is less than the preset distance to the display value.

[0151] Furthermore, the present solution also proposes a storage medium on which a computer-readable program is stored. When the computer-readable program is called, the above-mentioned display screen common voltage adjustment method is executed.

[0152] It is understandable that the storage medium may be a magnetic medium, such as a floppy disk, a hard disk, or a magnetic tape; an optical medium, such as a DVD; or a semiconductor medium, such as a solid state drive (SSD).

[0153] To sum up, the advantages of the present invention are: by setting a model building module, a data calculation module and a voltage adjustment module, the delay effect of the resistor and capacitor on the voltage of the pixel electrode along the gate signal and the different charging effects of the middle area and the two side areas of the screen are comprehensively considered, and the common voltage is adjusted in a targeted manner, so that the difference between the positive voltage minus the common voltage and the common voltage minus the negative voltage calculated by the common voltage is as small as possible, so that on the same gate line, the degree of picture flickering is as low as possible, thereby effectively improving the imaging stability of the display screen.

[0154] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions only describe the principles of the present invention. The present invention may be subject to various changes and improvements without departing from the spirit and scope of the present invention. These changes and improvements fall within the scope of the present invention. The scope of protection claimed by the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for adjusting a common voltage of a display screen, characterized in that: include: Acquire at least one gate line in the display screen, and acquire at least one liquid crystal molecule to which a pixel voltage is provided by the gate line; Dividing a single gate line at equal intervals to obtain at least one sampling point; Acquire the liquid crystal molecule corresponding to the sampling point as the sampling liquid crystal molecule; Performing coordinate modeling on a single gate line to obtain the coordinates of a sampling point; A charging effect distance model is established for a single gate line, and a resistance and capacitance delay model is established for a single gate line. When the charging effect distance model and the resistance and capacitance delay model are established, the positive voltage outputted by the single gate line is a characteristic positive voltage, and the negative voltage outputted by the single gate line is a characteristic negative voltage; The holding time of the voltage of the pixel electrode of the gate line is obtained as the voltage switching time, and the voltage of the pixel electrode of the gate line is converted once every the voltage switching time; During the voltage switching time, the positive output voltage and the negative output voltage of the gate line are obtained; Using a charging effect distance model, calculating the blocking effect of the distance on the pixel electrodes at different positions of the gate line, and obtaining a first real-time output positive voltage and a first real-time output negative voltage of the pixel electrode corresponding to the sampling point sampling liquid crystal molecules; Using a resistance-capacitance delay model, the delay effect of the resistance and capacitance on the pixel electrode of the gate line is calculated to obtain a second real-time output positive voltage and a second real-time output negative voltage of the pixel electrode of the sampling liquid crystal molecule corresponding to the sampling point; Divide the voltage switching time into equal intervals to obtain at least one time mark point; At a single time mark point, a third real-time output positive voltage and a third real-time output negative voltage of a pixel electrode of a sampled liquid crystal molecule corresponding to each sampling point are obtained; Calculating a display value of the common voltage at the time mark point according to the third real-time output positive voltage and the third real-time output negative voltage; At the time mark point, the value of the common voltage of the point on the gate line whose distance from the sampling point is less than the preset distance is adjusted to the display value; The calculation of the blocking effect of the distance on the pixel electrodes at different positions of the gate line comprises the following steps: The positive voltage of the output of the gate line is divided by the characteristic positive voltage, the characteristic positive ratio; The negative voltage of the output of the gate line is divided by the characteristic negative voltage, the characteristic negative ratio; Substituting the coordinates of the sampling point into the first positive voltage fitting function to obtain a first pre-output positive voltage; The characteristic positive ratio is multiplied by the first pre-output positive voltage to obtain a first real-time output positive voltage; Substituting the coordinates of the sampling point into the first negative voltage fitting function to obtain a first pre-output negative voltage; The characteristic negative ratio is multiplied by the first pre-output negative voltage to obtain a first real-time output negative voltage; The calculation of the delay effect of the resistance and capacitance on the pixel electrode of the gate line comprises the following steps: Divide the first real-time output positive voltage by the characteristic positive voltage, with a target positive ratio; Divide the first real-time output negative voltage by the characteristic negative voltage, a target negative ratio; Substituting the coordinates of the sampling point into the second positive voltage fitting function to obtain a second pre-output positive voltage; The target positive ratio is multiplied by the second pre-output positive voltage to obtain a second real-time output positive voltage; Substituting the coordinates of the sampling point into the second negative voltage fitting function to obtain a second pre-output negative voltage; The target negative ratio is multiplied by the second pre-output negative voltage to obtain a second real-time output negative voltage; The step of obtaining the third real-time output positive voltage and the third real-time output negative voltage of the pixel electrode of the sampled liquid crystal molecule corresponding to each sampling point comprises the following steps: Using the value of the second real-time positive output voltage corresponding to the same time mark point and sampling point as the third real-time positive output voltage as the third real-time positive output voltage; The value of the second real-time negative output voltage corresponding to the same time mark point and sampling point as the third real-time negative output voltage is used as the third real-time negative output voltage.

2. A display screen common voltage regulation method according to claim 1, characterized in that: The coordinate modeling of a single gate line to obtain the coordinates of a sampling point comprises the following steps: Taking the left end point of the single gate line as the coordinate origin, the single gate line as the horizontal axis, and the straight line perpendicularly passing through the left end point of the single gate line as the vertical axis, an xy coordinate system is obtained; In the xy coordinate system, get the coordinates of the sampling point, where the ordinate of the sampling point is 0.

3. A display screen common voltage regulation method according to claim 2, characterized in that: The step of establishing a charging effect distance model for a single gate line comprises the following steps: providing a voltage in a single gate line according to a characteristic positive voltage and a characteristic negative voltage; Acquire a first display positive voltage and a first display negative voltage corresponding to at least one sampling point; Fitting at least one sampling point and the first displayed positive voltage to obtain a first positive voltage fitting function, wherein the abscissa and ordinate of the sampling point are independent variables, and the first displayed positive voltage is a dependent variable; At least one sampling point and the first displayed negative voltage are fitted to obtain a first negative voltage fitting function, wherein the abscissa and ordinate of the sampling point are independent variables, and the first displayed negative voltage is a dependent variable.

4. A display screen common voltage regulation method according to claim 3, characterized in that: The step of establishing a resistance-capacitance delay model for a single gate line comprises the following steps: Select at least one of the sampling points as a target sampling point; providing a voltage in a single gate line according to a characteristic positive voltage and a characteristic negative voltage; At the target sampling point, obtaining a second display positive voltage and a second display negative voltage corresponding to at least one time mark point; Fitting at least one time mark point and the second displayed positive voltage to obtain a second positive voltage fitting function, wherein the value of the time mark point is an independent variable and the second displayed positive voltage is a dependent variable; At least one time mark point and the second displayed negative voltage are fitted to obtain a second negative voltage fitting function, wherein the value of the time mark point is an independent variable and the second displayed negative voltage is a dependent variable.

5. A display screen common voltage regulation method according to claim 4, characterized in that: The calculation to obtain the display value of the common voltage at the time mark point comprises the following steps: Solve the common voltage as an unknown variable and record the common voltage as the voltage unknown variable; For each sampling point, subtract the difference between the third real-time output positive voltage and the voltage unknown from the difference between the voltage unknown and the third real-time output negative voltage to obtain an unknown difference function; After squaring the unknown difference function of each sampling point, the conditional objective function is accumulated; The Lagrange multiplier method is used to obtain the value of the voltage unknown corresponding to the minimum value of the conditional objective function, which is used as the displayed value of the common voltage at the time mark point.

6. A display screen common voltage regulation system, used to implement the display screen common voltage regulation method according to any one of claims 1 to 5, characterized in that: include: A sampling acquisition module, wherein the sampling acquisition module acquires at least one gate line in the display screen, acquires at least one liquid crystal molecule to which a pixel voltage is provided by the gate line, obtains at least one sampling point, and acquires the liquid crystal molecule corresponding to the sampling point; A coordinate modeling module, wherein the coordinate modeling module performs coordinate modeling on a single gate line to obtain the coordinates of a sampling point; A model building module, wherein the model building module builds a charging effect distance model for a single gate line and a resistance and capacitance delay model for a single gate line; A data acquisition module, wherein the data acquisition module acquires the holding time of the voltage of the pixel electrode of the gate line, and acquires the output positive voltage and the output negative voltage of the gate line; A data calculation module, which calculates the blocking effect of the distance on the pixel electrodes at different positions of the gate line, calculates the delay effect of the resistor and capacitor on the pixel electrodes of the gate line, and calculates the display value of the common voltage at the time mark point; A voltage adjustment module adjusts the value of the common voltage of a point on the gate line whose distance from the sampling point is less than a preset distance to a display value at a time mark point.

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