Non-volatile content addressable memory and electronic devices based on ferroelectric capacitors

Abstract

The present disclosure relates to a non-volatile content-addressable memory based on ferroelectric capacitors and an electronic device. The memory includes: a plurality of storage cells, each of which comprises: a first switch and a second switch connected to a first capacitor and a second capacitor, respectively; a first capacitor and a third capacitor, and a gate of a first transistor, all connected to a first node; a second capacitor and a fourth capacitor, and a gate of a second transistor, all connected to a second node; at least one of the first and third capacitors is a ferroelectric capacitor, and at least one of the second and fourth capacitors is a ferroelectric capacitor; and a control unit for inputting a control signal to control the storage cell to perform a target operation. The disclosed embodiments achieve non-destructive reading of data, improve the service life of the memory, and reduce operation delays and energy consumption.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a non-volatile content addressable memory and electronic equipment based on ferroelectric capacitors. Background Art

[0002] As the scaling of CMOS processes described by Moore's Law gradually slows, the storage density of on-chip embedded memory that relies on traditional CMOS processes is difficult to further increase. This scaling is accompanied by increasingly significant leakage issues, resulting in non-negligible static power consumption. On the other hand, as applications such as artificial intelligence gradually become more prevalent at the edge, embedded devices in IoT scenarios are placing increasingly high demands on capacity and energy efficiency. However, bottlenecks in density and power consumption have limited the development of traditional CMOS embedded memory processes in these scenarios. In response to this, academia and industry have recently conducted a series of explorations into a number of new non-volatile memory (NVM) technologies. In addition to the non-volatile nature of maintaining data with zero leakage, the high speed and high density of NVM have also attracted widespread attention.

[0003] NVM is primarily categorized into two main types: resistive and capacitive. Resistive memories, such as RRAM and STT-RAM, exhibit non-volatile properties, but generally have a low dynamic range between states, making read operations difficult. They also consume significant DC power during write operations. Ferroelectric memory, a capacitive non-volatile device, offers extremely low write power consumption and a higher dynamic range, enabling better support for multi-value storage within a cell. This potential supports higher storage densities, coupled with excellent CMOS process compatibility. This makes ferroelectric memory a likely candidate for the next generation of memory.

[0004] Existing ferroelectric memories are mainly divided into ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) memories. FeRAM's read operation requires writing specific data to the circuit unit, which results in the destruction of the original data. This limits its application in scenarios with frequent matching operations, such as content-addressable memory. Although FeFET supports non-destructive read operations, its write operation generates excessively high voltage internally, resulting in a shorter write operation lifespan. The two existing types of ferroelectric memories struggle to balance non-destructive read and write operation lifespans, limiting the full utilization of the advantages of ferroelectric content-addressable memory. Summary of the Invention

[0005] According to one aspect of the present disclosure, a non-volatile content-addressable memory based on a ferroelectric capacitor is provided, the memory comprising:

[0006] A plurality of memory cells, each memory cell comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switch, a second switch, a first transistor, and a second transistor, wherein the second end of the first switch and the second end of the second switch are respectively connected to the first end of the first capacitor and the first end of the second capacitor, the second end of the first capacitor, the first end of the third capacitor, and the gate of the first transistor are all connected to a first node, and the second end of the second capacitor, the first end of the fourth capacitor, and the gate of the second transistor are all connected to a second node, wherein at least one of the first capacitor and the third capacitor is a ferroelectric capacitor, and at least one of the second capacitor and the fourth capacitor is a ferroelectric capacitor;

[0007] a control unit connected to the control end of the first switch, the control end of the second switch, the first end of the first switch, the first end of the second switch, the source of the first transistor, the source of the second transistor, the drain of the first transistor, the drain of the second transistor, and the second end of the third capacitor in each storage unit, and configured to:

[0008] A control signal is input to control the memory cell to perform a target operation.

[0009] In a possible embodiment, the storage unit further includes a first word line, a second word line, a third word line, a first write port, a second write port, a first read port, and a second read port, wherein the control end of the first switch and the control end of the second switch are connected to the first word line, the first end of the first switch and the first end of the second switch are respectively connected to the first write port and the second write port, the source of the first transistor is connected to the first read port, the source of the second transistor is connected to the second read port, the drain of the first transistor and the drain of the second transistor are both connected to the third word line, the second end of the third capacitor and the second end of the fourth capacitor are both connected to the second word line, and the control unit is connected to the first word line, the second word line, the third word line, the first write port, the second write port, the first read port, and the second read port.

[0010] In a possible implementation, the target operation includes a write operation, and the input control signal is used to control the storage unit to perform the target operation, including:

[0011] Control the voltages of the second end of the third capacitor and the second end of the fourth capacitor, the first end of the first switch, and the second switch, adjust the polarization state of the ferroelectric capacitor in the storage unit, and adjust the voltages of the first node and the second node to write the data to be stored.

[0012] In a possible implementation, inputting a control signal to control the storage unit to perform a target operation includes:

[0013] controlling the voltages of the control end of the first switch and the control end of the second switch to turn on the first switch and the second switch;

[0014] Controlling the bias voltages of the first end of the first switch and the first end of the second switch to be complementary voltages;

[0015] Controlling the second end of the third capacitor and the second end of the fourth capacitor to change from an initial voltage, and stay at a preset low voltage and a preset high voltage for a period of time respectively, and then returning to the initial voltage;

[0016] The voltages of the control end of the first switch and the control end of the second switch are controlled so that the first switch and the second switch are turned off, so as to write data to be stored.

[0017] In a possible implementation, the target operation includes a write operation, and the input control signal is used to control the storage unit to perform the target operation, including:

[0018] Control the bias voltage of the second end of the third capacitor, the second end of the fourth capacitor, the first end of the first switch, the second switch, and the duration of each bias voltage, and set the polarization state of each ferroelectric capacitor to one of more than two states, so that each ferroelectric capacitor stores more than one bit of data.

[0019] In one possible implementation, the polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state, and the input control signal to control the storage unit to perform a target operation includes:

[0020] If it is necessary to write '11' in the storage unit, the potential of the source of the first transistor is biased at a first positive voltage, the potential of the source of the second transistor is biased at a first negative voltage, and the potential of the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first biased at the first positive voltage for a first time length, and then biased to the first negative voltage for the first time length, so that the first capacitor becomes a strongly positive polarization state and the second capacitor maintains a strongly negative polarization state, thereby writing '11'.

[0021] In one possible implementation, the polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state, and the input control signal to control the storage unit to perform a target operation includes:

[0022] If it is necessary to write '10' in the storage cell, after writing '11', the source of the first transistor is biased at the first negative voltage, the source of the second transistor is biased at the first positive voltage, and the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first at the first positive voltage for a second time length, and then at the first negative voltage for a second time length, so that the second capacitor becomes a weakly negative polarization state and the first capacitor maintains a weakly positive polarization state, thereby writing '10', and the second time length is less than the first time length.

[0023] In one possible implementation, the polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state, and the input control signal to control the storage unit to perform a target operation includes:

[0024] If '00' needs to be written in the storage unit, the source potential of the first transistor is biased at a first negative voltage, the source potential of the second transistor is biased at a first positive voltage, and the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first at the first positive voltage and then at the first negative voltage, so as to change the first capacitor into a negative polarization state and the second capacitor into a strong positive polarization state, thereby writing '00'.

[0025] In one possible implementation, the polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state, and the input control signal to control the storage unit to perform a target operation includes:

[0026] If it is necessary to write '01' in the storage cell, after the step of writing '00', the source of the first transistor is biased at the first positive voltage, the source of the second transistor is biased at the first negative voltage, and the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first biased at the first positive voltage for a second time length, and then biased at the first negative voltage for a second time length, the first capacitor is changed to a weak negative polarization state, and the second capacitor is changed to a weak positive polarization state, thereby writing '01'.

[0027] In one possible implementation, the target operation includes a content-addressable operation, and the input control signal is used to control the storage unit to perform the target operation, including:

[0028] controlling the bias voltage of the source of the first transistor and the source of the second transistor, and inputting data that needs to be matched;

[0029] A matching result of the content addressing operation is obtained according to the voltage or current of the drain of the first transistor and the drain of the second transistor.

[0030] In a possible implementation, inputting a control signal to control the storage unit to perform a target operation includes:

[0031] When performing the content addressing operation, controlling the voltages of the second end of the third capacitor, the second end of the fourth capacitor, and the source of the first transistor so that the first transistor is turned on or off according to a matching result;

[0032] controlling the voltages of the second end of the third capacitor, the fourth capacitor, and the source of the second transistor so that the second transistor is turned on or off according to the matching structure;

[0033] The matching result of the content addressing operation is obtained based on the impedance value between the source and drain of the first transistor, the impedance value between the source and drain of the second transistor, or the influence of the impedance value on the voltage or current of the drain of the first transistor and the drain of the second transistor.

[0034] In a possible implementation, inputting a control signal to control the storage unit to perform a target operation includes:

[0035] By performing the content addressing operation multiple times and changing the bias voltages of the second end of the third capacitor and the second end of the fourth capacitor, the bias voltage of the first end of the first switch, and the bias voltage of the first end of the second switch during the multiple content addressing operations, more than one bit of data stored in the storage unit is matched successively.

[0036] In one possible embodiment, the memory cells are electrically connected to form a multi-row and multi-column layout, wherein the first word lines of the memory cells in the same row are connected, the second word lines of the memory cells in the same row are connected, the third word lines of the memory cells in the same row are connected, the first write ports of the memory cells in the same column are connected, the second write ports of the memory cells in the same column are connected, the first read ports of the memory cells in the same column are connected, and the second read ports of the memory cells in the same column are connected.

[0037] In a possible implementation manner, the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are implemented using a planar structure or a three-dimensional structure.

[0038] According to one aspect of the present disclosure, an electronic device is provided, comprising the ferroelectric capacitor-based nonvolatile content addressable memory.

[0039] The non-volatile content-addressable memory based on ferroelectric capacitors proposed in the embodiment of the present disclosure includes four capacitors, two switches and two transistors. At least one of the first capacitor and the third capacitor is a ferroelectric capacitor, and at least one of the second capacitor and the fourth capacitor is a ferroelectric capacitor. The embodiment of the present disclosure utilizes the hysteresis characteristics between the polarization strength and the port voltage of the ferroelectric capacitor, the modulatability of the voltages of the first node and the second node, and the adjustable relative area of ​​the ferroelectric capacitor to achieve non-destructive reading of data, improve the service life of the memory, and reduce operation delay and energy consumption.

[0040] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0042] Figure 1a A schematic diagram of a nonvolatile content-addressable memory based on ferroelectric capacitors according to an embodiment of the present disclosure is shown.

[0043] Figure 1b A schematic diagram of a nonvolatile content-addressable memory based on ferroelectric capacitors according to an embodiment of the present disclosure is shown.

[0044] Figure 1c A schematic diagram of a storage unit of a non-volatile content-addressable memory based on a ferroelectric capacitor according to an embodiment of the present disclosure is shown.

[0045] Figure 1d A schematic diagram of a storage unit of a non-volatile content-addressable memory based on a ferroelectric capacitor according to an embodiment of the present disclosure is shown.

[0046] Figure 2 A schematic diagram illustrating a write operation of a non-volatile content addressable memory based on a ferroelectric capacitor according to an embodiment of the present disclosure is shown.

[0047] Figure 3 A schematic diagram of a memory performing content addressing operations according to an embodiment of the present disclosure is shown.

[0048] Figure 4 A schematic diagram of the state of a storage unit when performing a multi-content addressing operation according to an embodiment of the present disclosure is shown.

[0049] Figure 5 A schematic diagram of transient waveforms of a storage unit under different write operations according to an embodiment of the present disclosure is shown.

[0050] Figure 6 A schematic diagram of transient waveforms of a memory cell under different multi-value write operations according to an embodiment of the present disclosure is shown.

[0051] Figure 7 Schematic diagrams of transient waveforms of a memory cell under different matching operations according to an embodiment of the present disclosure are shown.

[0052] Figure 8 A schematic diagram showing a storage unit performing a multi-value content addressing operation through multiple steps according to an embodiment of the present disclosure is shown.

[0053] Figure 9 A schematic diagram showing internal node voltage and ferroelectric polarization strength at different capacitance ratios in a memory cell according to an embodiment of the present disclosure is shown.

[0054] Figure 10 A schematic diagram of a physical implementation of a unit structure of a memory according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0055] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0056] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0057] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0058] In this disclosure, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood broadly. For example, they may refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on specific circumstances.

[0059] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0060] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0061] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0062] See also Figure 1a , Figure 1a A schematic diagram of a nonvolatile content-addressable memory based on ferroelectric capacitors according to an embodiment of the present disclosure is shown.

[0063] like Figure 1a As shown, the memory includes:

[0064] A plurality of memory cells 10, each memory cell 10 comprising a first capacitor CFE1, a second capacitor CFE2, a third capacitor CFE3, a fourth capacitor CFE4, a first switch T1, a second switch T2, a first transistor M1, and a second transistor M2, wherein the second end of the first switch T1 and the second end of the second switch T2 are respectively connected to the first end of the first capacitor CFE1 and the first end of the second capacitor CFE2, the second end of the first capacitor CFE1, the first end of the third capacitor CFE3, and the gate of the first transistor M1 are all connected to a first node G1, and the second end of the second capacitor CFE2, the first end of the fourth capacitor CFE4, and the gate of the second transistor M2 are all connected to a second node G2, wherein at least one of the first capacitor CFE1 and the third capacitor CFE3 is a ferroelectric capacitor, and at least one of the second capacitor CFE2 and the fourth capacitor CFE4 is a ferroelectric capacitor;

[0065] The control unit 20 is connected to the control end of the first switch T1, the control end of the second switch T2, the first end of the first switch T1, the first end of the second switch T2, the source of the first transistor M1, the source of the second transistor M2, the drain of the first transistor M1, the drain of the second transistor M2, and the second end of the third capacitor CFE3 in each storage unit 10, and is used to:

[0066] A control signal is input to control the memory unit 10 to perform a target operation.

[0067] The non-volatile content-addressable memory based on ferroelectric capacitors proposed in the embodiment of the present disclosure includes four capacitors, two switches and two transistors. At least one of the first capacitor CFE1 and the third capacitor CFE3 is a ferroelectric capacitor, and at least one of the second capacitor CFE2 and the fourth capacitor CFE4 is a ferroelectric capacitor. The embodiment of the present disclosure utilizes the hysteresis characteristics between the polarization strength and the port voltage of the ferroelectric capacitor, the modulatability of the voltages of the first node G1 and the second node G2, and the adjustable relative area characteristics of the ferroelectric capacitor to achieve non-destructive reading of data, improve the service life of the memory, and reduce operation delay and energy consumption.

[0068] The embodiment of the present disclosure can adjust the relative sizes of the first capacitor CFE1 and the third capacitor CFE3, as well as the relative sizes of the second capacitor CFE2 and the fourth capacitor CFE4, to adjust the voltage difference of the internal nodes corresponding to different storage data. At the same time, when the first switch T1 and the second switch T2 are turned off, the voltage of the first node G1 and the voltage of the second node G2 can be changed synchronously, thereby adjusting the resistance value between the drain and source of the first transistor M1 of the storage unit 10 corresponding to different storage data and the resistance value between the drain and source of the second transistor M2, to obtain a more ideal on / off resistance ratio, thereby realizing non-destructive content addressing operation that does not affect the polarization state of the ferroelectric capacitor, and reducing the delay and energy consumption of the read operation.

[0069] The non-volatile content-addressable memory based on ferroelectric capacitors proposed in the embodiments of the present disclosure is expected to support more than 1 million reads per write, and the write operation is expected to have the same lifespan as FeRAM.

[0070] The embodiments of the present disclosure do not limit the specific implementation of the control unit 20, and those skilled in the art can adopt appropriate technical means to implement it according to actual conditions and needs. In one example, the control unit 20 may include a processing component, and the processing component includes, for example, but is not limited to, a separate processor, or discrete components, or a combination of a processor and discrete components. The processor may include a controller with an execution instruction function in an electronic device, and the processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions can be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers and embedded microcontrollers.

[0071] The embodiment of the present disclosure does not limit the specific manner in which the control unit 20 and the control end of the first switch T1, the control end of the second switch T2, the first end of the first switch T1, the first end of the second switch T2, the source of the first transistor M1, the source of the second transistor M2, the drain of the first transistor M1, the drain of the second transistor M2, and the second end of the third capacitor CFE3 in each storage unit 10 are connected. For example, the embodiment of the present disclosure can set a dedicated word line or port to realize the connection between the control unit 20 and the storage unit 10.

[0072] See also Figure 1b, Figure 1b A schematic diagram of a nonvolatile content-addressable memory based on ferroelectric capacitors according to an embodiment of the present disclosure is shown.

[0073] In one possible implementation, Figure 1b As shown, the memory cell 10 may further include a first word line WS, a second word line PL, a third word line ML, a first write port BLW1, a second write port BLW2, a first read port BLR1, and a second read port BLR2, wherein the control end of the first switch T1 and the control end of the second switch T2 are connected to the first word line WS, the first end of the first switch T1 and the first end of the second switch T2 are connected to the first write port BLW1 and the second write port BLW2, respectively, the source of the first transistor M1 is connected to the first read port BLR1, the source of the second transistor M2 is connected to the second read port BLR2, the drain of the first transistor M1 and the drain of the second transistor M2 are both connected to the third word line ML, the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 are both connected to the second word line PL, and the control unit 20 is connected to the first word line WS, the second word line PL, the third word line ML, the first write port BLW1, the second write port BLW2, the first read port BLR1, and the second read port BLR2.

[0074] For example, Figure 1b As shown, the second end of the first capacitor CFE1 / the second capacitor CFE2 is connected to the first end of the third capacitor CFE3 / the fourth capacitor CFE4 and the gate of the first transistor M1 / the second transistor M2 to form a first node G1 / a second node G2, the first end of the first capacitor CFE1 / the second capacitor CFE2 is connected to the second end of the first switch T1 / the second switch T2, the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 are connected to the second word line PL, the control ends of the first switch T1 and the second switch T2 are connected to the first word line WS, and the first switch The first end of the switch T1 / the second switch T2 is connected to the first write port BLW1 / the second write port BLW2. The source of the first transistor M1 / the second transistor M2 is connected to the first read port BLR1 / the second read port BLR2. The drain of the first transistor M1 and the drain of the second transistor M2 are connected to the third word line ML. At least one of the first capacitor CFE1 and the third capacitor CFE3 is a ferroelectric capacitor, and at least one of the second capacitor CFE2 and the fourth capacitor CFE4 is a ferroelectric capacitor. The memory cell 10 utilizes the different polarization characteristics of ferroelectric capacitors to store data. In an embodiment of the present invention, the first capacitor CFE1 and the second capacitor CFE2 are implemented as ferroelectric capacitors.

[0075] Exemplarily, any one of the first capacitor CFE1 and the third capacitor CFE3 is a ferroelectric capacitor, or both are ferroelectric capacitors. Similarly, any one of the second capacitor CFE2 and the fourth capacitor CFE4 is a ferroelectric capacitor, or both are ferroelectric capacitors. This is not limited in the embodiments of the present disclosure.

[0076] In one example, if Figure 1a and Figure 1b As shown, the first capacitor CFE1 and the second capacitor CFE2 are ferroelectric capacitors, and the third capacitor CFE3 and the fourth capacitor CFE4 can be other types of capacitors.

[0077] See also Figure 1c , Figure 1c FIG. 1 is a schematic diagram of a memory cell 10 of a nonvolatile content-addressable memory based on a ferroelectric capacitor according to an embodiment of the present disclosure.

[0078] In one example, if Figure 1c As shown, the third capacitor CFE3 and the fourth capacitor CFE4 can be implemented by ferroelectric capacitors, and the first capacitor CFE1 and the second capacitor CFE2 can be other types of capacitors. This setting can still enable the internal nodes (first node G1, second node G2) to generate a voltage corresponding to the stored data through the above-mentioned write operation, and the data stored in the storage unit 10 can be distinguished through the above-mentioned write operation according to the resistance value between the drain and source of the transistor or the influence of the resistance value on the change of the voltage or current at the second reading end of the storage unit 10.

[0079] See also Figure 1d , Figure 1d FIG. 1 is a schematic diagram of a memory cell 10 of a nonvolatile content-addressable memory based on a ferroelectric capacitor according to an embodiment of the present disclosure.

[0080] In one example, if Figure 1d As shown, the first capacitor CFE1, the second capacitor CFE2, the third capacitor CFE3 and the fourth capacitor CFE4 can all be implemented with ferroelectric capacitors. In this case, each storage unit 10 can still use the above-mentioned write operation to make the internal nodes (first node G1, second node G2) generate a voltage corresponding to the stored data. Through the above-mentioned write operation, the data stored in the storage unit 10 can be distinguished according to the resistance value between the drain and source of the transistor or the influence of the resistance value on the change of the voltage or current at the second reading end of the storage unit 10.

[0081] The non-volatile content-addressable memory based on ferroelectric capacitors proposed in the embodiments of the present disclosure utilizes the hysteresis characteristics of the polarization state of the ferroelectric capacitor-port voltage, and modulates the voltage of the floating internal node in the middle through the second word line PL, thereby realizing non-destructive reading of data, improving the service life of the memory, and reducing the operation delay and energy consumption. The embodiments of the present disclosure do not impose specific restrictions on the implementation method of the control unit 20 and the specific method of the control unit 20 controlling the storage unit 10. Those skilled in the art can use appropriate processing components to implement the control unit 20 according to actual conditions and needs, and input control signals to each storage unit 10 according to actual conditions and needs to perform target operations.

[0082] Below is Figure 1b Taking the non-volatile content-addressable memory based on ferroelectric capacitors shown as an example (the first capacitor CFE1 and the second capacitor CFE2 are ferroelectric capacitors, and the third capacitor CFE3 and the fourth capacitor CFE4 can be other types of capacitors), an exemplary introduction is given to the control unit 20 of the embodiment of the present disclosure inputting a control signal to control the storage unit 10 to perform the target operation.

[0083] In a possible implementation, the target operation includes a write operation, and the input control signal to control the storage unit 10 to perform the target operation may include:

[0084] Control the voltages of the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4, the first end of the first switch T1, and the second switch T2, adjust the polarization state of the ferroelectric capacitor in the storage unit 10, and adjust the voltages of the first node G1 and the second node G2 to write the data to be stored.

[0085] For example, Figure 1b As shown, the control unit 20 of the embodiment of the present disclosure can control the voltages of the second word line PL, the first write port BLW1 and the second write port BLW2 when performing a write operation on the data stored in the storage cell 10, so that the polarization characteristics of the ferroelectric capacitor of the storage cell 10 and the voltage of the node are consistent with the data to be stored.

[0086] In a possible implementation, the inputting of a control signal to control the storage unit 10 to perform a target operation may include:

[0087] Controlling the voltages of the control end of the first switch T1 and the control end of the second switch T2 to turn on the first switch T1 and the second switch T2;

[0088] Controlling the bias voltages of the first end of the first switch T1 and the first end of the second switch T2 to be complementary voltages, for example, one of the first switch T1 and the second switch T2 is a high voltage and the other is a low voltage;

[0089] Controlling the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 to change from an initial voltage, stay at a preset low voltage and a preset high voltage for a period of time respectively, and then return to the initial voltage;

[0090] The voltages of the control terminals of the first switch T1 and the second switch T2 are controlled so that the first switch T1 and the second switch T2 are turned off, so as to write the data to be stored.

[0091] For example, Figure 1b As shown, the control unit 20 of the embodiment of the present disclosure can control the voltage of the first word line WS to turn on the first switch T1 and the second switch T2 of the storage unit 10, control the first write port BLW1 to be biased at a high voltage or a low voltage, control the second write port BLW2 to be biased at a high voltage or a low voltage, control the second word line PL to stay at a low voltage and a high voltage for a period of time (a first time length) and then restore to the original initial voltage, and turn off the first switch T1 and the second switch T2 of the storage unit 10 through the voltage of the first word line WS to write the data to be stored.

[0092] See also Figure 2 , Figure 2 A schematic diagram illustrating a write operation of a non-volatile content addressable memory based on a ferroelectric capacitor according to an embodiment of the present disclosure is shown.

[0093] For example, Figure 2 As shown, when the memory cell 10 is written, the voltage of the first word line WS is adjusted so that the first switch T1 and the second switch T2 are both in the on state.

[0094] If it is necessary to write '1' into the memory cell 10, the embodiment of the present disclosure can bias the potential of the first write port BLW1 to a first positive voltage (hereinafter referred to as +V W The second write port BLW2 is biased at -V W The second word line PL potential is biased twice: first biased at +V W , and then biased to the first negative voltage (hereinafter referred to as -V W Indicates), first biased to +V W When the information originally stored in the first capacitor CFE1 does not change, the second capacitor CFE2 becomes negatively polarized and is biased to -V WWhen , the information stored in the second capacitor CFE2 no longer changes, the first capacitor CFE1 becomes positively polarized, and the second capacitor CFE2 maintains a negative polarization state, that is, "1" is written. The first node G1 generates a positive voltage due to the positive polarization state, and the second node G2 generates a negative voltage due to the negative polarization;

[0095] If it is necessary to write '0' into the memory cell 10, the first write port BLW1 may be biased at -V W , bias the second write port BLW2 potential at +V W The second word line PL potential is biased twice: first biased at +V W , when biased to -V W , first biased to +V W When the first capacitor CFE1 changes to a negative polarization state, the information originally stored in the second capacitor CFE2 does not change, and the second bias is to -V W When the voltage is 0, the information stored in the first capacitor CFE1 does not change and remains in a negative polarization state. The second capacitor CFE2 changes to a positive polarization state, that is, a '0' is written. The first node G1 generates a negative voltage due to the negative polarization, and the second node G2 generates a positive voltage due to the positive polarization. By optimizing the relative sizes of the ferroelectric capacitor and the ordinary capacitor, the voltages of the first node G1 and the second node G2 can be adjusted to appropriate values.

[0096] It should be noted that the aforementioned storage state '1' can only match a '1' during a matching operation, the storage state '0' can only match an input '0' during a matching operation, and the storage state 'don't care' can match any input. The present disclosure does not limit the specific form of the don't care state. For example, the don't care state can be manifested as both the first node G1 and the second node G2 having negative voltages.

[0097] For example, Figure 1b As shown, if a "don't care" state needs to be written to the memory cell 10, the potential of the first write port BLW1 and the potential of the second write port BLW2 are both biased to -V W , the second word line PL potential is biased to +V W , the first capacitor CFE1 and the second capacitor CFE2 both become negatively polarized, and the first node G1 and the second node G2 both generate negative voltages due to the negative polarization.

[0098] In this embodiment, the relative sizes of the capacitors are adjusted so that the voltages of the first node G1 and the second node G2 corresponding to the '1' and '0' states are +0.5V and -0.5V respectively.

[0099] In a possible implementation, the target operation may include a write operation, and the input control signal to control the storage unit 10 to perform the target operation may include:

[0100] Control the bias voltages of the second end of the third capacitor CFE3, the second end of the fourth capacitor CFE4, the first end of the first switch T1, and the second switch T2, as well as the duration of each bias voltage, and set the polarization state of each ferroelectric capacitor to one of more than two states, so that each ferroelectric capacitor stores more than one bit of data.

[0101] For example, Figure 1b As shown, when a write operation is performed on the storage cell 10 described therein, the embodiment of the present disclosure can set the polarization of each ferroelectric capacitor in the storage cell 10 to one of more than two states through the bias voltage of the first write port BLW1, the bias voltage of the second write port BLW2, the bias voltage of the second word line PL, and the duration of the bias voltage, and each ferroelectric capacitor can store more than one bit of data.

[0102] In a possible implementation, the polarization state may include a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, a weak negative polarization state, etc. The input control signal to control the storage unit 10 to perform the target operation may include:

[0103] If it is necessary to write '11' into the memory cell 10, the potential of the source of the first transistor M1 is biased to a first positive voltage (+V W ), biasing the potential of the source of the second transistor M2 to a first negative voltage (-V W ), the potential of the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 are biased twice: first at the first positive voltage for a first duration, and then at the first negative voltage for a first duration, so that the first capacitor CFE1 becomes a strongly positive polarization state and the second capacitor CFE2 maintains a strongly negative polarization state, thereby writing '11'.

[0104] For example, the first duration can be a relatively long period of time, such as Figure 1b As shown, if '11' needs to be written into the memory cell 10, the potential of the first write port BLW1 can be biased at +V W , bias the potential of the second write port BLW2 at -V W The second word line PL potential is biased twice for a long time: first biased at +V for a long time (with the first time length) W , then biased for a long time, the first bias to +V WWhen the information originally stored in the first capacitor CFE1 does not change, the second capacitor CFE2 becomes a strong negative polarization state and is biased to -V for the second time. W When '11' is written, the first node G1 generates a high positive voltage due to the strong positive polarization state, and the second node G2 generates a negative voltage with a large absolute value due to the strong negative polarization state.

[0105] In a possible implementation, the polarization state may include a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, a weak negative polarization state, etc. The input control signal to control the storage unit 10 to perform the target operation may include:

[0106] If '10' needs to be written in the storage cell 10, after writing '11', the source of the first transistor M1 is biased at the first negative voltage, the source of the second transistor M2 is biased at the first positive voltage, and the potential of the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 are biased twice: first at the first positive voltage for a second time length, and then at the first negative voltage for a second time length, so that the second capacitor CFE2 becomes a weak negative polarization state and the first capacitor CFE1 maintains a weak positive polarization state, thereby writing '10', and the second time length is less than the first time length.

[0107] For example, the second duration may be a shorter time than the first duration, such as Figure 1b As shown, if it is necessary to write '10' into the memory cell 10, after writing '11' according to the above-mentioned steps, the first write port BLW1 can be biased at -V W , bias the second write port BLW2 at +V w , the potential of the second word line PL is biased twice for a short time: first for a short time (second time length) biased at +V w , biased at -V for a short time W , first biased to +V W When the first capacitor CFE1 changes to a weak positive polarization state, the second capacitor CFE2 still maintains a strong negative polarization state, and the second bias is -V W When '10' is written, the first node G1 generates a low positive voltage due to the weak positive polarization, and the second node G2 generates a negative voltage with a small absolute value due to the weak negative polarization.

[0108] In a possible implementation, the polarization state may include a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, a weak negative polarization state, etc. The input control signal to control the storage unit 10 to perform the target operation may include:

[0109] If '00' needs to be written in the storage cell 10, the source potential of the first transistor M1 is biased at a first negative voltage, the source potential of the second transistor M2 is biased at a first positive voltage, and the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 are biased twice: first at the first positive voltage and then at the first negative voltage, so as to change the first capacitor CFE1 to a negative polarization state and the second capacitor CFE2 to a strongly positive polarization state, thereby writing '00'.

[0110] For example, Figure 1b As shown, if '00' needs to be written into the memory cell 10, the potential of the first write port BLW1 can be biased at -V W , bias the potential of the second write port BLW2 at +V W , the potential of the second word line PL is biased twice: first biased at +V W , when biased to -V W , first biased to +V W When the first capacitor CFE1 changes to a strong negative polarization state, the information originally stored in the second capacitor CFE2 does not change, and the second bias to -V W When 0 is written, the information stored in the first capacitor CFE1 no longer changes and maintains the negative polarization state. The second capacitor CFE2 becomes a strong positive polarization state, that is, '00' is written. The first node G1 generates a negative voltage with a large absolute value due to the strong negative polarization, and the second node G2 generates a high positive voltage due to the strong positive polarization.

[0111] In a possible implementation, the polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, a weak negative polarization state, etc. The input control signal to control the storage unit 10 to perform the target operation may include:

[0112] If it is necessary to write '01' in the storage cell 10, after the step of writing '00', the source of the first transistor M1 is biased at the first positive voltage, the source of the second transistor M2 is biased at the first negative voltage, and the potential of the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4 are biased twice: first at the first positive voltage for a second duration, and then at the first negative voltage for a second duration, so that the first capacitor CFE1 is changed to a weak negative polarization state and the second capacitor CFE2 is changed to a weak positive polarization state, thereby writing '01'.

[0113] For example, Figure 1b As shown, if it is necessary to write '01' into the memory cell 10, after following the steps of writing '00', the first write port BLW1 is biased at +V W , bias the second write port BLW2 at -V w , the second word line PL potential is biased twice for a short time: first biased at +V for a short time w , biased at -V for a short time W , first biased to +V W When the first capacitor CFE1 is still maintained in a strong negative polarization state, the second capacitor CFE2 becomes a weak positive polarization state, and the second bias is -V W When the ferroelectric capacitor is switched to a weak negative polarization state, the information stored in the second capacitor CFE2 no longer changes. The first capacitor CFE1 becomes weakly negatively polarized, while the second capacitor CFE2 maintains a weakly positive polarization state. That is, '01' is written. The first node G1 generates a low negative voltage due to the weak negative polarization, while the second node G2 generates a low positive voltage due to the weak positive polarization. By optimizing the relative sizes of the ferroelectric capacitor and the conventional capacitor, the voltages of the internal nodes (the first node G1 and the second node G2) can be adjusted to appropriate values.

[0114] In this embodiment, the relative sizes of the capacitors are adjusted so that the voltages of the internal nodes (the first node G1 and the second node G2) corresponding to the '11', '10', '01', and '00' states are (+0.5V, -0.5V), (+0.2V, -0.2V), (-0.2V, +0.2V), and (-0.5V, +0.5V), respectively.

[0115] Of course, the above introduction to the polarization state of the ferroelectric capacitor is exemplary, and the introduction to the number of bits written is exemplary. The various storage units 10 of the embodiments of the present disclosure can also realize data storage of other bit numbers besides 1 bit and 2 bits. The embodiments of the present disclosure are not limited to this. In addition, the first duration, the second duration and the size of each voltage introduced in the above examples should not be regarded as limitations on the embodiments of the present disclosure.

[0116] In a possible implementation, the target operation may further include a content addressing operation, and the input control signal to control the storage unit 10 to perform the target operation may include:

[0117] Controlling the bias voltage of the source of the first transistor M1 and the source of the second transistor M2, and inputting data that needs to be matched;

[0118] The matching result of the content addressing operation is obtained according to the voltage or current of the drain of the first transistor M1 and the drain of the second transistor M2.

[0119] In a possible implementation, the inputting of a control signal to control the storage unit 10 to perform a target operation may include:

[0120] When performing the content addressing operation, controlling the voltages of the second end of the third capacitor CFE3, the second end of the fourth capacitor CFE4, and the source of the first transistor M1, so that the first transistor M1 is turned on or off according to the matching result;

[0121] controlling the voltages of the second end of the third capacitor CFE3, the fourth capacitor CFE4, and the source of the second transistor M2 so that the second transistor M2 is turned on or off according to the matching structure;

[0122] The matching result of the content addressing operation is obtained according to the impedance value between the source and the drain of the first transistor M1, the impedance value between the source and the drain of the second transistor M2, or the influence of the impedance value on the voltage or current of the drain of the first transistor M1 and the drain of the second transistor M2.

[0123] For example, Figure 1b As shown, when a content addressing operation is performed on the data stored in the memory cell 10, the voltages of the second word line PL and the first read port BLR1 can be controlled so that the first transistor M1 of the memory cell 10 is turned on or off according to the matching result. The second word line PL and the second read port BLR2 can turn the second transistor M2 of the memory cell 10 on or off according to the matching structure. The matching result of the memory cell 10 can be determined based on the impedance values ​​between the source and drain of the first transistor M1 and the source and drain of the second transistor M2, or the influence of the impedance values ​​on the voltage or current of the third word line ML of the memory cell 10.

[0124] See also Figure 3 , Figure 3 A schematic diagram of a memory performing content addressing operations according to an embodiment of the present disclosure is shown.

[0125] For example, Figure 3As shown, when performing a content addressing operation on the memory cell 10, the first word line WS can be adjusted so that both the first switch T1 and the second switch T2 are in the off state. The polarization state of the ferroelectric capacitor does not change, and the potentials of the first node G1 and the second node G2 change synchronously with the voltage of the second word line PL. The data to be matched is reflected in the potentials of the first read port BLR1 and the second read port BLR2. First, the first read port BLR1 and the second read port BLR2 are charged to a high voltage. If a '1' is input, the first read port BLR1 becomes floating and the second read port BLR2 is at a low voltage. If a '0' is input, the first read port BLR1 becomes low and the second read port BLR2 becomes floating. If a 'don't care' is input, both the first read port BLR1 and the second read port BLR2 become floating.

[0126] For example, Figure 3 As shown, when performing content addressing operation, the third word line ML is first charged to a high voltage, and the read information is determined by measuring the voltage change of the third word line ML. The potential of the second word line PL is biased at 0.5V, so that the internal node voltages corresponding to the '1' and '0' states are 1V and 0V respectively, and the transistors are in the on and off states respectively. If the state is '1', the first transistor M1 is on and the second transistor M2 is off. At this time, only when a '0' input is input and the first read port BLR1 is low, the potential of the third word line ML will decrease due to the potential of the first read port BLR1, indicating a 'mismatch'. For a '1' or 'don't care' input, the potential of the third word line ML will remain unchanged, indicating a 'match'. If the state is '0', the first transistor M1 is off and the second transistor M2 is on. At this time, only when a '1' input is input and the second port is low, the potential will decrease due to the potential of the second read port BLR2, indicating a 'mismatch'. For a '0' or 'don't care' input, the potential will remain unchanged, indicating a 'match'. If the state is 'don't care', both the first transistor M1 and the second transistor M2 are off and the potential remains unchanged, indicating a 'match'. These changes can be detected by measuring the voltage on the third word line ML using a voltage amplifier. Alternatively, the matching result can be determined by measuring the change in the current on the third word line ML. In a possible implementation, the inputting of a control signal to control the storage unit 10 to perform a target operation may include:

[0127] By performing the content addressing operation multiple times and changing the bias voltage of the second end of the third capacitor CFE3 and the second end of the fourth capacitor CFE4, the bias voltage of the first end of the first switch T1, and the bias voltage of the first end of the second switch T2 during the multiple content addressing operations, more than one bit of data stored in the storage unit 10 is matched successively.

[0128] For example, Figure 3 As shown, when performing multi-value content addressing operations on the memory array, the first word line WS is adjusted so that both the first switch T1 and the second switch T2 are in the off state. The polarization state of the ferroelectric capacitor does not change, and the potential of the first node G1 and the potential of the second node G2 change synchronously with the voltage of the second word line PL. The matching operation proceeds through multiple steps and various second word line PL potentials. The first transistor M1 and the second transistor M2 are turned off or on depending on the second word line PL potential and the multi-value storage state of the memory cell 10.

[0129] See also Figure 4 , Figure 4 FIG. 1 is a schematic diagram showing the state of the storage unit 10 when performing a multi-content addressing operation according to an embodiment of the present disclosure.

[0130] In this example, the memory cell 10 stores two-bit information, the data to be matched is two-bit information, and three second word line PL potentials V PL1 , V PL2 , V PL3 Under the influence of the three second word line PL potentials and storage states, the states of the first transistor M1 and the second transistor M2 are as follows: Figure 4 shown.

[0131] The matching operation first precharges the third word line ML to a high potential.

[0132] In the first step of matching, the input is the high-order bit of the data to be matched. If the high-order bit of the data to be matched is '1', the first read port BLR1 is suspended and the second read port BLR2 is electrically low; if the high-order bit of the data to be matched is '0', the first read port BLR1 is electrically low and the second read port BLR2 is suspended; the second word line PL is set to V PL2 Potential, if the high bit of the storage state is '0', that is, '00' or '01', the first transistor M1 is cut off and the second transistor M2 is turned on; if the high bit of the storage state is '1', that is, '10' or '11', the first transistor M1 is turned on and the second transistor M2 is cut off; when the high bit of the data to be matched is inconsistent with the high bit of the storage state, the first transistor M1 is turned on and the first read port BLR1 is at a low potential, or the second transistor M2 is turned on and the second read port BLR2 is at a low potential, so the third word line ML will be discharged to a low potential, resulting in a mismatch; when the high bit of the data to be matched is consistent with the high bit of the storage state, the third word line ML will remain at a high potential.

[0133] In the second step of matching, the input is the low bit of the data to be matched. There are two input situations. When the high bit of the first step is '1', if the low bit of the data to be matched is '1', the first read port BLR1 is suspended and the second read port BLR2 is electrically low. If the low bit of the data to be matched is '0', the first read port BLR1 is electrically low and the second read port BLR2 is suspended. The second word line PL is set to V PL1 The first transistor M1 is turned on only when the storage state is '11', and is turned off when the storage state is '00', '01', or '10'. The second transistor M2 is turned on only when the storage state is '00', and is turned off when the storage state is '01', '10', or '11'. When the storage state is '11' and the low bit to be matched is '0', there is a mismatch. In this case, the first transistor M1 is turned on, the first read port BLR1 is at a low potential, and the third word line ML is discharged to a low potential. When the storage state is '00' and the low bit to be matched is '1', there is a mismatch. In this case, the second transistor M2 is turned on, the second read port BLR2 is at a low potential, and the third word line ML is discharged to a low potential. When the storage state is '10' or '01', both the first transistor M1 and the second transistor M2 are turned off, so the third word line ML remains at a high potential. After the second step, the third word line ML is discharged to a low potential, indicating a low bit mismatch. If the third word line ML remains at a high potential, subsequent steps are required for matching.

[0134] In the third matching step, the second word line PL is set to V PL3 The first read port BLR1 and the second read port BLR2 are set according to the high bit of the stored state and the low bit of the data to be matched. If the high bit of the stored state is '1', that is, the stored state is '11' or '10', when the low bit to be matched is '1', the first read port BLR1 is set to floating and the second read port BLR2 is set to a low potential. If the low bit to be matched is mismatched, the second transistor M2 is turned on, and the third word line ML is discharged to a low potential. When the low bit to be matched is '0', the first read port BLR1 is set to floating, the second read port BLR2 is set to floating, and the third word line ML is maintained at a high potential. If the high bit of the storage state is '0', that is, the storage state is '00' or '01', when the low bit to be matched is '1', the first read port BLR1 is floating, the second read port BLR2 is floating, and the third word line ML is maintained at a high potential; when the low bit to be matched is '0', the first read port BLR1 is floating, the second read port BLR2 is at a low potential. If the low bit to be matched is mismatched, the second transistor M2 is turned on and the third word line ML is discharged to a low potential.

[0135] In one possible embodiment, the various memory cells 10 of the memory are combined into a multi-row and multi-column layout by electrical connection, wherein the first word lines WS of the memory cells 10 in the same row are connected, the second word lines PL of the memory cells 10 in the same row are connected, the third word lines ML of the memory cells 10 in the same row are connected, the first write ports BLW1 of the memory cells 10 in the same column are connected, the second write ports BLW2 of the memory cells 10 in the same column are connected, the first read ports BLR1 of the memory cells 10 in the same column are connected, and the second read ports BLR2 of the memory cells 10 in the same column are connected.

[0136] like Figure 2 As shown, when writing to the memory cell 10, the unselected rows adjust the potential of the first word line WS so that the first switch T1 and the second switch T2 are both turned off, and the storage state is not affected; the selected rows adjust the potential of the first word line WS so that the first switch T1 and the second switch T2 are both turned on. If '1' is written to the memory cell 10, the potential of the first write port BLW1 is biased at +V W , bias the second write port BLW2 potential at -V W , the second word line PL potential is biased twice: first biased at +V W , then biased to -V W , first biased to +V W When the information originally stored in the first capacitor CFE1 does not change, the second capacitor CFE2 becomes negatively polarized and is biased to -V W When '0' is written to the memory cell 10, the first write port BLW1 is biased at -V W , bias the second write port BLW2 potential at +V W , the second word line PL potential is biased twice: first biased at +V W , when biased to -V W , first biased to +V W When the first capacitor CFE1 changes to a negative polarization state, the information originally stored in the second capacitor CFE2 does not change, and the second bias is to -V W When , the information stored in the first capacitor CFE1 no longer changes and maintains the negative polarization state, the second capacitor CFE2 becomes positively polarized, that is, '0' is written, the first node G1 generates a negative voltage due to the negative polarization, and the second node G2 generates a positive voltage due to the positive polarization.

[0137] For example, by optimizing the relative sizes of the ferroelectric capacitor and the ordinary capacitor, the voltages of the internal nodes (the first node G1 and the second node G2) can be made to take appropriate values; if the "don't care" state is written to the memory cell 10, the potential of the first write port BLW1 and the potential of the second write port BLW2 are both biased to -V W , the second word line PL potential is biased to +V W , the first capacitor CFE1 and the second capacitor CFE2 both become negatively polarized, and the first node G1 and the second node G2 both generate negative voltages due to the negative polarization. In this embodiment, the relative sizes of the capacitors are adjusted so that the internal node voltages corresponding to the '1' and '0' states are +0.5V and -0.5V, respectively.

[0138] like Figure 3 As shown, when a binary content addressing operation is performed on the memory cell 10, all rows in the array can perform the content addressing operation simultaneously.

[0139] For example, the first word line WS can be adjusted so that both the first switch T1 and the second switch T2 are in the off state. The polarization state of the ferroelectric capacitor remains unchanged, and the potentials of the first node G1 and the second node G2 change synchronously with the voltage of the second word line PL. The data to be matched is reflected in the potentials of the first read port BLR1 and the second read port BLR2. First, the first read port BLR1 and the second read port BLR2 are charged to a high voltage. If a '1' input is input, the first read port BLR1 becomes floating and the second read port BLR2 is electrically low. If a '0' input is input, the first read port BLR1 becomes low and the second read port BLR2 becomes floating. If a 'don't care' input is input, both the first read port BLR1 and the second read port BLR2 become floating. The data to be matched is shared by all rows through the first read port BLR1 and the second read port BLR2. When performing content addressing operations, the third word line ML is first charged to a high voltage. The read information is determined by measuring the voltage change of the third word line ML. The second word line PL potential is biased at 0.5V, so that the internal node voltages corresponding to the '1' and '0' states are 1V and 0V respectively, and the transistors are in the on and off states respectively. If the state is '1', the first transistor M1 is on and the second transistor M2 is off. At this time, only when a '0' input is input, the first read port BLR1 is at a low level. The potential decreases due to the potential of the first read port BLR1, indicating a 'mismatch'. With a '1' or 'don't care' input, the potential remains unchanged, indicating a 'match'. If the state is '0', the first transistor M1 is off and the second transistor M2 is on. At this time, only when a '1' input is input, the second port is at a low level. The potential decreases due to the potential of the second read port BLR2, indicating a 'mismatch'. With a '0' or 'don't care' input, the potential remains unchanged, indicating a 'match'. If the state is 'don't care', both the first transistor M1 and the second transistor M2 are off and the potential remains unchanged, indicating a 'match'. These changes can be detected by measuring the voltage on the third word line ML using a voltage amplifier. Alternatively, the match result can be determined by measuring the change in current on the third word line ML. Each row in the array can independently provide a match result via its respective third word line ML.

[0140] For example, the write operation duration or the above-mentioned write voltage V wBy adjusting the voltage, the memory cell 10 can store more than one bit of multi-value information. For example, the first capacitor CFE1 and the second capacitor CFE2 can be in four or more states: strong positive polarization, weak positive polarization, strong negative polarization, and weak negative polarization. When performing a multi-value write operation on the memory cell 10, the potential of the first word line WS is adjusted in the unselected rows so that the first switch T1 and the second switch T2 are both turned off, and the storage state is not affected. The potential of the first word line WS is adjusted in the selected rows so that the first switch T1 and the second switch T2 are both turned on.

[0141] For example, if '11' is written into the memory cell 10, the first write port BLW1 is biased at +V W , bias the second write port BLW2 potential at -V W , the second word line PL potential is biased twice for a long time: first biased at +V for a long time W , then bias to -V for a long time W , first biased to +V W When the information originally stored in the first capacitor CFE1 does not change, the second capacitor CFE2 becomes a strong negative polarization state and is biased to -V for the second time. W When '11' is written, the first node G1 generates a high positive voltage due to the strong positive polarization state, and the second node G2 generates a negative voltage with a large absolute value due to the strong negative polarization state.

[0142] For example, if '10' is written into the memory cell 10, after the aforementioned step of writing '11', the first write port BLW1 is biased at -V W , bias the second write port BLW2 at +V w , the second word line PL potential is biased twice for a short time: first biased at +V for a short time w , biased at -V for a short time W , first biased to +V W When the first capacitor CFE1 changes to a weak positive polarization state, the second capacitor CFE2 still maintains a strong negative polarization state, and the second bias is -V W When '10' is written, the first node G1 generates a low positive voltage due to the weak positive polarization, and the second node G2 generates a negative voltage with a small absolute value due to the weak negative polarization.

[0143] For example, if '00' is written into the memory cell 10, the first write port BLW1 is biased at -V W, bias the second write port BLW2 potential at +V W , the second word line PL potential is biased twice: first biased at +V W , when biased to -V W , first biased to +V W When the first capacitor CFE1 changes to a strong negative polarization state, the information originally stored in the second capacitor CFE2 does not change, and the second bias to -V W When 0 is written, the information stored in the first capacitor CFE1 no longer changes and maintains the negative polarization state. The second capacitor CFE2 becomes a strong positive polarization state, that is, '00' is written. The first node G1 generates a negative voltage with a large absolute value due to the strong negative polarization, and the second node G2 generates a high positive voltage due to the strong positive polarization.

[0144] For example, if '01' is written into the memory cell 10, after the aforementioned step of writing '00', the first write port BLW1 is biased at +V W , bias the second write port BLW2 at -V w , the second word line PL potential is biased twice for a short time: first biased at +V for a short time w , biased at -V for a short time W , first biased to +V W When the first capacitor CFE1 is still maintained in a strong negative polarization state, the second capacitor CFE2 becomes a weak positive polarization state, and the second bias is -V W When the ferroelectric capacitor is switched to a weak negative polarization state, the information stored in the second capacitor CFE2 no longer changes. The first capacitor CFE1 becomes weakly negatively polarized, while the second capacitor CFE2 maintains a weakly positive polarization state. That is, '01' is written. The first node G1 generates a low negative voltage due to the weak negative polarization, while the second node G2 generates a low positive voltage due to the weak positive polarization. By optimizing the relative sizes of the ferroelectric capacitor and the conventional capacitor, the voltages of the internal nodes (the first node G1 and the second node G2) can be adjusted to appropriate values.

[0145] For example, in this embodiment, the relative sizes of the capacitors are adjusted so that the voltages of the internal nodes (G1, G2) corresponding to the '11', '10', '01', and '00' states are (+0.5V, -0.5V), (+0.2V, -0.2V), (-0.2V, +0.2V), and (-0.5V, +0.5V), respectively.

[0146] like Figure 3As shown, when performing multi-value content addressing operations on the memory array, the first word line WS is adjusted so that the first switch T1 and the second switch T2 are both in the off state. The polarization state of the ferroelectric capacitor does not change, and the potential of the first node G1 and the potential of the second node G2 change synchronously with the voltage of the second word line PLPL. The matching operation will go through multiple steps and multiple second word line PL potentials. The first transistor M1 and the second transistor M2 will be in the off or on state according to the second word line PL potential and the multi-value storage state of the memory cell 10. In this example, the memory cell 10 stores two bits of information, and the data to be matched is two bits of information. Three second word line PL potentials V PL1 , V PL2 , V PL3 Under the influence of the three second word line PL potentials and storage states, the states of the first transistor M1 and the second transistor M2 are as follows: Figure 4 The matching operation first precharges the third word line ML to a high potential.

[0147] For example, in the first step of matching, the input is the high-order bit of the data to be matched. If the high-order bit of the data to be matched is '1', the first read port BLR1 is left unconnected and the second read port BLR2 is electrically low. If the high-order bit of the data to be matched is '0', the first read port BLR1 is electrically low and the second read port BLR2 is left unconnected. The second word line PL is set to V PL2 Potential, if the high bit of the storage state is '0', that is, '00' or '01', the first transistor M1 is cut off and the second transistor M2 is turned on; if the high bit of the storage state is '1', that is, '10' or '11', the first transistor M1 is turned on and the second transistor M2 is cut off; when the high bit of the data to be matched is inconsistent with the high bit of the storage state, the first transistor M1 is turned on and the first read port BLR1 is at a low potential, or the second transistor M2 is turned on and the second read port BLR2 is at a low potential, so the third word line ML will be discharged to a low potential, resulting in a mismatch; when the high bit of the data to be matched is consistent with the high bit of the storage state, the third word line ML will remain at a high potential.

[0148] For example, in the second step of matching, the input is the low bit of the data to be matched. There are two input situations. When the high bit of the first step is '1', if the low bit of the data to be matched is '1', the first read port BLR1 is suspended and the second read port BLR2 is electrically low. If the low bit of the data to be matched is '0', the first read port BLR1 is electrically low and the second read port BLR2 is suspended. The second word line PL is set to V PL1The first transistor M1 is turned on only when the storage state is '11', and is turned off when the storage state is '00', '01', or '10'. The second transistor M2 is turned on only when the storage state is '00', and is turned off when the storage state is '01', '10', or '11'. When the storage state is '11' and the low bit to be matched is '0', there is a mismatch. In this case, the first transistor M1 is turned on, the first read port BLR1 is at a low potential, and the third word line ML is discharged to a low potential. When the storage state is '00' and the low bit to be matched is '1', there is a mismatch. In this case, the second transistor M2 is turned on, the second read port BLR2 is at a low potential, and the third word line ML is discharged to a low potential. When the storage state is '10' or '01', both the first transistor M1 and the second transistor M2 are turned off, so the third word line ML remains at a high potential. After the second step, the third word line ML is discharged to a low potential, indicating a low bit mismatch. If the third word line ML remains at a high potential, subsequent steps are required for matching.

[0149] Exemplarily, in the third matching step, the second word line PL is set to V PL3 The first read port BLR1 and the second read port BLR2 are set according to the high bit of the stored state and the low bit of the data to be matched. If the high bit of the stored state is '1', that is, the stored state is '11' or '10', when the low bit to be matched is '1', the first read port BLR1 is set to floating and the second read port BLR2 is set to a low potential. If the low bit to be matched is mismatched, the second transistor M2 is turned on, and the third word line ML is discharged to a low potential. When the low bit to be matched is '0', the first read port BLR1 is set to floating, the second read port BLR2 is set to floating, and the third word line ML is maintained at a high potential. If the high bit of the storage state is '0', that is, the storage state is '00' or '01', when the low bit to be matched is '1', the first read port BLR1 is floating, the second read port BLR2 is floating, and the third word line ML is maintained at a high potential; when the low bit to be matched is '0', the first read port BLR1 is floating, the second read port BLR2 is at a low potential. If the low bit to be matched is mismatched, the second transistor M2 is turned on and the third word line ML is discharged to a low potential.

[0150] See also Figure 5 , Figure 5 Schematic diagrams of transient waveforms of the storage unit 10 under different write operations according to an embodiment of the present disclosure are shown.

[0151] For example, Figure 5 As shown, the waveforms of the port voltages in the written state '1', the written state '0', and the written state 'don't care' are included.

[0152] See also Figure 6 , Figure 6 Schematic diagrams of transient waveforms of the memory cell 10 under different multi-value write operations according to an embodiment of the present disclosure are shown.

[0153] For example, Figure 6 As shown, the port voltage waveforms of the written state '11', the written state '10', the written state '00', and the written state '01' are included.

[0154] See also Figure 7 , Figure 7 Schematic diagrams of transient waveforms of the memory cell 10 under different matching operations according to an embodiment of the present disclosure are shown.

[0155] For example, Figure 7 Medium V G1 @'1' represents the potential of the first node G1 in the '1' state, V G1 @'0' represents the potential of the first node G1 in the '0' state, V G2 @'1' represents the potential of the second node G2 in the '1' state, V G2 @'0' represents the potential of the second node G2 in state '0', which is the potential of the third word line ML. Through the voltage coupling of the second word line PL, the potential of the first node G1 (V G1 ) and the second node G2 (V G2 ) potential will change according to the storage state. A higher potential will turn on the first transistor M1 or the second transistor M2. When mismatch occurs, the third word line ML will be discharged to a low potential. When match occurs, the third word line ML maintains a high potential.

[0156] See also Figure 8 , Figure 8 FIG. 1 is a schematic diagram showing a storage unit 10 performing a multi-value content addressing operation through multiple steps according to an embodiment of the present disclosure.

[0157] For example, Figure 8 As shown, through several matching steps, content addressing operations are performed on different bits in the multi-value input and the multi-value storage state.

[0158] See also Figure 9 , Figure 9 A schematic diagram showing internal node voltage and ferroelectric polarization strength at different capacitance ratios in a memory cell 10 according to an embodiment of the present disclosure is shown.

[0159] Figure 9 C PL Refers to the capacitance value of the first capacitor CFE1 or the second capacitor CFE2, C FE Refers to the capacitance value of the third capacitor CFE3 or the fourth capacitor CFE4, Q FERefers to the third capacitor CFE3 or the fourth capacitor CFE4C FE The charge, V FE Refers to the third capacitor CFE3 or the fourth capacitor CFE4C during the write operation FE The voltage across the terminals, V G Refers to the voltage of the intermediate node G1 or G2 to ground after the write operation is completed.

[0160] In a possible implementation manner, the first capacitor CFE1 , the second capacitor CFE2 , the third capacitor CFE3 , and the fourth capacitor CFE4 are implemented using a planar structure or a three-dimensional structure.

[0161] See also Figure 10 , Figure 10 A schematic diagram of a physical implementation of a unit structure of a memory according to an embodiment of the present disclosure is shown.

[0162] For example, Figure 10 As shown, the first switch T1 and the second switch T2 can be implemented by transistors, and the capacitors are respectively Figure 10 The plane structure and Figure 10 The three-dimensional structure in the right figure is realized. M represents the metal layer, I represents the ordinary dielectric layer, and F represents the ferroelectric dielectric layer.

[0163] According to one aspect of the present disclosure, an electronic device is provided, comprising the ferroelectric capacitor-based nonvolatile content addressable memory.

[0164] Exemplarily, an electronic device may include a terminal. In one example, a terminal is also referred to as a user equipment (UE), a mobile station (MS), a mobile terminal (MT), etc., and is a device that provides voice and / or data connectivity to a user, for example, a handheld device with wireless connection function, a vehicle-mounted device, etc. Currently, some examples of terminals include: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving (Self-driving), wireless terminals in remote medical surgery (Remote Medical Surgery), wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in the Internet of Vehicles, etc.

[0165] While various embodiments of the present disclosure have been described above, the above descriptions are illustrative, non-exhaustive, and not intended to be limiting of the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A non-volatile content addressable memory based on ferroelectric capacitors, characterized in that: The memory includes: A plurality of memory cells, each memory cell comprising a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first switch, a second switch, a first transistor, and a second transistor, wherein the second end of the first switch and the second end of the second switch are respectively connected to the first end of the first capacitor and the first end of the second capacitor, the second end of the first capacitor, the first end of the third capacitor, and the gate of the first transistor are all connected to a first node, and the second end of the second capacitor, the first end of the fourth capacitor, and the gate of the second transistor are all connected to a second node, wherein at least one of the first capacitor and the third capacitor is a ferroelectric capacitor, and at least one of the second capacitor and the fourth capacitor is a ferroelectric capacitor; a control unit connected to the control end of the first switch, the control end of the second switch, the first end of the first switch, the first end of the second switch, the source of the first transistor, the source of the second transistor, the drain of the first transistor, the drain of the second transistor, and the second end of the third capacitor in each storage unit, and configured to: A control signal is input to control the memory cell to perform a target operation.

2. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 1, characterized in that: The storage unit also includes a first word line, a second word line, a third word line, a first write port, a second write port, a first read port, and a second read port, wherein the control end of the first switch and the control end of the second switch are connected to the first word line, the first end of the first switch and the first end of the second switch are respectively connected to the first write port and the second write port, the source of the first transistor is connected to the first read port, the source of the second transistor is connected to the second read port, the drain of the first transistor and the drain of the second transistor are both connected to the third word line, the second end of the third capacitor and the second end of the fourth capacitor are both connected to the second word line, and the control unit is connected to the first word line, the second word line, the third word line, the first write port, the second write port, the first read port, and the second read port.

3. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 1 or 2, characterized in that: The target operation includes a write operation, and the input control signal is used to control the storage unit to perform the target operation, including: Control the voltages of the second end of the third capacitor and the second end of the fourth capacitor, the first end of the first switch, and the second switch, adjust the polarization state of the ferroelectric capacitor in the storage unit, and adjust the voltages of the first node and the second node to write the data to be stored.

4. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 3, characterized in that: The input control signal is used to control the storage unit to perform a target operation, including: controlling the voltages of the control end of the first switch and the control end of the second switch to turn on the first switch and the second switch; Controlling the bias voltages of the first end of the first switch and the first end of the second switch to be complementary voltages; Controlling the second end of the third capacitor and the second end of the fourth capacitor to change from an initial voltage, and stay at a preset low voltage and a preset high voltage for a period of time respectively, and then returning to the initial voltage; The voltages of the control end of the first switch and the control end of the second switch are controlled so that the first switch and the second switch are turned off, so as to write data to be stored.

5. The non-volatile content addressable memory based on ferroelectric capacitor according to claim 1 or 2, characterized in that: The target operation includes a write operation, and the input control signal is used to control the storage unit to perform the target operation, including: Control the bias voltage of the second end of the third capacitor, the second end of the fourth capacitor, the first end of the first switch, the second switch, and the duration of each bias voltage, and set the polarization state of each ferroelectric capacitor to one of more than two states, so that each ferroelectric capacitor stores more than one bit of data.

6. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 5, characterized in that: The polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state. The input control signal is used to control the storage unit to perform a target operation, including: If it is necessary to write '11' in the storage unit, the potential of the source of the first transistor is biased at a first positive voltage, the potential of the source of the second transistor is biased at a first negative voltage, and the potential of the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first biased at the first positive voltage for a first time length, and then biased to the first negative voltage for the first time length, so that the first capacitor becomes a strongly positive polarization state and the second capacitor maintains a strongly negative polarization state, thereby writing '11'.

7. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 6, characterized in that: The polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state. The input control signal is used to control the storage unit to perform a target operation, including: If it is necessary to write '10' in the storage cell, after writing '11', the source of the first transistor is biased at the first negative voltage, the source of the second transistor is biased at the first positive voltage, and the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first at the first positive voltage for a second time length, and then at the first negative voltage for a second time length, so that the second capacitor becomes a weakly negative polarization state and the first capacitor maintains a weakly positive polarization state, thereby writing '10', and the second time length is less than the first time length.

8. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 5, characterized in that: The polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state. The input control signal is used to control the storage unit to perform a target operation, including: If '00' needs to be written in the storage unit, the source potential of the first transistor is biased at a first negative voltage, the source potential of the second transistor is biased at a first positive voltage, and the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first at the first positive voltage and then at the first negative voltage, so as to change the first capacitor into a negative polarization state and the second capacitor into a strong positive polarization state, thereby writing '00'.

9. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 8, characterized in that: The polarization state includes a strong positive polarization state, a weak positive polarization state, a strong negative polarization state, and a weak negative polarization state. The input control signal is used to control the storage unit to perform a target operation, including: If it is necessary to write '01' in the storage cell, after the step of writing '00', the source of the first transistor is biased at the first positive voltage, the source of the second transistor is biased at the first negative voltage, and the second end of the third capacitor and the second end of the fourth capacitor are biased twice: first biased at the first positive voltage for a second time length, and then biased at the first negative voltage for a second time length, the first capacitor is changed to a weak negative polarization state, and the second capacitor is changed to a weak positive polarization state, thereby writing '01'.

10. The non-volatile content addressable memory based on ferroelectric capacitor according to claim 1 or 2, characterized in that: The target operation includes a content addressing operation, and the input control signal is used to control the storage unit to perform the target operation, including: controlling the bias voltage of the source of the first transistor and the source of the second transistor, and inputting data that needs to be matched; A matching result of the content addressing operation is obtained according to the voltage or current of the drain of the first transistor and the drain of the second transistor.

11. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 10, characterized in that: The input control signal is used to control the storage unit to perform a target operation, including: When performing the content addressing operation, controlling the voltages of the second end of the third capacitor, the second end of the fourth capacitor, and the source of the first transistor so that the first transistor is turned on or off according to a matching result; controlling the voltages of the second end of the third capacitor, the fourth capacitor, and the source of the second transistor so that the second transistor is turned on or off according to the matching structure; The matching result of the content addressing operation is obtained based on the impedance value between the source and drain of the first transistor, the impedance value between the source and drain of the second transistor, or the influence of the impedance value on the voltage or current of the drain of the first transistor and the drain of the second transistor.

12. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 10, characterized in that: The input control signal is used to control the storage unit to perform a target operation, including: By performing the content addressing operation multiple times and changing the bias voltages of the second end of the third capacitor and the second end of the fourth capacitor, the bias voltage of the first end of the first switch, and the bias voltage of the first end of the second switch during the multiple content addressing operations, more than one bit of data stored in the storage unit is matched successively.

13. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 2, characterized in that: The memory cells are electrically connected to form a multi-row and multi-column layout, wherein the first word lines of the memory cells in the same row are connected, the second word lines of the memory cells in the same row are connected, the third word lines of the memory cells in the same row are connected, the first write ports of the memory cells in the same column are connected, the second write ports of the memory cells in the same column are connected, the first read ports of the memory cells in the same column are connected, and the second read ports of the memory cells in the same column are connected.

14. The nonvolatile content addressable memory based on ferroelectric capacitor according to claim 1, characterized in that: The first capacitor, the second capacitor, the third capacitor and the fourth capacitor are implemented using a planar structure or a three-dimensional structure.

15. An electronic device, characterized in that: The electronic device comprises the nonvolatile content addressable memory based on ferroelectric capacitor according to any one of claims 1 to 14.

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