Image sensor and manufacturing method thereof

Abstract

The present invention discloses an image sensor and a manufacturing method thereof, belonging to the field of semiconductor technology. The image sensor at least includes: a substrate, including a first surface and a second surface arranged opposite to each other; a photodiode, a charge storage area and a floating diffusion area extending from the first surface into the substrate and arranged at intervals; a doping area extending from the first surface into the substrate, and the doping area and the photodiode, the charge storage area and the floating diffusion area are arranged at intervals; a global exposure transfer gate is arranged between the photodiode and the charge storage area, and covers part of the charge storage area; a transfer gate is arranged between the charge storage area and the floating diffusion area; a shading structure is arranged in the substrate and covers the charge storage area, and the shading structure is electrically connected to the doping area. The image sensor and the manufacturing method thereof provided by the present invention greatly improve the parasitic light response of the charge domain global image sensor, and avoid the residual image caused by insufficient electron transmission.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to an image sensor and its manufacturing method. Background Technology

[0002] CMOS image sensors (Complementary Metal Oxide Semiconductor Image Sensors, CIS) offer advantages such as high integration, low power supply voltage, and low technological barriers, leading to their widespread application in consumer electronics, autonomous driving, biometrics, and security. CMOS image sensors can employ two exposure methods: Global Shutter (GS) mode and Rolling Shutter (RS) mode. In Global Shutter mode, every row of the entire image is exposed simultaneously, and the charge signals are then simultaneously transferred and stored in the pixel's memory node. Finally, the signals from the memory node are read out line by line. Because Global Shutter mode exposes all rows of the entire image at the same time, it eliminates motion blur.

[0003] Global shutter pixels can be categorized into two types based on the type of storage nodes: charge domain and voltage domain. Compared to voltage domain pixels, charge domain pixels offer advantages such as scalability, low readout noise, and low dark current. However, a major technical challenge for charge domain global exposure image sensors is preventing the storage nodes from responding to incident light signals, thus avoiding parasitic light responses. The mainstream approach for front-illuminated global image sensors is to use a light-blocking structure to cover the storage nodes, effectively improving the parasitic light response of the image sensor. While back-illuminated global image sensors offer significantly higher quantum efficiency than front-illuminated sensors, their light-blocking structure design is not optimized, resulting in poor parasitic light response performance. Summary of the Invention

[0004] The purpose of this invention is to provide an image sensor and its manufacturing method. The image sensor and its manufacturing method provided by this invention can effectively prevent light from entering the charge storage region, greatly improve the parasitic light response of the global image sensor in the charge domain, and enhance the transmission capability of electrons from the charge storage region to the floating diffusion region, thus avoiding image retention caused by insufficient electron transmission.

[0005] To address the aforementioned technical problems, the present invention provides an image sensor, comprising at least:

[0006] The substrate includes a first surface and a second surface disposed opposite to each other;

[0007] A photodiode, a charge storage region, and a floating diffusion region extend from the first surface into the substrate and are disposed at intervals within the substrate;

[0008] The doped region extends from the first surface into the substrate and is disposed in the region between the photodiode, the charge storage region and the floating diffusion region, and is spaced apart.

[0009] A global exposure transfer gate is located on the first surface, disposed between the photodiode and the charge storage region, and covers a portion of the charge storage region;

[0010] A transfer gate, located on the first surface, is disposed between the charge storage region and the floating diffusion region; and

[0011] A light-shielding structure is disposed within the substrate and covers the charge storage region, and the light-shielding structure is electrically connected to the doped region.

[0012] In one embodiment of the present invention, a dielectric layer is disposed between the light-shielding structure and the charge storage region, and a portion of the light-shielding structure extends through the dielectric layer to the surface of the doped region.

[0013] In one embodiment of the present invention, an air gap is provided between the photodiode and the charge storage region, and the light-shielding structure covers the air gap.

[0014] In one embodiment of the present invention, the depth of the charge storage region in the substrate is 5% to 30% of the depth of the photodiode in the substrate.

[0015] In one embodiment of the present invention, the thickness of the light-shielding structure is 100nm~300nm, and the material of the light-shielding structure includes at least one of tungsten, aluminum, copper, cobalt, titanium, titanium nitride or nickel.

[0016] In one embodiment of the present invention, the global exposure transmission gate includes a planar gate and a vertical gate, wherein the vertical gate is disposed in the substrate and connected to a portion of the photodiode.

[0017] In one embodiment of the present invention, the image sensor includes a dielectric layer covering the second surface, and a metal grid is disposed within the dielectric layer, the metal grid exposing the photodiode.

[0018] In one embodiment of the present invention, in the circuit timing of the image sensor, when the transmission gate is turned on, the light-shielding structure is turned on by applying a negative voltage, the opening time of the transmission gate is earlier than the opening time of the light-shielding structure, and the closing time of the transmission gate is earlier than the closing time of the light-shielding structure.

[0019] The present invention also provides a method for manufacturing an image sensor, comprising at least the following steps:

[0020] A substrate is provided, the substrate including a first surface and a second surface disposed opposite to each other;

[0021] A photodiode, a charge storage region, and a floating diffusion region are formed at intervals from the first surface into the substrate;

[0022] A doped region is formed from the first surface into the substrate. The doped region is disposed in the region between the photodiode, the charge storage region and the floating diffusion region, and is spaced apart.

[0023] A global exposure transfer gate is formed from the first surface, the global exposure transfer gate is disposed between the photodiode and the charge storage region, and covers a portion of the charge storage region;

[0024] A transfer gate is formed from the first surface, the transfer gate being disposed between the charge storage region and the floating diffusion region; and

[0025] A light-shielding structure is formed within the substrate, the light-shielding structure covering the charge storage region, and the light-shielding structure being electrically connected to the doped region.

[0026] In one embodiment of the present invention, the manufacturing method further includes:

[0027] The substrate includes multiple shallow trench isolation structures, which are at least disposed between the photodiode and the charge storage region, around the doped region, and on the side of the floating diffusion region away from the charge storage region.

[0028] After the gate is formed, an interlayer dielectric layer and a metal wiring layer are formed on the first surface;

[0029] A carrier wafer is bonded to the first surface, the substrate is flipped, and the substrate is thinned to 2μm~3μm from the second surface;

[0030] The substrate is etched from the second surface until the shallow trench isolation structure is reached, forming a groove that exposes the doped region, the charge storage region, and the region between the doped region and the charge storage region; and

[0031] Remove the shallow trench isolation structure between the photodiode and the charge storage region to form an air gap.

[0032] In one embodiment of the present invention, the manufacturing method further includes:

[0033] After the air gap is formed, a dielectric layer is formed on the second surface and the bottom and sidewalls of the groove;

[0034] Etching removes a portion of the dielectric layer on the doped region to form an opening; and

[0035] A light-shielding structure is formed on the dielectric layer inside the opening and at the bottom of the groove.

[0036] In summary, this invention provides an image sensor and its fabrication method, which effectively prevents light from entering the charge storage region, greatly improving the parasitic light response of the global charge domain image sensor. By utilizing a light-shielding structure, a dielectric layer, and a charge storage region to form a parasitic transistor, the readout timing of the image sensor is designed, and the voltage and waveform of the light-shielding structure are specially set to adjust the potential barrier of the charge storage region, enhancing the electron transport capability from the charge storage region to the floating diffusion region and avoiding image retention caused by insufficient electron transport. This method can be widely applied in various types of back-illuminated CMOS image sensors. It also improves the isolation effect between photodiodes, reduces mutual interference between photodiodes, reduces dark current in the device, and improves the electrical performance of the CMOS image sensor. Furthermore, it ensures light intake efficiency and helps improve optical crosstalk between different pixel units.

[0037] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a planar schematic diagram of an image sensor in one embodiment.

[0040] Figure 2 for Figure 1 A cross-sectional view after the front-side process is completed along the abc direction.

[0041] Figure 3 for Figure 1 A cross-sectional view after the front-side process is completed along the de direction.

[0042] Figure 4 for Figure 1 A cross-sectional view of the substrate after bonding and thinning along the abc direction.

[0043] Figure 5 for Figure 1 A cross-sectional view of the substrate after bonding and thinning along the de direction.

[0044] Figure 6 for Figure 1 A cross-sectional view showing a groove formed along the abc direction.

[0045] Figure 7 for Figure 1 A cross-sectional view showing a groove formed along the de direction.

[0046] Figure 8 A plan view for forming the first photoresist layer.

[0047] Figure 9 for Figure 8 A cross-sectional view after removing the shallow trench isolation structure along the abc direction.

[0048] Figure 10 for Figure 8 A cross-sectional view after removing the shallow trench isolation structure along the de direction.

[0049] Figure 11 for Figure 1 A cross-sectional view showing the dielectric layer formed along the abc direction.

[0050] Figure 12 for Figure 1 A cross-sectional view showing the dielectric layer formed along the de direction.

[0051] Figure 13 for Figure 1 Cross-sectional view after etching part of the dielectric layer along the abc direction.

[0052] Figure 14 for Figure 1 A cross-sectional view after etching part of the dielectric layer along the de direction.

[0053] Figure 15 A plan view showing the formation of the light-blocking structure.

[0054] Figure 16 for Figure 15 A cross-sectional view of the light-blocking structure formed along the abc direction.

[0055] Figure 17 for Figure 15 A cross-sectional view of the light-blocking structure formed along the de direction.

[0056] Figure 18 for Figure 1 A cross-sectional view of the image sensor is formed along the abc direction.

[0057] Figure 19 for Figure 1 A cross-sectional view of the image sensor is formed along the de direction.

[0058] Figure 20This is a circuit timing diagram of an image sensor in one embodiment of the present invention.

[0059] Figure 21 This is a schematic diagram of the operation of the transmission gate and the light-shielding structure in one embodiment of the present invention.

[0060] Figure 22 Part (a) is the potential diagram when only the transmission gate is turned on, part (b) is the potential diagram when the transmission gate is turned on and then the light-shielding structure is turned on, part (c) is the potential diagram when the transmission gate is turned off while the light-shielding structure remains on, and part (d) is the potential diagram after the transmission gate and the light-shielding structure are turned off in sequence.

[0061] Label Explanation:

[0062] 10. Substrate; 11. Shallow trench isolation structure; 12. Photodiode; 13. Charge storage region; 14. Floating diffusion region; 15. Global exposure transfer gate; 16. Transfer gate; 17. Doped region; 18. Charge overflow control gate; 19. Drain of charge overflow control transistor; 20. Reset transistor; 21. Source follower transistor; 22. Row select transistor; 101. First well region; 102. Second well region; 103. First isolation well region; 104. Second isolation well region; 105. Pinning Layers; 110, Gate dielectric layer; 111, Front dielectric layer; 1111, Sidewall dielectric layer; 1112, Metal silicide barrier layer; 1113, Via etch stop layer; 112, Interlayer dielectric layer; 113, Conductive plug; 114, Metal wiring layer; 120, Groove; 121, First photoresist layer; 123, Air gap; 124, Dielectric layer; 125, Opening; 126, Light-shielding structure; 130, Dielectric layer; 131, Metal grid; 200, Carrier wafer. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0066] Please see Figure 1 and Figure 18 As shown, the present invention does not limit the type of image sensor. For the purpose of illustrating this application, the image sensor provided in this embodiment is, for example, a back-illuminated global shutter CMOS image sensor, and the image sensor includes a photodiode (PD) 12, a charge storage region (MN) 13, a floating diffusion region (FD) 14, a global exposure transfer gate 15, a transfer gate 16, a doped region 17, a charge overflow control gate 18, a charge overflow control transistor drain 19, a reset transistor (RST) 20, a source follower transistor (SF) 21, and a row select transistor (RS) 22, etc. In this embodiment, a light-shielding structure (LSM) 126 is formed within the substrate 10. The LSM 126 covers the charge storage region 13 and the doped region 17, and is electrically connected to the doped region 17. This prevents light interference with the charge storage region 13, improves parasitic light response, and allows for readout timing design. Special settings are made for the voltage and waveform of the LSM 126, utilizing parasitic transistor characteristics to adjust the potential barrier of the charge storage region 13. This enhances the electron transfer capability from the charge storage region 13 to the floating diffusion region 14, avoiding transfer lag caused by insufficient electron transfer. This method can be widely applied in various types of back-illuminated CMOS image sensors. This application also provides a method for fabricating an image sensor. In this embodiment, for example... Figure 1 The manufacturing process of the image sensor is explained using cross-sectional views along the abc and de directions as an example.

[0067] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, Figure 2 for Figure 1 A cross-sectional view after the front-side fabrication process is completed along the abc direction. Figure 3 for Figure 1A cross-sectional view after the front-side process is completed along the de direction. The substrate 10 can be any applicable semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), silicon germanium (GeSi), sapphire, or silicon wafers, and may also include stacked structures composed of these semiconductors, or silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked germanium, silicon-on-insulator, and germanium-on-insulator, etc., specifically selected according to the fabrication requirements of the image sensor. In this embodiment, the substrate 10 is, for example, a silicon wafer semiconductor substrate, or a P-type substrate. The substrate 10 includes a first surface and a second surface disposed opposite each other. The side forming the global exposure transfer gate 15, the transfer gate 16, and the charge overflow control gate 18 is defined as the first surface, and the side opposite the first surface is defined as the second surface.

[0068] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, a photodiode 12, a charge storage region 13, and a floating diffusion region 14 extend from a first surface into the substrate 10 and are spaced apart within the substrate 10. The charge storage region 13 is disposed, for example, on one side of the photodiode 12, and the floating diffusion region 14 is disposed on one side of the charge storage region 13. A doped region 17 is disposed within the substrate 10 between the photodiode 12, the charge storage region 13, and the floating diffusion region 14. A shallow trench isolation structure 11 is formed around the doped region 17. The impurity ions within the doped region 17 are, for example, boron (B) or boron fluoride (BF2). + P-type impurities such as P-type impurities. The photodiode 12, charge storage region 13 and floating diffusion region 14 are isolated by a shallow trench isolation structure 11 and / or a second isolation trap region 104.

[0069] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, the photodiode 12 includes a first well region 101 and a second well region 102. The depth of the second well region 102 in the substrate 10 is less than the depth of the first well region 101 in the substrate 10. The impurity ions in the first well region 101 are, for example, N-type impurities such as phosphorus or arsenic, and the impurity ions in the second well region 102 are, for example, P-type impurities such as boron. In this embodiment, the depth of the photodiode 12 in the substrate 10 is, for example, 2 μm to 4 μm. Furthermore, the doping concentration of the second well region 102 is greater than the doping concentration of the first well region 101, forming a built-in electric field pointing from the first well region 101 to the second well region 102. By setting a high-doped second well region 102, the depletion region of the first well region 101 is prevented from extending to the surface of the substrate 10, reducing the dark current caused by dangling bonds on the surface of the substrate 10.

[0070] Please see Figures 1 to 3As shown, in one embodiment of the present invention, a first isolation well region 103 is provided at the bottom and outside the sidewalls of the shallow trench isolation structure 11. The impurity ions in the first isolation well region 103 are, for example, P-type impurities such as boron, to improve the isolation effect. A second isolation well region 104 is also formed within the substrate 10, and the impurity ions in the second isolation well region 104 are, for example, P-type impurities such as boron. In this embodiment, the second isolation well region 104 encloses the first isolation well region 103 and the area of ​​the substrate 10 other than the photodiode, and the doping concentration of the first isolation well region 103 is greater than the doping concentration of the second isolation well region 104. The first isolation well region 103 is highly doped to prevent the depletion region of the photodiode from widening towards the interface of the shallow trench isolation structure 11, thereby reducing the dark current caused by interface defects. The second isolation well region 104 serves as an isolation between the photodiode and other structures, as well as between photodiodes, further improving the isolation effect between photodiodes and reducing mutual interference between photodiodes.

[0071] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, a pinning layer 105 is formed on the second well region 102. One end of the pinning layer 105 is located on the second isolation well region 104, and the other end is located on the second well region 102, with a predetermined distance from the edge of the second well region 102. The doped ions of the pinning layer 105 are, for example, p-type impurities such as boron, and the doping concentration of the pinning layer 105 is greater than the doping concentration of the second well region 102, for example, equal to the doping concentration of the first isolation well region 103. By forming the pinning layer, the depletion region of the first well region 101 is further prevented from extending to the surface of the substrate 10, and the dark current caused by dangling bonds on the surface of the substrate 10 is reduced, thereby improving the electrical performance of the CMOS image sensor.

[0072] Please see Figures 1 to 3 As shown, in one embodiment of the present invention, the impurity ions in the charge storage region 13 are, for example, N-type impurities such as phosphorus or arsenic, and the depth of the charge storage region 13 in the substrate is, for example, 5% to 30% of the depth of the photodiode in the substrate 10. From Figure 1 As can be seen, the charge storage region 13 and the photodiode are of equal length, that is, the two ends of the charge storage region 13 and the photodiode are aligned. The charge storage region 13 and the photodiode are partially isolated by the shallow trench isolation structure 11 and partially isolated by the second isolation well region 104. The impurity ions in the floating diffusion region 14 are, for example, N-type impurities such as phosphorus or arsenic, and the depths of the floating diffusion region 14 and the doped region 17 in the substrate are, for example, equal.

[0073] Please see Figures 1 to 3As shown, in one embodiment of the present invention, at least a global exposure transfer gate 15, a transfer gate 16, and a charge overflow control gate 18 are disposed on the first surface, and the gates are, for example, polysilicon gates or metal gates. The global exposure transfer gate 15 is disposed between the photodiode 12 and the charge storage region 13, and covers a portion of the charge storage region 13. In this embodiment, a portion of the global exposure transfer gate 15 also covers a portion of the photodiode 12. The global exposure transfer gate 15 includes a planar gate and a vertical gate. The vertical gate is disposed within the substrate 10 and connected to a portion of the photodiode 12 to accelerate charge transfer and increase the transfer speed. The transfer gate 16 is disposed between the charge storage region 13 and the floating diffusion region 14, with both sides aligned with the edges of the charge storage region 13 and the floating diffusion region 14. A charge overflow control gate 18 is disposed on the side of the photodiode 12 away from the charge storage region 13, for example, on a corner of the photodiode 12. A charge overflow control transistor drain 19 is disposed on the side of the charge overflow control gate 18 away from the photodiode 12. The charge overflow control gate 18 guides invalid photogenerated charges to the charge overflow control transistor drain 19, and extracts them through the photogenerated charge transfer channel. A gate dielectric layer 110 is disposed on the substrate 10 and between the gate and the substrate 10. The gate dielectric layer 110 is, for example, silicon oxide or a high dielectric constant material.

[0074] Please see Figures 1 to 3As shown, in one embodiment of the present invention, a front dielectric layer 111 is formed on a plurality of gates and gate dielectric layers 110, and includes, for example, a sidewall dielectric layer 1111, a metal silicide barrier layer 1112, and a via etching stop layer 1113. The sidewall dielectric layer 1111 is disposed at least on both sides of the gate, and is, for example, silicon oxide, silicon nitride, or a mixture of silicon oxide and silicon nitride. The metal silicide barrier layer 1112 is disposed on the sidewall dielectric layer 1111 and the substrate 10. The metal silicide barrier layer 1112 is, for example, silicon oxide, and has a thickness of, for example, 20 nm to 50 nm, to protect the photodiode, transfer gate, and floating diffusion region during the formation of the metal silicide. A contact etch stop layer 1113 (CESL) is disposed on the metal silicide barrier layer 1112. The CESL 1113 is, for example, a silicon nitride layer, with a thickness of, for example, 40nm to 60nm. An interlayer dielectric layer 112 is formed on the front dielectric layer 111. A plurality of conductive plugs 113 are disposed within the interlayer dielectric layer 112 to penetrate the front dielectric layer 111 and connect to different regions on the gate or substrate 10. A metal wiring layer 114 is disposed on the interlayer dielectric layer 112, partially connecting to the conductive plugs 113 on the global exposure transfer gate 15 and the transfer gate 16. The number of metal wiring layers 114 is, for example, 3-5. In this embodiment, only one layer is shown as an example for clarity. In this application, the fabrication method used in the front-side fabrication process of the CMOS image sensor can be obtained by any commonly used fabrication method.

[0075] Please see Figures 2 to 5 As shown, in one embodiment of the present invention, Figure 4 for Figure 1 A cross-sectional view along the abc direction. Figure 5 for Figure 1 A cross-sectional view along the de direction. After completing the front-side fabrication process, the carrier wafer 200 is bonded onto the interlayer dielectric layer 112. The bonded substrate is then flipped, and the substrate 10 is thinned from the second surface. For example, thinning is stopped when the remaining substrate thickness is, for example, 2 μm to 3 μm, or, for example, when thinning is stopped at the first well region 101. Thinning is performed, for example, by methods such as Chemical Mechanical Polishing (CMP). After thinning from the second surface, the second surface of the substrate 10 is used as the fabrication target for the back-side fabrication process.

[0076] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, Figure 6 for Figure 1 A cross-sectional view along the abc direction. Figure 7 for Figure 1A cross-sectional view along the de direction. After thinning the substrate 10, the substrate 10 is etched to form a trench 120. Specifically, a patterned photoresist layer (not shown) is formed on the substrate 10. The patterned photoresist layer at least covers the second well region 102, exposing, for example, the charge storage region 13, the doped region 17, a portion of the floating diffusion region 14, and the region between the charge storage region 13 and the doped region 17, while simultaneously exposing the second isolation well region 104 on at least a portion of the shallow trench isolation structure 11 surrounding the charge storage region 13 and the doped region 17. Using the patterned photoresist layer as a mask, the exposed substrate 10 is quantitatively removed, for example, by using an etching method such as dry etching, wet etching, or a combination of dry and wet etching, with the shallow trench isolation structure 11 as an etch stop layer, to form the trench 120. In this embodiment, for example, dry etching is used to form the groove 120, and the etching gas is, for example, chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), hydrogen fluoride (HF), or oxygen (O2). After etching, ashing oxidation or wet etching is used to remove the patterned photoresist layer. In this embodiment, the groove 120 exposes, for example, the charge storage region 13, or a portion of the substrate 10 is also present on the charge storage region 13. By controlling the etching up to the shallow trench isolation structure 11, the etching rate is the same in different areas when forming the groove 120, which ensures that a groove 120 with a flat bottom surface is obtained, improving the performance of the device, while not causing damage to the charge storage region, thus ensuring the electrical performance of the device.

[0077] Please see Figure 2 , Figures 8 to 10 As shown, in one embodiment of the present invention, Figure 8 This is a schematic diagram of the first photoresist layer. Figure 9 for Figure 8 A cross-sectional view along the abc direction. Figure 10 for Figure 8A cross-sectional view along the de direction. After forming the groove 120, a first photoresist layer 121 is formed on the substrate 10. The first photoresist layer 121 is strip-shaped and covers a portion of the shallow trench isolation structure 11 between the transmission gate 16, part of the floating diffusion region 14, the doped region 17, and the active region where the charge storage region 13 and the reset transistor 20 are located, to protect the portion of the shallow trench isolation structure 11. Using the first photoresist layer 121 as a mask, a portion of the shallow trench isolation structure 11, the gate dielectric layer 110, and the metal silicide barrier layer 1112 are removed to form an air gap 123. In this embodiment, the insulating medium, such as silicon oxide, in the shallow trench isolation structure 11 is removed, for example, by dry etching, wet etching, or a combination of dry and wet etching. After removing the insulating medium in the shallow trench isolation structure 11, the via etching stop layer 1113 in the front dielectric layer 111 is used as an etching stop layer to form the air gap 123. In this embodiment, an air gap 123 is formed, for example, at least between the photodiode 12 and the charge storage region 13. By forming the air gap 123, total internal reflection can occur, reducing light entering the charge storage region 13 and avoiding parasitic photoresponse.

[0078] Please see Figures 9 to 12 As shown, in one embodiment of the present invention, Figure 11 for Figure 1 A cross-sectional view along the abc direction. Figure 12 for Figure 1 A cross-sectional view along the de direction. After forming the air gap 123, a dielectric layer 124 is formed on the bottom and sidewalls of the substrate 10 and the groove 120. The dielectric layer 124 is, for example, silicon oxide or a high dielectric constant layer, and the dielectric layer 124 is prepared by, for example, chemical vapor deposition (CVD), and the thickness of the dielectric layer 124 is, for example, 100 nm to 200 nm.

[0079] Please see Figures 11 to 14 As shown, in one embodiment of the present invention, Figure 13 for Figure 1 A cross-sectional view along the abc direction. Figure 14 for Figure 1A cross-sectional view along the de direction. After forming the dielectric layer 124, the dielectric layer 124 is etched to remove a portion of the dielectric layer 124 on the doped region 17, forming an opening 125. Specifically, a patterned photoresist layer (not shown) is formed on the dielectric layer 124, exposing a portion of the dielectric layer 124 on the doped region 17. Using the patterned photoresist layer as a mask, the exposed dielectric layer 124 is removed, for example, by using an etching method such as dry etching, wet etching, or a combination of dry and wet etching, with the doped region 17 as an etching stop layer, forming the opening 125. In this embodiment, for example, dry etching is used to form the opening 125, and the etching gas is, for example, carbon tetrafluoride (CF4), trifluoromethane, difluoromethane, hydrogen fluoride, or oxygen. After etching, ashing oxidation or wet etching is used to remove the patterned photoresist layer.

[0080] Please see Figures 13 to 17 As shown, in one embodiment of the present invention, Figure 15 This is a plan view of the resulting light-blocking structure. Figure 16 for Figure 15 A cross-sectional view along the abc direction. Figure 17 for Figure 15 A cross-sectional view along the de direction. After forming the opening 125, a light-shielding structure 126 is formed at the bottom of the groove 120 and within the opening 125. The thickness of the light-shielding structure 126 at the bottom of the groove 120 is, for example, 100 nm to 300 nm. The material of the light-shielding structure 126 is, for example, at least one of opaque metal materials such as tungsten, aluminum, copper, cobalt, titanium, titanium nitride, or nickel. The metal material is formed, for example, by plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), or physical vapor deposition. Specifically, after depositing metal material in the substrate, groove 120, and opening 125, the metal material on the substrate 10 is removed by etching, leaving only the metal material at the bottom of the groove 120 and in the opening 125, with the top of the metal material flush with the surface. The light-shielding structure 126 at least covers the charge storage region 13 and the doped region 17. In this application, the light-shielding structure 126 is formed inside the substrate 10 and covers the entire charge storage region 13, effectively preventing light from entering the charge storage region 13 and greatly improving the parasitic light response of the charge domain global image sensor.

[0081] Please see Figures 16 to 17As shown, in one embodiment of the present invention, the metal material deposited in the opening contacts the doped region 17. On the one hand, this can further reduce the influence of light on the charge storage region 13. On the other hand, the light-shielding structure 126, the dielectric layer 124, and the charge storage region 13 form a parasitic transistor. Subsequently, the readout timing of the image sensor is designed, and the voltage and waveform of the light-shielding structure 126 are specially set. The characteristics of the parasitic transistor are used to adjust the potential barrier of the charge storage region 13, which enhances the transmission capability of electrons from the charge storage region 13 to the floating diffusion region 14 and avoids the afterimage caused by insufficient electron transmission.

[0082] Please see Figures 16 to 19 As shown, in one embodiment of the present invention, Figure 18 for Figure 1 A cross-sectional view along the abc direction. Figure 19 for Figure 1 A cross-sectional view along the de direction. After forming the light-shielding structure 126, a dielectric layer 130 is formed on the light-shielding structure 126 and the dielectric layer 124. The dielectric layer 130 is made of materials such as silicon oxide, silicon fluoride, silicon carbide, or silicon oxyfluoride, and is formed, for example, by chemical vapor deposition. After forming the dielectric layer 130, a planarization process is performed to make the surface of the dielectric layer 130 smooth. A metal grid 131 is formed within the dielectric layer 130. The metal grid 131 exposes the photodiode, ensuring light intake efficiency and helping to improve optical crosstalk between different pixel units. The fabrication process also involves filtering and microlens processes, which will not be elaborated here.

[0083] Please see Figures 20 to 22As shown, in one embodiment of the present invention, the circuit timing of the image sensor is set to obtain the potential diagram of the image sensor during operation. In this embodiment, the charge overflow control gate (AB) is first fully opened to clear the charge in all photodiodes (PDs), and then the photodiodes are subjected to global exposure. During the global exposure process, the transfer gate (TX) is opened to reset and clear the charge storage region (MN) and the floating diffusion region (FD). At the end of the global exposure, the global exposure transfer gate (GTX) is opened to transfer all the charge to the charge storage region, and the exposure ends. During readout, the row select transistor (RS) and reset transistor (RST) are turned on sequentially to reset and clear the floating diffuser region (FD). Then, the transfer gates (TX) are turned on sequentially row by row to transfer the charge signal from the charge storage region (MN) to the floating diffuser region (FD). At the end of the transfer, a negative voltage is applied to the light-shielding structure (LSM). That is, when the transfer gate (TX) is turned on, the light-shielding structure (LSM) is turned on by applying a negative voltage. The turn-on time of the transfer gate (TX) is earlier than the turn-on time of the light-shielding structure (LSM), and the turn-off time of the transfer gate (TX) is earlier than the turn-off time of the light-shielding structure (LSM). By applying a negative voltage to the light-shielding structure (LSM) and utilizing the characteristics of parasitic transistors, all electrons in the charge storage region (MN) are transferred to the floating diffuser region (FD).

[0084] Please see Figures 20 to 22 As shown, in one embodiment of the present invention, Figure 21 This is a schematic diagram of the operation of the transmission gate and the light-shielding structure. Figure 22 Part (a) indicates that when only the transfer gate (TX) is turned on, electrons are transferred from the charge storage region (MN) to the floating diffusion region (FD). The potential difference between the charge storage region (MN) and the floating diffusion region (FD) is insufficient, which may cause transfer lag due to insufficient electron transfer. Therefore, if the transfer gate is turned off directly, charge may flow back from the channel to the charge storage region, causing charge backflow. Figure 22 Part (b) indicates that during the process of opening the transfer gate (TX), the light-shielding structure (LSM) is then opened, the potential of the charge storage region (MN) becomes negative, all electrons are transferred to the floating diffusion region (FD), and the charge is fully transferred. Figure 22 Part (c) indicates that when the transfer gate (TX) is switched from on to off, the light-shielding structure (LSM) remains on, the potential of the charge storage region (MN) remains negative, no electrons flow back to the floating diffusion region (FD), and no charge flows back. Figure 22Part (d) indicates that after the transfer gate (TX) is turned off, the light-shielding structure (LSM) is then turned off, completing the electron transfer without charge backflow. This application, based on the readout timing of the image sensor, specifically sets the voltage and waveform of the light-shielding structure, utilizing the characteristics of parasitic transistors to adjust the potential barrier of the charge storage region. This enhances the electron transfer capability from the charge storage region to the floating diffusion region, avoiding image retention caused by insufficient electron transfer and improving the imaging quality of the image sensor.

[0085] In summary, this invention provides an image sensor and its fabrication method. By improving the structure and fabrication method of the image sensor, it effectively prevents light from entering the charge storage region, greatly improving the parasitic light response of the global charge domain image sensor. By forming a parasitic transistor through a light-shielding structure, a dielectric layer, and a charge storage region, and designing the readout timing of the image sensor, and by specifically setting the voltage and waveform of the light-shielding structure, the potential barrier of the charge storage region is adjusted using the characteristics of the parasitic transistor. This enhances the electron transport capability from the charge storage region to the floating diffusion region, avoiding image retention caused by insufficient electron transport. It can be widely applied in various types of back-illuminated CMOS image sensors. It improves the isolation effect between photodiodes, reduces mutual interference between photodiodes, reduces dark current in the device, and improves the electrical performance of the CMOS image sensor. It ensures light intake efficiency and also helps to improve optical crosstalk between different pixel units.

[0086] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. An image sensor, characterized in that: At least: A substrate comprising a first surface and a second surface disposed opposite to each other; The photodiode, the charge storage region and the floating diffusion region extend from the first surface into the substrate and are arranged in intervals in the substrate; a doped region extending from the first surface into the substrate, wherein the doped region is disposed in a region between the photodiode, the charge storage region and the floating diffusion region and is disposed at intervals; A global exposure transfer gate, located on the first surface, disposed between the photodiode and the charge storage area, and covering a portion of the charge storage area; A transfer gate, located on the first surface and disposed between the charge storage region and the floating diffusion region; as well as a light shielding structure, arranged in the substrate and covering the charge storage region, the light shielding structure being electrically connected to the doped region, a dielectric layer being arranged between the light shielding structure and the charge storage region, a portion of the light shielding structure penetrating the dielectric layer and extending to the surface of the doped region, the light shielding structure, the dielectric layer and the charge storage region forming a parasitic transistor; Among them, in the circuit timing of the image sensor, when the transmission gate is turned on, the shading structure is turned on by applying negative pressure, the opening time of the transmission gate is earlier than the opening time of the shading structure, and the closing time of the transmission gate is earlier than the closing time of the shading structure.

2. The image sensor according to claim 1, characterized in that An air gap is arranged between the photodiode and the charge storage area, and the light shielding structure covers the air gap.

3. The image sensor according to claim 1, characterized in that The depth of the charge storage region in the substrate is 5% to 30% of the depth of the photodiode in the substrate.

4. The image sensor according to claim 1, characterized in that The thickness of the light-shielding structure is 100 nm to 300 nm, and the material of the light-shielding structure includes at least one of tungsten, aluminum, copper, cobalt, titanium, titanium nitride or nickel.

5. The image sensor according to claim 1, characterized in that The global exposure transmission gate includes a planar gate and a vertical gate. The vertical gate is arranged in the substrate and connected to a part of the photodiode.

6. The image sensor according to claim 1, characterized in that: The image sensor comprises a dielectric layer, the dielectric layer covers the second surface, a metal grid is arranged in the dielectric layer, and the metal grid exposes the photodiode.

7. A method for manufacturing an image sensor, characterized in that: At least the following steps are included: Providing a substrate, the substrate comprising a first surface and a second surface arranged opposite to each other; forming a photodiode, a charge storage region and a floating diffusion region spaced apart from each other from the first surface into the substrate; forming a doped region from the first surface into the substrate, wherein the doped region is disposed in a region between the photodiode, the charge storage region and the floating diffusion region and is disposed at intervals; A global exposure transmission gate is formed by the first surface, wherein the global exposure transmission gate is disposed between the photodiode and the charge storage region and covers a portion of the charge storage region; A transfer gate is formed by the first surface, and the transfer gate is arranged between the charge storage region and the floating diffusion region; as well as A light shielding structure is formed in the substrate, the light shielding structure covers the charge storage region, the light shielding structure is electrically connected to the doped region, a dielectric layer is formed between the light shielding structure and the charge storage region, a portion of the light shielding structure penetrates the dielectric layer and extends to the surface of the doped region, and the light shielding structure, the dielectric layer and the charge storage region form a parasitic transistor; Among them, in the circuit timing of the image sensor, when the transmission gate is turned on, the shading structure is turned on by applying negative pressure, the opening time of the transmission gate is earlier than the opening time of the shading structure, and the closing time of the transmission gate is earlier than the closing time of the shading structure.

8. The method for manufacturing an image sensor according to claim 7, characterized in that: The production method further comprises: The substrate includes a plurality of shallow trench isolation structures, which are at least arranged between the photodiode and the charge storage region, around the doped region, and on a side of the floating diffusion region away from the charge storage region; After forming the gate, forming an interlayer dielectric layer and a metal wiring layer on the first surface; Bonding a carrier wafer on the first surface, flipping the substrate, and thinning the substrate from the second surface to 2 μm to 3 μm; Etching the substrate from the second surface until the shallow trench isolation structure is reached to form a groove, wherein the groove exposes the doped region, the charge storage region, and a region between the doped region and the charge storage region; and The shallow trench isolation structure between the photodiode and the charge storage region is removed to form an air gap.

9. The method for manufacturing an image sensor according to claim 8, characterized in that: The production method further comprises: After forming the air gap, forming a dielectric layer on the second surface and the bottom and sidewalls of the groove; Etching and removing a portion of the dielectric layer on the doped region to form an opening; and A light shielding structure is formed in the opening and on the dielectric layer at the bottom of the groove.

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