High-Speed ​​Two-Step Time Domain ADC

Abstract

The present invention is applicable to the field of analog-to-digital conversion and provides a high-speed two-step time-domain analog-to-digital converter, comprising: a common-mode voltage conversion unit for converting a differential voltage signal into first and second time pulse signals; a conversion and selection unit for sequentially delaying and encoding the first and second time pulse signals to obtain a first code, and selecting and outputting a first signal and a second signal from the first and second time pulse signals and the multiple delayed pulse signals obtained by the delay processing; a one-step multi-bit successive approximation analog-to-digital conversion unit for continuously quantizing and encoding the first and second signals, outputting a second code, and extending or shortening the transmission time of the first and / or second signals based on the second code; and a quantization coding unit for obtaining a target quantization code using the first and second codes. The solution provided by the present invention can effectively shorten quantization time, improve quantization efficiency, and improve quantization accuracy.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a high-speed two-step time-domain analog-to-digital converter. Background Art

[0002] With the development of large-scale integrated circuits and the continued reduction of process dimensions, Internet of Things (IoT) technology has flourished, driving the rapid development of numerous application scenarios, including wearable devices and smart homes. In these scenarios, electronic devices must maintain normal functionality while maintaining high energy efficiency to extend their lifecycle. However, the large number of wireless sensors used to acquire analog signals results in excessive power consumption across the entire system. The Successive Approximation Analog-to-Digital Converter (SA ADC), with its highly digital circuitry and excellent digital compatibility, stands out among numerous ADC architectures and has become a research hotspot in recent years.

[0003] Currently used time-domain ADCs are often hybrid voltage-time ADCs. Compared to pure time-domain ADCs, these require an additional amplifier stage, resulting in increased power consumption, poor linearity, and reduced accuracy. In particular, the successive approximation time-to-digital converter (SA TDC) in a hybrid voltage-time SA ADC requires twice as many delay elements as a successive approximation register time-to-digital converter (SAR TDC) based on selective delay adjustment elements. Furthermore, the large number of delay elements and their presence of subtle errors lead to significant delay offset, lengthening decision times and resulting in a long SA TDC quantization cycle. In other words, SA TDCs suffer from low quantization efficiency and poor accuracy. Summary of the Invention

[0004] To solve the above problems, the present invention provides a high-speed two-step time-domain analog-to-digital converter. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] The high-speed two-step time-domain analog-to-digital converter provided by the present invention includes: a common-mode voltage conversion unit for converting an input differential voltage signal into a first time pulse signal and a second time pulse signal having a time difference; a conversion and selection unit for sequentially performing delay processing and encoding processing on the first time pulse signal and the second time pulse signal to obtain multiple first codes, and selecting and outputting a first signal and a second signal from the first time pulse signal, the second time pulse signal, and the multiple delayed pulse signals obtained by the delay processing; wherein the first signal refers to the signal closest to the first time pulse signal among the multiple delayed pulse signals and the second time pulse signal, and the second signal refers to the signal closest to the second time pulse signal among the multiple delayed pulse signals and the first time pulse signal; a one-step multi-bit successive approximation analog-to-digital conversion unit for continuously quantizing and encoding the input first signal and the second signal, outputting multiple second codes, and extending or shortening the transmission time of the first signal and / or the second signal by generating pull-up or pull-down current according to the multiple second codes; and a quantization encoding unit for unifying the formats of the multiple first codes and the multiple second codes and combining them to obtain a target quantization code.

[0006] The present invention has the following beneficial technical effects: In response to the problems of low quantization efficiency and low precision in the existing SA TDC, the present invention proposes a high-speed two-step time domain analog-to-digital converter, which uses a common-mode voltage conversion unit to losslessly convert the differential voltage into a first time pulse signal and a second time pulse signal, and uses these two signals to be quantized in a conversion selection unit to generate multiple first codes, and inputs the first signal and the second signal output by the conversion selection unit into a one-step multi-bit successive approximation analog-to-digital conversion unit for continuous quantization coding to generate multiple second codes, and the second code is used to control the one-step multi-bit successive approximation analog-to-digital conversion unit to perform delay processing of different lengths on the first signal and the second signal. After unifying the formats of the first code and the second code and combining them for output, the quantization conversion of the analog voltage signal to the digital signal is completed. The high-speed two-step time-domain analog-to-digital converter proposed in the present invention can accurately simulate the effect of different delay units, thereby eliminating the need to add multiple delay units with certain delay duration values; at the same time, the reduction in the number of delay units means that the overall circuit structure layout complexity is reduced, further reducing circuit power consumption and area costs; and since the number of delay units is reduced, the error introduced by the increase in the number of delay units is also reduced, thereby reducing delay offset; finally, a one-step multi-bit successive approximation analog-to-digital conversion unit is used to continuously quantize and encode the first signal and the second signal, which can effectively shorten the quantization time and improve the quantization efficiency and quantization accuracy of the high-speed two-step time-domain analog-to-digital converter.

[0007] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 1 is a structural block diagram of a high-speed two-step time-domain analog-to-digital converter provided by an embodiment of the present invention;

[0009] Figure 2 1 is a circuit structure diagram of a common-mode voltage conversion unit and an example diagram of pulse signal changes thereof provided by an embodiment of the present invention;

[0010] Figure 3 1 is a schematic diagram of the circuit structure of the i-th one-step two-bit encoding unit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0012] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0013] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0014] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0015] Now combined Figure 1The high-speed two-step time-domain analog-to-digital converter proposed in the present invention is described in detail. Figure 1 : is a structural block diagram of a high-speed two-step time domain analog-to-digital converter provided by an embodiment of the present invention. Figure 1 As shown, the high-speed two-step time domain analog-to-digital converter proposed in the present invention includes: a common-mode voltage conversion unit, which is used to convert the input differential voltage signal into a first time pulse signal and a second time pulse signal with a time difference; a conversion and selection unit, which is used to sequentially delay and encode the first time pulse signal and the second time pulse signal to obtain multiple first codes, and select and output the first signal and the second signal from the first time pulse signal, the second time pulse signal and the multiple delayed pulse signals obtained by the delay processing; wherein the first signal refers to the signal closest to the first time pulse signal among the multiple delayed pulse signals and the second time pulse signal, and the second signal refers to the signal closest to the second time pulse signal among the multiple delayed pulse signals and the first time pulse signal; a one-step multi-bit successive approximation analog-to-digital conversion unit, which is used to continuously quantize and encode the input first signal and the second signal, output multiple second codes, and extend or shorten the transmission time of the first signal and / or the second signal by generating pull-up or pull-down current according to the multiple second codes; a quantization encoding unit, which is used to unify the formats of the multiple first codes and the multiple second codes and combine them to obtain a target quantization code.

[0016] here, Figure 2 1 is a circuit structure of a common mode voltage conversion unit and an example diagram of its pulse signal change according to an embodiment of the present invention. Figure 2 As shown in the left figure, the differential voltage signal includes: a first pulse signal IN1 and a second pulse signal IN2 with the same amplitude and opposite phase; the common mode voltage conversion unit includes: three switches CK T , switch CK D , two sampling capacitors C S , common mode capacitance C cm , the fourth time domain comparator, the fifth time domain comparator; wherein, the first CK T One end is connected to IN1, the first CK T The other end of the first C S Electrical connection, first C S The other end of the first CK is grounded. T The other end is also connected to the positive input end of the fourth time domain comparator, the negative input end of the fourth time domain comparator is connected to the reference voltage, the output end of the fourth time domain comparator is connected to the first input end of the conversion selection unit, and the output end of the fourth time domain comparator is used to output the first time pulse signal; the second CK T One end is connected to input IN2, the second CK T The other end of the second CS Electrical connection, second C S The other end of the second CK is grounded. T The other end is also connected to the positive input end of the fifth time domain comparator, the negative input end of the fifth time domain comparator is connected to the reference voltage, the output end of the fifth time domain comparator is connected to the second input end of the conversion selection unit, and the output end of the fifth time domain comparator is used to output the second time pulse signal; the positive input end of the fourth time domain comparator and the positive input end of the fifth time domain comparator are also connected to CK D One end of the connection, CK D The other end is connected to the current source, CK D One end is also connected to C cm One end and the third CK T One end of the connection, C cm The other end and the second CK T The other end is grounded.

[0017] like Figure 2 As shown in the right figure, during the sampling phase, CK T At high level, switch CK T Closed; CK D At low level, switch CK D Disconnect; at this time, the common mode capacitor C cm The charge on the capacitor is discharged to the ground, and the first pulse signal IN1 is stored in the first sampling capacitor C S The second pulse signal IN2 is stored in the second sampling capacitor C S In the maintenance phase, CK T At low level, switch CK T Disconnect; CK D At high level, switch CK D Closed; at this time, the current source to the common mode capacitor C cm The charge is stored in the first sampling capacitor C S and the second sampling capacitor C S IN1 and IN2 are pushed up to two slopes without mismatch. When the voltages of IN1 and IN2 exceed the reference voltage, IN1 is converted into a first time pulse signal, and IN2 is converted into a second time pulse signal, thus converting the differential voltage signal into a time pulse signal. TH Refers to the threshold voltage, C cm The voltage is symbolized by X CM Indicates that the voltage of IN1 is represented by the symbol X P Indicates that the voltage of IN2 is represented by the symbol X N Indicates that the first time pulse signal uses the symbol T P Indicates that the second time pulse signal uses the symbol T NThe time difference between the first time pulse signal and the second time pulse signal is represented by the symbol ΔT. Figure 2 As shown, the process of increasing the voltages of IN1 and IN2 is essentially lossless, and the voltage difference between the two is constant, thereby maintaining a constant time difference between the first and second time pulse signals. Using a common-mode voltage conversion unit can effectively reduce errors in converting voltage signals to time signals, improving conversion accuracy.

[0018] It should be noted that the present invention is not limited to using a common-mode voltage conversion unit to obtain the first pulse signal and the second pulse signal, and a variable slope voltage-time converter or a constant slope voltage-time converter can also be used to convert the differential voltage signal into the first pulse signal and the second pulse signal.

[0019] Here, the conversion selection unit includes a flash time-to-digital converter (Flash TDC) unit and a time residue generator (TRG) unit. The Flash TDC unit is the first stage of a high-speed, two-step time-domain analog-to-digital converter. The first and second time pulse signals pass through the Flash TDC unit and the TRG unit in sequence.

[0020] As an example, a Flash TDC unit with three delay units is used. It should be understood that the present invention does not limit the number of delay units in the Flash TDC unit. The Flash TDC unit operates as follows: three groups of delay units are used to delay the first and second time pulse signals, generating six groups of delayed pulse signals. These six groups of delayed pulse signals are then cross-compared, along with the first and second time pulse signals, to generate a 7-bit thermometer code (i.e., the first code). This 7-bit thermometer code is then transmitted to the quantization coding unit for further processing. The Flash TDC unit enables preliminary quantization of the first and second time pulse signals.

[0021] Next, based on the fact that the number of delay units in the Flash TDC unit is three, the operating principle of the TRG unit will be explained. Specifically, the TRG unit receives six delayed pulse signals, a first time pulse signal, and a second time pulse signal. It selects the signal closest to the first time pulse signal from the six delayed pulse signals and the second time pulse signal as the first signal, and selects the signal closest to the second time pulse signal from the six delayed pulse signals and the first time pulse signal as the second signal. These first and second signals are then transmitted to a one-step multi-bit successive approximation analog-to-digital conversion unit for further processing. The TRG unit also displays the residual value between the quantized first signal and the first time pulse signal, as well as the residual value between the quantized second signal and the second time pulse signal.

[0022] Here, the one-step multi-bit successive approximation analog-to-digital conversion unit is the second stage of the high-speed two-step time domain analog-to-digital converter. The one-step multi-bit successive approximation analog-to-digital conversion unit includes: at least one one-step two-bit encoding unit; each one-step two-bit encoding unit includes: a first delay unit, a second delay unit, a first buffer inverting unit, a second buffer inverting unit, a time domain comparison unit, a first combination logic unit, a second combination logic unit, a first current control unit, and a second current control unit; wherein the input end of the first delay unit, the input end of the first buffer inverting unit, the third input end and the fifth input end of the time domain comparison unit are all connected to the first signal; the output end of the first delay unit is connected to the first input end of the time domain comparison unit; the output end of the first buffer inverting unit is connected to the first input end of the next one-step two-bit unit or is left floating; the first output end, the third output end and the fifth output end of the time domain comparison unit are connected to the input end of the first combination logic unit; the output end of the first combination logic unit is connected to the first input end of the second current control unit, and the third output end of the time domain comparison unit is also connected to The first input end of the first current control unit and the first input end of the quantization coding unit, the output end of the first combination logic unit is also connected to the second input end of the quantization coding unit; the input end of the second delay unit, the input end of the second buffer inverting unit, the second input end and the fourth input end of the time domain comparison unit are all connected to the second signal; the output end of the second delay unit is connected to the sixth input end of the time domain comparison unit; the output end of the second buffer inverting unit is connected to the second input end of the next one-step two-bit unit or is left floating; the fourth output end of the time domain comparison unit is connected to the second input end of the first current control unit, and the fourth output end of the time domain comparison unit is also connected to the input end of the second combination logic unit together with the second output end and the sixth output end of the time domain comparison unit; the output end of the second combination logic unit is connected to the second input end of the second current control unit; the first output end of the first current control unit and the first output end of the second current control unit are both connected to the IN in the first buffer inverting unit. PThe second output terminal of the first current control unit and the second output terminal of the second current control unit are both connected to the MID in the first buffer inverting unit. P Node connection; MID P The node is used to generate a pull-up or pull-down current to extend or shorten the transmission time of the first signal; the third output terminal of the first current control unit and the third output terminal of the second current control unit are both connected to the IN in the second buffer inverting unit. N The fourth output terminal of the first current control unit and the fourth output terminal of the second current control unit are both connected to the MID in the second buffer inverting unit. N Node connection; MID N The node is used to generate a pull-up or pull-down current to extend or shorten the transmission time of the second signal.

[0023] Here, the first buffer inverting unit includes: a first buffer, a first inverter and a second inverter; the first buffer, the first inverter and the second inverter are connected in sequence, the input end of the first buffer is connected to the first signal, the output end of the second inverter is connected to the first input end of the next one-step two-bit unit or is left floating; and the output end of the first buffer is IN P Node, the output of the first inverter is MID P node.

[0024] Here, the second buffer inverting unit includes: a second buffer, a third inverter and a fourth inverter; the second buffer, the third inverter and the fourth inverter are connected in sequence, the input end of the second buffer is connected to the second signal, the output end of the fourth inverter is connected to the second input end of the next one-step two-bit unit or is left floating; and the output end of the second buffer is IN N Node, the output of the third inverter is MID N node.

[0025] It should be noted that when the one-step multi-bit successive approximation analog-to-digital conversion unit includes only one one-step two-bit encoding unit, the output end of the second inverter and the output end of the fourth inverter are left floating; when the one-step multi-bit successive approximation analog-to-digital conversion unit includes N one-step two-bit encoding units, the output end of the second inverter in the i-th one-step two-bit encoding unit is connected to the input end of the first buffer inverting unit in the i+1-th one-step two-bit encoding unit, and the output end of the fourth inverter in the i-th one-step two-bit encoding unit is connected to the input end of the second buffer inverting unit in the i+1-th one-step two-bit encoding unit; the output end of the second inverter and the output end of the fourth inverter in the N-th one-step two-bit encoding unit are left floating; wherein, the value of i is 1 to N-1.

[0026] Here, the first delay unit and the second delay unit are both 1 / 2REF delay units. And the output terminal of the second inverter is OUT P Node, the output of the fourth inverter is OUT N node.

[0027] It should be noted that since it takes a certain amount of time for the time domain comparison unit to provide a comparison result, the first buffer and the second buffer are used to delay the comparison result. In addition, each inverter is used to invert the phase of the input signal by 180 degrees.

[0028] Here, the time domain comparison unit includes: a first time domain comparator, a second time domain comparator and a third time domain comparator; the positive input end of the first time domain comparator is connected to the output end of the first delay unit, and the positive input end of the second time domain comparator and the positive input end of the third time domain comparator are both connected to the first signal; the negative input end of the first time domain comparator and the negative input end of the second time domain comparator are both connected to the second signal, and the negative input end of the third time domain comparator is connected to the output end of the second delay unit; the positive output end of the first time domain comparator, the positive output end of the second time domain comparator and the positive output end of the third time domain comparator are all connected to the input end of the first combination logic unit; the negative output end of the first time domain comparator, the negative output end of the second time domain comparator and the negative output end of the third time domain comparator are all connected to the input end of the second combination logic unit; the positive output end of the second time domain comparator is also connected to the first input end of the first current control unit and the first input end of the quantization coding unit respectively, and the negative output end of the second time domain comparator is also connected to the second input end of the first current control unit.

[0029] It should be noted that multiple one-step, two-bit encoding units are connected in series, and each one-step, two-bit encoding unit can generate two second codes. Specifically, the positive output of the second comparator and the output of the first combinational logic unit each generate a second code, and the second code is in binary format. The greater the number of one-step, two-bit encoding units connected in series, the greater the number of codes received by the quantization encoding unit. For example, when a one-step, multi-bit, successive approximation analog-to-digital conversion unit includes three one-step, two-bit encoding units, the number of second codes generated by the one-step, multi-bit, successive approximation analog-to-digital conversion unit is six.

[0030] Figure 3 : is a schematic diagram of the circuit structure of the i-th one-step two-bit encoding unit provided by an embodiment of the present invention. Figure 3 As shown, the first signal received by the i-th one-step two-bit encoding unit is represented by T P , and the second signal received is denoted as T N The first signal received by the i+1th one-step two-bit encoding unit is represented as T P<i+1> , and the second signal received is denoted as T N<i+1> The units included in the i-th one-step two-bit encoding unit are the same as the units included in the i+1-th one-step two-bit encoding unit. Among them, in the i-th one-step two-bit encoding unit, the first current control unit includes: PMOS transistors MP1, PMOS transistors MP2, PMOS transistors MP3 and PMOS transistors MP4, NMOS transistors MN1, NMOS transistors MN2, NMOS transistors MN3 and NMOS transistors MN4; the source of MP1 is connected to the power supply V DD The gate of MP1 and the gate of MN2 are both connected to the third output terminal of the time domain comparison unit, and the gate of MP2 and the gate of MN1 are both connected to IN P Node connection, the drain of MP2 and the source of MN1 are connected to MID P Node connection, the drain of MP1 is connected to the source of MP2, the drain of MN1 is connected to the source of MN2, the drain of MN2 is grounded; the source of MP3 is connected to V DD The gate of MP3 and the gate of MN4 are both connected to the fourth output terminal of the time domain comparison unit, and the gate of MP4 and the gate of MN3 are both connected to IN N Node connection, the drain of MP4 and the source of MN3 are connected to MID N The nodes are connected, the drain of MP3 is connected to the source of MP4, the drain of MN3 is connected to the source of MN4, and the drain of MN4 is grounded.

[0031] like Figure 3 As shown, the second current control unit includes: PMOS transistors MP5, MP6, MP7 and MP8, NMOS transistors MN5, MN6, MN7 and MN8; wherein the source of MP5 is connected to the power supply V DD The gate of MP5 and the gate of MN6 are both connected to the output terminal of the first combinational logic unit, and the gate of MP6 and the gate of MN5 are both connected to IN P Node connection, the drain of MP6 and the source of MN5 are connected to MID P Node connection, the drain of MP5 is connected to the source of MP6, the drain of MN5 is connected to the source of MN6, the drain of MN6 is grounded; the source of MP7 is connected to V DD The gate of MP7 and the gate of MN8 are connected to the output terminal of the second combinational logic unit, and the gate of MP8 and the gate of MN7 are connected to IN N Node connection, the drain of MP8 and the source of MN7 are connected to MID N The nodes are connected, the drain of MP7 is connected to the source of MP8, the drain of MN7 is connected to the source of MN8, and the drain of MN8 is grounded.

[0032] Here, the values ​​outputted by the third output terminal of the time domain comparison unit and the fourth output terminal of the time domain comparison unit are opposite; when the value outputted by the third output terminal of the time domain comparison unit is greater than the value outputted by the fourth output terminal of the time domain comparison unit, MN1 and MN2 are turned on, and MP1 and MP2 are turned off, so as to P A pull-down current is generated at the node; at the same time, MN3 and MN4 are turned off, and MP3 and MP4 are turned on to N A pull-up current is generated at the node; when the value output by the third output terminal of the time domain comparison unit is less than the value output by the fourth output terminal of the time domain comparison unit, MN1 and MN2 are turned off, MP1 and MP2 are turned on, so that P At the same time, MN3 and MN4 are turned on, and MP3 and MP4 are turned off, so that the MID N A pull-down current is generated at the node.

[0033] Here, the value outputted by the output terminal of the first combination logic unit is opposite to the value outputted by the output terminal of the second combination logic unit; when the value outputted by the output terminal of the first combination logic unit is greater than the value outputted by the output terminal of the second combination logic unit, MN5 and MN6 are turned on, and MP5 and MP6 are turned off, so as to P At the same time, MN7 and MN8 are turned off, and MP7 and MP8 are turned on to generate a pull-down current at the MID node. N A pull-up current is generated at the node; when the value outputted by the output terminal of the first combination logic unit is less than the value outputted by the output terminal of the second combination logic unit, MN5 and MN6 are turned off, and MP5 and MP6 are turned on to P At the same time, MN7 and MN8 are turned on, and MP7 and MP8 are turned off, so that the MID N A pull-down current is generated at the node.

[0034] For example, the positive output terminal of the second time domain comparator (denoted by symbol B The output value or the negative output terminal of the second time domain comparator (denoted by the symbol NB The output value can be 0 or 1. For example, when B When the output value is 0, NB The output value must be 1.

[0035] When B When it is 1, the first current control unit controls MID P Node is controlled, specifically, MN1 and MN2 are turned on, MP1 and MP2 are turned off, and MID P The node generates a pull-down current; at the same time, MN3 and MN4 are turned off, MP3 and MP4 are turned on, and the MID N The node generates a pull-up current.

[0036] When B When it is 0, the first current control unit controls MID N Node is controlled, specifically, MN1 and MN2 are turned off, MP1 and MP2 are turned on, and P The node generates a pull-up current; at the same time, MN3 and MN4 are turned on, MP3 and MP4 are turned off, and MID N The node generates a pull-down current.

[0037] And, the positive output terminal of the second time domain comparator (denoted by symbol B<i+1> The output value or the negative output terminal of the second time domain comparator (denoted by the symbol NB<i+1> The output value can be 0 or 1. For example, when B<i+1> When the output value is 0, NB<i+1> The output value must be 1.

[0038] When B<i+1> When it is 1, the second current control unit controls MID P Node is controlled, specifically, MN5 and MN6 are turned on, MP5 and MP6 are turned off, and MID P The node generates a pull-down current; at the same time, MN7 and MN8 are turned off, MP7 and MP8 are turned on, and the MID N The node generates a pull-up current.

[0039] When B<i+1> When it is 0, the second current control unit controls MID N Node is controlled, specifically, MN5 and MN6 are turned off, MP5 and MP6 are turned on, and MID P The node generates a pull-up current; at the same time, MN7 and MN8 are turned on, MP7 and MP8 are turned off, and the MID N The node generates a pull-down current.

[0040] When B The value of B is 1 and<i+1> When the value is 1, the rising edge time of the first signal arrives earlier than the rising edge time of the second signal, and the time difference is greater than 1 / 2T REF (Here, T REF is a reference time unit), the first current control unit and the second current control unit are in MID N The node generates a pull-down current, which makes the rising edge of the second signal fall faster, so that the first signal is transmitted to OUT P The rising edge time of the node is the same as the second signal transmitted to OUT N The rising edge time of the node changes, which is reflected externally as the transmission time difference between the original two signals is △T REF , the transmission time difference between the two signals is △T REF -3 / 4T REF Similarly, when B The value of B is 1 and<i+1> When the value is 0, the transmission time difference between the two signals is △T REF -1 / 4T REF When B The value of B is 0 and<i+1> When the value is 1, the transmission time difference between the two signals is △T REF +1 / 4T REF When B The value of B is 0 and<i+1> When the value is 0, the transmission time difference between the two signals is △T REF +3 / 4T REF .

[0041] In response to the problems of low quantization efficiency and low precision in the existing SA TDC, the present invention proposes a high-speed two-step time domain analog-to-digital converter, which uses a common-mode voltage conversion unit to losslessly convert the differential voltage into a first time pulse signal and a second time pulse signal, and uses these two signals to be quantized in a conversion selection unit to generate multiple first codes. The first signal and the second signal output by the conversion selection unit are input into a one-step multi-bit successive approximation analog-to-digital conversion unit for continuous quantization coding to generate multiple second codes. The second code is used to control the one-step multi-bit successive approximation analog-to-digital conversion unit to perform delay processing of different lengths on the first signal and the second signal. After unifying the formats of the first code and the second code and combining them for output, the quantization conversion of the analog voltage signal to the digital signal is completed. The high-speed two-step time-domain analog-to-digital converter proposed in the present invention can accurately simulate the effect of different delay units, thereby eliminating the need to add multiple delay units with certain delay duration values; at the same time, the reduction in the number of delay units means that the overall circuit structure layout complexity is reduced, further reducing circuit power consumption and area costs; and since the number of delay units is reduced, the error introduced by the increase in the number of delay units is also reduced, thereby reducing delay offset; finally, a one-step multi-bit successive approximation analog-to-digital conversion unit is used to continuously quantize and encode the first signal and the second signal, which can effectively shorten the quantization time and improve the quantization efficiency and quantization accuracy of the high-speed two-step time-domain analog-to-digital converter.

[0042] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A high-speed two-step time-domain analog-to-digital converter, characterized in that: include: A common-mode voltage conversion unit is used to convert an input differential voltage signal into a first time pulse signal and a second time pulse signal with a time difference; wherein the differential voltage signal includes: a first pulse signal IN1 and a second pulse signal IN2 with the same amplitude and opposite phases; the common-mode voltage conversion unit includes: three switches CK T , switch CK D , two sampling capacitors C S , common mode capacitance C cm , a fourth time domain comparator, a fifth time domain comparator; wherein the current source is connected to the common mode capacitor C cm The charge is stored in the first sampling capacitor C S and the second sampling capacitor C S IN1 and IN2 are respectively pushed up to two slopes without mismatch, and when the voltages of IN1 and IN2 exceed the reference voltage, IN1 is converted into the first time pulse signal, and IN2 is converted into the second time pulse signal, thereby converting the differential voltage signal into a time pulse signal; a conversion and selection unit, configured to sequentially perform delay processing and encoding processing on the first time pulse signal and the second time pulse signal to obtain a plurality of first codes, and select and output a first signal and a second signal from the first time pulse signal, the second time pulse signal, and the plurality of delayed pulse signals obtained by the delay processing; wherein the first signal refers to the signal closest to the first time pulse signal among the plurality of delayed pulse signals and the second time pulse signal, and the second signal refers to the signal closest to the second time pulse signal among the plurality of delayed pulse signals and the first time pulse signal; a one-step multi-bit successive approximation analog-to-digital conversion unit, configured to continuously quantize and encode the first and second input signals, output a plurality of second codes, and extend or shorten the transmission time of the first and / or second signals by generating a pull-up or pull-down current according to the plurality of second codes; The quantization coding unit is used to unify the formats of the multiple first codes and the multiple second codes and then combine them to obtain a target quantization code.

2. The high-speed two-step time domain analog-to-digital converter according to claim 1, wherein: The one-step multi-bit successive approximation analog-to-digital conversion unit includes: at least one one-step two-bit encoding unit; each one-step two-bit encoding unit includes: a first delay unit, a second delay unit, a first buffer inverting unit, a second buffer inverting unit, a time domain comparison unit, a first combination logic unit, a second combination logic unit, a first current control unit and a second current control unit; wherein, The input end of the first delay unit, the input end of the first buffer inverting unit, and the third input end and the fifth input end of the time domain comparison unit are all connected to the first signal; the output end of the first delay unit is connected to the first input end of the time domain comparison unit; the output end of the first buffer inverting unit is connected to the first input end of the next one-step two-bit unit or is left floating; the first output end, the third output end, and the fifth output end of the time domain comparison unit are connected to the input end of the first combinational logic unit; the output end of the first combinational logic unit is connected to the first input end of the second current control unit, the third output end of the time domain comparison unit is further connected to the first input end of the first current control unit and the first input end of the quantization coding unit, and the output end of the first combinational logic unit is further connected to the second input end of the quantization coding unit; The input end of the second delay unit, the input end of the second buffer inverting unit, the second input end and the fourth input end of the time domain comparison unit are all connected to the second signal; the output end of the second delay unit is connected to the sixth input end of the time domain comparison unit; the output end of the second buffer inverting unit is connected to the second input end of the next one-step two-bit unit or is left floating; the fourth output end of the time domain comparison unit is connected to the second input end of the first current control unit, and the fourth output end of the time domain comparison unit is also connected to the input end of the second combinational logic unit together with the second output end and the sixth output end of the time domain comparison unit; the output end of the second combinational logic unit is connected to the second input end of the second current control unit; The first output terminal of the first current control unit and the first output terminal of the second current control unit are both connected to the IN in the first buffer inverting unit. P The second output terminal of the first current control unit and the second output terminal of the second current control unit are both connected to the MID in the first buffer inverting unit. P Node connection; the MID P The node is used to generate a pull-up or pull-down current to extend or shorten the transmission time of the first signal; The third output terminal of the first current control unit and the third output terminal of the second current control unit are both connected to the IN in the second buffer inverting unit. N The fourth output terminal of the first current control unit and the fourth output terminal of the second current control unit are both connected to the MID in the second buffer inverting unit. N Node connection; the MID N The node is used to generate a pull-up or pull-down current to extend or shorten the transmission time of the second signal.

3. The high-speed two-step time domain analog-to-digital converter according to claim 2, wherein: The first buffer inverting unit includes: a first buffer, a first inverter and a second inverter; The first buffer, the first inverter, and the second inverter are connected in sequence, the input end of the first buffer is connected to the first signal, and the output end of the second inverter is connected to the first input end of the next one-step two-bit unit or is left floating; Furthermore, the output terminal of the first buffer is the IN P Node, the output end of the first inverter is the MID P node.

4. The high-speed two-step time domain analog-to-digital converter according to claim 2, wherein: The second buffer inverting unit includes: a second buffer, a third inverter and a fourth inverter; The second buffer, the third inverter and the fourth inverter are connected in sequence, the input end of the second buffer is connected to the second signal, and the output end of the fourth inverter is connected to the second input end of the next one-step two-bit unit or is left floating; Furthermore, the output terminal of the second buffer is the IN N Node, the output end of the third inverter is the MID N node.

5. The high-speed two-step time domain analog-to-digital converter according to claim 2, wherein: The time domain comparison unit includes: a first time domain comparator, a second time domain comparator and a third time domain comparator; The positive input terminal of the first time domain comparator is connected to the output terminal of the first delay unit, and the positive input terminal of the second time domain comparator and the positive input terminal of the third time domain comparator are both connected to the first signal; The negative input terminal of the first time domain comparator and the negative input terminal of the second time domain comparator are both connected to the second signal, and the negative input terminal of the third time domain comparator is connected to the output terminal of the second delay unit; The positive output terminal of the first time domain comparator, the positive output terminal of the second time domain comparator, and the positive output terminal of the third time domain comparator are all connected to the input terminal of the first combinational logic unit; the negative output terminal of the first time domain comparator, the negative output terminal of the second time domain comparator, and the negative output terminal of the third time domain comparator are all connected to the input terminal of the second combinational logic unit; The positive output end of the second time domain comparator is also connected to the first input end of the first current control unit and the first input end of the quantization coding unit respectively, and the negative output end of the second time domain comparator is also connected to the second input end of the first current control unit.

6. The high-speed two-step time-domain analog-to-digital converter according to claim 2, wherein: The first current control unit includes: PMOS transistors MP1, MP2, MP3, and MP4, and NMOS transistors MN1, MN2, MN3, and MN4; The source of MP1 is connected to the power supply V DD The gate of the MP1 and the gate of the MN2 are both connected to the third output terminal of the time domain comparison unit, and the gate of the MP2 and the gate of the MN1 are both connected to the IN P The drain of MP2 and the source of MN1 are connected to the MID P Node connection, the drain of MP1 is connected to the source of MP2, the drain of MN1 is connected to the source of MN2, and the drain of MN2 is grounded; The source of the MP3 is connected to the V DD The gate of the MP3 and the gate of the MN4 are both connected to the fourth output terminal of the time domain comparison unit, and the gate of the MP4 and the gate of the MN3 are both connected to the IN N Node connection, the drain of MP4 and the source of MN3 are connected to the MID N The nodes are connected, the drain of the MP3 is connected to the source of the MP4, the drain of the MN3 is connected to the source of the MN4, and the drain of the MN4 is grounded.

7. The high-speed two-step time-domain analog-to-digital converter according to claim 2, wherein: The second current control unit includes: PMOS transistors MP5, MP6, MP7, and MP8, and NMOS transistors MN5, MN6, MN7, and MN8; wherein, The source of MP5 is connected to the power supply V DD The gate of the MP5 and the gate of the MN6 are both connected to the output end of the first combinational logic unit, and the gate of the MP6 and the gate of the MN5 are both connected to the IN P Node connection, the drain of MP6 and the source of MN5 are connected to the MID P Node connection, the drain of MP5 is connected to the source of MP6, the drain of MN5 is connected to the source of MN6, and the drain of MN6 is grounded; The source of MP7 is connected to the V DD The gate of the MP7 and the gate of the MN8 are both connected to the output end of the second combinational logic unit, and the gate of the MP8 and the gate of the MN7 are both connected to the IN N Node connection, the drain of MP8 and the source of MN7 are connected to the MID N The nodes are connected, the drain of the MP7 is connected to the source of the MP8, the drain of the MN7 is connected to the source of the MN8, and the drain of the MN8 is grounded.

8. The high-speed two-step time-domain analog-to-digital converter according to claim 6, wherein: The third output terminal of the time domain comparison unit and the fourth output terminal of the time domain comparison unit output opposite values; When the value outputted from the third output terminal of the time domain comparison unit is greater than the value outputted from the fourth output terminal of the time domain comparison unit, the MN1 and the MN2 are turned on, and the MP1 and the MP2 are turned off, so that the MID P At the node, a pull-down current is generated; at the same time, the MN3 and the MN4 are turned off, and the MP3 and the MP4 are turned on to generate a pull-down current at the MID N A pull-up current is generated at the node; When the value outputted by the third output terminal of the time domain comparison unit is smaller than the value outputted by the fourth output terminal of the time domain comparison unit, the MN1 and the MN2 are turned off, and the MP1 and the MP2 are turned on, so as to P At the node, a pull-up current is generated; at the same time, the MN3 and the MN4 are turned on, and the MP3 and the MP4 are turned off, so that the MID N A pull-down current is generated at the node.

9. The high-speed two-step time-domain analog-to-digital converter according to claim 7, wherein: The value outputted by the output terminal of the first combinational logic unit is opposite to the value outputted by the output terminal of the second combinational logic unit; When the value outputted from the output terminal of the first combination logic unit is greater than the value outputted from the output terminal of the second combination logic unit, the MN5 and the MN6 are turned on, and the MP5 and the MP6 are turned off, so as to P At the node, a pull-down current is generated; at the same time, the MN7 and the MN8 are turned off, and the MP7 and the MP8 are turned on to generate a pull-down current at the MID N A pull-up current is generated at the node; When the value outputted from the output terminal of the first combination logic unit is smaller than the value outputted from the output terminal of the second combination logic unit, the MN5 and the MN6 are turned off, and the MP5 and the MP6 are turned on, so as to P At the node, a pull-up current is generated; at the same time, the MN7 and the MN8 are turned on, and the MP7 and the MP8 are turned off, so that the MID N A pull-down current is generated at the node.

10. The high-speed two-step time domain analog-to-digital converter according to claim 1, wherein: The first CK T One end is connected to the IN1, the first CK T The other end of the first C S Electrical connection, the first C S The other end of the first CK is grounded. T The other end is also connected to the positive input end of the fourth time domain comparator, the negative input end of the fourth time domain comparator is connected to the reference voltage, the output end of the fourth time domain comparator is connected to the first input end of the conversion and selection unit, and the output end of the fourth time domain comparator is used to output the first time pulse signal; Second CK T One end is connected to the input IN2, the second CK T The other end of the second C S Electrical connection, the second C S The other end of the second CK is grounded. T The other end is also connected to the positive input end of the fifth time domain comparator, the negative input end of the fifth time domain comparator is connected to the reference voltage, the output end of the fifth time domain comparator is connected to the second input end of the conversion and selection unit, and the output end of the fifth time domain comparator is used to output the second time pulse signal; The positive input terminal of the fourth time domain comparator and the positive input terminal of the fifth time domain comparator are also connected to the CK D One end of the CK D The other end of the CK is connected to the current source. D One end is also connected to the C cm One end and the third CK T One end of the C cm The other end and the second CK T The other end is grounded.

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