Ferroelectric memory and three-dimensional ferroelectric memory device

Abstract

The application discloses a ferroelectric memory and a three-dimensional ferroelectric memory device, and the ferroelectric memory comprises a first word line, a second word line, a first bit line, a second bit line and a plate line; a plurality of memory cells, each memory cell comprising: a first transistor, a second transistor, a first wire and a plurality of ferroelectric capacitors; wherein the control end of the first transistor is connected with the first word line, the first end of the first transistor is connected with the first wire, and the second end of the first transistor is connected with the first bit line; the control end of the second transistor is connected with the second word line, the second end of the second transistor is connected with the first wire, and the second end of the second transistor is connected with the second bit line; the first end of the ferroelectric capacitor is connected with the first wire, and the second end of the ferroelectric capacitor is connected with the plate line. The ferroelectric memory is stacked in the direction perpendicular to the substrate, so that the storage density can be improved, and the storage capacity of the ferroelectric memory can be improved. In addition, the first transistor and the second transistor jointly select the memory cell, so that the control precision of the memory cell can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a ferroelectric memory and a three-dimensional ferroelectric memory device including the ferroelectric memory. Background Art

[0002] With the development of information technology, there is a growing demand for low-latency and high-capacity memory. Low latency helps increase data processing speed, while high capacity helps improve storage density and reduce memory manufacturing costs.

[0003] Ferroelectric memory (FRAM) is a new type of memory that has attracted widespread attention due to its non-volatile data storage and fast access speeds. However, most current FRAMs utilize planar structures. Due to the physical size and characteristics of the devices, the scaling of these FRAMs has slowed, making it difficult to further increase storage density. Therefore, increasing the storage density and capacity of FRAMs remains a major challenge in their development. Summary of the Invention

[0004] Based on this, the embodiments of the present application provide a ferroelectric memory and a three-dimensional ferroelectric memory device including the ferroelectric memory, which have a high storage density.

[0005] In a first aspect, the present application provides a ferroelectric memory according to some embodiments, characterized in that it includes:

[0006] a first word line, a second word line, a first bit line, a second bit line, and a plate line;

[0007] A plurality of storage units, each of the storage units comprising:

[0008] a first transistor, a second transistor, a first conductive line, and a plurality of ferroelectric capacitors;

[0009] The control terminal of the first transistor is connected to the first word line, and the first terminal of the first transistor is connected to the first wire.

[0010] The second terminal of the first transistor is connected to the first bit line;

[0011] The control terminal of the second transistor is connected to the second word line, the second terminal of the second transistor is connected to the first wire, and the second terminal of the second transistor is connected to the second bit line;

[0012] A first end of the ferroelectric capacitor is connected to the first conductive line, and a second end of the ferroelectric capacitor is connected to the plate line.

[0013] In some embodiments, the first word line, the second word line, and the plate line extend along a first direction, the first bit line and the second bit line extend along a second direction, and the first conductive line extends along a third direction, and the first direction, the second direction, and the third direction are perpendicular to each other;

[0014] Control terminals of the first transistors in the plurality of memory cells arranged along the first direction are all connected to the first word line;

[0015] The control terminals of the second transistors in the plurality of memory cells arranged along the first direction are all connected to the second word line;

[0016] The second ends of the first transistors in the plurality of memory cells arranged along the second direction are all connected to the first bit line;

[0017] The second ends of the second transistors in the plurality of memory cells arranged along the second direction are all connected to the second bit line;

[0018] The second ends of the ferroelectric capacitors in the plurality of storage cells arranged along the first direction are all connected to the plate line;

[0019] In the same storage unit, the first ends of the plurality of ferroelectric capacitors arranged along the third direction are all connected to the first conductive line;

[0020] The plurality of ferroelectric capacitors are distributed on both sides of the first conductive line along the second direction.

[0021] In some embodiments, during a write phase, the first word line is used to receive a first word line first precharge control signal, so that the first transistor is turned on;

[0022] The second word line is used to receive a second word line first precharge control signal, so that the second transistor is turned off;

[0023] The first bit line is used to receive a first control signal for a first bit line, and the second bit line is used to receive a first control signal for a second bit line;

[0024] The plate line is used to receive a plate line first control signal, and a voltage difference between the first bit line first control signal and the plate line first control signal polarizes the ferroelectric film layer of the ferroelectric capacitor.

[0025] In some embodiments, during a read phase, the first word line is used to receive a first precharge control signal of the first word line, so that the first transistor is turned on;

[0026] The second word line is used to receive the second word line first precharge control signal, so that the second transistor is turned off;

[0027] The first bit line is used to receive the first bit line third control signal, and the second bit line is used to receive the second bit line first control signal;

[0028] The plate line is used to receive a plate line third control signal, and a voltage difference between the first bit line third control signal and the plate line third control signal causes a polarization state of the ferroelectric film layer of the ferroelectric capacitor to change.

[0029] In some embodiments, in a standby state, the first word line is used to receive a first word line second precharge control signal, so that the first transistor is turned on;

[0030] The second word line is used to receive a second word line second precharge control signal to turn on the second transistor;

[0031] The first bit line is used to receive a first bit line second control signal, and the second bit line is used to receive a second bit line first control signal;

[0032] The plate line is used to receive a plate line second control signal. The voltage difference between the first bit line second control signal, the second bit line first control signal and the plate line second control signal keeps the polarization state of the ferroelectric film layer of the ferroelectric capacitor unchanged.

[0033] In some embodiments, voltage values ​​of the first bit line second control signal, the second bit line first control signal, and the plate line second control signal are equal.

[0034] In a second aspect, the present application further provides a ferroelectric memory according to some embodiments, characterized in that it includes:

[0035] substrate;

[0036] a plurality of memory cells disposed on the substrate;

[0037] Each of the storage units comprises:

[0038] a first transistor, a second transistor, a first conductive line, and a plurality of ferroelectric capacitors;

[0039] The first wire extends along the third direction, and two ends of the first wire are respectively connected to the first end of the first transistor and the first end of the second transistor;

[0040] The plurality of ferroelectric capacitors extend along the second direction and are arranged along the third direction. The first ends of the ferroelectric capacitors are connected to the first conductive wires. The second direction is perpendicular to the third direction.

[0041] In some embodiments, the ferroelectric capacitor includes an upper electrode layer, a ferroelectric film layer, and a lower electrode layer, wherein the ferroelectric film layer is located between the upper electrode layer and the lower electrode layer;

[0042] The lower electrode layer is connected to the first wire.

[0043] In some embodiments, the plurality of ferroelectric capacitors are disposed on both sides of the first conductive line along the second direction.

[0044] In some embodiments, the plurality of ferroelectric capacitors are staggered on both sides of the first conductive line along the second direction.

[0045] In some embodiments, the first wire includes a first sub-wire and a second sub-wire arranged along the second direction, the first sub-wire and the second sub-wire are respectively connected to the first transistor and the second transistor, and the ferroelectric capacitors arranged on both sides of the first wire along the second direction are respectively connected to the first sub-wire and the second sub-wire.

[0046] In some embodiments, the ferroelectric memory further comprises:

[0047] a first word line, a second word line, a first bit line, a second bit line, and a plate line;

[0048] The control terminal of the first transistor is connected to the first word line, and the second terminal of the first transistor is connected to the first bit line;

[0049] The control terminal of the second transistor is connected to the second word line, and the second terminal of the second transistor is connected to the second bit line;

[0050] The second end of the ferroelectric capacitor is connected to the plate line.

[0051] In some embodiments, the first word line, the second word line, and the plate line extend along a first direction, the first direction is perpendicular to the substrate surface, and the first direction is perpendicular to the second direction and the third direction;

[0052] Control terminals of the first transistors in the plurality of memory cells arranged along the first direction are all connected to the first word line;

[0053] The control terminals of the second transistors in the plurality of memory cells arranged along the first direction are all connected to the second word line;

[0054] The second ends of the first transistors in the plurality of memory cells arranged along the second direction are all connected to the first bit line;

[0055] The second ends of the second transistors in the plurality of memory cells arranged along the second direction are all connected to the second bit line;

[0056] The second ends of the ferroelectric capacitors in the plurality of storage cells arranged along the first direction are all connected to the plate line;

[0057] In the same storage unit, the first ends of the plurality of ferroelectric capacitors arranged along the third direction are all connected to the first conducting wire.

[0058] In some embodiments, bit line contact conductive lines are provided, and the bit line contact conductive lines are connected to the first bit line and the second bit line, respectively.

[0059] In a third aspect, the present application further provides a three-dimensional ferroelectric memory device according to some embodiments, characterized in that it includes:

[0060] A ferroelectric memory, wherein the ferroelectric memory is the ferroelectric memory provided in the second aspect;

[0061] A peripheral device wafer is coupled to the ferroelectric memory.

[0062] The semiconductor structure and the method for manufacturing the same provided by this application have at least the following beneficial effects:

[0063] The ferroelectric memory and three-dimensional ferroelectric memory device provided by this application can improve storage density and increase the storage capacity of the ferroelectric memory. In addition, multiple ferroelectric capacitors share a first conductive line, and multiple first conductive lines share a first word line, which can further improve the storage density of the ferroelectric memory. In addition, the first transistor and the second transistor jointly select a memory cell, which can improve the control accuracy of the memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 A circuit diagram of a storage unit of a ferroelectric memory provided in an embodiment of the present application;

[0066] Figure 2 A circuit diagram of a memory cell array of a ferroelectric memory provided in an embodiment of the present application;

[0067] Figure 3 A circuit diagram of a memory cell array of a ferroelectric memory provided in an embodiment of the present application;

[0068] Figure 4 A timing diagram of voltage changes during reading and writing of a ferroelectric memory provided in an embodiment of the present application;

[0069] Figure 5 A process structure diagram of a storage unit of a ferroelectric memory provided in an embodiment of the present application;

[0070] Figure 6a and Figure 6b A cross-sectional view of a memory cell of a ferroelectric memory provided in an embodiment of the present application;

[0071] Figure 7 A process structure diagram of a storage array of a ferroelectric memory provided in an embodiment of the present application;

[0072] Figure 8 A process structure diagram of a three-dimensional ferroelectric memory device provided in an embodiment of the present application;

[0073] Figures 9-13 A manufacturing flow chart of a ferroelectric memory provided for some embodiments of the present application;

[0074] Description of reference numerals:

[0075] 100: substrate; 200: initial sacrificial layer; 201: first part of the sacrificial layer; 202: second part of the sacrificial layer; 203: third part of the sacrificial layer; 204: fourth part of the sacrificial layer; 300: initial active layer; 301: first part of the active layer (first bit line); 302: second part of the active layer; 303: third part of the active layer; 304: fourth part of the active layer (second bit line); 401: first word line; 402: second word line; 403: third word line; 404: fourth word line; 501: first sub-conductor; 500: first conductor; 502: second sub-conductor; 503: third part of the first conductor; 600: capacitor; 601: lower electrode; 602: ferroelectric film layer; 603: upper electrode; 701: first plate line; 702: second plate line; 800: bit line contact conductor; 900: back-end connection; 1000: peripheral device wafer. DETAILED DESCRIPTION

[0076] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0078] It should be understood that when an element or layer is referred to as being "on," "adjacent," or "connected to," it can be directly on, adjacent, or connected to the other element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present application, a first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, a first doped region may be referred to as a second doped region, and similarly, a second doped region may be referred to as a first doped region; the first doped region and the second doped region are different doped regions.

[0079] Spatially relative terms such as "on..." may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, the element or feature described as "on..." will be oriented "under" the other elements or features. Therefore, the exemplary term "on..." may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0080] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0081] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes as a result, for example, of manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present invention.

[0082] Figure 1 A circuit diagram of a memory cell of a ferroelectric memory provided in an embodiment of the present application. In some embodiments, the ferroelectric memory includes a first wordline (wordline 1, WL1), a second wordline (wordline 2, WL2), a first bitline (bite line 1, BL1), a second bitline (bite line 2, BL2), and plate lines (plate lines 1-6, PL1-6) and a plurality of memory cells, wherein the memory cell includes a first transistor, a second transistor, a first conductive line, and a plurality of ferroelectric capacitors. The control terminal of the first transistor is connected to the first wordline WL1, the first terminal of the first transistor is connected to the first conductive line, the second terminal of the first transistor is connected to the first bitline BL1, the control terminal of the second transistor is connected to the second wordline WL2, the first terminal of the second transistor is connected to the first conductive line, the second terminal of the second transistor is connected to the second bitline BL2, the first terminal of the ferroelectric capacitor is connected to the first conductive line, and the second terminal of the ferroelectric capacitor is connected to the plate lines PL1-6. When a certain voltage difference is formed between the first end of the ferroelectric capacitor and the plate line PL1-6, that is, a voltage difference is formed across the two ends of the ferroelectric capacitor, the polarization state of the ferroelectric film layer in the ferroelectric capacitor changes, thereby realizing the reading and writing operations of data.

[0083] In some embodiments of the present application, the first transistor and the second transistor in the memory cell may be NMOS (N-channel metal oxide semiconductor) transistors, or PMOS (P-channel metal oxide semiconductor) transistors. Figure 1 In the memory cell shown, the first transistor selects an NMOS transistor, and the second transistor also selects an NMOS transistor. In this case, when a high voltage is applied to the first word line or the second word line, the first transistor or the second transistor is turned on, and when a low voltage is applied to the first word line or the second word line, the first transistor or the second transistor is turned off. In other embodiments, the first transistor may select an NMOS transistor and the second transistor may also select a PMOS transistor, or the first transistor may select a PMOS transistor and the second transistor may also select a PMOS transistor.

[0084] Continue to refer Figure 1 In some embodiments, the storage unit further includes a plurality of ferroelectric capacitors, wherein the first ends of the plurality of ferroelectric capacitors are connected to the first conductor, and the second ends of the plurality of capacitors are connected to the plate line. The plurality of ferroelectric capacitors can be four, six, eight, ten, or several hundred, sharing a first conductor and a first transistor and a second transistor, which can improve storage density. When a voltage difference is generated between the voltage at the first end and the voltage at the second end of the selected ferroelectric capacitor, the polarization state of the ferroelectric film layer changes, while the voltage at the first end and the voltage at the second end of the unselected ferroelectric capacitor does not generate a voltage difference to maintain the polarization state of the ferroelectric film layer unchanged, thereby enabling multiple data in a storage unit to be read and written separately. There is no difference between the selected plate line PL and ferroelectric capacitor and the unselected plate line PL and ferroelectric capacitor. When a ferroelectric capacitor needs to be read or written, the plate line, word line, and bit line of the selected ferroelectric capacitor receive corresponding control signals, while the plate line, word line, and bit line of the unselected ferroelectric capacitor do not receive corresponding control signals.

[0085] Continue to refer Figure 1 In some embodiments, the control terminals of the first and second transistors are referred to as gates, and one of the drain or source of the MOS transistor is referred to as the first terminal, while the other terminal is referred to as the second terminal. For example, the first terminal of the first transistor can be the source, and the second terminal the drain; or the first terminal can be the drain, and the second terminal can be the source. The second transistor can be the same as or different from the first transistor, and will not be further described here.

[0086] Continue to refer Figure 1In some embodiments, each ferroelectric capacitor includes a lower electrode, a ferroelectric film layer, and a lower electrode. The ferroelectric film layer is located between the lower electrode and the upper electrode. The first end of the ferroelectric capacitor can be either the lower electrode or the upper electrode. Similarly, the second end of the ferroelectric capacitor can be either the lower electrode or the upper electrode. In this embodiment, the first end of the ferroelectric capacitor is the lower electrode connected to the first wire, and the second end of the ferroelectric capacitor is the upper electrode connected to the plate line. The ferroelectric film layer material can include a perovskite structure material such as a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), Pb(Zr,Ti)O3, barium titanate (BaTiO3), etc., and can also include an HfO2-based ferroelectric material doped with at least one element of zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd), and aluminum (Al) in the HfO2 material. This application does not limit the material and manufacturing process of the ferroelectric film layer. When the polarization direction of the ferroelectric film is reversed, a potential domain wall region will appear between the reversed and unreversed regions. When the polarization directions between the two are opposite, the domain wall is open, resulting in a conductive state, i.e., a low-resistance state. When the polarization directions between the two are the same, the domain wall is closed, resulting in an insulating state, i.e., a high-resistance state and a low-resistance state, respectively, representing the stored "0" and "1" states. For example, a high-resistance state corresponds to "0" and a low-resistance state corresponds to "1", or vice versa, a high-resistance state corresponds to "1" and a low-resistance state corresponds to "0", thus achieving the storage function.

[0087] Figure 2 A circuit diagram of a memory cell array of a ferroelectric memory provided in an embodiment of the present application. In some embodiments, a first word line, a second word line, and a plate line extend along a first direction, a first bit line and a second bit line extend along a second direction, and a first conductive line extends along a third direction, wherein the first direction, the second direction, and the third direction are mutually perpendicular; the control terminals of the first transistors in the plurality of memory cells arranged along the first direction are all connected to the first word line; the control terminals of the second transistors in the plurality of memory cells arranged along the first direction are all connected to the second word line; the second terminals of the first transistors in the plurality of memory cells arranged along the second direction are all connected to the first bit line; the second terminals of the second transistors in the plurality of memory cells arranged along the second direction are all connected to the second bit line; the second terminals of the ferroelectric capacitors in the plurality of memory cells arranged along the first direction are all connected to the plate line; the first terminals of the plurality of ferroelectric capacitors in the memory cells arranged along the third direction are all connected to the first conductive line; and the plurality of ferroelectric capacitors are distributed on both sides of the first conductive line along the second direction.

[0088] Figure 2 Can be seen as Figure 1 The memory cells in the array are arranged in such a way that each memory cell has the same circuit structure. Figure 2The structure shown includes four ferroelectric memory cell structures, each of which includes four ferroelectric capacitor structures. In other embodiments, the array may include more memory cells, each of which may include more ferroelectric capacitors. These memory cells may be arranged in a first direction, a second direction, and a third direction perpendicular to each other to form a three-dimensional memory array, where the first direction may be the Z direction, the second direction may be the X direction, and the third direction may be the Y direction.

[0089] Continue to refer Figure 2 In some embodiments, four word lines are included, namely WL1, WL2, WL3 and WL4. Each WL extends along the Z direction. The control ends of the first transistors of the memory cells arranged along the Z direction can share a word line, and the control ends of the second transistors of the memory cells arranged along the Z direction can share a word line, which can reduce the number of word lines and improve storage density.

[0090] Continue to refer Figure 2 In some embodiments, four bit lines are included, namely BL1, BL2, BL3 and BL4. Each BL extends along the X direction. The second ends of the first transistors of the memory cells arranged along the X direction can share a bit line, and the second ends of the second transistors of the memory cells arranged along the X direction can share a bit line. This can reduce the number of bit lines and improve storage density.

[0091] Continue to refer Figure 2 In some embodiments, six plate lines are included, namely PL1, PL2, PL3, PL4, PL5 and PL6. Each plate line extends along the Z direction. The second ends of the ferroelectric capacitors of the memory cells arranged along the Z direction can share a plate line. The second ends of the ferroelectric capacitors between adjacent memory cells can share a plate line, for example, PL3 and PL4. This can reduce the number of plate lines and improve storage density.

[0092] Continue to refer Figure 2 In some embodiments, four first conductive wires are included, the first conductive wires extend along the Y direction, and multiple ferroelectric capacitors of a storage unit are arranged along the Y direction. The first ends of the ferroelectric capacitors are connected to the first conductive wires. The ferroelectric capacitors can be distributed on both sides of the first conductive wires along the X direction, which can reduce the parasitic effect between two adjacent ferroelectric capacitors, or increase the number of ferroelectric capacitors to improve storage density.

[0093] Figure 3 A circuit diagram of a memory cell array of a ferroelectric memory provided in an embodiment of the present application. In some embodiments, the memory array includes five Figure 1The memory cells shown are arranged along the X direction, with bit lines BL1 and BL2 extending along the X direction. Ten transistors (Tr) are provided, wherein the second ends of five first transistors Tr1, Tr3, Tr5, Tr7, and Tr9 are connected to the bit line BL1, the second ends of five second transistors Tr2, Tr4, Tr6, Tr8, and Tr10 are connected to the bit line BL2, the control ends of the five first transistors Tr1, Tr3, Tr5, Tr7, and Tr9 are connected to WL1, WL3, WL5, WL7, and WL9, respectively, and the control ends of the five second transistors Tr2, Tr4, Tr6, Tr8, and Tr10 are connected to WL2, WL4, WL6, WL8, and WL10, respectively. Ten plate lines PL1, PL2, PL3, PL4, PL5, PL6, PL7, PL8, PL9, and PL10 extend along the X direction and are respectively connected to the second ends of ferroelectric capacitors. The second ends of ferroelectric capacitors at the same position arranged along the X direction share a plate line, which can improve storage density.

[0094] Figure 4 This is a timing diagram of voltage changes during reading and writing of a ferroelectric memory provided by the embodiment of the present application. Figure 3 , in some embodiments, Figure 4 The timing diagram of voltage change is Figure 3When a memory cell in a memory cell array is read or written, the voltage values ​​on the corresponding signal lines on the memory cell are as follows. First, a "1" operation is performed on the selected memory cell (Selective Cell, Sel Cell). The first word line WL1 is used to receive the first word line first precharge control signal, turning on the first transistor Tr1. The second word line WL2 is used to receive the second word line first precharge control signal, turning off the second transistor Tr2. The first bit line BL1 is used to receive the first bit line first control signal, and the second bit line is used to receive the second bit line first control signal. The plate line is used to receive the plate line first control signal. The voltage difference between the first bit line first control signal and the plate line first control signal polarizes the ferroelectric film layer of the ferroelectric capacitor. Specifically, in some embodiments, a high voltage is applied to the first bit line BL1 to provide a signal source for the transistors Tr1, Tr3, Tr5, Tr7 and Tr9, a low voltage is applied to the second bit line BL2, a high voltage is applied to the word lines WL1, WL4, WL6, WL8 and WL10 to turn on the transistors Tr1, Tr4, Tr6, Tr8 and Tr10, a low voltage is applied to the word lines WL2, WL3, WL5, WL7 and WL9 to turn off the transistors Tr2, Tr3, Tr5, Tr7 and Tr9 respectively, a low voltage is applied to the plate line PL9, and a low voltage is applied to the plate lines PL1-8 and 10 at the same time. At this time, the first end of the selected memory cell Sel Cell is the high voltage of the first bit line BL, and the second end is the low voltage of the plate line PL9. The voltage difference between the two ends polarizes the ferroelectric film layer of the ferroelectric capacitor of the selected memory cell Sel Cell, thereby realizing the write "1" operation. For other unselected memory cells, the ferroelectric film layer of the ferroelectric capacitor cannot be polarized because there is no voltage difference or the voltage difference is relatively small between the first and second terminals of the ferroelectric capacitor, and thus the write "1" operation is not implemented.

[0095] Continue to refer Figure 3 and Figure 4In some embodiments, during the reading phase, the first word line WL1 is used to receive the first word line first precharge control signal, so that the first transistor Tr1 is turned on, the second word line WL2 is used to receive the second word line first precharge control signal, so that the second transistor Tr2 is turned off, the first bit line BL1 is used to receive the first bit line third control signal, the second bit line is used to receive the second bit line first control signal, and the plate line is used to receive the plate line third control signal. The voltage difference between the first bit line third control signal and the plate line third control signal causes the polarization state of the ferroelectric film layer of the ferroelectric capacitor to change. Specifically, a low voltage is applied to the first bit line BL1 and the second bit line BL2, a high voltage is applied to the word lines WL1, WL4, WL6, WL8 and WL10, so that the transistors Tr1, Tr4, Tr6, Tr8 and Tr10 are turned on, a low voltage is applied to the word lines WL2, WL3, WL5, WL7 and WL9, so that the transistors Tr2, Tr3, Tr5, Tr7 and Tr9 are turned off respectively, a high voltage is applied to the plate line PL9, and a low voltage is applied to the plate lines PL1-8 and 10. At this time, the first end of the selected memory cell Sel Cell is the low voltage of the first bit line BL, and the second end is the high voltage of the plate line PL9. The voltage difference between the two ends causes the polarization state of the ferroelectric film layer of the ferroelectric capacitor of the selected memory cell Sel Cell to change, thereby realizing the read "1" operation. For other unselected memory cells, the polarization state of the ferroelectric film layer of the ferroelectric capacitor cannot be changed because there is no voltage difference or the voltage difference is relatively small between the first and second terminals of the ferroelectric capacitor, and thus the read "1" operation is not implemented.

[0096] Continue to refer Figure 3 and Figure 4 In some embodiments, in the standby stage, the first word line WL1 is used to receive the first word line second precharge control signal, so that the first transistor Tr1 is turned on, the second word line WL2 is used to receive the second word line second precharge control signal, so that the second transistor Tr2 is turned on, the first bit line BL1 is used to receive the first bit line second control signal, the second bit line BL2 is used to receive the second bit line first control signal, and the plate line PL is used to receive the plate line second control signal. The voltage difference between the first bit line second control signal, the second bit line first control signal and the plate line second control signal keeps the polarization state of the ferroelectric film layer of the ferroelectric capacitor unchanged but cannot keep the polarization or polarization state of the ferroelectric film layer of the ferroelectric capacitor unchanged. Specifically, a low voltage is applied to both the first bit line BL1 and the second bit line BL2, a high voltage is applied to the word line WL to turn on the transistor Tr, and a low voltage is applied to the plate line PL. There is no voltage difference or the voltage difference is relatively small across the ferroelectric capacitor, so that the polarization state of the ferroelectric film layer of the ferroelectric capacitor remains unchanged.

[0097] Continue to refer Figure 3 and Figure 4In some embodiments, during the standby phase, the voltage values ​​of the first bit line second control signal, the second bit line first control signal, and the plate line second control signal are equal. Specifically, the low voltage applied to both the first bit line BL1 and the second bit line BL2 is equal to the low voltage applied to the plate line PL, and the low voltage applied to the first bit line BL1, the second bit line BL2, and the plate line PL is less than the high voltage during the read or write phase. This can keep the memory cell away from a floating state, reduce charge and discharge time, and improve operation speed.

[0098] Figure 5 A process structure diagram of a memory cell of a ferroelectric memory provided in an embodiment of the present application. In some embodiments, the memory cell includes: a first transistor Tr1, a second transistor Tr2, a first conductive line 500, and a plurality of ferroelectric capacitors 600. The first conductive line 500 extends along the Y direction, with its two ends respectively connected to the first end of the first transistor Tr1 and the first end of the second transistor Tr2. The plurality of ferroelectric capacitors 600 extend along the X direction and are arranged along the Y direction, with the first ends of the ferroelectric capacitors 600 connected to the first conductive line 500. The second direction is perpendicular to the third direction.

[0099] Continue to refer Figure 5 In some embodiments, the first transistor Tr1 and the second transistor Tr2 in the storage unit can be NMOS (N-channel metal oxide semiconductor) tubes, or PMOS (P-channel metal oxide semiconductor) tubes. For example, Figure 5In the illustrated memory cell, the control terminals of the first transistor Tr1 and the second transistor Tr2 are connected to the first word line 401 and the second word line 402, respectively. The material of the first word line and the second word line is a conductive material, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first word line 401 and the second word line 402 can be the same or different. The first transistor Tr1 is an NMOS transistor, and the second transistor Tr2 is also an NMOS transistor. In this case, when a high voltage is applied to the first word line 401 or the second word line 402, the first transistor Tr1 and the second transistor Tr2 are turned on. When a low voltage is applied to the first word line 401 or the second word line 402, the first transistor Tr1 and the second transistor Tr2 are turned off. In other embodiments, the first transistor Tr1 may be an NMOS transistor and the second transistor Tr2 may be a PMOS transistor, or the first transistor Tr1 may be a PMOS transistor and the second transistor Tr2 may be a PMOS transistor. The first conductive line 500 extends along the Y direction and may include a first sub-conductor 501, a second sub-conductor 502, and a first conductive line third portion 503 disposed between the first conductive line and the ferroelectric capacitor 600. In some embodiments, the first conductive line may be made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), or metal silicide. The materials of the first sub-conductor 501, the second sub-conductor 502, and the first conductive line third portion 503 may be the same or different.

[0100] Continue to refer Figure 5In some embodiments, a plurality of ferroelectric capacitors 600 extend along the X direction and are arranged along the Y direction. The first ends of the plurality of ferroelectric capacitors 600 are connected to the third portion 503 of the first conductor. The third portion 503 of the first conductor is arranged between the ferroelectric capacitor 600 and the first sub-conductor 501 and the second sub-conductor 502 of the first conductor, which can reduce the contact resistance between the ferroelectric capacitor and the first conductor 500 while increasing the stability of the first conductor. The ferroelectric capacitors 600 can be distributed on both sides of the first conductor 500 along the X direction, which can reduce the parasitic effects between two adjacent ferroelectric capacitors, or increase the number of ferroelectric capacitors to improve storage density. In some embodiments, the ferroelectric capacitors 600 are distributed on both sides of the first conductor 500 along the X direction and are staggered, which can further reduce signal crosstalk between adjacent ferroelectric capacitors 600 and improve conductive performance. The ferroelectric capacitor 600 includes a lower electrode 601, a ferroelectric film layer 602 and an upper electrode 603. The ferroelectric film layer 602 is located between the upper electrode 603 and the lower electrode 601. Figure 6a and Figure 6b The ferroelectric capacitor can be a columnar, barreled, ring-shaped or other shaped structure, and can be a structure type in which the ferroelectric film layer 602 surrounds the lower electrode 601 and the upper electrode 603 surrounds the ferroelectric film layer 602, such as Figure 6a As shown, the lower electrode 601 may be formed into a groove shape, and the ferroelectric film layer 602 and the upper electrode 603 may fill the groove structure, as shown in FIG. Figure 6b As shown. The material of the lower electrode 601 and the upper electrode 603 is a conductive material, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the lower electrode 601 and the upper electrode 603 can be the same or different. The material of the ferroelectric film layer 602 is a material with ferroelectric properties. The ferroelectric film layer material may include perovskite structure materials such as Pb(Zr, Ti)O3, a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), barium titanate (BaTiO3), etc., and may also include HfO2-based ferroelectric materials in which at least one element of zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd) and aluminum (Al) is doped in the HfO2 material.

[0101] Continue to refer Figure 5 and Figure 6a as well as Figure 6bIn some embodiments, the ferroelectric memory cell further includes a plate line 700, which extends along the Z direction and is arranged along the Y direction. The plate line 700 is connected to the top electrode 603 of the ferroelectric capacitor 600. The plate line 700 is made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), or metal silicide. The plate line 700, the top electrode 603, and the bottom electrode 602 may be made of the same or different materials.

[0102] Figure 7 A process structure diagram of a storage array of a ferroelectric memory provided in an embodiment of the present application. Figure 7 The array process structure diagram can be Figure 5 The memory cell array is arranged in such a way that each memory cell has the same structure. Figure 7 The embodiment includes a memory cell array structure arranged in two columns along the X direction and stacked in three layers along the Z direction. In other embodiments, the array may include more memory cells, each of which may include more ferroelectric capacitors. These memory cells may be arranged in mutually perpendicular Z, X, and Y directions to form a three-dimensional memory array.

[0103] Continue to refer Figure 7In some embodiments, a ferroelectric memory includes a substrate 100, a plurality of memory cells disposed on the substrate 100, the plurality of memory cells being arranged along the X direction and stacked along the Z direction on the substrate 100, each memory cell including a first transistor, a second transistor, a first conductive line 500, and a plurality of ferroelectric capacitors 600. The first conductive line 500 extends along the Y direction, with two ends of the first conductive line 500 connected to a first end of the first transistor and a first end of the second transistor, respectively. The plurality of ferroelectric capacitors 600 extend along the X direction and are arranged along the Y direction, with the first ends of the ferroelectric capacitors 600 connected to the first conductive line 500. Specifically, in some embodiments, the substrate 100 may be a single crystal silicon substrate, a polycrystalline silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (e.g., silicon nitride or gallium arsenide), an oxide semiconductor substrate, or a substrate having a semiconductor device formed thereon. In some embodiments, the first transistor and the second transistor in the memory cell may be NMOS (N-channel metal oxide semiconductor) transistors, or PMOS (P-channel metal oxide semiconductor) transistors. In other embodiments, the first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor, or the first transistor may be a PMOS transistor and the second transistor may be a PMOS transistor.

[0104] Continue to refer Figure 7 In some embodiments, the ferroelectric capacitor 600 includes a lower electrode 601, a ferroelectric film layer 602, and an upper electrode 603. The ferroelectric film layer 602 is located between the upper electrode 603 and the lower electrode 601. The ferroelectric capacitor can be a columnar, barreled, ring-shaped, or other shaped structure. The ferroelectric film layer 602 can be surrounded by the lower electrode 601, and the upper electrode 603 can be surrounded by the ferroelectric film layer 602. Figure 6a As shown, the lower electrode 601 may be formed into a groove shape, and the ferroelectric film layer 602 and the upper electrode 603 may fill the groove structure, as shown in FIG. Figure 6bAs shown. The material of the lower electrode 601 and the upper electrode 603 is a conductive material, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the lower electrode 601 and the upper electrode 603 can be the same or different. The material of the ferroelectric film layer 602 is a material with ferroelectric properties. The ferroelectric film layer material includes perovskite structure materials such as Pb(Zr, Ti)O3, a mixture of lead zirconate (PbZrO3) and lead titanate (PbTiO3), barium titanate (BaTiO3), etc., and can also include HfO2-based ferroelectric materials in which at least one element of zirconium (Zr), silicon (Si), lanthanum (La), yttrium (Y), strontium (Sr), gadolinium (Gd) and aluminum (Al) is doped in the HfO2 material.

[0105] Continue to refer Figure 7 In some embodiments, a plurality of ferroelectric capacitors 600 extend along the X direction and are arranged along the Y direction. The first ends of the plurality of ferroelectric capacitors 600 are connected to the third portion 503 of the first conductor. The third portion 503 of the first conductor is arranged between the ferroelectric capacitor 600 and the first sub-conductor 501 and the second sub-conductor 502 of the first conductor. This can reduce the contact resistance between the ferroelectric capacitor and the first conductor 500 while increasing the stability of the first conductor. The ferroelectric capacitors 600 can be distributed on both sides of the first conductor 500 along the X direction, which can reduce the parasitic effect between two adjacent ferroelectric capacitors, or increase the number of ferroelectric capacitors to improve storage density. In some embodiments, the ferroelectric capacitors 600 are distributed on both sides of the first conductor 500 along the X direction and are staggered, which can further reduce the signal crosstalk between adjacent ferroelectric capacitors 600 and improve conductive performance.

[0106] Continue to refer Figure 7 In some embodiments, the first conductive line 500 extends along the Y direction. The first conductive line may include a first sub-conductor 501, a second sub-conductor 502, and a first conductive line third portion 503 disposed between the first conductive line and the ferroelectric capacitor 600. In some embodiments, the first conductive line may be made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), or metal silicide. The materials of the first sub-conductor 501, the second sub-conductor 502, and the first conductive line third portion 503 may be the same or different.

[0107] Continue to refer Figure 7 In some embodiments, the ferroelectric memory further includes a first word line 401, a second word line 402, a third word line 403, a fourth word line 404, a first bit line 301, a second bit line 304, and a first plate line 701 and a second plate line 702. Specifically, the first word line 401, the second word line 402, the third word line 403, the fourth word line 404, the first plate line 701 and the second plate line 702 extend along the Z direction, the first bit line 301 and the second bit line 304 extend along the X direction, and are stacked along the Z direction. The control terminals of the first transistor and the second transistor are referred to as gates, and one of the drain or source of the MOS transistor is referred to as the first terminal, and the other terminal is referred to as the second terminal. For example, the first terminal of the first transistor can be the source, and the second terminal can be the drain; or the first terminal can be the drain, and the second terminal can be the source. The second transistor and the first transistor can be the same or different, and will not be described in detail here. The first word line 401 and the third word line 403 are respectively connected to the control terminal of the first transistor, and the third word line 403 and the fourth word line 404 are respectively connected to the control terminal of the second transistor. The first bit line 301 is connected to the second terminal of the first transistor, i.e., the source or drain terminal, and the second bit line 304 is connected to the second terminal of the second transistor, i.e., the source or drain terminal. The ferroelectric capacitor 600 includes an upper electrode 603, a ferroelectric film layer 602, and a lower electrode 601. The lower electrode 601 is referred to as the first terminal, and the upper electrode 603 is referred to as the second terminal. The first plate line 701 and the second plate line 702 are respectively connected to the second terminal of the ferroelectric capacitor 600. The first word line 401, the second word line 402, the third word line 403, the fourth word line 404, the first bit line 301, the second bit line 304, and the first plate line 701 and the second plate line 702 are made of a conductive material, for example, at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first word line 401, the second word line 402, the third word line 403, the fourth word line 404, the first bit line 301, the second bit line 304, and the first plate line 701 and the second plate line 702 can be the same or different.

[0108] Continue to refer Figure 7In some embodiments, the first word line 401 and the third word line 403 extend along the Z direction, and the control terminals of the first transistors of the memory cells stacked along the Z direction are all connected to the first word line 401 and the second word line 403. The second word line 402 and the fourth word line 404 extend along the Z direction, and the control terminals of the first transistors of the memory cells stacked along the Z direction are all connected to the second word line 402 and the fourth word line 404. The first bit line 301 extends along the X direction, and the second terminals of all the first transistors arranged along the X direction are all connected to the first bit line 301. The second bit line 304 extends along the X direction, and the second terminals of all the second transistors arranged along the X direction are all connected to the second bit line 304. The first plate line 701 and the second plate line 702 extend along the Z direction, and the second terminals of the ferroelectric capacitors 600 of the memory cells stacked along the Z direction are all connected to the first plate line 701 and the second plate line 702. As described above, the first conductive line 500 extends along the Y direction, and the plurality of ferroelectric capacitors extend along the X direction and are arranged along the Y direction. The first ends of the plurality of ferroelectric capacitors are connected to the first conductive line 500. In some embodiments, the plurality of ferroelectric capacitors are distributed on both sides of the first conductive line along the X direction. Figure 7 In the three-dimensional ferroelectric memory, the memory cells stacked along the Z direction share word lines and plate lines, and the memory cells arranged along the X direction share bit lines, which can save more space and improve storage density.

[0109] Continue to refer Figure 7 In some embodiments, the ferroelectric memory further includes a bitline contact wire 800. Specifically, the bitline contact wire 800 extends along the Z direction and is respectively connected to the first bitline 301 and the second bitline 304 located in different layers, thereby enabling precise control of the bitlines stacked along the Z direction. The bitline contact wire 800 is made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc.

[0110] Figure 8 This is a process structure diagram of a three-dimensional ferroelectric memory device provided in an embodiment of the present application. The present disclosure also provides a three-dimensional ferroelectric memory device, such as Figure 8As shown, back-end connections 900 are provided on the memory cells. These connections are located above the three-dimensional memory and are connected to the first word line 401, the second word line 402, the third word line 403, the fourth word line 404, the bit line contact wire 800, and the first and second plate lines 701 and 702, respectively. Back-end connections 900 are made of a conductive material, such as at least one of the following: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), or metal silicide. The back-end connections can be made of the same or different materials as the first word line 401, the second word line 402, the third word line 403, the fourth word line 404, the bit line contact wire 800, and the first and second plate lines 701 and 702. In some embodiments, the three-dimensional ferroelectric memory device further includes a peripheral device wafer 1000, which has a variety of peripheral circuit devices, such as driver devices, decoder devices, error correction devices and other devices. The peripheral device wafer 1000 is connected to the back-end connection and bonded to the ferroelectric memory wafer.

[0111] The disclosed embodiments also provide a method for preparing a ferroelectric memory.

[0112] Figures 9-13 The manufacturing flow chart of the ferroelectric memory provided in some embodiments of the present application is as follows. Figures 9 to 13 The method for preparing the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0113] refer to Figure 9 In some embodiments, an initial sacrificial layer 200 and an initial active layer 300 are formed on a substrate 100. The initial sacrificial layer 200 and the initial active layer 300 are repeatedly stacked along the Z direction to form a multi-stack structure including the initial sacrificial layer 200 and the initial active layer 300. In some embodiments, the substrate 100 can be a single crystal silicon substrate, a polycrystalline silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, a III-V compound substrate (such as silicon nitride or gallium arsenide), an oxide semiconductor substrate, or a substrate having a semiconductor device formed thereon. The initial sacrificial layer 200 can be made of silicon nitride, silicon oxide, silicon oxynitride, or other materials different from the substrate. The initial active layer 300 can be made of a material having semiconductor properties, such as single crystal silicon, polycrystalline silicon, an oxide semiconductor material, etc.

[0114] refer to Figure 10In some embodiments, the initial sacrificial layer 200 and the initial active layer 300 are patterned and etched to form a stacked structure of a first sacrificial layer portion 201, a second sacrificial layer portion 202, a third sacrificial layer portion 203, a fourth sacrificial layer portion 204, a first active layer portion 301, a second active layer portion 302, a third active layer portion 303, and a fourth active layer portion 304, respectively. The first sacrificial layer portion 201 and the first active layer portion 301, as well as the fourth sacrificial layer portion 204 and the fourth active layer portion 304 extend along the X direction and are located at both ends along the Y direction. The third sacrificial layer portion 203 and the third active layer portion 303 extend along the Y direction and are located at the first sacrificial layer portion 201 and the first active layer portion 301, as well as the sacrificial layer portion 304. The fourth portion 204 is located between the fourth active layer portion 304 and the fourth active layer portion 304, and its two ends are connected to the first sacrificial layer portion 201 and the first active layer portion 301, as well as the fourth sacrificial layer portion 204 and the fourth active layer portion 304, respectively. The second sacrificial layer portion 202 and the second active layer portion 302 extend along the X direction. Multiple second sacrificial layer portions 202 and the second active layer portions 302 are arranged along the Y direction and connected to the third sacrificial layer portion 203 and the third active layer portion 303. In some embodiments, the second sacrificial layer portion 202 and the second active layer portion 302 are located on both sides of the third sacrificial layer portion 203 and the third active layer portion 303 along the X direction, and the second sacrificial layer portions 202 and the second active layer portions 302 located on both sides are alternately arranged.

[0115] refer to Figure 11In some embodiments, a first word line 401, a second word line 402, a third word line 403, and a fourth word line 404 are formed. The first word line 401, the second word line 402, the third word line 403, and the fourth word line 404 extend along the Z direction and are located at positions of the third portion 203 of the sacrificial layer and the third portion 303 of the active layer, close to the first portion 201 of the sacrificial layer and the first portion 301 of the active layer, and the fourth portion 204 of the sacrificial layer and the fourth portion 304 of the active layer, respectively. The first word line 401, the second word line 402, the third word line 403, and the fourth word line 404 can form a single-gate structure, a double-gate structure, a triple-gate structure, or a ring-gate structure. A gate oxide layer (not shown) is further provided between the first word line 401, the second word line 402, the third word line 403, and the fourth word line 404 and the third portion 203 of the sacrificial layer and the third portion 303 of the active layer. The first word line 401, the second word line 402, the third word line 403, and the fourth word line 404 are made of conductive materials, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first word line 401, the second word line 402, the third word line 403, and the fourth word line 404 can be the same or different.

[0116] refer to Figure 12 In some embodiments, a portion of the third portion 303 of the active layer is converted into a first conductive line 500. The first conductive line can be a whole, or can include a first sub-conductor 501, a second sub-conductor 502, and a first conductive line third portion 503. In some embodiments, the first conductive line can be made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), or metal silicide. The materials of the first sub-conductor 501, the second sub-conductor 502, and the first conductive line third portion 503 can be the same or different.

[0117] refer to Figure 13In some embodiments, a ferroelectric capacitor 600 and a plate line 701 and a plate line 702 are formed, wherein the plurality of ferroelectric capacitors 600 extend along the X direction and are arranged along the Y direction. The first ends of the plurality of ferroelectric capacitors 600 are connected to the third portion 503 of the first conductor, and the third portion 503 of the first conductor is arranged between the ferroelectric capacitor 600 and the first sub-conductor 501 and the second sub-conductor 502 of the first conductor, thereby reducing the contact resistance between the ferroelectric capacitor and the first conductor 500 and increasing the stability of the first conductor. The ferroelectric capacitors 600 can be distributed on both sides of the first conductor 500 along the X direction, thereby reducing the parasitic effect between two adjacent ferroelectric capacitors, or increasing the number of ferroelectric capacitors and improving storage density. In some embodiments, the ferroelectric capacitors 600 are distributed on both sides of the first conductor 500 along the X direction and are staggered, thereby further reducing the signal crosstalk between adjacent ferroelectric capacitors 600 and improving conductive performance. The first plate line 701 and the second plate line 702 extend along the Z direction. The ferroelectric capacitor 600 includes an upper electrode 603, a ferroelectric film layer 602, and a lower electrode 601. The lower electrode 601 is referred to as the first end, and the upper electrode 603 is referred to as the second end. The first plate line 701 and the second plate line 702 are respectively connected to the second end of the ferroelectric capacitor 600. Ferroelectric capacitors located between adjacent memory cells share a second plate line 702, which can save more space and improve storage density. The lower electrode 601, the upper electrode 602, the first plate line 701, and the second plate line 702 are made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc. The materials of the first word line 401 , the lower electrode 601 , the upper electrode 602 , the first plate line 701 , and the second plate line 702 may be the same or different.

[0118] Continue to refer Figure 7 , forming a bitline contact wire 800. The bitline contact wire 800 extends along the Z direction and connects to the first bitline 301 and the second bitline 304 located in different layers, respectively, to achieve precise control of the bitlines stacked along the Z direction. The bitline contact wire 800 is made of a conductive material, such as at least one of the following materials: titanium nitride (TiN), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), tantalum nitride (TaN), cobalt (Co), aluminum (Al), copper (Cu), polysilicon (Si), metal silicide, etc.

[0119] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, any combination of the technical features is deemed to be within the scope of the present disclosure as long as there is no inconsistency.

[0120] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A ferroelectric memory, characterized in that: include: a first word line, a second word line, a first bit line, a second bit line, and a plate line; A plurality of storage units, each of the storage units comprising: a first transistor, a second transistor, a first conductive line, and a plurality of ferroelectric capacitors; The control terminal of the first transistor is connected to the first word line, and the first terminal of the first transistor is connected to the first wire. The second terminal of the first transistor is connected to the first bit line; The control terminal of the second transistor is connected to the second word line, the first terminal of the second transistor is connected to the first wire, and the second terminal of the second transistor is connected to the second bit line; A first end of the ferroelectric capacitor is connected to the first wire, and a second end of the ferroelectric capacitor is connected to the plate line; The first word line, the second word line and the plate line extend along a first direction, the first bit line and the second bit line extend along a second direction, the first conductive line extends along a third direction, and the first direction, the second direction and the third direction are perpendicular to each other; Control terminals of the first transistors in the plurality of memory cells arranged along the first direction are all connected to the first word line; The control terminals of the second transistors in the plurality of memory cells arranged along the first direction are all connected to the second word line; The second ends of the first transistors in the plurality of memory cells arranged along the second direction are all connected to the first bit line; The second ends of the second transistors in the plurality of memory cells arranged along the second direction are all connected to the second bit line; The second ends of the ferroelectric capacitors in the plurality of storage cells arranged along the first direction are all connected to the plate line; In the same storage unit, the first ends of the plurality of ferroelectric capacitors arranged along the third direction are all connected to the first conductive line; The plurality of ferroelectric capacitors are distributed on both sides of the first conductive line along the second direction.

2. The ferroelectric memory according to claim 1, wherein In the write phase, the first word line is used to receive a first word line first precharge control signal, so that the first transistor is turned on; The second word line is used to receive a second word line first precharge control signal, so that the second transistor is turned off; The first bit line is used to receive a first control signal for a first bit line, and the second bit line is used to receive a first control signal for a second bit line; The plate line is used to receive a plate line first control signal, and a voltage difference between the first bit line first control signal and the plate line first control signal polarizes the ferroelectric film layer of the ferroelectric capacitor.

3. The ferroelectric memory according to claim 2, wherein: In a reading phase, the first word line is used to receive a first precharge control signal of the first word line, so that the first transistor is turned on; The second word line is used to receive the second word line first precharge control signal, so that the second transistor is turned off; The first bit line is used to receive the first bit line third control signal, and the second bit line is used to receive the second bit line first control signal; The plate line is used to receive a plate line third control signal, and a voltage difference between the first bit line third control signal and the plate line third control signal causes a polarization state of the ferroelectric film layer of the ferroelectric capacitor to change.

4. The ferroelectric memory according to claim 2, wherein: In a standby state, the first word line is used to receive a first word line second precharge control signal, so that the first transistor is turned on; The second word line is used to receive a second word line second precharge control signal to turn on the second transistor; The first bit line is used to receive a first bit line second control signal, and the second bit line is used to receive a second bit line first control signal; The plate line is used to receive a plate line second control signal. The voltage difference between the first bit line second control signal, the second bit line first control signal and the plate line second control signal keeps the polarization state of the ferroelectric film layer of the ferroelectric capacitor unchanged.

5. The ferroelectric memory according to claim 4, wherein: Voltage values ​​of the first bit line second control signal, the second bit line first control signal, and the plate line second control signal are equal.

6. A ferroelectric memory, characterized in that: include: substrate; a plurality of memory cells disposed on the substrate; Each of the storage units comprises: a first transistor, a second transistor, a first conductive line, and a plurality of ferroelectric capacitors; The first wire extends along the third direction, and two ends of the first wire are respectively connected to the first end of the first transistor and the first end of the second transistor; The plurality of ferroelectric capacitors extend along the second direction and are arranged along the third direction, the first ends of the ferroelectric capacitors are connected to the first wires, and the second direction is perpendicular to the third direction; Wherein, the plurality of ferroelectric capacitors are arranged on both sides of the first conductive line along the second direction.

7. The ferroelectric memory according to claim 6, wherein: The ferroelectric capacitor comprises an upper electrode layer, a ferroelectric film layer and a lower electrode layer, wherein the ferroelectric film layer is located between the upper electrode layer and the lower electrode layer; The lower electrode layer is connected to the first wire.

8. The ferroelectric memory according to claim 6, wherein: The plurality of ferroelectric capacitors are staggeredly arranged on both sides of the first conductive line along the second direction.

9. The ferroelectric memory according to claim 8, wherein The first conductor includes a first sub-conductor and a second sub-conductor arranged along a second direction, the first sub-conductor and the second sub-conductor are both connected to the first transistor and the second transistor, and the ferroelectric capacitors arranged on both sides of the first conductor along the second direction are respectively connected to the first sub-conductor and the second sub-conductor.

10. The ferroelectric memory according to any one of claims 6 to 9, wherein: Also includes: a first word line, a second word line, a first bit line, a second bit line, and a plate line; The control terminal of the first transistor is connected to the first word line, and the second terminal of the first transistor is connected to the first bit line; The control terminal of the second transistor is connected to the second word line, and the second terminal of the second transistor is connected to the second bit line; The second end of the ferroelectric capacitor is connected to the plate line.

11. The ferroelectric memory according to claim 10, wherein: The first word line, the second word line and the plate line extend along a first direction, the first direction is perpendicular to the substrate surface, and the first direction is perpendicular to the second direction and the third direction; Control terminals of the first transistors in the plurality of memory cells arranged along the first direction are all connected to the first word line; The control terminals of the second transistors in the plurality of memory cells arranged along the first direction are all connected to the second word line; The second ends of the first transistors in the plurality of memory cells arranged along the second direction are all connected to the first bit line; The second ends of the second transistors in the plurality of memory cells arranged along the second direction are all connected to the second bit line; The second ends of the ferroelectric capacitors in the plurality of storage cells arranged along the first direction are all connected to the plate line; In the same storage unit, the first ends of the plurality of ferroelectric capacitors arranged along the third direction are all connected to the first conducting wire.

12. The ferroelectric memory according to claim 10, wherein: Also includes: The bit line contact conductive lines are connected to the first bit line and the second bit line respectively.

13. A three-dimensional ferroelectric memory device, characterized in that: include: A ferroelectric memory, wherein the ferroelectric memory is the ferroelectric memory according to any one of claims 6 to 12; A peripheral device wafer is coupled to the ferroelectric memory.

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