Chip detection method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a chip detection method and device, electronic equipment and storage medium. The method comprises: setting a plurality of to-be-tested chips in a plurality of environments, and inputting a test vector set to the plurality of to-be-tested chips multiple times, collecting electromagnetic radiation curves corresponding to each to-be-tested chip in each input test vector set process under each environment; performing average processing on the plurality of electromagnetic radiation curves corresponding to each to-be-tested chip in each input test vector set process under each environment, to obtain average electromagnetic radiation curves corresponding to the plurality of to-be-tested chips under the plurality of environments; performing feature extraction on the average electromagnetic radiation curves corresponding to the plurality of to-be-tested chips under a target environment, to obtain feature curves corresponding to the plurality of to-be-tested chips under the target environment; performing binary classification training on the feature curves corresponding to the plurality of to-be-tested chips under the target environment, to obtain training result classification differences corresponding to the plurality of to-be-tested chips under the target environment; and determining whether there is hardware malicious logic in the plurality of to-be-tested chips under the target environment.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to a chip testing method, apparatus, electronic device and storage medium. Background Technology

[0002] With the development of the integrated circuit industry, chips are at risk of being compromised by malicious agents, seriously threatening the information security of integrated circuits. However, current chip testing methods typically involve testing each chip sequentially, which results in low chip testing efficiency.

[0003] Therefore, improving the detection efficiency of chips has become an urgent technical problem to be solved. Summary of the Invention

[0004] In view of this, the purpose of this disclosure is to provide a chip testing method, apparatus, electronic device and storage medium to solve or partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, the first aspect of this disclosure provides a chip detection method, the method comprising:

[0006] Multiple chips under test are placed in various environments, and test vector sets are input to the multiple chips under test multiple times. The electromagnetic radiation curves of each chip under test are collected during each input of test vector sets in each environment.

[0007] The average electromagnetic radiation curves corresponding to each chip under test are averaged for each input test vector set under each environment to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test under the various environments.

[0008] Feature extraction is performed on the average electromagnetic radiation curves corresponding to the multiple chips under test in the target environment to obtain the feature curves corresponding to the multiple chips under test in the target environment; wherein, the target environment can be any one of multiple environments;

[0009] Binary classification training is performed on the feature curves corresponding to the multiple chips under test in the target environment to obtain the classification differences of the training results corresponding to the multiple chips under test in the target environment.

[0010] Based on the classification differences of the training results, it is determined whether the multiple chips under test have malicious hardware logic in the target environment;

[0011] The process involves determining that the plurality of chips under test do not have malicious hardware logic in the target environment, then re-determining a new target environment in at least one environment other than the target environment, and judging whether the plurality of chips under test have malicious hardware logic in the new target environment, until all environments have been judged, or the plurality of chips under test have malicious hardware logic in the new target environment.

[0012] If it is determined that the multiple chips under test contain malicious hardware logic in the target environment or the new target environment, the malicious logic analysis is performed on the hardware, and the analysis results are output.

[0013] Based on the same inventive concept, a second aspect of this disclosure proposes a chip detection device, comprising:

[0014] The acquisition module is configured to place multiple chips under test in various environments and input test vector sets to the multiple chips under test multiple times, and acquire the electromagnetic radiation curve corresponding to each chip under test in each environment during each input of test vector sets;

[0015] The averaging module is configured to average the multiple electromagnetic radiation curves corresponding to each chip under test in each input test vector set under each environment, so as to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test under the various environments.

[0016] The feature extraction module is configured to extract features from the average electromagnetic radiation curves corresponding to the plurality of chips under test in the target environment, thereby obtaining the feature curves corresponding to the plurality of chips under test in the target environment; wherein, the target environment can be any of a plurality of environments;

[0017] The binary classification training module is configured to perform binary classification training on the feature curves corresponding to the multiple chips under test in the target environment, and obtain the classification differences of the training results corresponding to the multiple chips under test in the target environment.

[0018] The first judgment module is configured to determine whether the multiple chips under test have malicious hardware logic in the target environment based on the classification differences of the training results.

[0019] The second judgment module is configured to determine that the plurality of chips under test do not have malicious hardware logic in the target environment, re-determine a new target environment in at least one environment other than the target environment, and judge whether the plurality of chips under test have malicious hardware logic in the new target environment, until all environments are judged, or the plurality of chips under test have malicious hardware logic in the new target environment.

[0020] The analysis module is configured to determine that the plurality of chips under test contain malicious hardware logic in the target environment or the new target environment, perform malicious logic analysis on the hardware, and output the analysis results.

[0021] Based on the same inventive concept, a third aspect of this disclosure proposes an electronic device including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method described above when executing the computer program.

[0022] Based on the same inventive concept, a fourth aspect of this disclosure provides a non-transitory computer-readable storage medium that stores computer instructions for causing a computer to perform the methods described above.

[0023] As described above, the chip testing method, apparatus, electronic device, and storage medium provided in this disclosure involve placing multiple chips under test in various environments and repeatedly inputting test vector sets to these chips, collecting the electromagnetic radiation curves corresponding to each chip under test during each input of the test vector set in each environment. This allows for the detection of whether multiple chips under test possess malicious hardware logic in different environments. Based on the classification differences of the training results, the presence of malicious hardware logic in multiple chips under test in the target environment is determined. Thus, while testing a large number of chips of the same batch and model for malicious hardware logic, the efficiency and accuracy of chip testing are effectively improved. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a chip detection method according to an embodiment of the present disclosure;

[0026] Figure 2A This is a flowchart of a chip hardware malicious logic detection method according to an embodiment of this disclosure;

[0027] Figure 2B This is a schematic diagram of the structure of a chip hardware malicious logic detection device according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic diagram of the chip detection device according to an embodiment of the present disclosure;

[0029] Figure 4This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0031] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0032] Based on the background description, with the globalization of the integrated circuit industry, most design, manufacturing, and testing processes have been transferred to untrusted third-party entities around the world. This creates a risk that attackers may insert malicious circuits into the hardware design. Such circuits lurk within the original circuitry, causing it to malfunction when operating under certain values ​​or conditions. These malicious circuits can purposefully modify the original circuitry, such as leaking information to attackers, altering circuit functionality, or even directly damaging the circuit. Hardware Trojans can modify hardware such as Application Specific Integrated Circuits (ASICs), microprocessors, microcontrollers, network processors, and digital signal processors (DSPs), as well as firmware such as the bitstream of Field Programmable Gate Arrays (FPGAs). This seriously threatens the information security of integrated circuits.

[0033] Side-channel information refers to electromagnetic and electromagnetic radiation information related to logic 0 and logic 1 that leaks out when electronic devices are operating. Side-channel analysis methods utilize the side-channel information leaked by cryptographic chips during encryption and decryption operations, combined with various analytical methods such as observation and comparison, differential calculation, statistical classification, and normal distribution analysis, to analyze cryptographic systems. Using side-channel analysis, sensitive information related to secret information can be gradually extracted, and sometimes even the key can be directly obtained. When a chip contains malicious logic, additional electromagnetic radiation will be generated during encryption operations. By analyzing and comparing the side-channel information related to electromagnetic radiation, the presence of malicious hardware logic in the chip under test can be detected. However, for large-scale testing of chips, the detection of malicious hardware logic suffers from problems such as long detection processes and low detection efficiency. The threat of malicious hardware logic to information security systems is increasing, and research on malicious hardware logic detection has high application value and significant practical importance for the detection of large quantities of chips.

[0034] To address the shortcomings of the aforementioned batch chip testing methods, this embodiment proposes a hardware malicious logic detection method based on mutual verification of differences in chip electromagnetic side-channel information features. This method involves collecting side-channel information of the strongest electromagnetic radiation points of security chips of the same batch and model under different environments during encryption operations. Gaussian filtering is used to preprocess the collected electromagnetic radiation information for noise reduction. A nonlinear fitting algorithm is used to compensate for process deviations. Independent Component Analysis (ICA) and deep learning methods are employed to extract features from the preprocessed average electromagnetic radiation curves. Statistical methods are then used to perform feature difference mutual verification and correlation analysis on these power consumption curves. Based on the analysis results, the method can detect whether a large batch of chips of the same model possesses hardware malicious logic.

[0035] To improve the efficiency and accuracy of detecting malicious hardware logic in chips under test (TBD), this embodiment describes a hardware malicious logic detection method based on mutual verification of feature differences at the strongest point of electromagnetic radiation on the chip. This method can improve the detection efficiency for testing a large number of chips, helping companies discover chip-level security defects, mitigate security risks, and improve product functionality.

[0036] As mentioned above, improving the detection efficiency of chips has become an important research question.

[0037] Based on the above description, such as Figure 1 As shown, the chip detection method proposed in this embodiment includes:

[0038] Step 101: Set multiple chips under test in various environments and input test vector sets to the multiple chips under test multiple times, and collect the electromagnetic radiation curves of each chip under test corresponding to each input test vector set in each environment.

[0039] In practice, the multiple environments include at least one of the following: multiple temperature environments, multiple humidity environments, multiple voltage environments, multiple pH environments, and multiple radiation environments. The test vector set contains multiple sets of test vectors, such as q > 10. Each set of test vectors contains plaintext and a key.

[0040] Before step 101, the process includes: performing a conformance check and a self-test on the chips. Specifically, each batch of chips undergoes a conformance check to determine if it meets the specified requirements. Chips that meet the requirements are then subjected to a self-test. The self-test checks whether the chip functions correctly. The chip is run using the Advanced Encryption Standard (AES) symmetric encryption algorithm, with a random plaintext sequence and key input. The actual circuit encryption result is compared point-by-point with the software encryption result. If the encryption results match, it indicates that the circuit's logical function is correct. Chips with correct results are then used as candidates for subsequent testing to detect malicious hardware logic.

[0041] Step 102: Average the multiple electromagnetic radiation curves corresponding to each chip under test in each input test vector set under each environment to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test under the various environments.

[0042] In practice, the multiple electromagnetic radiation curves corresponding to each chip under test are averaged for each input test vector set under each environment to obtain the average electromagnetic radiation curves corresponding to multiple chips under test under each environment.

[0043] The average electromagnetic radiation curves of multiple chips under test in each environment are summarized to obtain the average electromagnetic radiation curves of the multiple chips under test in various environments.

[0044] Step 103: Extract features from the average electromagnetic radiation curves of the multiple chips under test in the target environment to obtain the feature curves of the multiple chips under test in the target environment; wherein, the target environment can be any of multiple environments.

[0045] In practice, the target environment is determined from multiple environments, and the presence of malicious hardware logic in multiple chips under test in the target environment is first judged.

[0046] Effective point features and peak features are extracted from the average electromagnetic radiation curves of multiple chips under test in the target environment. The effective point features and peak features are then combined to obtain the feature curve corresponding to each chip under test in the target environment.

[0047] Step 104: Perform binary classification training on the feature curves corresponding to the multiple chips under test in the target environment to obtain the training result classification differences corresponding to the multiple chips under test in the target environment.

[0048] In practice, in the feature difference mutual verification module, the feature curves corresponding to multiple chips under test in the target environment are trained by binary classification to obtain the classification difference of the training results corresponding to multiple chips under test in the target environment.

[0049] Among them, the training result classification difference represents the magnitude of the difference between multiple chips under test in the target environment, and the training result classification difference is expressed as a percentage.

[0050] Step 105: Based on the classification differences of the training results, determine whether the multiple chips under test have malicious hardware logic in the target environment.

[0051] In practice, the differences in the training results are compared with a preset difference threshold, and the comparison results are used to determine whether multiple chips under test have malicious hardware logic in the target environment.

[0052] Step 106: Determine that the plurality of chips under test do not have malicious hardware logic in the target environment, re-determine a new target environment in at least one environment other than the target environment, and judge whether the plurality of chips under test have malicious hardware logic in the new target environment, until all environments have been judged, or the plurality of chips under test have malicious hardware logic in the new target environment.

[0053] In practice, if multiple chips under test (DUTs) exhibit malicious hardware logic in the target environment, step 107 is executed. If multiple DUTs do not exhibit malicious hardware logic in the target environment, the system checks whether malicious hardware logic exists in other environments. If malicious hardware logic exists in other environments, step 107 is executed; if malicious hardware logic does not exist in any of the multiple environments, the process ends. "Other environments" refers to environments other than the target environment.

[0054] For example, after determining that multiple chips under test do not contain malicious hardware logic in the target environment, a new target environment is determined in at least one environment other than the target environment. Steps 103 to 106 are then executed to determine whether the multiple chips under test contain malicious hardware logic in the new target environment. If it is determined that multiple chips under test contain malicious hardware logic in the new target environment, step 107 is executed. If it is determined that multiple chips under test do not contain malicious hardware logic in any of the multiple environments, the process ends.

[0055] Step 107: Determine that the multiple chips under test contain malicious hardware logic in the target environment or the new target environment, perform malicious logic analysis on the hardware, and output the analysis results.

[0056] In practice, it is determined that multiple chips under test have malicious hardware logic in the target environment or a new target environment, the hardware is analyzed for malicious logic, and the analysis results are output.

[0057] Specifically, when multiple chips under test contain malicious hardware logic in the target environment or a new target environment, the multiple chips under test are grouped to obtain multiple groups of chips under test, and the malicious hardware logic is detected in each of the grouped chips under test. The target chip containing malicious hardware logic is then identified from the multiple chips under test.

[0058] For example, when multiple chips under test have malicious hardware logic in the target environment or a new target environment, the multiple chips under test are divided into two groups, and steps 103 to 106 are executed on the two groups of chips under test respectively, that is, the two groups of chips under test are tested for malicious hardware logic, and the target chip group with malicious hardware logic is determined from the two groups of chips under test. The chips under test in the target chip group are further grouped, and the above steps are repeated until the target chip with malicious hardware logic is determined.

[0059] Through the above embodiments, multiple chips under test (DUTs) are placed in various environments, and test vector sets are input to these DUTs multiple times. Electromagnetic radiation curves for each DUT are collected during each input of the test vector set in each environment. This allows for the detection of whether multiple DUTs exhibit malicious hardware logic in different environments. Based on the classification differences from the training results, the presence of malicious hardware logic in the target environment is determined. This effectively improves the efficiency and accuracy of chip detection while testing a large number of chips of the same batch and model for malicious hardware logic.

[0060] In some embodiments, step 101 includes:

[0061] Step 1011: Based on the pre-set scanning parameters, determine the number of N target scanning points in the target scanning area where the radiation signal of each chip under test is strongest.

[0062] Step 1012: Set the k chips under test in b types of environments, and perform c times on the target scanning area of ​​the N target scanning points of the k chips under test; wherein, the test vector set includes q sets of test vectors, and each set of test vectors contains plaintext and key.

[0063] Step 1013: Collect the electromagnetic radiation curves corresponding to the k chips under test during the process of executing the test vector set on the k chips under test c times under b environments; wherein, the electromagnetic radiation curves corresponding to each chip under test under the target environment are N×c×q; and the electromagnetic radiation curves corresponding to each chip under test under b environments are (N×c×b)×q.

[0064] In practice, N target scanning areas with the strongest radiation signals are selected as the scanning locations for subsequent batch detection of malicious logic in the chip under test. This results in more significant characteristic and difference in the electromagnetic information curves, making it more conducive to the detection of malicious hardware logic.

[0065] Establish a test vector set for the chip under test. Each test vector set contains plaintext and a key. The number of test vectors in the test vector set is q > 10, so as to facilitate the subsequent encryption operation process.

[0066] K chips of the same batch and model (3≤k≤j, where j is the maximum number of chips the test system can accommodate) are placed in the side-channel acquisition test system for functional testing. The test system, according to user settings, inputs the test vector set into the chips under test sequentially for encryption operations. It also collects the electromagnetic radiation curve of each chip under test during operation using an electromagnetic probe and transmits the curves to the host computer for further analysis.

[0067] Due to the covert nature of malicious hardware logic, its activation state will inevitably differ in different environments. The chip under test (DUT) is placed in b different environments. In each environment, the same test vector set is input to each DUT, and the operation is performed c times (c≥30), collecting the electromagnetic radiation curve for each encryption process. The presence and absence of malicious logic circuitry in the DUT within the same environment will inevitably lead to significant differences in the corresponding computation times on the electromagnetic radiation curves, and their corresponding average electromagnetic radiation curves will also differ. The differences between two identical DUTs in different environments will vary; the greater the difference, the more active the malicious hardware logic is in that environment.

[0068] Using the above method, k chips under test are placed in b environments, and the target scanning area of ​​the N target scanning points of the k chips under test is input to the test vector set and executed c times. This yields (N×c×b)×q electromagnetic radiation curves for each chip under test in b environments. By analyzing and processing these (N×c×b)×q electromagnetic radiation curves, accurate detection of malicious hardware logic in the chips under test can be achieved.

[0069] In some embodiments, step 1011 includes:

[0070] Step 1011A: Determine the initial number of scan points from the preset scan parameters.

[0071] In practice, a scanning path is planned based on the selected area, and then scanning parameters are set, including the number of scans, scanning interval, and scanning speed. The method of scanning the point with the strongest electromagnetic information is adopted. First, the size of the chip under test is determined, and electromagnetic probes with different accuracies are selected for different chip sizes. The relationship between probe resolution and chip size is weighed according to the actual situation to determine the number of scanning data points. For example, the initial number of scanning points can be set to 25 (5×5) or 100 (10×10). Assuming the length and width of the chip under test are both l, and the initial number of scanning points is (n×n), the distance between two adjacent points is expressed as:

[0072]

[0073] Where D is the distance between two adjacent scan data points; l is the length and width of the chip under test; and n×n is the initial number of scan points.

[0074] Step 1011B: Multiply the initial number of scan points with the preset radiation signal parameters to obtain the N target scan points in the target scan region where the radiation signal of each chip under test is strongest.

[0075] N = n × n × m

[0076] Wherein, n×n is the initial number of scan points, and m is the preset radiation signal parameter.

[0077] In practice, the preset radiation signal parameters are the ratio coefficients between the initial number of scan points and the target number of scan points.

[0078] For example, if the preset radiation signal parameter is 10%, then the number of N target scan points in the target scan region where the radiation signal of each chip under test is strongest is represented as:

[0079] N = n × n × 10%

[0080] Where N is the number of target scan points; n×n is the initial number of scan points; and 10% is the preset radiation signal parameter.

[0081] The above scheme determines the scanning parameters based on the size of the chip under test (DUT), making the initial number of scan points more accurate. Furthermore, for DUTs of different sizes, electromagnetic probes of varying precision can be selected to accurately acquire the electromagnetic radiation curves of the DUT. Additionally, multiplying the initial number of scan points with preset radiation signal parameters further enhances the accuracy of the determined target scan point count.

[0082] In some embodiments, step 102 includes:

[0083] Step 1021: For each environment, the target scanning area of ​​the N target scanning points of the k chips under test is input to the test vector set and executed c times. The N×c×q electromagnetic radiation curves corresponding to each chip under test are averaged to obtain b×k average electromagnetic radiation curves corresponding to the multiple chips under test in the multiple environments.

[0084] In practice, the N×c×q electromagnetic radiation curves corresponding to each chip under test are averaged to obtain b×k average electromagnetic radiation curves corresponding to multiple chips under test in multiple environments.

[0085]

[0086]

[0087] …

[0088]

[0089] in, and The average electromagnetic radiation curves of multiple chips under test are shown in different environments. 1 represents the average electromagnetic radiation curves of multiple chips under test in the first environment; 2 represents the average electromagnetic radiation curves of multiple chips under test in the second environment; 3 represents the average electromagnetic radiation curves of multiple chips under test in the b-th environment; c represents the number of encryption operations executed; q represents the number of test vector groups. The electromagnetic radiation curves collected from N target scanning points when the encryption operation is performed c times on k chips under test using q sets of test vectors in environment b. This indicates that the electromagnetic radiation curves corresponding to the number of encryption operations executed from 1 to c are summed. This indicates that the electromagnetic radiation curves corresponding to test vector groups ranging from 1 to q are summed.

[0090] The above scheme, by averaging the electromagnetic radiation curves corresponding to each chip under test, makes the average electromagnetic radiation curves of multiple chips under test under multiple environments more accurate.

[0091] In some embodiments, step 103 includes:

[0092] Step 1031: Extract effective point features from the average electromagnetic radiation curves of the multiple chips under test in the target environment using the independent component analysis algorithm to obtain effective point features.

[0093] In practice, Independent Component Analysis (ICA) is used to extract features from the preprocessed average electromagnetic radiation curve. The effective point features can better reflect the characteristics of the average electromagnetic radiation curve.

[0094] Step 1032: Peak features are extracted from the average electromagnetic radiation curves of the multiple chips under test in the target environment using a deep learning algorithm.

[0095] In practice, deep learning methods are used to automatically extract peak features from the average electromagnetic radiation curve. Peak features that reflect the peak weights of electromagnetic leakage information have a better effect on peak points.

[0096] Step 1033: Based on the effective point features and the peak features, determine the feature curve corresponding to each chip under test in the target environment.

[0097] In practice, effective point features and peak features are processed together to obtain the feature curves corresponding to each chip under test in the target environment.

[0098] Through the above scheme, the effective point feature can better reflect the characteristics of the average electromagnetic radiation curve, while the peak feature better reflects the peak points corresponding to the peak weights of electromagnetic leakage information. By summarizing the effective point feature and the peak feature, the characteristic curve corresponding to each chip under test in a defined target environment can simultaneously reflect both the effective point feature and the peak feature of the average electromagnetic radiation curve.

[0099] In some embodiments, prior to step 103, the method further includes:

[0100] Step 103A: The average electromagnetic radiation curve is filtered using a Gaussian filtering algorithm to obtain the filtered average electromagnetic radiation curve.

[0101] In practice, since electromagnetic radiation is a weak signal and is easily affected by internal circuit noise and external environmental noise during the acquisition process, a Gaussian filtering algorithm is used to preprocess the acquired average electromagnetic radiation curve to reduce noise and improve the signal-to-noise ratio.

[0102] Step 103B: The average electromagnetic radiation curve after filtering is compensated by a nonlinear fitting algorithm to obtain the compensated average electromagnetic radiation curve.

[0103] In practice, a nonlinear fitting algorithm is used to quantify and compensate for the magnitude of process deviations. As the area ratio of malicious logic circuits in the hardware gradually decreases, the resulting differences in side-channel information are easily hidden within these deviations, thus requiring compensation.

[0104] The above scheme utilizes a Gaussian filtering algorithm to filter the average electromagnetic radiation curve, achieving noise reduction preprocessing and improving the signal-to-noise ratio. A nonlinear fitting algorithm is then used to compensate for the filtered average electromagnetic radiation curve, making it more accurate and reducing the impact of process deviations on the average electromagnetic radiation curve.

[0105] In some embodiments, step 105 includes:

[0106] Step 1051: Compare the differences in the training results with a preset difference threshold.

[0107] Step 1052: In response to the difference in the training result analysis being less than or equal to the difference threshold, it is determined that the plurality of chips under test do not have malicious hardware logic in the target environment.

[0108] Step 1053: In response to the difference in the training result analysis being greater than the difference threshold, it is determined that the plurality of chips under test have malicious hardware logic in the target environment.

[0109] In practice, the differences in the training results are compared with a preset difference threshold. The differences in the training results are expressed as a percentage.

[0110] For example, with a preset difference threshold of 0.2, if the difference in the training results analysis is less than or equal to 0.2, it is determined that multiple chips under test do not have malicious hardware logic in the target environment; if the difference in the training results analysis is greater than 0.2, it is determined that at least one of the multiple chips under test contains malicious hardware logic in the target environment. For example, with a preset difference threshold of 0.5, if the difference in the training results analysis is less than or equal to 0.5, it is determined that multiple chips under test do not have malicious hardware logic in the target environment; if the difference in the training results analysis is greater than 0.5, it is determined that at least one of the multiple chips under test contains malicious hardware logic in the target environment.

[0111] By using the above scheme, and comparing the differences in the training results with the preset difference threshold, it is possible to accurately determine whether any chip under test has malicious hardware logic in the target environment among multiple chips under test. At the same time, it is possible to achieve large-scale detection of chips under test and improve the detection efficiency of chips under test.

[0112] Through the above embodiments, multiple chips under test (DUTs) are placed in various environments, and test vector sets are input to these DUTs multiple times. Electromagnetic radiation curves for each DUT are collected during each input of the test vector set in each environment. This allows for the detection of whether multiple DUTs exhibit malicious hardware logic in different environments. Based on the classification differences from the training results, the presence of malicious hardware logic in the target environment is determined. This effectively improves the efficiency and accuracy of chip detection while testing a large number of chips of the same batch and model for malicious hardware logic.

[0113] It should be noted that the embodiments of this disclosure can also be further described in the following ways:

[0114] like Figure 2A As shown, Figure 2A This is a flowchart of a chip hardware malicious logic detection method according to an embodiment of this disclosure. The chip hardware malicious logic detection method includes:

[0115] Step 20A: Consistency verification and self-test of the chip under test.

[0116] Step 20B: After scanning the electromagnetic information of the chip under test several times, the scan points are selected, and the point with the strongest electromagnetic radiation is selected as the subsequent information collection point.

[0117] Step 20C: Run the encryption algorithm in different environments and collect the electromagnetic radiation curves of the chip under test during operation.

[0118] Step 20D: Use a Gaussian filtering algorithm to reduce noise in the electromagnetic information.

[0119] Step 20E: Compensate for process deviations using a nonlinear fitting algorithm.

[0120] Step 20F involves extracting peak features using independent component analysis and deep learning algorithms.

[0121] Step 20G involves performing binary classification training on the obtained electromagnetic feature curves in the feature difference mutual verification module.

[0122] Step 20H: Detect whether any chips in the batch of chips to be tested contain malicious hardware logic.

[0123] A hardware malicious logic detection method based on mutual verification of differences in chip electromagnetic side channel information features specifically includes:

[0124] Step 1: Perform a quality consistency inspection on each batch of chips to determine whether the chips meet the specified requirements. For chips that meet the requirements, proceed to the self-test in Step 2.

[0125] Step 2: Perform a self-test on the chip, i.e., check if the chip is functioning correctly. Run the chip with the Advanced Encryption Standard (AES) symmetric encryption algorithm, input a random plaintext sequence and key, and compare the actual circuit encryption result with the software encryption result point by point. If the encryption results match, it means that the logic function of the circuit is correct. The chip with the correct result is selected as the chip to be tested for subsequent detection of malicious hardware logic.

[0126] Step 3: Set up the test environment. Install the chip under test (DUT) on the chip test motherboard, connecting the metal contacts of the motherboard to the pins of the DUT. Place the chip test motherboard and the DUT into the test system, which includes a test platform, oscilloscope, current probe, and high-frequency signal lines.

[0127] Step 4: Initialize the test parameters of the chip under test and the test environment, such as setting the power supply voltage, input signal timing, oscilloscope input impedance, sampling frequency, number of sampling points, bandwidth, time base and trigger mode.

[0128] Step 5: Establish a test vector set for the chip under test. Each test vector set contains plaintext and a key. The number of test vectors in the test vector set is q > 10, so as to facilitate the subsequent encryption operation process.

[0129] Step 6: Place k chips of the same batch and model (3≤k≤j, where j is the maximum number of chips the test system can accommodate) into the side-channel acquisition test system and perform functional testing. The test system, according to user settings, inputs the test vector set into the chips under test sequentially to perform encryption operations. It also collects the electromagnetic radiation curve of each chip under test during operation using an electromagnetic probe and transmits the curve to the host computer for further analysis.

[0130] Step 7: Based on the difference in electromagnetic radiation during operation with and without malicious hardware logic, feature extraction is performed on the electromagnetic radiation curve. The basic assumption is that, according to the principle that a changing electric field generates a magnetic field, the changes in the electric field of the algorithm circuit during operation can be reflected through electromagnetic radiation. During the execution of the same cryptographic operation instructions by the chip, its electromagnetic radiation leakage depends on the internal circuitry. Furthermore, the electromagnetic radiation of a chip without malicious hardware logic depends only on the algorithm circuit, while the electromagnetic radiation of a chip containing malicious hardware logic depends on both the algorithm circuit and the malicious logic circuit. Clearly, the electromagnetic radiation leakage information will differ between the two. The specific implementation process is shown in steps 8 to 15.

[0131] Step 8: Place the electromagnetic probe above each chip under test. During operation, the encrypted chip radiates electromagnetic radiation closely related to the encrypted content. Chips containing malicious hardware logic will radiate additional electromagnetic radiation. The near-field electromagnetic probe can collect the radiation within a certain range of the chip under test. Because electromagnetic radiation is a weak signal, the near-field electromagnetic probe has a built-in amplifier to amplify the signal for easier subsequent processing. An oscilloscope is used to display the signal waveform and transmit it to the host computer. The electromagnetic information acquisition method is shown in steps 9 to 12.

[0132] Step 9: Acquire image information within the field of view. Through noise reduction and deblurring, highlight the necessary details. Use the pixel coordinates of the image to delineate the scanning area and select the scanning start point. Save the coordinates of the scanning start point; subsequent identical detection experiments will directly use the saved coordinates.

[0133] Step 10: Plan the scanning path based on the selected area, and then set the scanning parameters, including the number of scans, scanning interval, and scanning speed. The method of scanning the point with the strongest electromagnetic information is adopted. First, determine the size of the chip under test. For chips of different sizes, select electromagnetic probes with different accuracies. Based on the actual situation, weigh the relationship between probe resolution and chip size to determine the number of scanning data points. For example, set the initial number of scanning points to 25 (5×5) or 100 (10×10). Assume the length and width of the chip under test are both l, and the initial number of scanning points is (n×n). Then the distance between two adjacent points is expressed as:

[0134]

[0135] Where D is the distance between two adjacent scan data points; l is the length and width of the chip under test; and n×n is the initial number of scan points.

[0136] Step 11: The host computer converts the coordinate information of the scanning starting point into corresponding instructions and sends them to the controller of the displacement platform to control the electromagnetic probe to move accordingly and complete the positioning of the scanning starting point. According to the scanning area and number of data set by the host computer, the corresponding scanning route is planned, the distance of each movement of the electric displacement stage is determined, and after the scanning is completed, the electromagnetic probe is moved back to the scanning starting point, and the electromagnetic information data (i.e., the electromagnetic radiation curve) is recorded.

[0137] Step 12: Screening the scan points of the chip under test. After performing a (a>5) full scans on the chip under test (steps 10 to 11), the data from all scan points (a sets) are averaged, and N points with the strongest radiation signals (N is calculated using the formula below, rounded up) are selected as the scan locations for subsequent batch detection of malicious hardware logic on the chip under test. The resulting electromagnetic information curves exhibit more significant characteristics and differences, making them more conducive to the detection of malicious hardware logic.

[0138] N = n × n × 10%

[0139] Step 13: Due to the covert nature of malicious hardware logic, its activation state will inevitably differ in different environments. Place the chip under test in b different environments, such as different temperature environments, different humidity environments, and different voltage environments. In each environment, input the same test vector set to each chip under test, execute c (c≥30) times, and collect the electromagnetic radiation curve for each encryption process. Then, chips under test containing and not containing malicious logic circuitry in the same environment will inevitably cause significant differences in the corresponding operation times on the electromagnetic radiation curves, and their corresponding average electromagnetic radiation curves will also inevitably differ. The differences between the same two chips under test in different environments will vary; the greater the difference, the more active the malicious hardware logic is in that environment.

[0140] Step 14: The electromagnetic radiation curve of each chip under test in each environment contains N points (the selected points of strongest electromagnetic radiation, i.e., the scanning points), which can be represented as follows: Where b represents the environment, k is the number of chips under test, and each scan point performs c encryption operations on q test vectors. The (c×q) data points collected from each scan point of each chip under test in each environment are averaged to obtain (b×k) electromagnetic curves, improving the signal-to-noise ratio. This is illustrated in the following formula.

[0141]

[0142]

[0143] …

[0144]

[0145] in, and The average electromagnetic radiation curves of multiple chips under test are shown in different environments. 1 represents the average electromagnetic radiation curves of multiple chips under test in the first environment; 2 represents the average electromagnetic radiation curves of multiple chips under test in the second environment; 3 represents the average electromagnetic radiation curves of multiple chips under test in the b-th environment; c represents the number of encryption operations executed; q represents the number of test vector groups. The electromagnetic radiation curves collected from N target scanning points when the encryption operation is performed c times on k chips under test using q sets of test vectors in environment b. This indicates that the electromagnetic radiation curves corresponding to the number of encryption operations executed from 1 to c are summed. This indicates that the electromagnetic radiation curves corresponding to test vector groups ranging from 1 to q are summed.

[0146] Step 15: Since electromagnetic radiation is a weak signal and is easily affected by internal circuit noise and external environmental noise during the acquisition process, this embodiment uses a Gaussian filtering algorithm to perform noise reduction preprocessing on the acquired electromagnetic radiation curve to improve the signal-to-noise ratio.

[0147] Step 16: Quantify and compensate for the magnitude of process deviations using a nonlinear fitting algorithm. As the area ratio of malicious logic circuits in the hardware gradually decreases, the resulting differences in side-channel information are easily hidden within these deviations, thus requiring compensation.

[0148] Step 17: Use Independent Component Analysis (ICA) to extract features from the preprocessed average electromagnetic radiation curve. Effective point features can better reflect the characteristics of the average electromagnetic radiation curve.

[0149] Step 18: Using deep learning methods, peak features in the average electromagnetic radiation curve are automatically extracted. Peak features that reflect the peak weights of electromagnetic leakage information have a better effect on peak points.

[0150] Step 19: After steps 5 to 19, a total of b×k electromagnetic radiation curves are obtained from k chips under test. The characteristic curves from different chips under test in the same environment are then processed in the characteristic difference mutual verification module. This is detailed in steps 20 to 22.

[0151] Step 20: In the feature difference mutual verification module, feature curves from different chips under test in the same environment are trained using binary classification. If the percentage difference in the training results is less than or equal to 0.2, the same training operation is performed in the next environment. If the percentage difference in the training results of different chips under test in all different environments is less than or equal to 0.2, a pass test is performed, indicating that all chips under test do not contain malicious hardware logic. If the percentage difference in the training results is greater than 0.2, it indicates that at least one of the k chips under test has output data that does not conform to the expected logical state, and this test result is recorded as the presence of malicious hardware logic.

[0152] Step 21: If the test results are recorded as indicating the presence of malicious hardware logic, divide the k chips under test into two equal parts and repeat steps 6 to 20 to gradually narrow down the test scope until the chip under test with malicious hardware logic is found.

[0153] Step 22: Once all chips under test have passed through the testing system, the testing is complete.

[0154] like Figure 2B As shown, Figure 2B This is a schematic diagram of the chip hardware malicious logic detection device according to an embodiment of the present disclosure. The chip hardware malicious logic detection device includes: an electromagnetic radiation strongest point curve acquisition module 20a, a data preprocessing and curve feature extraction module 20b, and a feature difference mutual verification and detection module 20c.

[0155] The above embodiments effectively improve the efficiency and accuracy of testing for malicious hardware logic in a large number of chips of the same batch and model. No extensive professional knowledge is required from operators, enabling rapid and accurate detection of malicious hardware logic in large batches of chips. Furthermore, for enterprises, the earlier malicious hardware logic is detected in chips, the lower the production and manufacturing costs, saving valuable time for design and manufacturing. Simultaneously, it helps enterprises discover chip-level security flaws, mitigate security risks, and improve product functionality, providing corresponding testing methods and safeguards for the development of chip security and the rapid implementation of national cryptographic technologies in chips.

[0156] It should be noted that the method of this disclosure embodiment can be executed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method of this disclosure embodiment, and the multiple devices will interact with each other to complete the method described.

[0157] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0158] Based on the same inventive concept, corresponding to any of the above embodiments, this disclosure also provides a chip testing device.

[0159] refer to Figure 3 The chip detection device includes:

[0160] The acquisition module 301 is configured to place multiple chips under test in multiple environments, input test vector sets to the multiple chips under test multiple times, and acquire the electromagnetic radiation curve of each chip under test in each environment during each input of test vector sets.

[0161] The averaging module 302 is configured to average the multiple electromagnetic radiation curves corresponding to each chip under test in each input test vector set under each environment, so as to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test under the multiple environments.

[0162] The feature extraction module 303 is configured to extract features from the average electromagnetic radiation curves corresponding to the plurality of chips under test in the target environment, and obtain the feature curves corresponding to the plurality of chips under test in the target environment; wherein, the target environment can be any one of a plurality of environments;

[0163] The binary classification training module 304 is configured to perform binary classification training on the feature curves corresponding to the multiple chips under test in the target environment, and obtain the training result classification difference corresponding to the multiple chips under test in the target environment.

[0164] The first judgment module 305 is configured to judge whether the multiple chips under test have malicious hardware logic in the target environment based on the classification differences of the training results.

[0165] The second judgment module 306 is configured to determine that the plurality of chips under test do not have malicious hardware logic in the target environment, re-determine a new target environment in at least one environment other than the target environment, and judge whether the plurality of chips under test have malicious hardware logic in the new target environment, until all environments are judged, or the plurality of chips under test have malicious hardware logic in the new target environment.

[0166] The analysis module 307 is configured to determine that the plurality of chips under test contain malicious hardware logic in the target environment or the new target environment, perform malicious logic analysis on the hardware, and output the analysis results.

[0167] In some embodiments, the acquisition module 301 includes:

[0168] The target scan point determination unit is configured to determine the number of N target scan points in the target scan region where the radiation signal of each chip under test is strongest, based on pre-set scan parameters.

[0169] The test vector input unit is configured to set k chips under test in b environments and input a test vector set to the target scanning area of ​​the N target scanning points of the k chips under test and execute it c times; wherein, the test vector set includes q sets of test vectors, and each set of test vectors contains plaintext and a key;

[0170] The acquisition unit is configured to acquire the electromagnetic radiation curves corresponding to the k chips under test during the process of executing the input test vector set on the k chips under test c times under b environments; wherein, the electromagnetic radiation curves corresponding to each chip under test under the target environment are N×c×q; and the electromagnetic radiation curves corresponding to each chip under test under the b environments are (N×c×b)×q.

[0171] In some embodiments, the target scan point determination unit includes:

[0172] The initial scan point number determination subunit is configured to determine the initial scan point number from preset scan parameters;

[0173] The target scan point determination subunit is configured to multiply the initial scan point number with preset radiation signal parameters to obtain the number of N target scan points in the target scan region where the radiation signal of each chip under test is strongest.

[0174] N = n × n × m

[0175] Wherein, n×n is the initial number of scan points, and m is the preset radiation signal parameter.

[0176] In some embodiments, the averaging module 302 includes:

[0177] The averaging unit is configured to perform c times on the target scan area input test vector set of the N target scan points of k chips under test in each environment, and to average the N×c×q electromagnetic radiation curves corresponding to each chip under test to obtain b×k average electromagnetic radiation curves corresponding to the multiple chips under test in the multiple environments.

[0178] In some embodiments, the feature extraction module 303 includes:

[0179] The effective point feature extraction unit is configured to extract effective point features from the average electromagnetic radiation curves corresponding to the multiple chips under test in the target environment using an independent component analysis algorithm, thereby obtaining effective point features.

[0180] The peak feature extraction unit is configured to extract peak features from the average electromagnetic radiation curves corresponding to the multiple chips under test in the target environment using a deep learning algorithm, thereby obtaining peak features.

[0181] The feature curve unit is configured to determine the feature curve corresponding to each chip under test in the target environment based on the effective point features and the peak features.

[0182] In some embodiments, the apparatus further includes:

[0183] The filtering module is configured to perform filtering on the average electromagnetic radiation curve using a Gaussian filtering algorithm to obtain the filtered average electromagnetic radiation curve.

[0184] The compensation processing module is configured to perform compensation processing on the filtered average electromagnetic radiation curve using a nonlinear fitting algorithm to obtain the compensated average electromagnetic radiation curve.

[0185] In some embodiments, the first determining module 305 includes:

[0186] The comparison processing unit is configured to analyze the differences in the training results and compare them with a preset difference threshold.

[0187] The first result determination unit is configured to determine, in response to the training result analysis difference being less than or equal to the difference threshold, that the plurality of chips under test do not have malicious hardware logic in the target environment.

[0188] The second result determination unit is configured to determine, in response to the training result analysis difference being greater than the difference threshold, that the plurality of chips under test have malicious hardware logic in the target environment.

[0189] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, in implementing this disclosure, the functions of each module can be implemented in one or more software and / or hardware.

[0190] The apparatus of the above embodiments is used to implement the corresponding chip detection method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0191] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the chip detection method described in any of the above embodiments.

[0192] Figure 4 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0193] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0194] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0195] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0196] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB (Universal Serial Bus), network cable, etc.) or wireless means (such as mobile network, WIFI (Wireless Fidelity), Bluetooth, etc.).

[0197] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0198] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0199] The electronic devices described above are used to implement the corresponding chip detection methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0200] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions for causing the computer to execute the chip detection method as described in any of the above embodiments.

[0201] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0202] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the chip detection method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0203] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0204] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuitry) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0205] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0206] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A chip detection method, characterized in that, The method includes: Multiple chips under test are placed in various environments, and test vector sets are input to the multiple chips under test multiple times. The electromagnetic radiation curves of each chip under test are collected during each input of test vector sets in each environment. The average electromagnetic radiation curves corresponding to each chip under test are averaged for each input test vector set under each environment to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test under the various environments. Feature extraction is performed on the average electromagnetic radiation curves corresponding to the multiple chips under test in the target environment to obtain the feature curves corresponding to the multiple chips under test in the target environment; wherein, the target environment can be any one of multiple environments; Binary classification training is performed on the feature curves corresponding to the multiple chips under test in the target environment to obtain the classification differences of the training results corresponding to the multiple chips under test in the target environment. Based on the classification differences of the training results, it is determined whether the multiple chips under test have malicious hardware logic in the target environment; The process involves determining that the plurality of chips under test do not have malicious hardware logic in the target environment, then re-determining a new target environment in at least one environment other than the target environment, and judging whether the plurality of chips under test have malicious hardware logic in the new target environment, until all environments have been judged, or the plurality of chips under test have malicious hardware logic in the new target environment. If it is determined that the multiple chips under test contain malicious hardware logic in the target environment or the new target environment, the malicious logic analysis is performed on the hardware, and the analysis results are output.

2. The method according to claim 1, characterized in that, The process involves placing multiple chips under test (DUTs) in various environments and repeatedly inputting test vector sets to the multiple DUTs, collecting the electromagnetic radiation curves corresponding to each DUT during each input of test vector sets in each environment, including: Based on the pre-set scanning parameters, determine the number of N target scanning points in the target scanning area where the radiation signal of each chip under test is strongest; K chips under test are set up in b types of environments, and a test vector set is input to the target scanning area of ​​the N target scanning points of the k chips under test and executed c times; wherein, the test vector set includes q sets of test vectors, and each set of test vectors contains plaintext and key; The electromagnetic radiation curves corresponding to the k chips under test are collected during the process of executing the test vector set c times under b environments; wherein, the electromagnetic radiation curves corresponding to each chip under test under the target environment are N×c×q; and the electromagnetic radiation curves corresponding to each chip under test under b environments are (N×c×b)×q.

3. The method according to claim 2, characterized in that, The process of determining the number of N target scan points in the target scan region with the strongest radiation signal for each chip under test based on pre-set scan parameters includes: The initial number of scan points is determined from the preset scan parameters; The initial number of scan points is multiplied by the preset radiation signal parameters to obtain the N target scan points in the target scan region where the radiation signal of each chip under test is strongest. N = n × n × m Wherein, n×n is the initial number of scan points, and m is the preset radiation signal parameter.

4. The method according to claim 2, characterized in that, The step of averaging multiple electromagnetic radiation curves corresponding to each chip under test in each input test vector set under each environment to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test in the various environments includes: For each of the k chips under test in each environment, the target scanning area of ​​the N target scanning points is input to the test vector set and executed c times. The N×c×q electromagnetic radiation curves corresponding to each chip under test are averaged to obtain b×k average electromagnetic radiation curves corresponding to the multiple chips under test in the various environments.

5. The method according to claim 1, characterized in that, The step of extracting features from the average electromagnetic radiation curves corresponding to the multiple chips under test in the target environment to obtain the feature curves corresponding to the multiple chips under test in the target environment includes: Effective point features are obtained by extracting effective point features from the average electromagnetic radiation curves of the multiple chips under test in the target environment using the independent component analysis algorithm. Peak features are obtained by extracting peak features from the average electromagnetic radiation curves of the multiple chips under test in the target environment using a deep learning algorithm. Based on the effective point features and the peak features, the characteristic curve corresponding to each chip under test in the target environment is determined.

6. The method according to claim 1, characterized in that, Before extracting features from the average electromagnetic radiation curves corresponding to the multiple chips under test in the target environment to obtain the feature curves corresponding to the multiple chips under test in the target environment, the method further includes: The average electromagnetic radiation curve is filtered by a Gaussian filtering algorithm to obtain the filtered average electromagnetic radiation curve. The average electromagnetic radiation curve after filtering is compensated by a nonlinear fitting algorithm to obtain the compensated average electromagnetic radiation curve.

7. The method according to claim 1, characterized in that, The step of determining whether the multiple chips under test possess malicious hardware logic in the target environment based on the classification differences of the training results includes: The classification differences of the training results are compared with a preset difference threshold. In response to the training result classification difference being less than or equal to the difference threshold, it is determined that the plurality of chips under test do not have malicious hardware logic in the target environment; In response to the training result classification difference being greater than the difference threshold, it is determined that the plurality of chips under test have malicious hardware logic in the target environment.

8. A chip detection device, characterized in that, include: The acquisition module is configured to place multiple chips under test in various environments and input test vector sets to the multiple chips under test multiple times, and acquire the electromagnetic radiation curve corresponding to each chip under test in each environment during each input of test vector sets; The averaging module is configured to average the multiple electromagnetic radiation curves corresponding to each chip under test in each input test vector set under each environment, so as to obtain the average electromagnetic radiation curves corresponding to the multiple chips under test under the various environments. The feature extraction module is configured to extract features from the average electromagnetic radiation curves corresponding to the plurality of chips under test in the target environment, thereby obtaining the feature curves corresponding to the plurality of chips under test in the target environment; wherein, the target environment can be any of a plurality of environments; The binary classification training module is configured to perform binary classification training on the feature curves corresponding to the multiple chips under test in the target environment, and obtain the classification differences of the training results corresponding to the multiple chips under test in the target environment. The first judgment module is configured to determine whether the multiple chips under test have malicious hardware logic in the target environment based on the classification differences of the training results. The second judgment module is configured to determine that the plurality of chips under test do not have malicious hardware logic in the target environment, re-determine a new target environment in at least one environment other than the target environment, and judge whether the plurality of chips under test have malicious hardware logic in the new target environment, until all environments are judged, or the plurality of chips under test have malicious hardware logic in the new target environment. The analysis module is configured to determine that the plurality of chips under test contain malicious hardware logic in the target environment or the new target environment, perform malicious logic analysis on the hardware, and output the analysis results.

9. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the method as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions for causing a computer to perform the method according to any one of claims 1 to 7.

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