Bandgap reference circuit and RF module

Abstract

The present application relates to a bandgap reference circuit and a radio frequency module. The bandgap reference circuit of the embodiment of the present application includes: a reference voltage generation module, configured to form a bandgap reference architecture based on an NPN transistor and an operational amplifier to generate a reference voltage; a source follower, configured to obtain an output control signal from the input of the operational amplifier, and use the output control signal for the bandgap reference architecture to resist changes in the reference voltage to control the stable output of the reference voltage; wherein the source follower and the NPN transistor of a branch in the bandgap reference architecture form a negative feedback loop, which is used to offset the change when the reference voltage changes, so that the bandgap reference circuit outputs a stable reference voltage; the net feedback of all feedback loops of the bandgap reference circuit is negative feedback. The embodiment of the present application can provide a high-precision, high-stability voltage and current reference, and the entire circuit is system-stable.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a bandgap reference circuit and a radio frequency module. Background Art

[0002] The bandgap reference circuit is a crucial module in analog circuits, power management, and RF circuits, and is also an important component of RF modules. In order to meet usage requirements, the reference voltage or reference current provided by the bandgap reference circuit needs to be sufficiently stable and basically unaffected by process, voltage, and temperature.

[0003] Therefore, how to improve the stability of the bandgap reference circuit is crucial. Summary of the invention

[0004] In view of this, embodiments of the present application provide a bandgap reference circuit and a radio frequency module to solve at least one problem existing in the background technology.

[0005] In a first aspect, an embodiment of the present application provides a bandgap reference circuit, the bandgap reference circuit comprising:

[0006] A reference voltage generation module is configured to form a bandgap reference architecture based on an NPN transistor and an operational amplifier to generate a reference voltage;

[0007] A source follower configured to obtain an output control signal from an input terminal of the operational amplifier and use the output control signal for the bandgap reference architecture to resist the variation of the reference voltage so as to control a stable output of the reference voltage;

[0008] The source follower and the NPN transistor of a branch in the bandgap reference architecture form a negative feedback loop, which is used to offset the change when the reference voltage changes, so that the bandgap reference circuit outputs a stable reference voltage;

[0009] The net feedback of all feedback loops of the bandgap reference circuit is negative feedback.

[0010] In combination with the first aspect, in an optional implementation manner, the source follower includes: a third transistor circuit and a third resistor;

[0011] The control terminal of the third transistor circuit is connected to the negative input terminal of the operational amplifier, the first signal terminal of the third transistor circuit is connected to the first power supply terminal, the second signal terminal of the third transistor circuit is respectively connected to the reference voltage output terminal of the bandgap reference circuit and the first terminal of the third resistor, and the second terminal of the third resistor is connected to the second power supply terminal;

[0012] Wherein, a negative feedback loop is formed at least based on the control end of the third transistor circuit, the second signal end of the third transistor circuit, the reference voltage output end of the bandgap reference circuit and the NPN transistor of a branch in the bandgap reference architecture.

[0013] In combination with the first aspect, in an optional implementation manner, the third transistor circuit includes a third NMOS transistor;

[0014] The gate of the third NMOS transistor is connected to the negative input terminal of the operational amplifier, the drain of the third NMOS transistor is connected to the first power supply terminal, and the source of the third NMOS transistor is connected to the reference voltage output terminal of the bandgap reference circuit;

[0015] A negative feedback loop is formed at least based on the gate of the third NMOS transistor, the source of the third NMOS transistor, the reference voltage output terminal of the bandgap reference circuit and the NPN transistor of a branch in the bandgap reference architecture.

[0016] In combination with the first aspect, in an optional implementation, the reference voltage generating module includes: a first transistor circuit, a second transistor circuit, the operational amplifier, a first NPN-type triode, a second NPN-type triode, a first resistor and a second resistor;

[0017] The collector of the first NPN transistor is connected to the positive input terminal of the operational amplifier and the second signal terminal of the first transistor circuit respectively, the emitter of the first NPN transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the second power supply terminal;

[0018] The collector of the second NPN transistor is respectively connected to the negative input terminal of the operational amplifier, the second signal terminal of the second transistor circuit and the input terminal of the source follower, and the emitter of the second NPN transistor is respectively connected to the second end of the first resistor and the first end of the second resistor;

[0019] The base of the first NPN transistor, the base of the second NPN transistor and the output end of the source follower are respectively connected to the reference voltage output end of the bandgap reference circuit; the reference voltage output end is configured to output the reference voltage;

[0020] The output end of the operational amplifier is connected to the control end of the first transistor circuit and the control end of the second transistor circuit respectively, and the first signal end of the first transistor circuit and the first signal end of the second transistor circuit are connected to the first power supply end respectively;

[0021] Wherein, a first negative feedback loop is formed based at least on the positive input terminal of the operational amplifier, the first transistor circuit and the output terminal of the operational amplifier;

[0022] A second positive feedback loop is formed based at least on the negative input terminal of the operational amplifier, the second transistor circuit and the output terminal of the operational amplifier;

[0023] A third positive feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the first NPN transistor, a collector of the first NPN transistor, a positive input terminal of the operational amplifier, an output terminal of the operational amplifier, the second transistor circuit and a negative input terminal of the operational amplifier;

[0024] A fourth negative feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the second NPN transistor, a collector of the second NPN transistor, a negative input terminal of the operational amplifier, an output terminal of the operational amplifier, and the second transistor circuit;

[0025] The net feedback of the first negative feedback loop and the second positive feedback loop is negative feedback; the net feedback of the third positive feedback loop and the fourth negative feedback loop is negative feedback.

[0026] In combination with the first aspect, in an optional implementation manner, the ratio of the current amplification factors of the first NPN transistor and the second NPN transistor is N:1;

[0027] Wherein, N is a natural number greater than or equal to 1.

[0028] In combination with the first aspect, in an optional implementation, the first transistor circuit includes a first PMOS transistor; the second transistor circuit includes a second PMOS transistor;

[0029] The drain of the first PMOS transistor is connected to the positive input terminal of the operational amplifier, the drain of the second PMOS transistor is connected to the negative input terminal of the operational amplifier, the gate of the first PMOS transistor and the gate of the second PMOS transistor are respectively connected to the output terminal of the operational amplifier, and the source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the first power supply terminal;

[0030] Wherein, a first negative feedback loop is formed based at least on the positive input terminal of the operational amplifier, the drain of the first PMOS transistor, the gate of the first PMOS transistor and the output terminal of the operational amplifier;

[0031] A second positive feedback loop is formed based at least on the negative input terminal of the operational amplifier, the drain of the second PMOS transistor, the gate of the second PMOS transistor and the output terminal of the operational amplifier;

[0032] A third positive feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the first NPN transistor, a collector of the first NPN transistor, a positive input terminal of the operational amplifier, an output terminal of the operational amplifier, a gate of the second PMOS transistor, a drain of the second PMOS transistor and a negative input terminal of the operational amplifier;

[0033] A fourth negative feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the second NPN transistor, a collector of the second NPN transistor, a negative input terminal of the operational amplifier, an output terminal of the operational amplifier, a gate of the second PMOS transistor, and a drain of the second PMOS transistor;

[0034] The net feedback of the first negative feedback loop and the second positive feedback loop is negative feedback; the net feedback of the third positive feedback loop and the fourth negative feedback loop is negative feedback.

[0035] In combination with the first aspect, in an optional implementation, the operational amplifier comprises a folded cascode amplifier;

[0036] And / or, the operational amplifier includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor and a fifteenth PMOS transistor;

[0037] The gate of the fourth PMOS transistor is configured as the first input terminal of the operational amplifier, and the gate of the fifth PMOS transistor is configured as the second input terminal of the operational amplifier;

[0038] The source of the fourth PMOS transistor and the source of the fifth PMOS transistor are respectively connected to the drain of the seventh PMOS transistor, the gate of the seventh PMOS transistor and the gate of the sixth PMOS transistor are respectively configured to obtain a bias electrical signal, and the source of the sixth PMOS transistor and the source of the seventh PMOS transistor are respectively connected to the first power supply terminal;

[0039] The drain of the fourth PMOS transistor is respectively connected to the drain of the eighth NMOS transistor and the source of the eleventh NMOS transistor, and the gate of the eighth NMOS transistor is respectively connected to the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, the drain of the tenth NMOS transistor, and the source of the thirteenth NMOS transistor; the drain of the fifth PMOS transistor is respectively connected to the drain of the ninth NMOS transistor and the source of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor is respectively connected to the gate of the eleventh NMOS transistor, the gate of the thirteenth NMOS transistor, the drain of the thirteenth NMOS transistor, and the drain of the sixth PMOS transistor, the drain of the eleventh NMOS transistor is respectively connected to the drain of the fourteenth PMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the fifteenth PMOS transistor, and the drain of the twelfth NMOS transistor is connected to the drain of the fifteenth PMOS transistor and is configured as the output end of the operational amplifier;

[0040] The sources of the eighth NMOS transistor, the ninth NMOS transistor and the tenth NMOS transistor are respectively connected to the second power supply terminal, and the sources of the fourteenth PMOS transistor and the fifteenth PMOS transistor are respectively connected to the first power supply terminal.

[0041] In combination with the first aspect, in an optional implementation, the bandgap reference circuit further includes a bias circuit configured to provide the bias electrical signal;

[0042] And / or, the bandgap reference circuit further includes a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor and a fourth resistor to provide the bias electrical signal;

[0043] The drain of the sixteenth NMOS transistor is configured to obtain the start-up electrical signal; the drain of the sixteenth NMOS transistor is respectively connected to the drain of the eighteenth PMOS transistor, the gate of the eighteenth PMOS transistor and the gate of the nineteenth PMOS transistor, and the gate of the nineteenth PMOS transistor is configured to provide the bias electrical signal;

[0044] The gate of the sixteenth NMOS transistor is respectively connected to the gate of the seventeenth NMOS transistor, the drain of the seventeenth NMOS transistor and the drain of the nineteenth PMOS transistor, the source of the sixteenth NMOS transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor and the source of the seventeenth NMOS transistor are respectively connected to the second power supply terminal, and the source of the eighteenth PMOS transistor and the source of the nineteenth PMOS transistor are respectively connected to the first power supply terminal.

[0045] In combination with the first aspect, in an optional implementation manner, the bandgap reference circuit further includes a startup circuit configured to provide the startup electrical signal;

[0046] And / or, the bandgap reference circuit further includes a twentieth NMOS transistor, a twenty-first NMOS transistor and a fifth resistor to provide the start-up electrical signal;

[0047] The first end of the fifth resistor is connected to the first power supply terminal, the second end of the fifth resistor is respectively connected to the gate of the twentieth NMOS transistor, the gate of the twenty-first NMOS transistor and the drain of the twenty-first NMOS transistor, the source of the twenty-first NMOS transistor is connected to the second power supply terminal, the drain of the twentieth NMOS transistor is connected to the first power supply terminal, and the source of the twentieth NMOS transistor is configured to provide the start electrical signal.

[0048] In combination with the first aspect, in an optional implementation, the bandgap reference circuit further includes a reference current generating module configured to output a reference current determined according to the reference voltage through a current mirror;

[0049] And / or, the bandgap reference circuit further includes a twenty-second PMOS transistor and a twenty-third PMOS transistor to output a reference current determined according to the reference voltage through a current mirror;

[0050] The drain of the twenty-second PMOS transistor is respectively connected to the drain of the third NMOS transistor of the source follower, the gate of the twenty-second PMOS transistor and the gate of the twenty-third PMOS transistor, the source of the twenty-second PMOS transistor and the source of the twenty-third PMOS transistor are respectively connected to the first power supply terminal, and the drain of the twenty-third PMOS transistor is configured to output the reference current.

[0051] In a second aspect, an embodiment of the present application provides a radio frequency module, comprising the bandgap reference circuit as described in the first aspect.

[0052] The beneficial effects brought by the technical solution provided by the embodiment of the present application include: the embodiment of the present application forms a bandgap reference architecture based on an NPN transistor and an operational amplifier to generate a reference voltage, so as to obtain a reference voltage with higher precision. And the output control signal is obtained from the input end of the operational amplifier through a source follower, and the output control signal is used in the bandgap reference architecture to resist the change of the reference voltage to control the stable output of the reference voltage, and a negative feedback loop is formed by the source follower and the NPN transistor of a branch in the bandgap reference architecture, when the reference voltage changes, the change is offset, and the reference voltage can be kept in a stable state, thereby improving the stability of the reference voltage and the system stability of the entire bandgap reference circuit.

[0053] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below and in part will become apparent from the description below or will be learned through the practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0055] Figure 1 A circuit diagram of a specific example of a BJT-based voltage-mode bandgap reference circuit in the related art;

[0056] Figure 2 A circuit diagram of Example 1 of a bandgap reference circuit in an embodiment of the present application;

[0057] Figure 3 Schematic diagram of a feedback network of a bandgap reference circuit in an embodiment of the present application;

[0058] Figure 4 A circuit diagram of Example 2 of a bandgap reference circuit in an embodiment of the present application;

[0059] Figure 5 This is a circuit diagram of Example 3 of the bandgap reference circuit in the embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the technical solutions and beneficial effects of the present invention more clearly understandable, the following is a detailed description by listing specific embodiments. The drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features; unless otherwise defined, the technical and scientific terms used herein have the same meanings as those in the technical field to which this application belongs.

[0061] In each embodiment of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the embodiments are consistent and can be referenced to each other. The technical features in different embodiments can be combined to form a new embodiment based on their internal logical relationships.

[0062] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0063] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above", "said", "aforementioned", "this", etc., may mean "one and only one", or "one or more", "at least one", etc. For example, when using articles such as "a", "an", "the" in English in translation, the noun after the article may be understood as a singular expression or a plural expression.

[0064] In the embodiments of the present application, "plurality" refers to two or more.

[0065] In some embodiments, the terms “at least one”, “one or more”, “a plurality of”, “multiple”, etc. can be used interchangeably.

[0066] The prefixes such as "first" and "second" in the embodiments of the present application are only used to distinguish different description objects, and do not constitute restrictions on the position, order, priority, value or content of the description objects. The statement of the description object refers to the description in the context of the claims or embodiments, and should not constitute unnecessary restrictions due to the use of prefixes. For example, the numerical value of the description object is not limited by the ordinal number, and can be one or more. Take "first device" as an example, where the numerical value of "device" can be one or more. In addition, the objects modified by different prefixes can be the same or different. For example, if the description object is "device", the "first device" and the "second device" can be the same device or different devices, and their types can be the same or different.

[0067] In some embodiments, the term "connection" may indicate that an electrical signal or data is transmitted between a connected end and a connected end, and may be understood as "electrical connection", "communication connection", etc. "Connection" may be a direct connection between two components, an indirect connection established through other components, internal communication between two components, or any other possible connection form.

[0068] In the process of implementing the present invention, the inventors found that the related art has the following problems:

[0069] Figure 1 FIG. 1 shows a voltage-mode bandgap reference circuit based on a BJT (bipolar junction transistor, or triode) in the related art. Figure 1As shown, the circuit includes a first-to-first PMOS transistor (P-type metal oxide semiconductor field effect transistor) M111, a first-to-second PMOS transistor M112, a first-to-third PMOS transistor M113, a first-to-first operational amplifier U111, a first-to-first resistor R111, a first-to-second resistor R112, a first-to-first PNP transistor (PNP bipolar junction transistor) Q111, a first-to-second PNP transistor Q112 and a first-to-third PNP transistor Q113.

[0070] The source of the first-to-first PMOS transistor M111, the source of the first-to-second PMOS transistor M112, and the source of the first-to-third PMOS transistor M113 are respectively connected to the power supply terminal VDD, the gate of the first-to-first PMOS transistor M111, the gate of the first-to-second PMOS transistor M112, and the gate of the first-to-third PMOS transistor M113 are respectively connected to the output terminal of the first-to-first operational amplifier U111, the drain of the first-to-first PMOS transistor M111 is respectively connected to the positive input terminal of the first-to-first operational amplifier U111 and the first end of the first-to-first resistor R111, the second end of the first-to-first resistor R111 is connected to the emitter of the first-to-first PNP transistor Q111; the drain of the first-to-first PMOS transistor M112 is respectively connected to the first-to-first PMOS transistor Q111. The negative input terminal of the operational amplifier U111 is connected to the emitter of the 112 PNP transistor Q112; the drain of the 113 PMOS transistor M113 is connected to the first end of the 112 resistor R112, and the second end of the 112 resistor R112 is connected to the emitter of the 113 PNP transistor Q113; the base of the 111 PNP transistor Q111, the collector of the 111 PNP transistor Q111, the base of the 112 PNP transistor Q112, the collector of the 112 PNP transistor Q112, the base of the 113 PNP transistor Q113 and the collector of the 113 PNP transistor Q113 are respectively connected to the ground terminal GND; the drain of the 113 PMOS transistor M113 is configured to output a reference voltage Vbgr.

[0071] The above-mentioned BJT-based voltage-mode bandgap reference circuit uses a PNP-type transistor to form a traditional voltage-mode bandgap reference architecture, and the accuracy of the reference voltage obtained is relatively low.

[0072] Unlike the PNP transistor, whose collector can only be connected to the substrate and can only build a traditional bandgap reference architecture, the NPN transistor can be used with different bandgap reference architectures due to its flexible three-terminal connection method, thereby achieving higher accuracy.

[0073] To this end, the present application embodiment provides a bandgap reference circuit, such as Figure 2As shown, the bandgap reference circuit includes:

[0074] The reference voltage generating module 10 is configured to form a bandgap reference architecture based on an NPN transistor and an operational amplifier to generate a reference voltage;

[0075] A source follower 20 configured to obtain an output control signal from an input terminal of the operational amplifier, and use the output control signal for the bandgap reference architecture to resist the change of the reference voltage, so as to control the stable output of the reference voltage;

[0076] The source follower and the NPN transistor of a branch in the bandgap reference architecture form a negative feedback loop, which is used to offset the change when the reference voltage changes, so that the bandgap reference circuit outputs a stable reference voltage;

[0077] The net feedback of all feedback loops of the bandgap reference circuit is negative feedback.

[0078] In the embodiment of the present application, the net feedback of all feedback loops of the bandgap reference circuit can be negative feedback, thereby ensuring that the system of the entire bandgap reference circuit is stable, thereby improving the stability of the system.

[0079] In some possible implementations, the bandgap reference architecture based on the NPN transistor and the operational amplifier in the reference voltage generation module 10 may include at least one of the following: a voltage-mode bandgap reference architecture; a current-mode bandgap reference architecture.

[0080] In the embodiments of the present application, the source follower may be referred to by different names, such as a common-drain amplifier, a voltage follower, etc., and the name is not limited here.

[0081] In some possible implementations, the source follower 20 may include at least one of the following:

[0082] A BJT-based source follower uses a BJT as a core component, for example, the base of the BJT can be the input terminal, and the emitter of the BJT can be the output terminal;

[0083] A source follower based on a FET (field effect transistor) uses a FET (such as a MOSFET, a metal oxide semiconductor field effect transistor) as a core component, for example, the gate of the MOSFET may be an input terminal, and the source of the MOSFET may be an output terminal.

[0084] In some possible implementations, the output control signal obtained by the source follower 20 from the input terminal of the operational amplifier of the reference voltage generating module 10 may be a voltage signal or a current signal. Exemplarily, the current signal may be the collector current of an NPN transistor connected to the negative input terminal of the operational amplifier.

[0085] In this way, the embodiment of the present application forms a bandgap reference architecture based on an NPN transistor and an operational amplifier to generate a reference voltage, and can obtain a reference voltage with higher precision. And the output control signal is obtained from the input end of the operational amplifier through a source follower, and the output control signal is used in the bandgap reference architecture to resist the change of the reference voltage to control the stable output of the reference voltage, and a negative feedback loop is formed by the source follower and the NPN transistor of a branch in the bandgap reference architecture. When the reference voltage changes, the change is offset, and the reference voltage can be kept in a stable state, thereby improving the stability of the reference voltage and the system stability of the entire bandgap reference circuit.

[0086] In an alternative embodiment, if Figure 2 As shown, the source follower 20 includes: a third transistor circuit and a third resistor R3;

[0087] The control end of the third transistor circuit is connected to the negative input end of the operational amplifier AMP, the first signal end of the third transistor circuit is connected to the first power supply end vdda, the second signal end of the third transistor circuit is respectively connected to the reference voltage output end of the bandgap reference circuit and the first end of the third resistor R3, and the second end of the third resistor R3 is connected to the second power supply end vssa;

[0088] Wherein, a negative feedback loop is formed at least based on the control end of the third transistor circuit, the second signal end of the third transistor circuit, the reference voltage output end of the bandgap reference circuit and the NPN transistor of a branch in the bandgap reference architecture.

[0089] In the embodiment of the present application, the third resistor R3 may be a single resistor, or a plurality of resistors connected in series and / or in parallel, or may include a passive resistor network or an active resistor network of resistors, capacitors, inductors, etc.

[0090] In some possible implementations, the third transistor circuit may include a control terminal, a first signal terminal, and a second signal terminal, and its working principle is that under the control of a control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal. The third transistor circuit may include a controllable semiconductor device, and may include, for example, at least one of the following: a PMOS transistor; an NMOS transistor (N-type metal oxide semiconductor field effect transistor); a BJT; an IGBT (insulated gate bipolar transistor); a GTO (gate turn-off thyristor); an SCR (silicon controlled thyristor); an MCT (MOS controlled thyristor); an IGCT (integrated gate commutated thyristor); and an IEGT (electron injection enhanced gate transistor).

[0091] In an optional implementation, the third transistor circuit includes a third NMOS transistor M3;

[0092] The gate of the third NMOS transistor M3 is connected to the negative input terminal of the operational amplifier AMP, the drain of the third NMOS transistor M3 is connected to the first power supply terminal vdda, and the source of the third NMOS transistor M3 is connected to the reference voltage output terminal of the bandgap reference circuit;

[0093] A negative feedback loop is formed at least based on the gate of the third NMOS transistor, the source of the third NMOS transistor, the reference voltage output terminal of the bandgap reference circuit and the NPN transistor of a branch in the bandgap reference architecture.

[0094] In this way, the embodiment of the present application connects the input end of the source follower 20 to the negative input end of the operational amplifier AMP and the collector of the NPN transistor of a branch in the bandgap reference architecture, and the output end of the source follower 20 is connected to the reference voltage output end Vref and the base of the NPN transistor of a branch in the bandgap reference architecture, forming a negative feedback loop. When the reference voltage increases, the increase of the reference voltage can be limited by the negative feedback loop, so that the reference voltage remains stable. Conversely, when the reference voltage decreases, the decrease of the reference voltage can be limited by the negative feedback loop, so that the reference voltage remains stable, thereby improving the stability of the reference voltage.

[0095] In an alternative embodiment, if Figure 2 As shown, the reference voltage generating module 10 includes: a first transistor circuit, a second transistor circuit, the operational amplifier AMP, a first NPN transistor Q1, a second NPN transistor Q2, a first resistor R1 and a second resistor R2;

[0096] The collector of the first NPN transistor Q1 is connected to the positive input terminal of the operational amplifier AMP and the second signal terminal of the first transistor circuit respectively, the emitter of the first NPN transistor Q1 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is connected to the second power supply terminal vsa;

[0097] The collector of the second NPN transistor Q2 is respectively connected to the negative input terminal of the operational amplifier AMP, the second signal terminal of the second transistor circuit and the input terminal of the source follower 20, and the emitter of the second NPN transistor Q2 is respectively connected to the second end of the first resistor R1 and the first end of the second resistor R2;

[0098] The base of the first NPN transistor Q1, the base of the second NPN transistor Q2 and the output end of the source follower 20 are respectively connected to the reference voltage output end Vref of the bandgap reference circuit; the reference voltage output end is configured to output the reference voltage;

[0099] The output end of the operational amplifier AMP is connected to the control end of the first transistor circuit and the control end of the second transistor circuit respectively, and the first signal end of the first transistor circuit and the first signal end of the second transistor circuit are connected to the first power supply end vdda respectively;

[0100] Wherein, a first negative feedback loop is formed based at least on the positive input terminal of the operational amplifier AMP, the first transistor circuit and the output terminal of the operational amplifier AMP;

[0101] A second positive feedback loop is formed based at least on the negative input terminal of the operational amplifier AMP, the second transistor circuit and the output terminal of the operational amplifier AMP;

[0102] A third positive feedback loop is formed based at least on a reference voltage output terminal Vref of the bandgap reference circuit, a base of the first NPN transistor Q1, a collector of the first NPN transistor Q1, a positive input terminal of the operational amplifier AMP, an output terminal of the operational amplifier AMP, the second transistor circuit and a negative input terminal of the operational amplifier AMP;

[0103] A fourth negative feedback loop is formed based at least on a reference voltage output terminal Vref of the bandgap reference circuit, a base of the second NPN transistor Q2, a collector of the second NPN transistor Q2, a negative input terminal of the operational amplifier AMP, an output terminal of the operational amplifier AMP and the second transistor circuit;

[0104] The net feedback of the first negative feedback loop and the second positive feedback loop is negative feedback; the net feedback of the third positive feedback loop and the fourth negative feedback loop is negative feedback.

[0105] In the embodiment of the present application, the first NPN transistor Q1 and the second NPN transistor Q2 may be a single NPN transistor, or a plurality of NPN transistors connected in series and / or in parallel. The first resistor R1 and the second resistor R2 may be a single resistor, or a plurality of resistors connected in series and / or in parallel, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.

[0106] In some possible implementations, the first transistor circuit and the second transistor circuit may include a control terminal, a first signal terminal, and a second signal terminal, and the working principle is that under the control of the control signal input to the control terminal, the path between the first signal terminal and the second signal terminal is turned on or off to connect or block the signal transmission between the first signal terminal and the second signal terminal. The first transistor circuit and the second transistor circuit may include controllable semiconductor devices, and may include at least one of the following: PMOS transistor; NMOS transistor (N-type metal oxide semiconductor field effect transistor); BJT; IGBT (insulated gate bipolar transistor); GTO (gate turn-off thyristor); SCR (silicon controlled thyristor); MCT (MOS controlled thyristor); IGCT (integrated gate commutated thyristor); IEGT (electron injection enhanced gate transistor).

[0107] Exemplarily, the first power terminal vdda may provide a positive power voltage, and the second power terminal vsa may be grounded to provide a zero voltage.

[0108] In this way, the embodiment of the present application connects the input end of the source follower 20 to the negative input end of the operational amplifier AMP and the collector of the second NPN transistor Q2 respectively, and the output end of the source follower 20 is connected to the reference voltage output end Vref, thereby forming a stable control of the reference voltage, thereby improving the stability of the reference voltage and the system stability of the entire bandgap reference circuit.

[0109] In an optional implementation, the ratio of the current amplification factor of the first NPN transistor Q1 and the second NPN transistor Q2 is N:1;

[0110] Wherein, N is a natural number greater than or equal to 1.

[0111] The bandgap reference circuit of the embodiment of the present application is as follows: Figure 2 As shown, through the virtual short characteristic of the operational amplifier AMP, the voltages at point X and point Y are equal, so the voltage difference ΔVbe on R1 can be obtained as:

[0112]

[0113] Among them, V T is the thermal voltage, N is the ratio of the current amplification factors of Q1 and Q2, Vbe2 is the base-emitter voltage of Q2, and Vbe1 is the base-emitter voltage of Q1.

[0114] Therefore, the reference voltage V output by the bandgap reference circuit can be obtained. REF for:

[0115]

[0116] Where R1 is the resistance value of R1, and R2 is the resistance value of R2. Vbe2 is a PN junction diode voltage with a negative temperature coefficient, for example, about -2mV / ℃. Thermal voltage V T It is proportional to the absolute temperature. For example, the temperature coefficient at room temperature is +0.085mV / ℃. Therefore, the reference voltage can be obtained by adjusting the ratio of R1 and R2. And the bandgap reference architecture based on NPN transistors can obtain a higher-precision reference voltage and better offset noise suppression.

[0117] In an optional implementation, the first transistor circuit includes a first PMOS transistor M1; the second transistor circuit includes a second PMOS transistor M2;

[0118] The drain of the first PMOS transistor M1 is connected to the positive input terminal of the operational amplifier AMP, the drain of the second PMOS transistor M2 is connected to the negative input terminal of the operational amplifier AMP, the gate of the first PMOS transistor M1 and the gate of the second PMOS transistor M2 are respectively connected to the output terminal of the operational amplifier AMP, and the source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 are respectively connected to the first power supply terminal vdda;

[0119] Wherein, a first negative feedback loop (loop 1) is formed based at least on the positive input terminal of the operational amplifier AMP, the drain of the first PMOS transistor M1, the gate of the first PMOS transistor M1 and the output terminal of the operational amplifier AMP;

[0120] A second positive feedback loop (loop 2) is formed based at least on the negative input terminal of the operational amplifier AMP, the drain of the second PMOS transistor M2, the gate of the second PMOS transistor M2 and the output terminal of the operational amplifier AMP;

[0121] A third positive feedback loop (loop 3) is formed based at least on a reference voltage output terminal Vref of the bandgap reference circuit, a base of the first NPN transistor Q1, a collector of the first NPN transistor Q1, a positive input terminal of the operational amplifier AMP, an output terminal of the operational amplifier AMP, a gate of the second PMOS transistor M2, a drain of the second PMOS transistor M2 and a negative input terminal of the operational amplifier AMP;

[0122] A fourth negative feedback loop (loop 4) is formed based at least on the reference voltage output terminal Vref of the bandgap reference circuit, the base of the second NPN transistor Q2, the collector of the second NPN transistor Q2, the negative input terminal of the operational amplifier AMP, the output terminal of the operational amplifier AMP, the gate of the second PMOS transistor M2 and the drain of the second PMOS transistor M2;

[0123] The net feedback of the first negative feedback loop and the second positive feedback loop is negative feedback; the net feedback of the third positive feedback loop and the fourth negative feedback loop is negative feedback.

[0124] like Figure 3 As shown, the embodiment of the present application may include five feedback networks of loop 1, loop 2, loop 3, loop 4 and loop 5. Among them, the four feedback networks including loop 1, loop 2, loop 3 and loop 4 can be respectively formed by using operational amplifier AMP, which can be used to generate a stable system.

[0125] The feedback network of loop 1 is: from point X to point A, and then back to point X, which is a negative feedback network. The feedback network of loop 2 is: from point Y to point A, and then back to point Y, which is a positive feedback network. These two loops have a common loop path, and the loop gains of the two loops are determined by the common source amplifiers formed by M1 and M2 respectively. Since the common source amplifier load resistor corresponding to M1 has more R1 than the common source amplifier load resistor corresponding to M2, the loop gain of loop 1 is greater than the loop gain of loop 2, and the net feedback network of these two loops is a negative feedback network.

[0126] The feedback network of loop 3 is: from point Vref through Q1 to point X, then through AMP to point A, then through M2 to point Y, and then back to point Vref, which is a positive feedback network. The feedback network of loop 4 is: from point Vref through Q2 to point Y, then through AMP to point A, then through M2 to point Y, and then back to point Vref, which is a negative feedback network. These two loops have a common loop path, and the loop gains of the two loops are determined by the common emitter amplifiers formed by Q1 and Q2 respectively. Under the same current bias, since the Gm of the common emitter amplifier corresponding to Q1 (multiple R1, so Rs is larger, Gm is the reciprocal of Rs, so Gm is smaller) is smaller than the Gm of the common emitter amplifier corresponding to Q2, the loop gain of loop 3 is smaller than the loop gain of loop 4, and the net feedback network of these two loops is a negative feedback network.

[0127] Loop 5 is a negative feedback network including M3 and Q2. When the reference voltage at point Vref increases, the voltage at point Y (output control signal) decreases due to the inversion of Q2, that is, the gate voltage of M3 decreases. Due to the source follower formed by M3, the reference voltage at point Vref decreases, thereby making the reference voltage stable. Similarly, vice versa is also true, which will not be repeated.

[0128] In addition, the net feedback of the above five loops is negative feedback, which makes the entire system of the bandgap reference circuit in negative feedback, so the entire system is stable and can work stably, thereby improving the stability of the system.

[0129] In some possible implementations, the operational amplifier AMP may be a folded cascode amplifier to improve the reference voltage stability.

[0130] In an alternative embodiment, if Figure 4 As shown, the operational amplifier AMP includes (or the folded cascode amplifier includes) a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth NMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M11, a twelfth NMOS transistor M12, a thirteenth NMOS transistor M13, a fourteenth PMOS transistor M14 and a fifteenth PMOS transistor M15;

[0131] The gate of the fourth PMOS transistor M4 is configured as the first input terminal of the operational amplifier AMP, and the gate of the fifth PMOS transistor M5 is configured as the second input terminal of the operational amplifier AMP;

[0132] The source of the fourth PMOS transistor M4 and the source of the fifth PMOS transistor M5 are respectively connected to the drain of the seventh PMOS transistor M7, the gate of the seventh PMOS transistor M7 and the gate of the sixth PMOS transistor M6 are respectively configured to obtain a bias electrical signal, and the source of the sixth PMOS transistor M6 and the source of the seventh PMOS transistor M7 are respectively connected to the first power supply terminal vdda;

[0133] The drain of the fourth PMOS transistor M4 is respectively connected to the drain of the eighth NMOS transistor M8 and the source of the eleventh NMOS transistor M11, and the gate of the eighth NMOS transistor M8 is respectively connected to the gate of the ninth NMOS transistor M9, the gate of the tenth NMOS transistor M10, the drain of the tenth NMOS transistor M10 and the source of the thirteenth NMOS transistor M13; the drain of the fifth PMOS transistor M5 is respectively connected to the drain of the ninth NMOS transistor M9 and the source of the twelfth NMOS transistor M12, and the gate of the twelfth NMOS transistor M12 is respectively connected to the gate of the ninth NMOS transistor M9, the gate of the tenth NMOS transistor M10, the drain of the tenth NMOS transistor M10 and the source of the thirteenth NMOS transistor M13. The gate is respectively connected to the gate of the eleventh NMOS transistor M11, the gate of the thirteenth NMOS transistor M13, the drain of the thirteenth NMOS transistor M13 and the drain of the sixth PMOS transistor M6, the drain of the eleventh NMOS transistor M11 is respectively connected to the drain of the fourteenth PMOS transistor M14, the gate of the fourteenth PMOS transistor M14 and the gate of the fifteenth PMOS transistor M15, the drain of the twelfth NMOS transistor M12 is connected to the drain of the fifteenth PMOS transistor M15 and is configured as the output end of the operational amplifier AMP;

[0134] Sources of the eighth NMOS transistor M8, the ninth NMOS transistor M9 and the tenth NMOS transistor M10 are respectively connected to the second power supply terminal vssa, and sources of the fourteenth PMOS transistor M14 and the fifteenth PMOS transistor M15 are respectively connected to the first power supply terminal vdda.

[0135] In the embodiment of the present application, the first input terminal of the operational amplifier AMP may be a positive input terminal, and the second input terminal of the operational amplifier AMP may be a negative input terminal.

[0136] In some possible implementations, the bias electrical signal may be a bias voltage signal or a bias current signal. The bias electrical signal may be provided by the inside of the bandgap reference circuit or by a control device outside the bandgap reference circuit. The control device may be programmable.

[0137] In an alternative embodiment, if Figure 4 As shown, the bandgap reference circuit further includes a bias circuit 30 configured to provide the bias electrical signal to provide a bias voltage of a desired magnitude to improve stability.

[0138] In an alternative embodiment, if Figure 4 As shown, the bandgap reference circuit further includes (or the bias circuit 30 includes) a sixteenth NMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth PMOS transistor M18, a nineteenth PMOS transistor M19 and a fourth resistor R4 to provide the bias electrical signal;

[0139] The drain of the sixteenth NMOS transistor M16 is configured to obtain the start-up electrical signal; the drain of the sixteenth NMOS transistor M16 is respectively connected to the drain of the eighteenth PMOS transistor M18, the gate of the eighteenth PMOS transistor M18 and the gate of the nineteenth PMOS transistor M19, and the gate of the nineteenth PMOS transistor M19 is configured to provide the bias electrical signal;

[0140] The gate of the sixteenth NMOS transistor M16 is respectively connected to the gate of the seventeenth NMOS transistor M17, the drain of the seventeenth NMOS transistor M17 and the drain of the nineteenth PMOS transistor M19, the source of the sixteenth NMOS transistor M16 is connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 and the source of the seventeenth NMOS transistor M17 are respectively connected to the second power supply terminal vssa, and the source of the eighteenth PMOS transistor M18 and the source of the nineteenth PMOS transistor M19 are respectively connected to the first power supply terminal vdda.

[0141] In some possible implementations, the start-up electrical signal may be a start-up voltage signal or a start-up current signal. The start-up electrical signal may be provided by the inside of the bandgap reference circuit or by a control device outside the bandgap reference circuit. The control device may be programmable. The start-up electrical signal is used to make the bandgap reference circuit get rid of the zero coalescence point.

[0142] In an alternative embodiment, if Figure 4 As shown, the bandgap reference circuit further includes a start-up circuit 40 configured to provide the start-up electrical signal to enable the bandgap reference circuit to get rid of the zero merger point.

[0143] In an alternative embodiment, if Figure 4 As shown, the bandgap reference circuit further includes (or the startup circuit 40 includes) a twentieth NMOS transistor M20, a twenty-first NMOS transistor M21 and a fifth resistor R5 to provide the startup electrical signal;

[0144] A first end of the fifth resistor R5 is connected to the first power supply terminal vdda, a second end of the fifth resistor R5 is respectively connected to the gate of the twentieth NMOS transistor M20, the gate of the twenty-first NMOS transistor M21 and the drain of the twenty-first NMOS transistor M21, a source of the twenty-first NMOS transistor M21 is connected to the second power supply terminal vssa, a drain of the twentieth NMOS transistor M20 is connected to the first power supply terminal vdda, and a source of the twentieth NMOS transistor M20 is configured to provide the start electrical signal.

[0145] In an alternative embodiment, if Figure 4 and Figure 5 As shown, the bandgap reference circuit further includes a reference current generating module 50, which is configured to output a reference current determined according to the reference voltage through a current mirror, thereby improving the stability of the reference current.

[0146] In an alternative embodiment, if Figure 4 and Figure 5 As shown, the bandgap reference circuit further includes (or the reference current generating module 50 includes) a twenty-second PMOS transistor and a twenty-third PMOS transistor, so as to output the reference current determined according to the reference voltage through a current mirror;

[0147] The drain of the twenty-second PMOS transistor M22 is respectively connected to the drain of the third NMOS transistor M3 of the source follower, the gate of the twenty-second PMOS transistor M22 and the gate of the twenty-third PMOS transistor M23, the source of the twenty-second PMOS transistor M22 and the source of the twenty-third PMOS transistor M23 are respectively connected to the first power supply terminal vdda, and the drain of the twenty-third PMOS transistor M23 is configured to output the reference current.

[0148] In some possible implementations, the bandgap reference circuit is configured with a reference current output terminal Iref for outputting the reference current.

[0149] In the embodiment of the present application, M22 and M23 can form a current mirror, and the reference current is transmitted through the current mirror. The reference current is generated on R3 as:

[0150]

[0151] Among them, I REF is the reference current, V REF is the reference voltage, and R3 is the resistance value of R3.

[0152] The embodiment of the present application provides a BJT-based voltage and current reference circuit (BGVCR), which can generate high-precision voltage reference and current reference with high stability and system stability.

[0153] The PMOS transistor or NMOS transistor in the embodiment of the present application may be a single one, or a plurality of them may be connected in series and / or in parallel.

[0154] An embodiment of the present application also provides a radio frequency module, comprising the bandgap reference circuit of the above embodiment.

[0155] In this way, the stability of the RF module can be improved by providing a highly stable reference voltage and a bandgap reference circuit with high system stability.

[0156] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations included in the claims. Various modifications and changes may be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form other embodiments of the present application that may not be explicitly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A radio frequency module, characterized in that: including a bandgap reference circuit; The bandgap reference circuit comprises: A reference voltage generation module is configured to form a bandgap reference architecture based on an NPN transistor and an operational amplifier to generate a reference voltage; A source follower configured to obtain an output control signal from an input terminal of the operational amplifier and use the output control signal for the bandgap reference architecture to resist the variation of the reference voltage so as to control a stable output of the reference voltage; The source follower and the NPN transistor of a branch in the bandgap reference architecture form a negative feedback loop, which is used to offset the change when the reference voltage changes, so that the bandgap reference circuit outputs a stable reference voltage; The net feedback of all feedback loops of the bandgap reference circuit is negative feedback; Wherein, the reference voltage generating module comprises: a first transistor circuit, a second transistor circuit and the operational amplifier; the first signal end of the first transistor circuit and the first signal end of the second transistor circuit are respectively connected to the first power supply end; the second signal end of the first transistor circuit is connected to the positive input end of the operational amplifier; the second signal end of the second transistor circuit is connected to the negative input end of the operational amplifier; the output end of the operational amplifier is respectively connected to the control end of the first transistor circuit and the control end of the second transistor circuit; The operational amplifier includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth PMOS transistor and a fifteenth PMOS transistor; The gate of the fourth PMOS transistor is configured as the positive input terminal of the operational amplifier, and the gate of the fifth PMOS transistor is configured as the negative input terminal of the operational amplifier; The source of the fourth PMOS transistor and the source of the fifth PMOS transistor are respectively connected to the drain of the seventh PMOS transistor, the gate of the seventh PMOS transistor and the gate of the sixth PMOS transistor are respectively configured to obtain a bias electrical signal, and the source of the sixth PMOS transistor and the source of the seventh PMOS transistor are respectively connected to the first power supply terminal; The drain of the fourth PMOS transistor is respectively connected to the drain of the eighth NMOS transistor and the source of the eleventh NMOS transistor, and the gate of the eighth NMOS transistor is respectively connected to the gate of the ninth NMOS transistor, the gate of the tenth NMOS transistor, the drain of the tenth NMOS transistor, and the source of the thirteenth NMOS transistor; the drain of the fifth PMOS transistor is respectively connected to the drain of the ninth NMOS transistor and the source of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor is respectively connected to the gate of the eleventh NMOS transistor, the gate of the thirteenth NMOS transistor, the drain of the thirteenth NMOS transistor, and the drain of the sixth PMOS transistor, the drain of the eleventh NMOS transistor is respectively connected to the drain of the fourteenth PMOS transistor, the gate of the fourteenth PMOS transistor, and the gate of the fifteenth PMOS transistor, and the drain of the twelfth NMOS transistor is connected to the drain of the fifteenth PMOS transistor and is configured as the output end of the operational amplifier; The source of the eighth NMOS transistor, the source of the ninth NMOS transistor and the source of the tenth NMOS transistor are respectively connected to the second power supply terminal, and the source of the fourteenth PMOS transistor and the source of the fifteenth PMOS transistor are respectively connected to the first power supply terminal; The bandgap reference circuit further comprises a bias circuit configured to provide the bias electrical signal; The source follower includes: a third transistor circuit; The bandgap reference circuit further includes a twenty-second PMOS transistor and a twenty-third PMOS transistor; The control terminal of the third transistor circuit is connected to the negative input terminal of the operational amplifier; the first signal terminal of the third transistor circuit is respectively connected to the drain of the twenty-second PMOS transistor, the gate of the twenty-second PMOS transistor and the gate of the twenty-third PMOS transistor; the second signal terminal of the third transistor circuit is connected to the reference voltage output terminal of the bandgap reference circuit; the source of the twenty-second PMOS transistor and the source of the twenty-third PMOS transistor are respectively connected to the first power supply terminal, and the drain of the twenty-third PMOS transistor is configured to output a reference current; The source follower further includes: a third resistor; The control end of the third transistor circuit is connected to the negative input end of the operational amplifier, the second signal end of the third transistor circuit is connected to the reference voltage output end of the bandgap reference circuit and the first end of the third resistor respectively, and the second end of the third resistor is connected to the second power supply end; Wherein, a negative feedback loop is formed at least based on the control terminal of the third transistor circuit, the second signal terminal of the third transistor circuit, the reference voltage output terminal of the bandgap reference circuit and the NPN transistor of a branch in the bandgap reference architecture; The third transistor circuit comprises a third NMOS transistor; The gate of the third NMOS transistor is connected to the negative input terminal of the operational amplifier, the drain of the third NMOS transistor is respectively connected to the drain of the twenty-second PMOS transistor, the gate of the twenty-second PMOS transistor and the gate of the twenty-third PMOS transistor, and the source of the third NMOS transistor is connected to the reference voltage output terminal of the bandgap reference circuit; Wherein, a negative feedback loop is formed based on at least the gate of the third NMOS transistor, the source of the third NMOS transistor, the reference voltage output terminal of the bandgap reference circuit and the NPN transistor of a branch in the bandgap reference architecture; The reference voltage generation module further includes: a first NPN transistor, a second NPN transistor, a first resistor and a second resistor; The collector of the first NPN transistor is connected to the positive input terminal of the operational amplifier and the second signal terminal of the first transistor circuit respectively, the emitter of the first NPN transistor is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is connected to the second power supply terminal; The collector of the second NPN transistor is respectively connected to the negative input terminal of the operational amplifier, the second signal terminal of the second transistor circuit and the input terminal of the source follower, and the emitter of the second NPN transistor is respectively connected to the second end of the first resistor and the first end of the second resistor; The base of the first NPN transistor, the base of the second NPN transistor and the output end of the source follower are respectively connected to the reference voltage output end of the bandgap reference circuit; the reference voltage output end is configured to output the reference voltage; Wherein, a first negative feedback loop is formed based at least on the positive input terminal of the operational amplifier, the first transistor circuit and the output terminal of the operational amplifier; A second positive feedback loop is formed based at least on the negative input terminal of the operational amplifier, the second transistor circuit and the output terminal of the operational amplifier; A third positive feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the first NPN transistor, a collector of the first NPN transistor, a positive input terminal of the operational amplifier, an output terminal of the operational amplifier, the second transistor circuit and a negative input terminal of the operational amplifier; A fourth negative feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the second NPN transistor, a collector of the second NPN transistor, a negative input terminal of the operational amplifier, an output terminal of the operational amplifier, and the second transistor circuit; The net feedback of the first negative feedback loop and the second positive feedback loop is negative feedback; the net feedback of the third positive feedback loop and the fourth negative feedback loop is negative feedback; The first transistor circuit includes a first PMOS transistor; the second transistor circuit includes a second PMOS transistor; The drain of the first PMOS transistor is connected to the positive input terminal of the operational amplifier, the drain of the second PMOS transistor is connected to the negative input terminal of the operational amplifier, the gate of the first PMOS transistor and the gate of the second PMOS transistor are respectively connected to the output terminal of the operational amplifier, and the source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the first power supply terminal; Wherein, a first negative feedback loop is formed based at least on the positive input terminal of the operational amplifier, the drain of the first PMOS transistor, the gate of the first PMOS transistor and the output terminal of the operational amplifier; A second positive feedback loop is formed based at least on the negative input terminal of the operational amplifier, the drain of the second PMOS transistor, the gate of the second PMOS transistor and the output terminal of the operational amplifier; A third positive feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the first NPN transistor, a collector of the first NPN transistor, a positive input terminal of the operational amplifier, an output terminal of the operational amplifier, a gate of the second PMOS transistor, a drain of the second PMOS transistor and a negative input terminal of the operational amplifier; A fourth negative feedback loop is formed based at least on a reference voltage output terminal of the bandgap reference circuit, a base of the second NPN transistor, a collector of the second NPN transistor, a negative input terminal of the operational amplifier, an output terminal of the operational amplifier, a gate of the second PMOS transistor, and a drain of the second PMOS transistor; The net feedback of the first negative feedback loop and the second positive feedback loop is negative feedback; the net feedback of the third positive feedback loop and the fourth negative feedback loop is negative feedback; The bandgap reference circuit further includes a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor and a fourth resistor to provide the bias electrical signal; The drain of the sixteenth NMOS transistor is configured to obtain the start-up electrical signal; the drain of the sixteenth NMOS transistor is respectively connected to the drain of the eighteenth PMOS transistor, the gate of the eighteenth PMOS transistor and the gate of the nineteenth PMOS transistor, and the gate of the nineteenth PMOS transistor is configured to provide the bias electrical signal; The gate of the sixteenth NMOS transistor is respectively connected to the gate of the seventeenth NMOS transistor, the drain of the seventeenth NMOS transistor and the drain of the nineteenth PMOS transistor, the source of the sixteenth NMOS transistor is connected to the first end of the fourth resistor, the second end of the fourth resistor and the source of the seventeenth NMOS transistor are respectively connected to the second power supply terminal, and the source of the eighteenth PMOS transistor and the source of the nineteenth PMOS transistor are respectively connected to the first power supply terminal; The bandgap reference circuit further includes a startup circuit configured to provide the startup electrical signal; The startup circuit further includes a 20th NMOS transistor, a 21st NMOS transistor and a fifth resistor to provide the startup electrical signal; A first end of the fifth resistor is connected to the first power supply terminal, a second end of the fifth resistor is respectively connected to the gate of the 20th NMOS transistor, the gate of the 21st NMOS transistor, and the drain of the 21st NMOS transistor, a source of the 21st NMOS transistor is connected to the second power supply terminal, a drain of the 20th NMOS transistor is connected to the first power supply terminal, and a source of the 20th NMOS transistor is configured to provide the start-up electrical signal; The ratio of the current amplification factors of the first NPN transistor and the second NPN transistor is N:1; Wherein, N is a natural number greater than 1; The operational amplifier comprises a folded cascode amplifier; The bandgap reference circuit further includes a reference current generating module configured to output a reference current determined according to the reference voltage through a current mirror.

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