A cyclic scheduling method in the form of dynamic task chains

Abstract

The application discloses a loop scheduling method in the form of a dynamic task chain, relates to the technical field of dynamic task scheduling of a heterogeneous multi-core computing system, and is suitable for dynamic task scheduling of a heterogeneous multi-core computing system based on a coarse-grained reconfigurable architecture and oriented to dense computing applications. The loop body task is regarded as a whole, and a unified priority is given. In the first round of executing the loop task, the loop body task is sequentially scheduled and the loop task scheduling result is recorded to generate a dynamic task chain. In the loop after the first round, the dynamic task chain is used for scheduling. In the subsequent loop execution process, only the input and output of the dynamic task chain are scheduled, and secondary scheduling in the loop body is avoided. The loop scheduling method in the technical scheme of the application is specially used for scheduling in the second round and the subsequent rounds of the loop body task, solves the defect that the original dynamic scheduling method does not support loop task scheduling, and effectively avoids scheduling bottlenecks caused by repeated scheduling of the same structure task.

Description

Technical Field

[0001] The present application relates to the technical field of dynamic task scheduling of heterogeneous multi-core computing systems based on a coarse-grained reconfigurable architecture for intensive computing applications, and in particular to a cyclic scheduling method in the form of a dynamic task chain. Background Art

[0002] The rapid development of computer and microelectronics technology has led to the emergence of microprocessors with multiple computing cores, known as multi-core processors. These multi-core processors are divided into two types: homogeneous multi-core processors and heterogeneous multi-core processors. Heterogeneous multi-core processors integrate cores of varying architectures on the same chip, enabling tasks to be assigned to the most appropriate core based on their characteristics.

[0003] In systems using heterogeneous multi-core processors, the core issues of resource scheduling and management are how to fully utilize processor resources with varying performance, what task allocation strategies to adopt for resource management, and how to achieve automatic adjustment and load balancing of processor resources while maintaining flexibility and adaptability in task allocation. Addressing these issues is crucial to fully realizing the potential of processor resources and leveraging the characteristics of heterogeneous multi-core processor systems.

[0004] Currently, methods for solving the task scheduling problem in heterogeneous multi-core processor systems can be divided into two main categories: static task scheduling technology and dynamic scheduling technology. In dynamic scheduling technology, although task scheduling has achieved certain research results and effectively utilizes the dependencies between tasks to optimize scheduling performance, the ability to process tasks in parallel still needs to be improved. In particular, the scheduling methods for tasks containing loop structures are still not perfect. In previous studies, existing dynamic scheduling algorithms did not support the defects of loop task scheduling. Most of them split tasks with loop structures into independent tasks for scheduling. Although this reduces the difficulty of scheduling method design, it does not fully utilize the highly repetitive data exchange patterns and task dependencies during the execution of loop tasks. In addition, the scheduling bottleneck caused by the repeated scheduling of tasks with the same structure leads to a significant increase in scheduling overhead. Summary of the Invention

[0005] The purpose of this application is to solve the defect that the original dynamic scheduling method does not support cyclic task scheduling in the dynamic task scheduling of heterogeneous multi-core computing systems based on coarse-grained reconfigurable architecture and oriented to intensive computing applications, and effectively avoid the scheduling bottleneck caused by repeated scheduling of tasks with the same structure.

[0006] The technical solution of the present application is to provide a cyclic scheduling method in the form of a dynamic task chain, which is used in a heterogeneous multi-core system. The heterogeneous multi-core system includes a dynamic scheduling controller and a state network. The dynamic scheduling controller includes a scheduling control unit, a mapping unit, and a transmitting unit. The method is characterized in that the method includes:

[0007] Step 1: The scheduling control unit obtains the task label and generates the corresponding scheduling control instruction SCI, which is sent to the decision queue;

[0008] Step 2: The judgment queue identifies the task type of SCI. If it is a cyclic task, execute step 3; if it is an independent task, execute step 7.

[0009] Step 3: The scheduling control unit sends the SCI to the cyclic task queue and stores the field representing the cyclic task information in the SCI;

[0010] Step 4: The scheduling control unit searches for the SCI in the cyclic task queue that matches the processing unit coordinates of the previous task, and sends the necessary task information RMI in its main segment to the active queue, obtains the mapping result of the current RMI from the mapping unit, writes the mapping result into the RMI as the current task T_curr, and sends it to the ready queue for emission. After T_curr is emitted, the scheduling control unit obtains the mapping result of the subsequent RMI. After T_curr is executed, the scheduling control unit writes its corresponding scheduling result into the cyclic scheduling queue, and emits the tasks in the current loop body in sequence until all tasks complete the first round of scheduling. Based on the scheduling results of all tasks in the current loop body, a dynamic task chain of the loop body is generated, wherein, when the SCI has no previous task, the default processing unit coordinates are matched;

[0011] Step 5: The write-back determination module receives the subsequent RMI output by the active queue, and selects a write-back method for the result data of T_curr based on the specific bit information in the subsequent RMI and the usage of the corresponding processing unit, and performs the write-back operation according to the selected write-back method;

[0012] Step 6: After the first round of scheduling is completed, the scheduling control unit directly sends the RMI corresponding to the SCI in the cyclic task queue to the ready queue for transmission according to the scheduling result in the cyclic scheduling queue, and performs a write-back operation;

[0013] Step 7: The scheduling control unit sends the RMI of the SCI with the highest priority to the active queue and sends the remaining SCIs to the dormant queue;

[0014] Step 8, the scheduling control unit reads the RMI in the active queue, obtains the mapping result of the current RMI from the mapping unit, writes the mapping result into the RMI, and sends the RMI as a current task T_curr into the ready queue for transmission. After the transmission of T_curr is completed, the mapping result of a subsequent task is obtained.

[0015] Step 9, the scheduling control unit finds an SCI in the sleep queue that matches the processing unit coordinates of T_curr, and sends the RMI of the SCI into the active queue. The write-back judgment module selects a write-back mode of the result data of T_curr according to the information of T_curr and the information of the subsequent RMI, and performs a write-back operation.

[0016] Further, step 4 specifically includes:

[0017] Step 4.1, the scheduling control unit finds an SCI in the loop task queue that matches the coordinates of the default processing unit of the first batch of tasks, and sends the RMI corresponding to the SCI into the active queue.

[0018] Step 4.2, the scheduling control unit reads the RMI in the active queue, obtains the mapping result of the current RMI from the mapping unit, writes the mapping result into the current RMI as a current task T_curr, and sends T_curr into the ready queue for transmission. After the transmission of T_curr is completed, the mapping result of a subsequent RMI is obtained.

[0019] Step 4.3, after the execution of T_curr is completed, the scheduling control unit writes the scheduling result of T_curr into the loop scheduling queue, obtains the coordinate information of the processing unit corresponding to T_curr through the state network, finds a subsequent SCI in the loop task queue that matches the coordinate information, and writes the RMI corresponding to the SCI into the active queue.

[0020] Step 4.4, the scheduling control unit writes the mapping result of the subsequent RMI into the corresponding RMI, and sends the RMI as a subsequent task T_succ into the ready queue for transmission. The tasks in the loop body are processed in sequence according to the method in steps 4.2 to 4.4, until all the tasks in the current loop body complete the first round of scheduling.

[0021] Step 4.5, based on the scheduling result of all the tasks in the current loop body, the processing units and routing paths used are temporarily locked, and a dynamic task chain of the loop body is generated.

[0022] Further, step 5 specifically includes:

[0023] Step 5.1, the write-back judgment module judges whether T_curr has a subsequent task T_succ according to the matching result of T_curr and the coordinates of SCI. If there is no SCI in the cyclic task queue that matches the coordinate information of T_curr, it is determined that T_curr has no T_succ, and the result data of T_curr is forcibly written back to DDR. If there is an SCI in the cyclic task queue that matches the coordinate information of T_curr, it is determined that T_curr has T_succ, and step 5.2 is performed;

[0024] Step 5.2, judge whether the priority difference between the subsequent RMI and T_curr is greater than 1 according to the specific position information of the subsequent RMI. If it is greater than 1, the result data of T_curr is forcibly written back to DDR, and the III-type write-back SCI is generated by the scheduling control unit and written into the III-type write-back SCI queue, and the wake-up condition is set as: T_succ has been transmitted. If the priority difference between the subsequent RMI and T_curr is less than or equal to 1, step 5.3 is performed;

[0025] Step 5.3, the type of the processing unit corresponding to the subsequent RMI is obtained, and the write-back type is determined according to the transmission of the corresponding T_succ and the idle condition of the processing unit of the type, as follows:

[0026] If T_succ has been transmitted, the result data of T_curr is written into the local storage of the processing unit corresponding to T_succ;

[0027] If T_succ has not been transmitted and there are enough processing units of the corresponding type, the write-back operation is temporarily suspended until the corresponding processing unit is configured, and then the result data of T_curr is written into the local storage of the processing unit corresponding to T_succ;

[0028] If there are not enough processing units of the corresponding type, the result data of T_curr is written back to the on-chip cache, and the I-type write-back SCI is generated by the scheduling control unit and written into the I-type write-back SCI queue, and the wake-up condition is set as: there is an idle processing unit of the corresponding type or T_succ has been transmitted;

[0029] If there are not enough processing units of the corresponding type and the on-chip cache is insufficient, the result data of T_curr is written back to DDR, and the II-type write-back SCI is generated by the scheduling control unit and written into the II-type write-back SCI queue, and the wake-up condition is set as: there is an idle processing unit of the corresponding type or T_succ has been transmitted.

[0030] Furthermore, during the dynamic task chain generation process, when there is an intermediate task in the loop body that needs to be written back to the on-chip cache or DDR, the dynamic scheduling controller divides the used processing units and routing paths into multiple groups based on the intermediate task, and generates dynamic task chains respectively, and uses these dynamic task chains to jointly complete the scheduling task; when the dynamic task chain generation process blocks the execution of independent tasks, the dynamic scheduling controller enables the counter and starts counting from the temporary suspension of the independent task blocking. When the count value reaches the set threshold, the dynamic task chain stops generating and schedules the tasks in the loop body as independent tasks.

[0031] Furthermore, step 6 specifically includes:

[0032] Step 6.1, the scheduling control unit directly sends the RMI corresponding to the SCI in the loop task queue to the ready queue in sequence according to the scheduling results corresponding to the tasks in the loop body;

[0033] Step 6.2: The ready queue sends the tasks corresponding to the RMI to the launch unit in the order of writing. After each task is completed, the scheduling control unit notifies the launch unit to perform the write-back operation through a signal.

[0034] In step 6.3, the dynamic scheduling controller checks whether the current loop task meets the end condition. If so, the loop is terminated and the processing units and routing paths occupied by the loop task are released. Otherwise, the next round of loop scheduling is continued.

[0035] Furthermore, step 9 specifically includes:

[0036] Step 9.1: The scheduling control unit matches the coordinate information of the T_curr processing unit with the mapped coordinate segments of the SCI in the dormant queue one by one. If the coordinates match successfully, the RMI of the SCI is sent to the active queue as the next-level RMI. Otherwise, the SCI is put back to the end of the dormant queue.

[0037] Step 9.2: The write-back judgment module receives the subsequent RMI output by the active queue, and selects the write-back method for the result data of T_curr according to the specific bit information in the subsequent RMI and the usage of the corresponding processing unit, and performs the write-back operation.

[0038] Furthermore, step 1 specifically includes:

[0039] The scheduling control unit obtains the task tag with the highest priority from the memory, and preprocesses the task tag to form the corresponding static task information STI. The storage address of the STI is determined according to the data segment representing the execution order in the task tag, and the STI is written into the static task information library of the scheduling control unit in sequence according to the storage address. The STI is then retrieved from the static task information library in the writing order, and the main segment of the STI is spliced ​​with its different communication segments one by one. The splicing result is merged with the previous task mapping coordinate to generate the corresponding SCI, and the SCI is sent to the judgment queue.

[0040] Furthermore, the prerequisite for generating a dynamic task chain is that the task to be scheduled is a cyclic task, and the result data of the previous task must be written back to the processing unit of the current task.

[0041] Furthermore, the write-back method and operation of the result data of T_curr selected in step 9.2 are the same as those in step 5.

[0042] The beneficial effects of this application are:

[0043] First, the technical solution in this application regards the loop body task as a whole, records the scheduling results of all tasks in the loop body when the loop is executed for the first time, and temporarily locks the processing units and routing paths used to generate a dynamic task chain. After completing the first round of scheduling, the dynamic task chain is used to complete the scheduling of subsequent loops. During the subsequent loop execution process, the dynamic scheduling controller only schedules the input and output of the dynamic task chain, and directly sends the tasks in the loop task queue to the ready queue for transmission based on the obtained scheduling results, and performs a write-back operation, omitting the work of matching the subsequent tasks, obtaining the mapping results, and determining the write-back method in the first round of scheduling, thereby avoiding the secondary scheduling of tasks within the loop body. Compared with the method of splitting the loop body task into independent tasks for scheduling in the prior art, the technical solution in this application makes full use of the highly repetitive data exchange rules and task dependencies during the execution of the loop task, effectively improving the scheduling quality of the loop task, significantly reducing the scheduling overhead of the loop task, and improving the computing performance of the heterogeneous multi-core processor system.

[0044] Second, the technical solution in the application is applied in a heterogeneous multi-core computing system based on a coarse-grained reconfigurable architecture and oriented to dense computing applications. Different scheduling modes are adopted to realize dynamic task scheduling of independent tasks and loop tasks. The technical solution in the application also adopts a method of dividing a new dynamic task chain to solve the situation that a dynamic task chain cannot be generated because of the need to write back on-chip cache or DDR during execution of an intermediate task in a loop body. The method supports division of a loop task into multiple local task chains, cooperative completion of loop task scheduling, and further enhancement of flexibility in processing loop tasks. The method adopts a method of forcibly stopping generation of a dynamic task chain to solve the situation that an independent task is blocked for a long time and cannot be sent because of insufficient on-chip resources or too many processing units in the loop body. While the loop body task is executed by using a dynamic task chain, independent tasks are not affected by system scheduling. The method solves the defect in the prior art that a dynamic scheduling method does not support loop task scheduling, and effectively avoids a scheduling bottleneck caused by repeated scheduling of the same structure task.

[0045] Third, the dynamic task chain generated in the technical solution of the application supports scheduling of explicit loop and implicit loop tasks. For an explicit loop body task, an end condition of the explicit loop is provided by a global variable. For an implicit loop body task, the dynamic scheduling controller will issue a loop end condition as the last task of the loop body. Whether the end condition is met is detected at the end of each round of calculation. BRIEF DESCRIPTION OF DRAWINGS

[0046] The above and / or additional aspects of the present application will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0047] Figure 1 is a running process of task scheduling in a heterogeneous multi-core system according to an embodiment of the application;

[0048] Figure 2 is a general architecture of a dynamic scheduling controller according to an embodiment of the application;

[0049] Figure 3 is a scheduling process diagram of a dynamic task chain scheduling mode according to an embodiment of the application;

[0050] Figure 4 is a SCI generation process according to an embodiment of the application;

[0051] Figure 5 is a scheduling process of an independent task scheduling mode according to an embodiment of the application;

[0052] Figure 6 is a module structure and running mechanism of a heterogeneous multi-core system according to an embodiment of the application. DETAILED DESCRIPTION

[0053] In order to more clearly understand the above-mentioned objectives, features and advantages of the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features therein can be combined with each other in the absence of conflict.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present application is not limited to the specific embodiments disclosed below.

[0055] like Figure 2 、 Figure 6 As shown, this embodiment provides a cyclic scheduling method in the form of a dynamic task chain, which is used for task scheduling in a heterogeneous multi-core system. The heterogeneous multi-core system includes a main controller, a dynamic scheduling controller, a configuration network, a state network, a data network, a global variable network, a processing unit PE and a memory DDR.

[0056] The dynamic scheduling controller is used for specific task scheduling and resource allocation. It includes an instruction fetch unit, a mapping unit, a write-back management unit, a launch unit, and a scheduling control unit. The overall architecture of the dynamic scheduling controller is as follows: Figure 2 As shown, it also contains an on-chip network layout diagram for storing the coordinates of the processing unit's on-chip network. The dynamic scheduling controller's external interfaces include a configuration network interface, a status network interface, a global variable network interface for receiving and updating global variables, and a DDR interface for obtaining the task dependency table (a data structure used to describe the dependencies between tasks).

[0057] The instruction fetch unit is used to obtain task-related information from the memory DDR; the mapping unit is used to obtain the coordinate information of the previous task processing unit from the status network, and generate a mapping result based on the coordinate information and feed it back to the scheduling control unit; the write-back management unit is used to manage the write-back operation of the current task result data and decide when to write the result data back to the target processing unit (for example, when the current task result data is written back to the on-chip cache, the write-back management unit provides a cache identifier to the scheduling control unit, and when the subsequent wake-up conditions are met, the result data is written from the on-chip cache back to the target processing unit); the launch unit is used to launch tasks; the scheduling control unit is the core of the dynamic scheduling controller, responsible for the coordination between the various units within the dynamic scheduling controller, including the acquisition of task labels, the determination of task mapping coordinates, the real-time update of task execution status and the management of task write-back, to complete the out-of-order execution and dynamic scheduling of tasks.

[0058] The configuration network is configured to deliver control instructions and configuration data for the dynamic scheduling controller and the main controller at system initialization and runtime, so that the processing elements PE can correctly perform tasks; the state network is configured to collect and return information of all computing nodes in real time, and monitor the state of the processing elements PE performing tasks; the data network is responsible for data transmission between various modules in the system; the global variable network is configured to store and manage global variables in the system, and share data with various modules in the system; the processing element PE is a unit actually performing a computing task in the heterogeneous multi-core system, configured to receive control instructions and perform corresponding computing tasks; and the memory DDR is configured to store data during system operation.

[0059] As shown in Figures 1 to 6 The embodiment provides a cyclic scheduling method in the form of a dynamic task chain, and the cyclic scheduling method in the form of a dynamic task chain comprises the following steps:

[0060] In step 1, the scheduling control unit obtains a task tag from the memory DDR through the instruction fetch unit, generates corresponding scheduling control instructions SCI, and sends the scheduling control instructions SCI into a decision queue.

[0061] After the system is initialized, the task enters a task execution phase, the task dependency table is stored in the memory DDR, the scheduling control unit obtains a task tag with the highest priority from the task dependency table through the instruction fetch unit, and pre-processes the task tag to remove a reserved segment (the reserved segment usually refers to redundant or unnecessary information that does not affect task scheduling and execution in the task tag) to form corresponding short static task information STI (Static Task Information, STI). The task tag contains a data segment representing an execution order, the scheduling control unit determines a storage address of the static task information STI according to the data segment representing the execution order, and writes the corresponding static task information STI into a static task information library of the scheduling control unit according to the storage address.

[0062] The scheduling control unit takes out STI from the static task information library in the order of writing, and splices the main segment of STI with its different communication segments one by one, merges the splicing result with the previous task mapping coordinates, generates the corresponding scheduling control instruction SCI (Scheduling Control Instruction SCI), and sends the SCI to the judgment queue. The previous task mapping coordinates of the SCI corresponding to the scheduling task with priority 0 are set to 0. Specifically, the task label includes a main segment, a communication segment and a reserved segment, wherein there is one main segment and one or more communication segments. After taking out STI from the static task information library, first remove the reserved segment in the task label, then splice the main segment of STI with its different communication segments one by one, and then merge the splicing result with the previous task mapping coordinates (that is, the coordinates of the task that has been launched) to finally generate the corresponding scheduling control instruction SCI. One task label can generate multiple scheduling control instructions SCI. The generation process of SCI is as follows: Figure 4 shown.

[0063] In this embodiment, the task types scheduled by the heterogeneous multi-core system include independent tasks and cyclic tasks. Independent tasks do not require cyclic scheduling, and the priorities of independent tasks are different. Cyclic tasks, however, require cyclic scheduling. The priorities of cyclic tasks within a loop body (a loop body includes multiple cyclic tasks) are the same. When the scheduling control unit obtains the task tag of an independent task from the task dependency table, it obtains the task tag with the highest priority each time. When the scheduling control unit obtains the task tag of a cyclic task from the task dependency table, it obtains all the task tags of the loop body. In addition, after each cyclic task within the loop body generates a scheduling control instruction SCI, the SCI contains a data segment representing the execution order. Therefore, the priority of each SCI is different. When executing a cyclic task, it is sent to the ready queue according to the data segment representing the execution order in the SCI.

[0064] In this embodiment, during the initialization phase of the heterogeneous multi-core system, the main controller initializes the system components (including the dynamic scheduling controller) according to BIOS instructions (BIOS instructions are a set of preset instructions built into the motherboard firmware, used to initialize the hardware at startup). The dynamic scheduling controller only performs initialization and does not participate in the configuration work at this stage. After the system completes initialization and enters the task execution phase, the dynamic scheduling controller takes over control of the system's task configuration instructions and stores the original configuration instructions issued by the main controller, such as Figure 6 As shown, the dynamic scheduling controller then dynamically generates, modifies and issues these configuration instructions according to the real-time operating status of the system, as shown in Figure 1 shown.

[0065] Step 2: The judgment queue identifies the task type of the SCI. When the task type is a cyclic task (ie, a task in a loop body), step 3 is executed. When the task type is an independent task, step 7 is executed.

[0066] The scheduling control instructions SCI generated in step 1 are sent to the decision queue in turn. The decision queue identifies the task type of SCI in turn and uses different methods to process different types of scheduling control instructions SCI. In this embodiment, a cyclic scheduling method in the form of a dynamic task chain is used to process cyclic tasks.

[0067] Step 3: The scheduling control unit sends the SCI to the cyclic task queue and stores the field representing the cyclic task information in the scheduling control instruction SCI into the register.

[0068] For the first round of SCI calculations for a cyclic task, the scheduling control unit needs to enter the SCI into the cyclic task queue and simultaneously enter the field representing the cyclic task information in the SCI into the task additional information segment of the task information register group. In this embodiment, the dynamic scheduling controller provides a task information register group, which consists of several registers and is used to record frequently accessed task information, including the current task ID, the coordinates of the processing unit executing the current task, the number of outputs, and task additional information.

[0069] Step 4: The scheduling control unit searches for the SCI in the cyclic task queue that matches the processing unit coordinates of the previous task, and sends the necessary task information RMI in its main segment to the active queue, obtains the mapping result of the current RMI from the mapping unit, writes the mapping result into the RMI as the current task T_curr, and sends it to the ready queue for emission. After T_curr is emitted, the scheduling control unit obtains the mapping result of the subsequent RMI. After T_curr is executed, the scheduling control unit writes its corresponding scheduling result into the cyclic scheduling queue, and emits the tasks in the current loop body in sequence until all tasks complete the first round of scheduling. Based on the scheduling results of all tasks in the current loop body, a dynamic task chain of the loop body is generated, wherein, when the SCI has no previous task, the default processing unit coordinates are matched.

[0070] Step 4.1, the scheduling control unit searches for the SCI in the cyclic task queue that matches the coordinates of the default processing unit of the first batch of tasks, and sends its corresponding RMI to the active queue;

[0071] The scheduling control unit matches the coordinate information of the default processing unit of the first batch of tasks with the mapped coordinate segments of the SCI in the cyclic task queue one by one. If the coordinates match successfully, the RMI corresponding to the current SCI is sent to the active queue. Otherwise, the SCI is returned to the end of the cyclic task queue. Before entering the active queue, the task must match the processing unit coordinates of its predecessor task. For cyclic tasks, the first batch of tasks has no predecessor task. Therefore, when performing coordinate matching in step 4, the first batch of tasks must match the processing unit coordinates of the system default predecessor task. Here, the coordinates of the default processing unit are used.

[0072] In this embodiment, tasks within the same loop have different priorities and must be executed in a specific order. Therefore, the RMI corresponding to the highest-priority task in the loop is placed in the active queue first. Since this task has no predecessor task, the scheduling control unit uses the system's default processing unit coordinates to search the loop task queue for an SCI with matching coordinates and places the corresponding RMI in the active queue (i.e., the first task in the loop). Since the first RMI to enter the active queue has no predecessor task, there's no need to write back the result data of the predecessor task.

[0073] Step 4.2: The scheduling control unit reads the RMI in the active queue and obtains the mapping result of the current RMI from the mapping unit. It writes the mapping result into the current RMI as the current task T_curr and sends it to the ready queue for emission. After T_curr is emitted, it continues to obtain the mapping result of the subsequent RMI.

[0074] The scheduling control unit reads the RMI in the active queue and checks the launch conditions (a series of conditions that must be met during the task scheduling process set within the system to ensure that the task can be correctly sent to the execution unit), marks the RMI that currently meets the launch conditions as ready to launch, and sends its mapping identifier to the mapping unit in the dynamic scheduling controller, requests the mapping result from the mapping unit, and the mapping unit processes the received mapping identifier by optimizing the mapping mode to generate a mapping result. After obtaining the mapping result, the scheduling control unit writes it to the corresponding RMI and sends the modified RMI to the ready queue as the current task T_curr to be launched. The ready queue sends T_curr to the launch unit in the dynamic scheduling controller for launch.

[0075] After the launch unit launches the current task T_curr, the system begins executing the calculation. The scheduling control unit waits for T_curr to complete and continues to send the mapping identifier of the subsequent-stage RMI to the mapping unit to request the mapping result. The mapping unit generates the mapping result based on the mapping identifier and stores it in the candidate result queue, awaiting the scheduling control unit's call. After the current task T_curr completes, the scheduling control unit calls the mapping result from the candidate result queue and writes it to the subsequent-stage RMI. The modified RMI is then written to the ready queue as the subsequent-stage task T_succ (i.e., T_succ is the subsequent-stage task pointed to by the result data after T_curr's execution).

[0076] Step 4.3: After T_curr is executed, the scheduling control unit writes the scheduling result of T_curr into the cyclic scheduling queue, obtains the coordinate information of the processing unit corresponding to T_curr through the state network, searches for the subsequent SCI in the cyclic task queue that matches the coordinate information, and writes its corresponding RMI into the active queue;

[0077] After the currently transmitted task T_curr is completed, the scheduling control unit writes the number of T_curr, the cycle number, the task internal priority, the mapping result and the destination of the write-back result data as the scheduling result into the cycle scheduling queue.

[0078] After the currently launched task T_curr is completed, the scheduling control unit obtains the coordinate information of the processing unit used by the task through the state network, and matches the mapping coordinate segments of the SCI with the coordinate information one by one in the cyclic task queue. If the coordinates match successfully, the corresponding RMI is sent to the active queue to execute the next step. If the coordinates do not match, the SCI is put back to the end of the cyclic task queue. Among them, the subsequent RMI that is sent to the active queue due to the completion of the currently launched task T_curr will be sent to the write-back judgment module after being output from the active queue.

[0079] In step 4.4, the scheduling control unit writes the mapping result of the subsequent RMI into the corresponding RMI, and sends it to the ready queue as the subsequent task T_succ for emission. The tasks in the loop body are processed in sequence according to the methods in steps 4.2 to 4.4 until all tasks in the current loop body complete the first round of scheduling.

[0080] In this embodiment, the scheduling control unit searches the candidate result queue for the mapping result of the subsequent RMI and writes it into the corresponding RMI. The modified subsequent RMI is sent to the ready queue as T_succ, which is then sent to the transmit unit for transmission. The tasks in the loop body are processed sequentially according to the method described in steps 4.2 to 4.4 until all tasks in the current loop body have completed the first round of scheduling.

[0081] Step 4.5: Based on the scheduling results of all tasks in the current loop body, the used processing units PE and routing paths are temporarily locked to generate a dynamic task chain for the loop body.

[0082] The scheduling control unit obtains the scheduling result of the loop body according to the loop scheduling queue, obtains the data of the processing unit PE and routing path obtained in the first round of scheduling of the loop body according to the scheduling result, and temporarily locks the processing unit PE and routing path used to execute the task based on these data to form the dynamic task chain of the loop body.

[0083] The generation of a dynamic task chain must meet the following two prerequisites: the first is that the task to be scheduled must be a cyclic task; the second is that the result data of the previous task in the dynamic task chain must be written back to the processing unit of the current task.

[0084] During the dynamic task chain generation process (i.e., the first round of scheduling), there are two situations that hinder generation: 1. The result data of an intermediate task in the loop body needs to be written back to the on-chip cache or DDR, resulting in the inability to generate the dynamic task chain; 2. Insufficient on-chip resources or too many processing units used in the loop body, waiting for the dynamic task chain to be generated, blocking the sending of independent tasks for a long time.

[0085] In response to the above two situations that hinder generation, the dynamic scheduling controller uses the following method to generate dynamic task chains:

[0086] When there is an intermediate task in the loop body that needs to be written back to the on-chip cache or DDR, the dynamic scheduling controller divides the used processing units PE and routing paths into multiple groups based on the intermediate task, and generates dynamic task chains respectively, and uses these dynamic task chains to jointly complete the scheduling task. Specifically, the dynamic scheduling controller forms a dynamic task chain with the processing units from the starting task to the intermediate task, and forms another dynamic task chain with the subsequent processing units that meet the dynamic task chain generation conditions to jointly complete the scheduling of the cyclic task. During this process, if multiple identical obstructions occur, the cyclic task can be divided into multiple dynamic task chains. At this time, the dynamic scheduling controller only needs to schedule the input and output of each dynamic task chain.

[0087] When the dynamic task chain generation process blocks the execution of independent tasks, the dynamic scheduling controller enables the counter and starts counting from the temporary suspension of the independent task blockage. When the count value reaches the set threshold, the dynamic task chain stops generating and the tasks in the loop body are scheduled as independent tasks.

[0088] In this embodiment, after completing the first round of scheduling of all tasks in the entire loop body, the loop scheduling queue obtains the scheduling results of all tasks in the loop body. When performing subsequent second to Nth rounds (N is a positive integer) of loop scheduling, the scheduling control unit can obtain the scheduling results of the loop body based on the loop scheduling queue. Therefore, starting from the second round of scheduling, the scheduling control unit enters the dynamic task chain scheduling mode. During this process, the scheduling control unit not only transmits tasks according to the internal priority of the loop task, but also simultaneously issues the scheduling results of each task in the loop body. The dynamic task chain autonomously schedules tasks based on the issued scheduling results. There is no need for the scheduling control unit to directly intervene in the scheduling process in the same way as the first round of task scheduling, thereby simplifying the scheduling requirements in subsequent cycles.

[0089] Step 5: The write-back judgment module receives the subsequent RMI output by the active queue, and selects the write-back method of the T_curr result data according to the specific bit information in the subsequent RMI and the usage of the corresponding processing unit. The scheduling control unit performs the write-back operation according to the selected write-back method.

[0090] The loop body includes multiple loop tasks. After the current task is completed, the result data needs to be written back to the local storage of the processing unit corresponding to the subsequent task. The launch status of the subsequent task and the usage of the corresponding processing unit will affect the write-back method. In this embodiment, different situations correspond to different write-back methods.

[0091] As can be seen from the above step 4.3, after T_curr is executed, the scheduling control unit obtains the coordinate information of the processing unit corresponding to T_curr through the state network and reads the SCI in the cyclic task queue, finds the SCI that matches the coordinate information, and writes its corresponding RMI into the active queue. The subsequent RMI sent to the active queue due to the completion of the current task T_curr will be sent to the write-back judgment module in turn. The write-back judgment module selects the write-back method of the T_curr result data based on the specific bit information in the subsequent RMI and the usage of the corresponding processing unit, and performs the write-back operation, as follows:

[0092] Step 5.1: The write-back judgment module determines whether there is a subsequent task T_succ based on the matching result of the coordinate information of the processing unit corresponding to T_curr and the SCI. If there is no SCI matching the coordinate information of the currently transmitted task T_curr in the cyclic task queue (i.e., there is no subsequent SCI of T_curr), it is determined that the currently transmitted task T_curr has no subsequent task T_succ, and a forced write-back DDR operation is performed on the result data of T_curr. The scheduling control unit itself does not generate a write-back SCI. If there is an SCI matching the coordinate information of the currently transmitted task T_curr in the cyclic task queue, it is determined that the currently transmitted task T_curr has a subsequent task T_succ, and step 5.2 is executed.

[0093] In step 5.2, the write-back determination module determines whether the priority difference between the subsequent-stage RMI (i.e., the RMI corresponding to the subsequent-stage SCI) and T_curr is greater than 1 based on the specific bit information. If so, a forced write-back DDR operation is performed on T_curr's result data. The scheduling control unit generates a Type III write-back SCI and writes it into the Type III write-back SCI queue. The wake-up condition for the write-back operation of the T_curr result data in the Type III write-back SCI queue is set to: T_succ has been transmitted. Once the wake-up condition is met, the scheduling control unit writes T_curr's result data to the local storage of the processing unit corresponding to T_succ. If the priority difference between the subsequent-stage RMI and T_curr is less than or equal to 1, step 5.3 is executed.

[0094] Step 5.3: Obtain the processing unit type of T_succ corresponding to the subsequent RMI. The write-back judgment module determines the write-back type based on the emission status of T_succ and the idle status of the processing unit type fed back by the mapping unit. The rules are as follows:

[0095] When T_succ has been transmitted, the write-back judgment module determines to directly perform the write-back operation, and the scheduling control unit writes the result data of T_curr into the local storage of the processing unit corresponding to T_succ; wherein, the scheduling control unit informs the transmitting unit of the write-back status of the result data of T_curr through the work_mode signal so that the transmitting unit can perform the write-back operation.

[0096] When T_succ is not transmitted and there are enough processing units of the corresponding type, the write-back judgment module determines to temporarily suspend the write-back operation, and the scheduling control unit temporarily suspends the write-back operation of the result data of T_curr until the configuration of the corresponding processing unit is completed, and then writes the result data of T_curr into the local storage of the processing unit of T_succ; wherein, the scheduling control unit will inform the transmitting unit of the write-back status of the result data of T_curr through the work_mode signal so that the transmitting unit can perform the write-back operation.

[0097] When there are insufficient processing units of the corresponding type, the write-back judgment module determines to write back to the on-chip cache. The scheduling control unit writes the result data of T_curr back to the on-chip cache, generates a Type I write-back SCI, and writes it into the Type I write-back SCI queue. The wake-up condition for the write-back operation of the result data of T_curr in the Type I write-back SCI queue is set as follows: there is an idle processing unit of the corresponding type or T_succ has been transmitted. After the wake-up condition is met, the scheduling control unit writes the result data of T_curr to the local storage of the processing unit corresponding to T_succ. Specifically, the scheduling control unit selects the type of processing unit with the most idle units on the current chip and selects one of them as the on-chip cache to store the result data of T_curr.

[0098] When there are insufficient processing units of the corresponding type and the on-chip cache is insufficient, the write-back judgment module determines to write back to the memory DDR, and the scheduling control unit writes the result data of T_curr back to the DDR, generates a Type II write-back SCI and writes it into the Type II write-back SCI queue, and sets the wake-up condition for the write-back operation of the result data of T_curr in the Type II write-back SCI queue to: there is an idle processing unit of the corresponding type or T_succ has been emitted; after the wake-up condition is met, the scheduling control unit writes the result data of T_curr into the local storage of the processing unit corresponding to T_succ.

[0099] Specifically, for the three situations of writing back to DDR due to a priority difference between the subsequent RMI and T_curr being greater than 1, writing back to the on-chip cache due to insufficient corresponding processing units, and writing back to the memory DDR due to insufficient on-chip cache, the scheduling control unit will generate a specific communication task based on the cache identifier provided by the write-back management unit in the dynamic scheduling controller, and send the communication task to the ready queue. At the same time, the communication task is copied to the write-back SCI queue to generate a write-back SCI. These SCIs generated by copying are called write-back SCIs, and the queue that stores the write-back SCIs is called the write-back SCI queue. Among them, the communication task generated due to writing back to DDR due to a priority difference between the subsequent RMI and T_curr being greater than 1 corresponds to Type III write-back SCI, the communication task generated due to writing back to the on-chip cache due to insufficient corresponding processing units corresponds to Type I write-back SCI, and the communication task generated due to writing back to the memory DDR due to insufficient on-chip cache corresponds to Type II write-back SCI, where I, II, and III represent the type identifiers of the write-back SCI. In this embodiment, during the task scheduling process, different wake-up conditions are set for the three types of write-back SCIs generated by the scheduling control unit, namely Type I write-back SCI, Type II write-back SCI and Type III write-back SCI, and independent queues are configured for these three types of write-back SCIs. When the wake-up conditions are met, the write-back SCI will be activated by the scheduling control unit to perform the write-back operation.

[0100] The above-mentioned write-back operation is performed on the result data of the launched tasks in sequence until the first round of scheduling of all tasks in the loop body is completed. In this embodiment, after the scheduling control unit enters the dynamic task chain scheduling mode, the processing units and routing paths involved in the calculation will be temporarily locked. They will not be released immediately after the processing unit completes a calculation. They will only be released after the loop ends. This ensures that after the first round of scheduling of the loop task, the subsequent second to N rounds of scheduling can be successfully completed based on the scheduling results in the loop scheduling queue. During the second to N rounds of scheduling of the loop body task, the result data of T_curr is directly written back to the processing unit corresponding to T_succ.

[0101] Step 6: After the first round of scheduling is completed, the scheduling control unit directly sends the necessary task information RMI corresponding to the SCI in the cyclic task queue to the ready queue for transmission according to the scheduling result in the cyclic scheduling queue, and performs a write-back operation.

[0102] After the tasks in the loop body complete the first round of scheduling, a dynamic task chain of the loop body tasks is generated, and the scheduling control unit enters the dynamic task chain scheduling mode to perform the second to Nth rounds of loop scheduling.

[0103] Step 6.1, the tasks in the loop body start the second round of scheduling. The scheduling control unit directly sends the RMI corresponding to the SCI in the loop task queue to the ready queue in sequence according to the scheduling results corresponding to the tasks in the loop body;

[0104] The loop scheduling queue includes the scheduling results corresponding to the RMI. The scheduling control unit can read the data in the scheduling results. There is no need to perform the complicated scheduling process in step 4 again. It only needs to execute the loop task through the formed dynamic task chain. That is, the dynamic scheduling controller only schedules the input and output of the dynamic task chain, avoiding secondary scheduling inside the loop body.

[0105] In step 6.2, the ready queue sends the tasks corresponding to the RMI to the launch unit in the order of writing for launch. After each task is completed, the scheduling control unit notifies the launch unit to perform the write-back operation through a signal.

[0106] In this embodiment, after the scheduling control unit enters the dynamic task chain scheduling mode, the processing units and routing paths in the dynamic task chain can only be used to execute the current cyclic task. Therefore, after the current task is completed, the scheduling control unit will hand over the operation of writing back the current task result data to the transmitting unit through the work_mode signal, and the transmitting unit will perform the write-back operation.

[0107] In step 6.3, the dynamic scheduling controller checks whether the current loop task meets the end condition. If so, the loop is terminated and the processing units and routing paths occupied by the loop task are released in sequence. If not, the next round of loop scheduling is continued.

[0108] In this embodiment, the heterogeneous multi-core system divides loop tasks into two categories: the first category is explicit loop tasks. The characteristic of this type of loop task is that the number of loops is determined before the task is executed, and the number of loops can be given by a global variable in the heterogeneous multi-core system. The second category is implicit loop tasks. The characteristic of this type of loop task is that the number of loops cannot be determined before the task is executed, and a conditional judgment is required after each round of loop tasks ends. The dynamic task chain scheduling mode can support the scheduling of explicit loop tasks and implicit loop tasks; for explicit loop tasks, the end condition is provided by a global variable. For example, if the end condition is to reach the corresponding number of loops, the system will count each time a loop is completed, and when the number of loops reaches the set value, the loop is terminated. For implicit loop tasks, the dynamic scheduling controller will issue the loop end condition as the last task of the loop body. After each round of calculation, it will check whether the end condition is met. If the loop body task meets the end condition, the processing units occupied by the loop body task will be released in order, otherwise the next round of loop scheduling will continue.

[0109] Step 7: The scheduling control unit sends the RMI of the SCI with the highest priority to the active queue and sends the remaining SCIs to the dormant queue.

[0110] The scheduling control unit identifies the priority of the current scheduling control instruction SCI, and sends the required mission information RMI (Required Mission Information, RMI) in the main segment of the SCI with the highest priority to the active queue, and sends the remaining SCIs with lower priorities to the sleep queue, where the necessary task information RMI includes the amount of task input data, the type of processing unit PE (Process Element, processing unit) required for the task, etc.; in this embodiment, when the heterogeneous multi-core system is scheduled for the first time, the SCI with a priority of 0 is sent to the active queue, and the SCI with a priority greater than 0 is sent to the sleep queue.

[0111] In this embodiment, for the scheduling control instructions SCI of independent tasks, different SCIs have different priorities, and the RMIs corresponding to the SCIs also have different priorities. The RMIs with higher priorities are processed first so that the tasks with higher priorities can obtain system resources first.

[0112] Step 8: The scheduling control unit reads the RMI in the active queue and obtains the mapping result of the current RMI from the mapping unit. After writing the mapping result into the corresponding RMI, it is sent to the ready queue as the current task T_curr for transmission. After T_curr transmission is completed, the mapping result of the subsequent task is obtained.

[0113] The scheduling control unit reads the RMIs in the active queue one by one and checks the launch conditions (a series of conditions that must be met during the task scheduling process set within the system to ensure that the task can be correctly sent to the execution unit), marks the RMI that meets the launch conditions as ready to launch, and sends its mapping identifier to the mapping unit in the dynamic scheduling controller, requests the mapping result from the mapping unit, and the mapping unit processes the received mapping identifier by optimizing the mapping mode to generate a mapping result. After obtaining the mapping result, the scheduling control unit writes it to the corresponding RMI and sends the modified RMI to the ready queue as the task to be launched. The ready queue sends the task to be launched to the launch unit in the dynamic scheduling controller in sequence according to the write order to launch the task.

[0114] After the launch unit launches the current task T_curr, the system begins executing the calculation. The scheduling control unit waits for T_curr to complete and continues to send the mapping identifier of the subsequent-stage RMI to the mapping unit to request the mapping result. The mapping unit generates the mapping result based on the mapping identifier and stores it in the candidate result queue, awaiting the scheduling control unit's call. After the current task T_curr completes, the scheduling control unit calls the mapping result from the candidate result queue and writes it to the subsequent-stage RMI. The modified RMI is then written to the ready queue as the subsequent-stage task T_succ (i.e., T_succ is the subsequent-stage task pointed to by the result data after T_curr's execution).

[0115] Step 9: The scheduling control unit searches the dormant queue for an SCI that matches the processing unit coordinates of the currently launched task T_curr, and sends its RMI to the active queue. The write-back judgment module selects a write-back method for the result data of T_curr based on the information of T_curr and the information of the RMI output by the active queue, and performs the write-back operation, which specifically includes:

[0116] Step 9.1: The scheduling control unit matches the coordinate information of the processing unit PE used by the currently launched task T_curr with the mapped coordinate segments of the scheduling control instruction SCI in the sleep queue one by one. If the coordinates match successfully, the RMI of SCI is sent to the active queue as the next-level RMI. Otherwise, SCI is placed back to the end of the sleep queue.

[0117] After the currently launched task T_curr is completed, the scheduling control unit obtains the coordinate information of the processing unit PE used by the task through the state network, and matches the mapping coordinate segments of the SCI with the coordinate information one by one in the sleep queue. If the coordinates match successfully, the RMI of the corresponding SCI is sent to the active queue to execute the next step. If the coordinates do not match, the SCI is put back to the end of the sleep queue. This subsequent RMI that is sent to the active queue due to the completion of the currently launched task T_curr will be sent to the write-back judgment module in sequence after being output from the active queue.

[0118] Step 9.2: The write-back judgment module receives the RMI output by the active queue, and selects the write-back method for the result data of the currently emitted task T_curr according to the specific bit information in the RMI and the usage of the corresponding processing unit, and performs the write-back operation.

[0119] The process of selecting the write-back mode and executing the write-back operation in this step is the same as that in step 5. The write-back judgment module determines whether there is a subsequent task T_succ based on the matching result of the coordinate information of the processing unit corresponding to T_curr and the SCI. If there is no subsequent SCI for the currently transmitted task T_curr, it is determined that the currently transmitted task T_curr has no subsequent task T_succ, and a forced write-back DDR operation is performed on the result data of T_curr. The scheduling control unit itself does not generate a write-back SCI. If there is a subsequent SCI for the currently transmitted task T_curr, it is determined that the currently transmitted task T_curr has a subsequent task T_succ.

[0120] After discovering the subsequent-stage RMI of the currently launched task T_curr, the write-back judgment module determines whether the priority difference between the subsequent-stage RMI and T_curr is greater than 1 based on the specific bit information of the subsequent-stage RMI. If it is greater than 1, a forced write-back DDR operation is performed on the result data of T_curr. The scheduling control unit generates a Type III write-back SCI and writes it into the Type III write-back SCI queue. The wake-up condition for the write-back operation of the result data of T_curr in the Type III write-back SCI queue is set to: T_succ has been launched; if the priority difference between the subsequent-stage RMI and T_curr is less than or equal to 1, the processing unit type of T_succ corresponding to the subsequent-stage RMI is obtained. The write-back judgment module determines the write-back type based on the launch status of T_succ and the idle status of the processing unit of this type fed back by the mapping unit. The rules are as follows:

[0121] When T_succ has been transmitted, the write-back judgment module determines to directly perform the write-back operation, and the scheduling control unit writes the result data of T_curr into the local storage of the processing unit corresponding to T_succ; wherein, the scheduling control unit informs the transmitting unit of the write-back status of the result data of T_curr through the work_mode signal so that the transmitting unit can perform the write-back operation.

[0122] When T_succ is not transmitted and there are enough processing units of the corresponding type, the write-back judgment module determines to temporarily suspend the write-back operation, and the scheduling control unit temporarily suspends the write-back operation of the result data of T_curr until the configuration of the corresponding processing unit is completed, and then writes the result data of T_curr into the local storage of the processing unit of T_succ; wherein, the scheduling control unit will inform the transmitting unit of the write-back status of the result data of T_curr through the work_mode signal so that the transmitting unit can perform the write-back operation.

[0123] When there are insufficient processing units of the corresponding type, the write-back judgment module determines to write back to the on-chip cache, and the scheduling control unit writes the result data of T_curr back to the on-chip cache, and generates an I-type write-back SCI to write into the I-type write-back SCI queue, and sets the wake-up condition for the write-back operation of the result data of T_curr in the I-type write-back SCI queue to: there is an idle processing unit of the corresponding type or T_succ has been emitted; specifically, the scheduling control unit selects the type of the processing unit with the most idle units on the current chip, and selects one of the processing units as the on-chip cache to store the result data of T_curr.

[0124] When there are insufficient processing units of the corresponding type and the on-chip cache is insufficient, the write-back judgment module determines to write back to the memory DDR, the scheduling control unit writes the result data of T_curr back to the DDR, and generates a Type II write-back SCI to write into the Type II write-back SCI queue, and sets the wake-up condition for the write-back operation of the result data of T_curr in the Type II write-back SCI queue to: there is an idle processing unit of the corresponding type or T_succ has been emitted.

[0125] This embodiment establishes an operating mechanism for a heterogeneous multi-core system. During system operation, the main controller and the dynamic scheduling controller collaborate to manage system operation and task scheduling. This heterogeneous multi-core system operating mechanism includes independent task scheduling mode and dynamic task chain scheduling mode. The aforementioned dynamic task chain-based cyclic scheduling method is used for scheduling cyclic tasks, which is the dynamic task chain scheduling mode. Heterogeneous multi-core systems also include independent task scheduling, which is the independent task scheduling mode.

[0126] In summary, the present application proposes a loop scheduling method in the form of a dynamic task chain, which is suitable for dynamic task scheduling of heterogeneous multi-core computing systems based on a coarse-grained reconfigurable architecture and oriented to intensive computing applications. In this method, the dynamic scheduling controller regards the loop body task as a whole, and the loop body task is given a unified priority. When the loop task is executed in the first round, the loop body task is scheduled in sequence and the loop task scheduling results are recorded to generate a dynamic task chain. The loops after the first round are scheduled using the dynamic task chain. In the subsequent loop execution process, the dynamic scheduling controller only schedules the input and output of the dynamic task chain to avoid secondary scheduling inside the loop body. Through the technical solution of the present application, the problem that the existing dynamic scheduling solution cannot support loop task scheduling is effectively solved, the scheduling quality of loop tasks is effectively improved, and the scheduling overhead of loop tasks is significantly reduced, thereby improving the computing performance of the heterogeneous multi-core processor system.

[0127] The steps in this application can be adjusted in order, combined, and deleted according to actual needs.

[0128] The units in the device of the present application can be combined, divided and deleted according to actual needs.

[0129] Although the present application is disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and are not intended to limit the application of the present application. The scope of protection of the present application is defined by the appended claims and may include various modifications, alterations and equivalents made to the invention without departing from the scope and spirit of the present application.

Claims

1. A dynamic task chain-based cyclic scheduling method for a heterogeneous multi-core system, wherein the heterogeneous multi-core system comprises a dynamic scheduling controller and a state network, wherein the dynamic scheduling controller comprises a scheduling control unit, a mapping unit, and a transmitting unit, wherein: The method comprises: Step 1: The scheduling control unit obtains the task label and generates the corresponding scheduling control instruction SCI, which is sent to the decision queue; Step 2: The judgment queue identifies the task type of SCI. If it is a cyclic task, execute step 3; if it is an independent task, execute step 7. Step 3: The scheduling control unit sends the SCI to the cyclic task queue and stores the field representing the cyclic task information in the SCI; Step 4: The scheduling control unit searches for the SCI in the cyclic task queue that matches the processing unit coordinates of the previous task, and sends the necessary task information RMI in its main segment to the active queue, obtains the mapping result of the current RMI from the mapping unit, writes the mapping result into the RMI as the current task T_curr, and sends it to the ready queue for emission. After T_curr is emitted, the scheduling control unit obtains the mapping result of the subsequent RMI. After T_curr is executed, the scheduling control unit writes its corresponding scheduling result into the cyclic scheduling queue, and emits the tasks in the current loop body in sequence until all tasks complete the first round of scheduling. Based on the scheduling results of all tasks in the current loop body, a dynamic task chain of the loop body is generated, wherein, when the SCI has no previous task, the default processing unit coordinates are matched; Step 5: The write-back determination module receives the subsequent RMI output by the active queue, and selects a write-back method for the result data of T_curr based on the specific bit information in the subsequent RMI and the usage of the corresponding processing unit, and performs the write-back operation according to the selected write-back method; Step 6: After the first round of scheduling is completed, the scheduling control unit directly sends the RMI corresponding to the SCI in the cyclic task queue to the ready queue for transmission according to the scheduling result in the cyclic scheduling queue, and performs a write-back operation; Step 7: The scheduling control unit sends the RMI of the SCI with the highest priority to the active queue and sends the remaining SCIs to the dormant queue; Step 8: The scheduling control unit reads the RMI in the active queue and obtains the mapping result of the current RMI from the mapping unit. The mapping result is written into the RMI as the current task T_curr and sent to the ready queue for emission. After T_curr is emitted, the mapping result of the subsequent task is obtained. Step 9: The scheduling control unit searches for the SCI in the dormant queue that matches the processing unit coordinates of T_curr, and sends its RMI to the active queue. The write-back judgment module selects the write-back method for the result data of T_curr based on the information of T_curr and the information of the subsequent RMI, and performs the write-back operation.

2. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 1, characterized in that: The step 4 specifically includes: Step 4.1, the scheduling control unit searches for the SCI in the cyclic task queue that matches the coordinates of the default processing unit of the first batch of tasks, and sends the corresponding RMI to the active queue; Step 4.2: The scheduling control unit reads the RMI in the active queue and obtains the mapping result of the current RMI from the mapping unit, writes the mapping result into the current RMI as the current task T_curr, and sends it to the ready queue for emission. After T_curr is emitted, it continues to obtain the mapping result of the subsequent RMI; Step 4.3: After T_curr is executed, the scheduling control unit writes the scheduling result of T_curr into the cyclic scheduling queue, obtains the coordinate information of the processing unit corresponding to T_curr through the state network, searches for the subsequent SCI matching the coordinate information in the cyclic task queue, and writes its corresponding RMI into the active queue; In step 4.4, the scheduling control unit writes the mapping result of the subsequent RMI into the corresponding RMI and sends it to the ready queue as the subsequent task T_succ for emission. The tasks in the loop body are processed in sequence according to the methods in steps 4.2 to 4.4 until all tasks in the current loop body complete the first round of scheduling; Step 4.5: Based on the scheduling results of all tasks in the current loop body, the used processing units and routing paths are temporarily locked to generate a dynamic task chain for the loop body.

3. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 2, characterized in that: The step 5 specifically includes: Step 5.1: The write-back judgment module determines whether T_curr has a subsequent task T_succ based on the coordinate matching results of T_curr and SCI. If there is no SCI matching the coordinate information of T_curr in the cyclic task queue, it is determined that T_curr does not have T_succ, and the result data of T_curr is forcibly written back to DDR. If there is an SCI matching the coordinate information of T_curr in the cyclic task queue, it is determined that T_curr has T_succ, and step 5.2 is executed. Step 5.2: Determine whether the priority difference between the RMI and T_curr is greater than 1 based on the specific bit information of the subsequent stage RMI. If it is greater than 1, the result data of T_curr is forcibly written back to the DDR. The scheduling control unit generates a Type III write-back SCI and writes it into the Type III write-back SCI queue. The wake-up condition is set to: T_succ has been transmitted. If the priority difference between the RMI and T_curr is less than or equal to 1, execute step 5.

3. Step 5.3, obtain the processing unit type corresponding to the subsequent RMI, and determine the write-back type based on the emission status of the corresponding T_succ and the idle status of the processing unit type, as follows: If T_succ has been emitted, write the result data of T_curr into the local storage of the processing unit corresponding to T_succ; If T_succ has not been issued and there are enough processing units of the corresponding type, the write-back operation is temporarily suspended until the corresponding processing unit is configured, and then the result data of T_curr is written to the local storage of the processing unit of T_succ; If the corresponding type of processing units is insufficient, the result data of T_curr is written back to the on-chip cache, the scheduling control unit generates an I-type write-back SCI and writes it into the I-type write-back SCI queue, and sets the wake-up condition as: there is an idle processing unit of the corresponding type or T_succ has been emitted; If there are insufficient processing units of the corresponding type and the on-chip cache is insufficient, the result data of T_curr is written back to the DDR, the scheduling control unit generates a Type II write-back SCI and writes it into the Type II write-back SCI queue, and sets the wake-up condition as: there is an idle processing unit of the corresponding type or T_succ has been transmitted.

4. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 3, characterized in that: During the dynamic task chain generation process, when there is an intermediate task in the loop body that needs to be written back to the on-chip cache or DDR, the dynamic scheduling controller divides the used processing units and routing paths into multiple groups based on the intermediate task, and generates dynamic task chains for each group, and uses these dynamic task chains to jointly complete the scheduling task; when the dynamic task chain generation process blocks the execution of an independent task, the dynamic scheduling controller enables a counter and starts counting from the temporary suspension of the independent task blockage. When the count value reaches a set threshold, the dynamic task chain stops generating and the tasks in the loop body are scheduled as independent tasks.

5. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 3, characterized in that: The step 6 specifically includes: Step 6.1, the scheduling control unit directly sends the RMI corresponding to the SCI in the loop task queue to the ready queue in sequence according to the scheduling results corresponding to the tasks in the loop body; Step 6.2: The ready queue sends the tasks corresponding to the RMI to the launch unit in the order of writing. After each task is completed, the scheduling control unit notifies the launch unit to perform the write-back operation through a signal. In step 6.3, the dynamic scheduling controller checks whether the current loop task meets the end condition. If so, the loop is terminated and the processing units and routing paths occupied by the loop task are released. Otherwise, the next round of loop scheduling is continued.

6. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 1, characterized in that: The step 9 specifically includes: Step 9.1, the scheduling control unit matches the coordinate information of the T_curr processing unit with the mapped coordinate segments of the SCI in the sleep queue one by one. If the coordinates match successfully, the RMI of the SCI is sent to the active queue as the subsequent RMI, otherwise the SCI is put back to the end of the sleep queue; Step 9.2: The write-back judgment module receives the subsequent RMI output by the active queue, and selects the write-back method for the result data of T_curr according to the specific bit information in the subsequent RMI and the usage of the corresponding processing unit, and performs the write-back operation.

7. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 1, characterized in that: The step 1 specifically includes: The scheduling control unit obtains the task tag with the highest priority from the memory, and preprocesses the task tag to form the corresponding static task information STI. The storage address of the STI is determined according to the data segment representing the execution order in the task tag, and the STI is written into the static task information library of the scheduling control unit in sequence according to the storage address. The STI is then retrieved from the static task information library in the writing order, and the main segment of the STI is spliced ​​with its different communication segments one by one. The splicing result is merged with the previous task mapping coordinate to generate the corresponding SCI, and the SCI is sent to the judgment queue.

8. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 4, characterized in that: The prerequisite for generating the dynamic task chain is that the task to be scheduled is a cyclic task, and the result data of the previous task must be written back to the processing unit of the current task.

9. The cyclic scheduling method in the form of a dynamic task chain as claimed in claim 6, characterized in that: The write-back method and operation of the result data of selecting T_curr in step 9.2 are the same as those in step 5.

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