Signed multiplication and multiplication-accumulation circuit based on 14T-TFET-SRAM unit circuit

Abstract

The present application relates to a signed multiplication and multiplication-accumulation operation circuit based on a 14T-TFET-SRAM unit circuit, wherein the unit circuit includes NTFET tubes N0-N6 and PTFET tubes P0-P6; the source, drain and gate of P0 are electrically connected to the drain of P4, the drain and gate of N0, respectively, and the drain of P0 is provided with a storage node Q; the source, drain and gate of P1 are electrically connected to the power supply VDD, the drain and gate of N1, respectively, and the drain of P1 is provided with a storage node QB; the source, drain and gate of P2 are electrically connected to the drain of P3, the drain of N2 and the gate of N4, respectively; the source and gate of P3 are electrically connected to the power supply VDD and the write control signal line WLB, respectively; the source and gate of P4 are electrically connected to the power supply VDD and the gate of N2, respectively. The invention relates to a transistor-based SRAM cell circuit comprising a first transistor and a second transistor; ...

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a signed multiplication and multiplication-accumulation operation circuit based on a 14T-TFET-SRAM unit circuit. Background Art

[0002] To overcome the problem in von Neumann architecture computer systems where the data transfer rate between memory and the processor (CPU) cannot keep pace with the processor's ultra-high data processing rate, creating a bottleneck in the computer system's data processing efficiency, researchers have proposed a new computing mechanism that can perform calculations in memory, namely Computing-In-Memory (CIM). The CIM architecture can be implemented based on a variety of memories.

[0003] Among the various memory chips that support storage-computing architectures, static random access memory (SRAM) has been proven to be one of the mature structures in the CIM system due to its excellent characteristics of low power consumption and high speed. Most existing SRAMs are based on CMOS processes; however, affected by the Boltzmann distribution, the subthreshold swing of traditional MOSFET devices has physical limits in low-voltage applications, which greatly affects the switching characteristics of MOSFET devices. Its leakage current increases exponentially with decreasing voltage, which greatly hinders its application in ultra-low power chips. At the same time, the existing CIM chips based on the dual-port 6T-CMOS-SRAM structure design generally have a read corruption problem that cannot be ignored.

[0004] Compared to MOSFET devices, tunneling field-effect transistors (TFETs), as non-Boltzmann distribution devices, have higher switching ratios and lower subthreshold swings, which makes TFET devices have broad application prospects in the field of low voltage and low power consumption, and have great potential in replacing MOSFET devices. However, due to the uneven doping of the source and drain of TFET devices and their unidirectional conductivity, they may have forward bias currents that are not controlled by the gate voltage during operation, which will increase the static power consumption of the TFET-SRAM unit circuit and the SRAM, and destroy the voltage stability of the storage node.

[0005] Currently, no effective solution has been proposed to the problem of high static power consumption of existing TFET-SRAM unit circuits. Summary of the Invention

[0006] The present invention provides a 14T-TFET-SRAM unit circuit, an operation circuit, a CIM chip and a memory to solve the problem of high static power consumption of the existing TFET-SRAM unit circuit.

[0007] In a first aspect, the present invention provides a 14T-TFET-SRAM unit circuit, wherein the 14T-TFET-SRAM unit circuit includes first to seventh NTFET transistors and first to seventh PTFET transistors;

[0008] The source, drain and gate of the first PTFET transistor P0 are electrically connected to the drain of the fifth PTFET transistor P4 and the drain and gate of the first NTFET transistor N0 respectively. The drain of the first PTFET transistor P0 is provided with a first storage node Q.

[0009] The source, drain and gate of the second PTFET transistor P1 are electrically connected to the power supply VDD and the drain and gate of the second NTFET transistor N1 respectively, and the drain of the second PTFET transistor P1 is provided with a second storage node QB;

[0010] The source, drain, and gate of the third PTFET transistor P2 are electrically connected to the drain of the fourth PTFET transistor P3, the drain of the third NTFET transistor N2, and the gate of the fifth NTFET transistor N4, respectively;

[0011] The source and gate of the fourth PTFET transistor P3 are electrically connected to the power supply VDD and the first row write control signal line WLB respectively;

[0012] The source and gate of the fifth PTFET transistor P4 are electrically connected to the power supply VDD and the gate of the third NTFET transistor N2, respectively;

[0013] The source, drain and gate of the sixth PTFET transistor P5 are electrically connected to the drain of the seventh PTFET transistor P6, the first bit line RBLB and the drain of the second NTFET transistor N1, respectively;

[0014] The source and gate of the seventh PTFET transistor P6 are electrically connected to the power supply VDD and the first input word line INWLB respectively;

[0015] The source of the first NTFET transistor N0 is electrically connected to the drain of the fifth NTFET transistor N4;

[0016] The source of the second NTFET transistor N1 is electrically connected to the ground line VSS;

[0017] The source and gate of the third NTFET transistor N2 are electrically connected to the drain of the fourth NTFET transistor N3 and the first column write control signal BLB, respectively;

[0018] The source and gate of the fourth NTFET transistor N3 are electrically connected to the ground line VSS and the second row write control signal line WL, respectively;

[0019] The source and gate of the fifth NTFET transistor N4 are electrically connected to the ground line VSS and the second column write control signal line BL, respectively;

[0020] The source, drain, and gate of the sixth NTFET transistor N5 are electrically connected to the ground line VSS, the source of the seventh NTFET transistor N6, and the drain of the third NTFET transistor N2, respectively;

[0021] The drain and gate of the seventh NTFET transistor N6 are electrically connected to the second bit line RBL and the second input word line INWL, respectively.

[0022] In a second aspect, the present invention provides a 14T-TFET-SRAM unit circuit array, which includes a plurality of 14T-TFET-SRAM unit circuits according to the first aspect distributed in an array.

[0023] In a third aspect, the present invention provides a signed multiplication and multiplication-accumulation operation circuit based on a 14T-TFET-SRAM unit circuit, wherein the signed multiplication and multiplication-accumulation operation circuit includes the 14T-TFET-SRAM unit circuit array described in the second aspect, and the 14T-TFET-SRAM unit circuit array includes M×N 14T-TFET-SRAM unit circuits.

[0024] In a fourth aspect, the present invention provides a 14T-TFET-SRAM operation method, which is applied to the signed multiplication and multiplication-accumulation operation circuit based on the 14T-TFET-SRAM unit circuit described in the third aspect;

[0025] The operation method includes:

[0026] The M×N 14T-TFET-SRAM cell circuit array is divided into multiple Mi×N sub-arrays from top to bottom, and each Mi×N sub-array uses an independent first bit line RBLB and a second bit line RBL;

[0027] The data to be pre-stored is stored in different Mi×N sub-arrays from top to bottom in the order of the least significant bit to the most significant bit;

[0028] The second bit line RBL of each column is precharged to a high level and the first bit line RBLB is precharged to a low level, and signed and unsigned numbers are input through the second input word line INWL and the first input word line INWLB respectively, generating signals with different pulse widths according to the values;

[0029] When the discharge / charge results of the first bit line RBLB and the second bit line RBL are stable, the switches between the first global bit line GBLN and the second global bit line GBLP and each Mi×N sub-array are sequentially opened to perform charge sharing, and the voltages on the first global bit line GBLN and the second global bit line GBLP are quantized to obtain a multiplication-accumulation result.

[0030] Subtract the negative value from the quantized positive value to get the final multiplication and accumulation result.

[0031] In a fifth aspect, the present invention provides a CIM chip, which integrates a plurality of signed multiplication and multiplication-accumulation operation circuits based on the 14T-TFET-SRAM unit circuit described in the third aspect and peripheral circuits cooperating with the signed multiplication and multiplication-accumulation operation circuits.

[0032] Compared to related technologies, the 14T-TFET-SRAM unit circuit provided by the present invention implements read-write separation by providing an independent data read channel. This prevents the read corruption problem caused by opening multiple rows in traditional 6T-SRAM and simultaneously supports multi-bit multiplication and multiply-accumulate operations between signed and unsigned numbers. Furthermore, the drain voltage of transistor N5 is always no lower than the source voltage of transistor N5, thereby preventing the TFET from generating forward bias current uncontrolled by the gate, reducing the static power consumption of the unit circuit, and solving the problem of high static power consumption in existing TFET-SRAM unit circuits.

[0033] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a structural diagram of a 14T-TFET-SRAM unit circuit provided in an embodiment of the present invention;

[0035] Figure 2 is an operating timing diagram of a 14T-TFET-SRAM unit circuit provided in an embodiment of the present invention;

[0036] Figure 3 is a structural diagram of a 2×2 unit circuit array provided in an embodiment of the present invention;

[0037] Figure 4 This is a data comparison chart of the static power consumption of a 2×2 unit circuit array provided in an embodiment of the present invention and the static power consumption of other arrays with the same structure;

[0038] Figure 51 is a structural diagram of a signed multiplication and multiplication-accumulation operation circuit based on a 14T-TFET-SRAM unit circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0040] Unless otherwise defined, the technical terms or scientific terms involved in this application should have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "an", "a", "the", "these" and the like in this application do not indicate quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "plurality" involved in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. Generally, the character " / " indicates that the related objects are in an "or" relationship. The terms "first," "second," "third," etc. used in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0041] The present invention provides a 14T-TFET-SRAM unit circuit, Figure 1 14T-TFET-SRAM unit circuit provided in an embodiment of the present invention, as shown in FIG. Figure 1 As shown, the 14T-TFET-SRAM unit circuit includes first to seventh NTFET transistors and first to seventh PTFET transistors.

[0042] The source, drain and gate of the first PTFET transistor P0 are electrically connected to the drain of the fifth PTFET transistor P4 and the drain and gate of the first NTFET transistor N0, respectively. The drain of the first PTFET transistor P0 is provided with a first storage node Q; the source, drain and gate of the second PTFET transistor P1 are electrically connected to the power supply VDD and the drain and gate of the second NTFET transistor N1, respectively. The drain of the second PTFET transistor P1 is provided with a second storage node QB; the source, drain and gate of the third PTFET transistor P2 are electrically connected to the drain of the fourth PTFET transistor P3, the drain of the third NTFET transistor N2 and the gate of the fifth NTFET transistor N4, respectively; the source and gate of the fourth PTFET transistor P3 are electrically connected to the power supply VDD and the first row write control signal line WLB, respectively; the source and gate of the fifth PTFET transistor P4 are electrically connected to the power supply VDD and the gate of the third NTFET transistor N2, respectively; the source, drain and gate of the sixth PTFET transistor P5 are electrically connected to the drain of the seventh PTFET transistor P6, the first bit line RBLB is electrically connected to the drain of the second NTFET transistor N1; the source and gate of the seventh NTFET transistor P6 are electrically connected to the power supply VDD and the first input word line INWLB, respectively; the source of the first NTFET transistor N0 is electrically connected to the drain of the fifth NTFET transistor N4; the source of the second NTFET transistor N1 is electrically connected to the ground line VSS; the source and gate of the third NTFET transistor N2 are electrically connected to the drain of the fourth NTFET transistor N3 and the first column write control signal BLB, respectively; the source and gate of the fourth NTFET transistor N3 are electrically connected to the ground line VSS and the second row write control signal line WL, respectively; the source and gate of the fifth NTFET transistor N4 are electrically connected to the ground line VSS and the second column write control signal line BL, respectively; the source, drain and gate of the sixth NTFET transistor N5 are electrically connected to the ground line VSS, the source of the seventh NTFET transistor N6 and the drain of the third NTFET transistor N2, respectively; the drain and gate of the seventh NTFET transistor N6 are electrically connected to the second bit line RBL and the second input word line INWL, respectively.

[0043] Among them, the sixth NTFET transistor N5 and the seventh NTFET transistor N6 constitute the read operation and signed number calculation part; the first PTFET transistor P0 and the first NTFET transistor N0 constitute an inverter, the second PTFET transistor P1 and the second NTFET transistor N1 constitute another inverter, and the two inverters form a latch structure; the fifth PTFET transistor P4 and the fifth NTFET transistor N4 are write auxiliary transistors, the third PTFET transistor P2, the fourth PTFET transistor P3, the third NTFET transistor N2, and the fourth NTFET transistor N3 are write transistors, and the sixth PTFET transistor P5 and the seventh PTFET transistor P6 constitute the unsigned number calculation part.

[0044] See Figure 2 , is a working timing diagram of the 14T-TFET-SRAM unit circuit in this embodiment.

[0045] (1) In the hold state, the row write control signal line WL and the column write control signal line BLB are low, the row write control signal line WLB and the column write control signal line BL are high, transistors N2, N3, P2, and P3 are off, transistors N4 and P4 are on, and the latch structure is in the latched state, ensuring the stability of the SRAM cell in the hold state. The bit line RBL is low, the bit line RBLB is high, the input word line INWL is low, and the input word line INWLB is high. Transistors N6 and P6 are off, and the read path and the symbol number calculation part are closed.

[0046] In addition, the drain voltage of the transistor N5 is always not lower than the source voltage of the transistor N5, thereby preventing the TFET tube from having a forward bias current that is not controlled by the gate, and reducing the static power consumption of the unit circuit.

[0047] (2) In the read operation phase, the bit line RBL is connected to a sense amplifier, the write control signal lines WLB and BL are high, the write control signal lines WL and BLB are low, the input word lines INWL and INWLB are set to high, and the bit lines RBL and RBLB are precharged to high.

[0048] If the stored data is "1", that is, "Q=1, QB=0", the bit line RBL is discharged through transistors N5 and N6, and the sense amplifier detects the change in the level of the bit line RBL and reads the output "0 (not Q)";

[0049] If the stored data is "0", that is, "Q=0, QB=1", the bit line RBL remains at a high level, the sense amplifier detects that the level of the bit line RBL has not changed, and reads the output "1 (not Q)".

[0050] For the sense amplifier, its first input terminal is connected to the bit line RBL, its second input terminal is connected to the reference voltage, and its output terminal is used to output a read value.

[0051] (3) In the write operation phase, the input word line INWL is at a low level, the input word line INWLB is at a high level, the row write control signal line WL is at a high level, and the row write control signal line WLB is at a low level. The state of the control signal is different depending on the write data.

[0052] When the stored data is "1", that is, "Q=1, QB=0", when performing a write "0" operation, the column write control signal lines BL and BLB are high, the row write control signal line WL is high, and the row write control signal line WLB is low, transistors N2, N3, and N4 are turned on, transistors P2 and P4 are turned off, and transistor P3 is turned on. The storage node Q is discharged to the ground through transistors N2 and N3, and the level of the storage node QB is flipped through the latch structure; the power supply VDD charges the storage node QB through transistor P1, so that the voltage of the storage node QB quickly rises to a high level, completing the write "0" operation.

[0053] When the stored data is "0", that is, "Q=0, QB=1", when performing a write "1" operation, the column write control signal lines BL and BLB are low, the row write control signal line WL is high, and the row write control signal line WLB is low, transistors P2, P3, and P4 are turned on, transistors N2 and N4 are turned off, and transistor N3 is turned on. The power supply VDD charges the storage node Q through transistors P2 and P3, and flips the level of the storage node QB through the latch structure; the storage node QB discharges to the ground line VSS through transistor N1, so that the voltage of the storage node QB quickly drops to a low level, completing the write "1" operation.

[0054] After the write operation is completed, the row write control signal line WL is set to a low level, the row write control signal line WLB is set to a high level, the column write control signal line BL is set to a high level, the column write control signal line BLB is set to a low level, transistors P4 and N4 are turned on, and the latch structure returns to the latched state.

[0055] (4) During the calculation phase, the row write control signal line WL is low, the row write control signal line WLB is high, the column write control signal line BL is high, the column write control signal line BLB is low, the bit line RBL is precharged to a high level, and the bit line RBLB is precharged to a low level. The strategy for implementing the multiplication operation between positive and negative numbers and single-bit weights is as follows:

[0056] Step S1: pre-store a value representing a single-bit weight in a storage node of a 14T-TFET-SRAM unit circuit.

[0057] Step S2, divide the single-bit or multi-bit positive and negative numbers into positive and negative parts, generate input signals with different pulse widths according to the numerical values ​​of the positive or negative parts, the negative part is input through the input word line INWL, and the positive part is input through the input word line INWLB.

[0058] Step S3 samples and quantizes the discharge / charge voltages of bit lines RBL / RBLB. A product value is generated based on the discharge / charge voltages, and the sign of the product value is determined based on the source. When the discharge voltage from bit line RBL is sampled, the product value is negative; when the charge voltage from bit line RBLB is sampled, the product value is positive.

[0059] When the stored data is "0", that is, "Q=0, QB=1", indicating that the single-bit weight is 0, transistors N5 and P5 are turned off, and bit lines RBL / RBLB are not discharged / charged. When the stored data is "1", that is, "Q=1, QB=0", indicating that the single-bit weight is 1, transistors N5 and P5 are turned on, and bit lines RBL / RBLB are discharged / charged according to the input of input word lines INWL / INWLB.

[0060] As described above, the basic principles of the 14T-TFET-SRAM unit circuit provided by the present invention have been relatively fully introduced. This 14T-TFET-SRAM unit circuit implements read-write separation by providing an independent data read channel, which can prevent the read corruption problem caused by opening multiple rows in traditional 6T-SRAM and simultaneously support multi-bit multiplication and multiply-accumulate operations between signed and unsigned numbers. In addition, the drain voltage of transistor N5 is always no lower than the source voltage of transistor N5, thereby preventing the TFET from generating forward bias current not controlled by the gate, reducing the static power consumption of the unit circuit, and solving the problem of high static power consumption of existing TFET-SRAM unit circuits.

[0061] Furthermore, the 14T-TFET-SRAM unit circuit can be expanded into a circuit array. When expanded into the circuit array, the fourth PTFET transistor P3 and the fourth NTFET transistor N3 serve as row-shared transistors, while the fifth PTFET transistor P4 and the fifth NTFET transistor N4 serve as column-shared transistors. Therefore, the 14T-TFET-SRAM unit circuit supports transistor sharing and expansion into an array structure, reducing chip area.

[0062] The present invention further provides a 14T-TFET-SRAM unit circuit array, which includes a plurality of 14T-TFET-SRAM unit circuits provided by the present invention distributed in an array.

[0063] Multiple 14T-TFET-SRAM cell circuits in the same row share a fourth PTFET transistor P3 and a fourth NTFET transistor N3; multiple 14T-TFET-SRAM cell circuits in the same column share a fifth PTFET transistor P4 and a fifth NTFET transistor N4. Multiple 14T-TFET-SRAM cell circuits in the same row are connected to the same first input word line INWLB and second input word line INWL; and multiple 14T-TFET-SRAM cell circuits in the same column are electrically connected to the same first bit line RBLB and second bit line RBL.

[0064] As follows, the 14T-TFET-SRAM unit circuit array provided by the present invention is specifically described by taking a 2×2 unit circuit array as an example.

[0065] Reference Figure 3 The 2×2 array uses transistor row sharing and column sharing to reduce area. The transistors connected to the row write control signal lines WL and WLB are row-shared transistors, and the column write control signal lines BL <0> and BL <1> The source of the connected PTFET tubes is connected to the R1 node, and at the same time, the row write control signal line WLB <0> The drain of the connected PTFET transistor is also connected to this node. In this way, the row control signal line WLB can control the write "1" path of the two unit circuits in the same row; similarly, the row control signal WL can control the write "0" path of the two unit circuits in the same row through this connection method.

[0066] Similarly, the gate and column write control signal BLB <0> The drain of the PTFET, whose source is electrically connected to power supply VDD, is electrically connected to the source of two PTFETs. This node is denoted as J1. The same applies to node K1. Through column sharing, the write-assist PTFET can be shared by cells in the same column, reducing the array area. The larger the array area, the closer the average cell area is to 10T after row and column sharing.

[0067] See Figure 4This chart compares the static power consumption of a 2×2 array composed of shared transistors in a 14T-TFET-SRAM cell circuit with that of arrays with the same structure using other structures. Specifically, the chart shows, under a supply voltage of 0.5V to 0.9V, a 2×2 array composed of the present 14T-TFET-SRAM cell circuit, denoted as 14T TFET; a 2×2 array of a traditional read-write separated 8T CMOS SRAM, denoted as 8T(1W1R); a 2×2 array of an 8T-CMOS-SRAM based on current accumulation operation, denoted as 8TCICC'2020; a 2×2 array of a 10T-CMOS-SRAM based on voltage accumulation operation, denoted as 10T ISSCC'2018; and a 2×2 array of a 10T-CMOS-SRAM used for positive and negative number calculations, denoted as 10T TCASII'2023. The static power consumption (Static Power) of these array structures is compared.

[0068] Static power consumption is the overall power consumption of the unit in the hold state. Figure 4 It can be seen that 14T-TFET has lower static power consumption than 8T(1W1R), 8TCICC'2020, 10T ISSCC'2018, and 10T TCASII'2023: for example, when the voltage is 0.8V, the static power consumption of 14T TFET is 7.721nW, compared with the static power consumption of 44.79nW of 8T(1W1R) and 46.29nW of 8T CICC'2020, which are reduced by 82.76% and 82.89% respectively.

[0069] The present invention also provides a signed multiplication and multiplication-accumulation operation circuit based on a 14T-TFET-SRAM unit circuit. The signed multiplication and multiplication-accumulation operation circuit based on a 14T-TFET-SRAM unit circuit includes the 14T-TFET-SRAM unit circuit array provided by the present invention. The 14T-TFET-SRAM unit circuit array includes M×N 14T-TFET-SRAM unit circuits. Based on the signed multiplication circuit (2×2 unit circuit array) of the 14T-TFET-SRAM, a multiplication-accumulation circuit (operation circuit) based on the 14T-TFET-SRAM is further provided. The entire multiplication-accumulation array is an M×N array composed of 14T-TFET-SRAM transistors. When performing a multiplication-accumulation operation, each column in the storage and calculation array serves as a basic unit for performing a multiplication operation, and the entire storage and calculation array realizes the accumulation of the multiplication operation results of each column.

[0070] The present invention also provides a 14T-TFET-SRAM operation method, which is applied to the signed multiplication and multiplication-accumulation operation circuit based on the 14T-TFET-SRAM unit circuit provided by the present invention. The operation method includes:

[0071] Step S1: Divide the M×N 14T-TFET-SRAM unit circuit array from top to bottom into a plurality of Mi×N (i=0, 1, 2 . . . ) sub-arrays, each Mi×N sub-array using an independent first bit line RBLB and second bit line RBL.

[0072] In step S2, the data to be pre-stored is stored in different Mi×N sub-arrays from top to bottom in the order of least significant bit (LSB) to most significant bit (MSB); taking the binary number "1100" as an example, the MSB is the leftmost "1" and the LSB is the rightmost "0". "1100" is pre-stored in M4×N to M1×N, and the pre-stored values ​​are located in the same position of different Mi×N arrays in the same column.

[0073] Step S3, pre-charging the second bit line RBL of each column to a high level and the first bit line RBLB to a low level, inputting signed numbers and unsigned numbers through the second input word line INWL and the first input word line INWLB respectively, and generating signals with different pulse widths according to the values;

[0074] In step S4, after the discharge / charge results of the first bit line RBLB and the second bit line RBL have stabilized, the switches between the first global bit line GBLN and the second global bit line GBLP and each Mi×N subarray are sequentially opened to enable charge sharing. The voltages on the first global bit line GBLN and the second global bit line GBLP are quantized to obtain a multiplication-accumulation result. When the quantized voltage comes from the first global bit line GBLN, the multiplication-accumulation result is negative; when the quantized voltage comes from the second global bit line GBLP, the multiplication-accumulation result is positive. It should be noted that the bit lines RBL of multiple unit circuits in the same subarray are connected to the same local bit line MBLN, and the bit lines RBLB of multiple unit circuits are connected to the same local bit line MBLP. Local bit lines MBLN of different subarrays are connected to the same global bit line GBLN via switch s, and local bit lines MBLP of different subarrays are connected to the same global bit line GBLP via switch s.

[0075] Step S5: subtract the negative value from the positive value quantized by the ADC to obtain the final multiplication and accumulation operation result.

[0076] The following will be a Figure 5Taking an array of 64×4 shared 14T-TFET-SRAM unit circuits (denoted as CAU) with 64 rows and 4 columns as an example, the implementation process of multiplication and accumulation operations of multiple 4-bit signed numbers is described in detail.

[0077] First, the storage array should be divided into four 16×4 arrays (denoted as LAU#0, LAU#1, LAU#2, and LAU#3) from top to bottom according to the high and low bit weights, from top to bottom, in order from LSB to MSB. One LAU contains 16 rows and 4 columns, and a serial multi-bit scheme is used to support the accumulation of up to 16 product results. Because the storage array contains 4 LAUs, it supports up to 4-bit signed product or multiplication and accumulation operations.

[0078] In this embodiment, the number of rows in the storage and computation array is defined as r, and the number of columns is defined as c; r = 0, 1, 2, ... 63, and c = 0, 1, 2, 3. r values ​​of 0-15 correspond to LAU#0, r values ​​of 16-31 correspond to LAU#1, r values ​​of 32-47 correspond to LAU#2, and r values ​​of 48-63 correspond to LAU#3. When the stored data is "1," i.e., "Q = 1, QB = 0," indicating a single-bit weight of 1, transistors N5 and P5 are turned on, and bit lines RBL / RBLB are discharged / charged according to the input of input word lines INWL / INWLB. When the stored data is "0," i.e., "Q = 0, QB = 1," indicating a single-bit weight of 0, transistors N5 and P5 are turned off, and the voltage of bit lines RBL / RBLB remains unchanged.

[0079] Next, this embodiment will implement the “accumulation” of the multiplication results on the positive or negative phase by switching the switches between the bit lines in turn. Figure 5 As shown, each LAU corresponds to a switch s and a local bit line MBLN / MBLP and a global bit line GBLN / GBLP. The switch s is set between the local bit line and the global bit line. The capacitance between each bit line is

[0080] C RBL =C RBLB >>C MBLN =C MBLP =C GBLN =C GBLP Local bit lines MBLN / MBLP

[0081] Connected to the selected bit line RBL / RBLB, at this time, V RBL =V MBLN , V RBLB =V MBLP ; The voltage of GBLN is precharged to V (VDD), and the voltage of GBLP is precharged to 0 (VSS).

[0082] After the calculation is completed, the bit line voltage comparison table for each bit line before charge sharing is shown in the following table:

[0083] Table 1 Comparison of bit line voltages for each bit line before charge sharing

[0084]

[0085] Step 1: Close switch s#0 and open switches s#1, s#2, and s#3. Bit lines GBLN and MBLN#0 share charge, and bit lines GBLP and MBLP#0 share charge. After time T, switches s#0-s#3 are opened again. At this point, the voltage on the global bit line is:

[0086]

[0087] Step 2: Close switch s#1 and open switches s#0, s#2, and s#3; bit lines GBLN and MBLN#1 share charge, and bit lines GBLP and MBLP#1 share charge. After time T, open switches s#0-s#3 again. At this point, the voltage on the global bit line is:

[0088]

[0089] Step 3: Close switch s#2 and open switches s#0, s#1, and s#3; bit lines GBLN and MBLN#2 share charge, and bit lines GBLP and MBLP#2 share charge. After time T, open switches s#0-s#3 again. At this point, the voltage on the global bit line is:

[0090]

[0091] Step 4: Close switch s#3 and open switches s#0, s#1, and s#2; bit lines GBLN and MBLN#3 share charge, and bit lines GBLP and MBLP#3 share charge. After time T, switches s#0-s#3 are opened again. At this point, the voltage on the global bit line is:

[0092]

[0093] Analyzing the above formulas, we can see that after multiple charge sharing operations, GBLN / GBLP is connected to the ADC, the ADC is enabled, and the multiplication and accumulation output on the global bit lines is read. GBLN quantizes the sum of all negative numbers in the multiplication and accumulation process, while GBLP quantizes the sum of all positive numbers in the multiplication and accumulation process. Subtracting the quantized result from the GBLP from the quantized result from the GBLN yields the final multiplication and accumulation result.

[0094] In summary, the signed multiplication and multiplication-accumulation operation circuit based on the 14T-TFET-SRAM unit circuit provided by the present invention can realize multiplication-accumulation operation.

[0095] The present invention also provides a CIM chip, which integrates multiple signed multiplication and multiplication-accumulation operation circuits based on 14T-TFET-SRAM unit circuits provided by the present invention and peripheral circuits that cooperate with the signed multiplication and multiplication-accumulation operation circuits based on 14T-TFET-SRAM unit circuits.

[0096] When implementing data storage functions, the required peripheral circuits include: wordline drivers, address decoders, precharge circuits, timing control modules, mode switching circuits, and read / write control circuits. The wordline drivers control the activation of each wordline (WL, WLB, INWL, and INWLB). The address decoder is connected to the wordline drivers and decodes address signals before transmitting them to the wordline drivers. The precharge circuit precharges signal lines such as the bitlines BL and BLB. The timing control module generates the clock signals required to perform data storage tasks or multiplication and multiply-accumulate operations. The mode switching circuit switches the operating mode of the CIM circuit.

[0097] When performing logical operation tasks, the necessary peripheral circuits include at least: a channel selection circuit for inputting the corresponding input signal to the input word line INWL or INWLB according to the sign bit of the input data; a pulse width modulation circuit for generating different numerical inputs; a signal sampling circuit and an ADC quantization circuit for obtaining the calculation results; a subtractor for accumulating the positive and negative data quantized on different bit lines, etc.

[0098] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0099] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

Claims

1. A 14T-TFET-SRAM unit circuit, characterized in that: The 14T-TFET-SRAM unit circuit includes first to seventh NTFET transistors and first to seventh PTFET transistors; The source, drain and gate of the first PTFET transistor P0 are electrically connected to the drain of the fifth PTFET transistor P4 and the drain and gate of the first NTFET transistor N0 respectively. The drain of the first PTFET transistor P0 is provided with a first storage node Q. The source, drain and gate of the second PTFET transistor P1 are electrically connected to the power supply VDD and the drain and gate of the second NTFET transistor N1 respectively, and the drain of the second PTFET transistor P1 is provided with a second storage node QB; The source, drain, and gate of the third PTFET transistor P2 are electrically connected to the drain of the fourth PTFET transistor P3, the drain of the third NTFET transistor N2, and the gate of the fifth NTFET transistor N4, respectively; The source and gate of the fourth PTFET transistor P3 are electrically connected to the power supply VDD and the first row write control signal line WLB respectively; The source and gate of the fifth PTFET transistor P4 are electrically connected to the power supply VDD and the gate of the third NTFET transistor N2, respectively; The source, drain and gate of the sixth PTFET transistor P5 are electrically connected to the drain of the seventh PTFET transistor P6, the first bit line RBLB and the drain of the second NTFET transistor N1, respectively; The source and gate of the seventh PTFET transistor P6 are electrically connected to the power supply VDD and the first input word line INWLB respectively; The source of the first NTFET transistor N0 is electrically connected to the drain of the fifth NTFET transistor N4; The source of the second NTFET transistor N1 is electrically connected to the ground line VSS; The source and gate of the third NTFET transistor N2 are electrically connected to the drain of the fourth NTFET transistor N3 and the first column write control signal BLB, respectively; The source and gate of the fourth NTFET transistor N3 are electrically connected to the ground line VSS and the second row write control signal line WL, respectively; The source and gate of the fifth NTFET transistor N4 are electrically connected to the ground line VSS and the second column write control signal line BL, respectively; The source, drain, and gate of the sixth NTFET transistor N5 are electrically connected to the ground line VSS, the source of the seventh NTFET transistor N6, and the drain of the third NTFET transistor N2, respectively; The drain and gate of the seventh NTFET transistor N6 are electrically connected to the second bit line RBL and the second input word line INWL, respectively.

2. The 14T-TFET-SRAM unit circuit according to claim 1, characterized in that: The fourth PTFET transistor P3 and the fourth NTFET transistor N3 are row-shared transistors; The fifth PTFET transistor P4 and the fifth NTFET transistor N4 are column-common transistors.

3. A 14T-TFET-SRAM unit circuit array, characterized in that: The 14T-TFET-SRAM unit circuit array includes a plurality of 14T-TFET-SRAM unit circuits according to claim 1 or 2 distributed in an array.

4. The 14T-TFET-SRAM computing array according to claim 3, wherein: Multiple 14T-TFET-SRAM unit circuits in the same row share the fourth PTFET transistor P3 and the fourth NTFET transistor N3; Multiple 14T-TFET-SRAM cell circuits in the same column share the fifth PTFET transistor P4 and the fifth NTFET transistor N4.

5. The 14T-TFET-SRAM computing array according to claim 4, wherein: A plurality of 14T-TFET-SRAM cell circuits in a same row are connected to the same first input word line INWLB and second input word line INWL; A plurality of 14T-TFET-SRAM cell circuits in the same column are electrically connected to the same first bit line RBLB and second bit line RBL.

6. A signed multiplication and multiplication-accumulation circuit based on a 14T-TFET-SRAM unit circuit, characterized in that: The signed multiplication and multiplication-accumulation operation circuit includes the 14T-TFET-SRAM unit circuit array according to any one of claims 3 to 5, wherein the 14T-TFET-SRAM unit circuit array includes M×N 14T-TFET-SRAM unit circuits.

7. A 14T-TFET-SRAM operation method, characterized in that: The signed multiplication and multiplication-accumulation operation circuit based on the 14T-TFET-SRAM unit circuit as claimed in claim 6; The operation method includes: The M×N 14T-TFET-SRAM cell circuit array is divided into multiple Mi×N sub-arrays from top to bottom, and each Mi×N sub-array uses an independent first bit line RBLB and a second bit line RBL; The data to be pre-stored is stored in different Mi×N sub-arrays from top to bottom in the order of the least significant bit to the most significant bit; The second bit line RBL of each column is precharged to a high level and the first bit line RBLB is precharged to a low level, and signed and unsigned numbers are input through the second input word line INWL and the first input word line INWLB respectively, generating signals with different pulse widths according to the values; When the discharge / charge results of the first bit line RBLB and the second bit line RBL are stable, the switches between the first global bit line GBLN and the second global bit line GBLP and each Mi×N sub-array are sequentially opened to perform charge sharing, and the voltages on the first global bit line GBLN and the second global bit line GBLP are quantized to obtain a multiplication-accumulation result. Subtract the negative value from the quantized positive value to get the final multiplication and accumulation result.

8. A CIM chip, characterized in that: The CIM chip integrates a plurality of signed multiplication and multiplication-accumulation operation circuits based on the 14T-TFET-SRAM unit circuit according to claim 6 and peripheral circuits cooperating with the signed multiplication and multiplication-accumulation operation circuits.

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