A Schottky barrier oxide thin film transistor and a method for preparing the same

Abstract

The present application provides a Schottky barrier oxide thin film transistor and a method for preparing the same, relating to the field of semiconductor technology. The present application sequentially prepares a patterned gate layer, a gate dielectric layer, a patterned semiconductor layer, a patterned diffusion barrier layer, a patterned work function control layer, and a patterned source layer on a substrate, wherein the projection area of ​​the diffusion barrier layer on the substrate is within the projection area of ​​the semiconductor layer on the substrate, and the source layer covers the portion of the outer surface of the semiconductor layer not covered by the diffusion barrier layer. At this time, a portion of the source layer directly contacts the semiconductor layer to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer is spaced apart from the work function control portion and the diffusion barrier layer to form a Schottky barrier with the semiconductor layer, thereby ensuring the device electrical characteristics of a high saturation output current, effectively reducing the capture of carriers by interface defects, and avoiding the generation of carrier traps, thereby improving the stability and reliability of the device and effectively reducing the cost of device preparation.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a Schottky barrier oxide thin film transistor and a method for preparing the same. Background Art

[0002] With the continuous development of technology, Schottky barrier metal oxide thin film transistors (SBMO-TFTs) have gradually attracted more attention due to their excellent intrinsic electrical properties. Compared with ordinary metal oxide thin film transistors, SBMO-TFTs generally have the advantages of high intrinsic gain, low power consumption, significantly reduced short channel effect, better device stability, and stable current output characteristics after saturation. Therefore, SBMO-TFTs are suitable for application in high-pixel density AMLCDs (active matrix liquid crystal displays), AMOLEDs (active matrix organic light-emitting diode displays), Mini-LED (mini light-emitting diode) display devices, Micro-LED (micro light-emitting diode) display devices and other current-driven display devices or low-power integrated circuits. They are also suitable for use in the construction of dynamic random access memory (DRAM).

[0003] For SBMO-TFT, the key to its production is to form a good Schottky contact between the source electrode and the semiconductor layer to form a Schottky barrier between the source electrode and the semiconductor layer. At present, the industry mainly reduces the Schottky barrier of the corresponding SBMO-TFT by strictly controlling the oxygen plasma treatment intensity or intercalation thickness at the contact interface between the source electrode and the semiconductor layer, so that the source electrode has a strong carrier injection capability, thereby ensuring that the corresponding SBMO-TFT has a high saturation output current. However, it is worth noting that the Schottky barrier contact portion of the source electrode in this SBMO-TFT will capture a large number of injected carriers due to interface defects, which is very likely to cause hysteresis in the device electrical characteristics, seriously affecting the stability of the device. At the same time, when the aforementioned SBMO-TFT is operating in a saturated state, the depletion region in the semiconductor layer will generate a strong longitudinal electric field, which will cause the injected carriers to undergo a hot carrier effect (i.e., causing the metal-oxygen ion bond in the semiconductor to break, or causing carriers to be injected into the gate dielectric layer), thereby seriously affecting the reliability of the device. Summary of the Invention

[0004] In view of this, the purpose of the present application is to provide a Schottky barrier oxide thin film transistor and a preparation method thereof, which can ensure the device electrical characteristics of high saturation output current by utilizing the ohmic (quasi-ohmic) contact and Schottky contact formed at the source layer, and avoid carrier traps caused by the diffusion of the electrode material of the source layer to the semiconductor layer through a diffusion barrier layer with carrier tunneling characteristics, and greatly improve the work function difference of the source layer relative to the semiconductor layer through the work function regulation layer, which can greatly increase the Schottky barrier height and greatly reduce the carrier injection of the source layer at the Schottky contact part, so as to effectively reduce the capture of carriers by interface defects and avoid the hot carrier effect and carrier traps generated by the depletion region in the semiconductor layer under a strong longitudinal electric field, thereby greatly improving the hysteresis phenomenon of the device electrical characteristics and improving the stability and reliability of the device. At the same time, there is no need to use high-cost precious metals (such as Pt, Pd, Au, etc.) to prepare a high-work function source layer, so as to effectively reduce the preparation cost of the device.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a method for preparing a Schottky barrier oxide thin film transistor, the method comprising:

[0007] providing a substrate;

[0008] A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate to obtain a first semiconductor device, wherein the gate layer and the semiconductor layer are both patterned;

[0009] A diffusion barrier layer, a work function regulation layer, and an electrode film layer are prepared on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device, wherein the diffusion barrier layer satisfies the carrier tunneling effect, the work function regulation layer is arranged between the diffusion barrier layer and the electrode film layer, the projection areas of the diffusion barrier layer and the work function regulation layer on the substrate overlap with each other, and the projection area corresponding to the diffusion barrier layer is within the projection area of ​​the semiconductor layer on the substrate, the electrode film layer covers the outer surface of the semiconductor layer not covered by the diffusion barrier layer, wherein the work function regulation layer is used to improve the work function of the electrode film layer, and the diffusion barrier layer is used to prevent the electrode material of the electrode film layer from diffusing into the semiconductor layer;

[0010] Photolithographic patterning is performed on the side of the second semiconductor device away from the substrate to pattern the electrode film layer into a source layer and a drain layer spaced apart from each other, and the work function control layer is patterned into two work function control portions that are laterally aligned with the source layer and the drain layer, respectively; or, photolithographic patterning is performed on the side of the second semiconductor device away from the substrate to pattern the electrode film layer into a source layer that is laterally aligned with both the diffusion barrier layer and the work function control layer, and then the film layer portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer is conductorized to form a conductorized film layer portion for serving as a drain region.

[0011] In an optional embodiment, the step of sequentially stacking a gate layer, a gate dielectric layer, and a semiconductor layer on one side of the substrate to obtain the first semiconductor device includes:

[0012] sputtering and depositing a gate layer on one side surface of the substrate, and performing photolithographic patterning on the deposited gate layer;

[0013] On the side of the substrate where the gate layer is formed, growing the gate dielectric layer based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the gate dielectric layer covers the gate layer and the side area of ​​the substrate not blocked by the gate layer;

[0014] The semiconductor layer is deposited on the outer surface of the gate dielectric layer away from the substrate based on magnetron sputtering or atomic layer deposition, and the deposited semiconductor layer is patterned by photolithography to obtain the first semiconductor device.

[0015] In an optional embodiment, the step of preparing a diffusion barrier layer, a work function regulating layer, and an electrode film layer on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device includes:

[0016] On the outer surface of the first semiconductor device away from the substrate, sequentially depositing the diffusion barrier layer and the work function control layer based on magnetron sputtering or atomic layer deposition, wherein the diffusion barrier layer satisfies the carrier tunneling effect;

[0017] Sequentially performing photolithographic patterning on the deposited work function regulating layer and the diffusion barrier layer, so that the projection areas corresponding to the patterned diffusion barrier layer and the work function regulating layer overlap with each other, and the projection area corresponding to the patterned diffusion barrier layer is within the projection area corresponding to the semiconductor layer;

[0018] An electrode film layer is formed by sputtering deposition on a side of the work function regulating layer away from the diffusion barrier layer to obtain the second semiconductor device.

[0019] In an optional embodiment, the step of preparing a diffusion barrier layer, a work function regulating layer, and an electrode film layer on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device includes:

[0020] Depositing the diffusion barrier layer satisfying the carrier tunneling effect on the outer surface of the first semiconductor device away from the substrate by magnetron sputtering or atomic layer deposition, and photolithographically patterning the diffusion barrier layer so that a projection area corresponding to the patterned diffusion barrier layer is within a projection area corresponding to the semiconductor layer;

[0021] forming an electrode film layer by sputtering deposition on a side of the diffusion barrier layer away from the semiconductor layer;

[0022] The electrode film layer and the diffusion barrier layer are annealed in a vacuum atmosphere or an inert gas atmosphere to cause an oxidation reaction in a local area of ​​the electrode film layer that is in direct contact with the diffusion barrier layer to form the work function regulation layer that overlaps with the projection area of ​​the diffusion barrier layer, thereby obtaining the second semiconductor device.

[0023] In an optional embodiment, the step of conducting a conductor on a portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer to form a conductorized portion of the semiconductor layer serving as a drain region includes:

[0024] Argon plasma is used to bombard the film layer portion of the semiconductor layer that is not covered by the source layer and the diffusion barrier layer, so as to convert the bombarded film layer portion with semiconductor characteristics into the conductive film layer portion.

[0025] In an optional embodiment, the step of conducting a conductor on a portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer to form a conductorized portion of the semiconductor layer serving as a drain region includes:

[0026] On the outer surface of the source layer of the second semiconductor device, at least silicon nitride material and silicon dioxide material are used to deposit a passivation layer, and the passivation layer is annealed to make the film layer portion of the semiconductor layer that is in direct contact with the passivation layer conductive under the action of hydrogen diffusion doping of the passivation layer, so as to convert the film layer portion of the semiconductor layer that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion.

[0027] In an optional embodiment, the material of the gate layer is any one of Al, Cu, Mo, Ti, and ITO;

[0028] The gate dielectric layer is made of a stack of any one or more materials selected from the group consisting of SiO2, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide.

[0029] The material of the semiconductor layer is any one of InGaZnO, InZnO, InZnSnO, Ln-IZO, InGaO, ZnO, Ga2O3, SnO2 and In2O3;

[0030] The material of the diffusion barrier layer is any one of SiO2, Al2O3, HfO2, and ZrO2;

[0031] The material of the electrode film layer is any one of Cu, Mo, Co, Ti, Ni, W, Cr, Ag or ITO, wherein the work function of the electrode film layer is greater than the work function of the semiconductor layer;

[0032] The material of the work function regulating layer is any one of copper oxide, molybdenum oxide, cobalt oxide, titanium oxide, nickel oxide, tungsten oxide, chromium oxide, silver oxide, tellurium oxide, and tin oxide.

[0033] In an optional embodiment, the gate layer has a thickness ranging from 10 to 1000 nm;

[0034] The thickness of the gate dielectric layer is in the range of 5-500 nm;

[0035] The thickness of the semiconductor layer is in the range of 5-200 nm;

[0036] The thickness of the diffusion barrier layer is in the range of 1-5 nm;

[0037] The thickness of the work function regulation layer is in the range of 1-100 nm.

[0038] In a second aspect, the present application provides a Schottky barrier oxide thin film transistor, comprising:

[0039] substrate;

[0040] A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer;

[0041] A diffusion barrier layer, a work function regulation layer, and an electrode film layer are sequentially stacked on the semiconductor layer, wherein the diffusion barrier layer satisfies the carrier tunneling effect, the work function regulation layer is arranged between the diffusion barrier layer and the electrode film layer, the projection area of ​​the diffusion barrier layer on the substrate is within the projection area of ​​the semiconductor layer on the substrate, the work function regulation layer is used to improve the work function of the electrode film layer, and the diffusion barrier layer is used to prevent the electrode material of the electrode film layer from diffusing into the semiconductor layer;

[0042] The work function regulating layer comprises two work function regulating sites spaced apart from each other, and the projection areas of the two work function regulating sites on the substrate are both within the projection area corresponding to the diffusion barrier layer;

[0043] The electrode film layer includes a source layer and a drain layer spaced apart from each other, the source layer covers a portion of the outer surface of the semiconductor layer not covered by the diffusion barrier layer, and the drain layer covers the remaining outer surface of the semiconductor layer not covered by the diffusion barrier layer, the source layer is aligned with the side of one work function regulation portion, and the drain layer is aligned with the side of another work function regulation portion, wherein a portion of the source layer is in direct contact with the semiconductor layer to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer is spaced apart from the corresponding work function regulation portion and the diffusion barrier layer to form a Schottky barrier with the semiconductor layer.

[0044] In a third aspect, the present application provides a Schottky barrier oxide thin film transistor, comprising:

[0045] substrate;

[0046] A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer;

[0047] A diffusion barrier layer, a work function regulation layer, and a source layer are sequentially stacked on the semiconductor layer, wherein the diffusion barrier layer satisfies the carrier tunneling effect, the work function regulation layer is arranged between the diffusion barrier layer and the source layer, the projection area of ​​the diffusion barrier layer on the substrate is within the projection area of ​​the semiconductor layer on the substrate, the projection areas of the diffusion barrier layer and the work function regulation layer on the substrate overlap with each other, the source layer covers the portion of the outer surface of the semiconductor layer not covered by the diffusion barrier layer, and the source layer is laterally aligned with the diffusion barrier layer and the work function regulation layer, wherein the work function regulation layer is used to increase the work function of the source layer, and the diffusion barrier layer is used to prevent the electrode material of the source layer from diffusing into the semiconductor layer;

[0048] The semiconductor layer includes a semiconductor film layer portion and a conductive film layer portion, wherein the conductive film layer portion is a film layer portion of the semiconductor layer that is not covered by the source layer and the diffusion barrier layer, and the semiconductor film layer portion is a remaining film layer portion of the semiconductor layer except the conductive film layer portion, wherein the conductive film layer portion is used as a drain region of the corresponding thin film transistor, a partial area of ​​the source layer is in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, and a partial area of ​​the source layer is separated by the work function control layer and the diffusion barrier layer and forms a Schottky barrier with the semiconductor film layer portion.

[0049] In this case, the beneficial effects of the embodiments of the present application may include the following:

[0050] The present application sequentially prepares a patterned gate layer, a gate dielectric layer, a patterned semiconductor layer, a patterned diffusion barrier layer, a patterned work function control layer and a patterned source layer on a substrate, wherein the projection area of ​​the diffusion barrier layer on the substrate is within the projection area of ​​the semiconductor layer on the substrate, and the source layer covers the outer surface of the semiconductor layer that is not covered by the diffusion barrier layer. At this time, a part of the source layer is in direct contact with the semiconductor layer to form an ohmic contact or a quasi-ohmic contact, and a part of the source layer is spaced apart from the corresponding work function control part and the diffusion barrier layer to form a Schottky barrier with the semiconductor layer, thereby ensuring the electrical characteristics of the device with a high saturation output current by utilizing the ohmic (quasi-ohmic) contact and Schottky contact formed at the source layer. The diffusion barrier layer with sufficient carrier tunneling effect prevents the electrode material of the source layer from diffusing into the semiconductor layer, so as to avoid the carrier traps caused by the diffusion of the electrode material of the source layer into the semiconductor layer, and greatly improves the work function difference of the source layer relative to the semiconductor layer through the work function regulation layer, which can greatly increase the Schottky barrier height, greatly reduce the carrier injection of the source layer at the Schottky contact part, so as to effectively reduce the capture of carriers by interface defects, avoid the hot carrier effect and carrier traps generated in the depletion region of the semiconductor layer under a strong longitudinal electric field, thereby greatly improving the hysteresis phenomenon of the electrical characteristics of the device, improving the stability and reliability of the device, and at the same time, there is no need to use high-cost precious metals to prepare the source layer with a high work function, so as to effectively reduce the preparation cost of the device.

[0051] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0053] Figure 1 This is a schematic diagram of the composition of a Schottky barrier oxide thin film transistor provided in an embodiment of the present application;

[0054] Figure 2 The second schematic diagram of the composition of the Schottky barrier oxide thin film transistor provided in an embodiment of the present application;

[0055] Figure 3This is a schematic diagram of a process for preparing a Schottky barrier oxide thin film transistor according to an embodiment of the present application;

[0056] Figure 4 for Figure 3 A schematic flow chart of the sub-steps included in step S220;

[0057] Figure 5 A schematic diagram of manufacturing a first semiconductor device provided in an embodiment of the present application;

[0058] Figure 6 for Figure 3 One of the flowcharts of the sub-steps included in step S230;

[0059] Figure 7 One of the schematic diagrams for manufacturing the second semiconductor device provided in an embodiment of the present application;

[0060] Figure 8 for Figure 3 2 is a flow chart of the sub-steps included in step S230;

[0061] Figure 9 The second schematic diagram of the manufacturing of the second semiconductor device provided in the embodiment of the present application;

[0062] Figure 10 This is a second flow chart of the method for preparing a Schottky barrier oxide thin film transistor provided in an embodiment of the present application.

[0063] Icon: 10-Schottky barrier oxide thin film transistor; 11-substrate; 12-gate layer; 13-gate dielectric layer; 14-semiconductor layer; 15-diffusion barrier layer; 16-work function control layer; 17-source layer; 18-drain layer; 141-conductive film layer portion; 142-semiconductor film layer portion; 19-depletion region. DETAILED DESCRIPTION

[0064] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0065] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0066] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0067] In the description of this application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the application is usually placed when in use, or are the orientation or position relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0068] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0069] In addition, in the description of the present application, it is also understood that relational terms such as the terms "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also include elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0070] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0071] Please refer to Figure 1 , Figure 1This is one of the schematic diagrams of the composition of the Schottky barrier oxide thin film transistor 10 provided in the embodiment of the present application. In the embodiment of the present application, the Schottky barrier oxide thin film transistor 10 provided in the present application can prevent the electrode material at the source from diffusing into the semiconductor layer on the basis of maintaining the device electrical characteristics of a high saturation output current, so as to avoid carrier traps caused by the diffusion of the electrode material of the source into the semiconductor layer, and improve the work function difference of the source relative to the semiconductor layer while reducing the source preparation cost, so as to greatly increase the Schottky barrier height, greatly reduce the carrier injection of the source at the Schottky contact part, facilitate the effective reduction of the capture of carriers by interface defects, and avoid the generation of hot carrier effects and carrier traps in the depletion region of the semiconductor layer under a strong longitudinal electric field, thereby improving the hysteresis phenomenon of the device electrical characteristics, improving the stability and reliability of the device, and reducing the preparation cost of the device.

[0072] In the embodiments of this application, Figure 1 The Schottky barrier oxide thin film transistor 10 shown may include a substrate 11 , a gate layer 12 , a gate dielectric layer 13 , a semiconductor layer 14 , a diffusion barrier layer 15 , a work function regulation layer 16 , a source layer 17 and a drain layer 18 .

[0073] In this embodiment, the gate layer 12, the gate dielectric layer 13, and the semiconductor layer 14 are sequentially stacked on one side of the substrate 11. The gate dielectric layer 13 covers the outer surface of the gate layer 12 away from the substrate 11, as well as the side areas of the substrate 11 on which the gate layer 12 is formed that are not blocked by the gate layer 12. The projected area of ​​the gate layer 12 on the substrate 11 is less than or equal to the area of ​​the side of the substrate 11 on which the gate layer 12 is formed.

[0074] In this embodiment, the diffusion barrier layer 15 and the work function control layer 16 are sequentially stacked on the outer surface of the semiconductor layer 14 away from the substrate 11. The diffusion barrier layer 15 satisfies the carrier tunneling effect, i.e., carriers injected into the diffusion barrier layer 15 can tunnel through the diffusion barrier layer 15. The projection area of ​​the diffusion barrier layer 15 on the substrate 11 is within the projection area of ​​the semiconductor layer 14 on the substrate 11, and the projection area corresponding to the diffusion barrier layer 15 is smaller than the projection area corresponding to the semiconductor layer 14.

[0075] In the embodiment of the present application, the work function regulation layer 16 may include two work function regulation sites spaced apart from each other, and the projection areas of the two work function regulation sites on the substrate 11 are both within the projection area corresponding to the diffusion barrier layer 15 .

[0076] In the embodiment of the present application, the source layer 17 and the drain layer 18 are spaced apart from each other. The source layer 17 covers a work function control portion included in the work function control layer 16 and also covers a portion of the outer surface of the semiconductor layer 14 that is not covered by the diffusion barrier layer 15, so that a portion of the source layer 17 is in direct contact with the semiconductor layer 14 to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer 17 is spaced apart from the corresponding covered work function control portion and the diffusion barrier layer 15 to form a Schottky contact with the semiconductor layer 14 to form a Schottky barrier, wherein the source layer 17 is aligned with the side of the work function control portion it covers; The drain electrode layer 18 covers the other work function control portion included in the work function control layer 16 and also covers the remaining outer surface of the semiconductor layer 14 not covered by the diffusion barrier layer 15, so that a portion of the drain electrode layer 18 is in direct contact with the semiconductor layer 14 to form an ohmic contact or a quasi-ohmic contact, and a portion of the drain electrode layer 18 is spaced apart from the corresponding covered work function control portion and the diffusion barrier layer 15 to form a Schottky contact with the semiconductor layer 14 to form a Schottky barrier, wherein the drain electrode layer 18 is aligned with the side of the work function control portion it covers. Figure 1 When the Schottky barrier oxide thin film transistor 10 shown is operating in a saturated state, the depletion region 19 corresponding to the source layer 17 in the Schottky barrier oxide thin film transistor 10 is a local semiconductor region in the semiconductor layer 14 that is overlapped and covered by the projections of the source layer 17, the work function control layer 16, and the diffusion barrier layer 15. The depletion region 19 extends from the side where the source layer 17 achieves ohmic (quasi-ohmic) contact to the side where the drain layer 18 is located, and reaches the interface between the semiconductor layer 14 and the gate dielectric layer 13 on the drain layer 18 side (refer to Figure 1 The expansion distribution of the depletion region 19 in the embodiment of the present invention is used to achieve the pinch-off effect of the channel.

[0077] In the embodiment of the present application, the source layer 17 and the drain layer 18 belong to the same electrode film layer, and the work function control layer 16 can use its own work function control portion in contact with the source layer 17 or the drain layer 18 to improve the work function of the corresponding contacted source layer 17 or the drain layer 18, so that there is no need to use expensive precious metals to prepare the source layer 17 and the drain layer 18 with high work function, thereby reducing the source preparation cost and effectively improving the work function difference of the source layer 17 and the drain layer 18 relative to the semiconductor layer 14, thereby greatly improving the Schottky barrier height (including the The Schottky barrier height between the source layer 17 and the semiconductor layer 14, and the Schottky barrier height between the drain layer 18 and the semiconductor layer 14) are greatly reduced, which greatly reduces the carrier injection of the source layer 17 at the Schottky contact portion (that is, the portion of the source layer 17 that forms the Schottky contact), so as to effectively reduce the capture of carriers by interface defects, and avoid the depletion region 19 in the semiconductor layer 14 corresponding to the source layer 17 to generate hot carrier effects and carrier traps under a strong longitudinal electric field, thereby greatly improving the hysteresis phenomenon of the device electrical characteristics and enhancing the stability and reliability of the device.

[0078] In the embodiment of the present application, the diffusion barrier layer 15, while having the carrier tunneling property, can effectively prevent the electrode materials of the source layer 17 and the drain layer 18 from diffusing into the semiconductor layer 14, so as to avoid the local semiconductor region corresponding to the Schottky barrier in the semiconductor layer 14 from changing the electrical properties due to the diffusion doping of the electrode material, thereby effectively avoiding the carrier traps generated by the diffusion of the electrode material of the source layer 17 into the semiconductor layer 14.

[0079] Therefore, the application provides Figure 1The Schottky barrier oxide thin film transistor 10 shown can, on the basis of ensuring the device electrical characteristics of high saturation output current by utilizing the ohmic (quasi-ohmic) contact and Schottky contact formed at the source layer 17, prevent the electrode material of the source layer 17 from diffusing into the semiconductor layer 14 through a diffusion barrier layer 15 having carrier tunneling characteristics (i.e., satisfying the carrier tunneling effect), so as to avoid the carrier traps generated by the diffusion of the electrode material of the source layer 17 into the semiconductor layer 14, and greatly improve the work function difference of the source layer 17 relative to the semiconductor layer 14 through the work function control layer 16, thereby greatly improving the Schottky barrier oxide thin film transistor 10. The base barrier height (for example, the barrier height of the Schottky barrier in the thermal equilibrium state is greater than or equal to 0.6 eV) greatly reduces the carrier injection of the source layer 17 at the Schottky contact portion, so as to effectively reduce the capture of carriers by interface defects, and avoid the depletion region 19 corresponding to the source layer 17 in the semiconductor layer 14 to generate hot carrier effects and carrier traps under a strong longitudinal electric field, thereby greatly improving the hysteresis phenomenon of the device electrical characteristics, improving the stability and reliability of the device, and at the same time, there is no need to use expensive precious metals to prepare the source layer 17 and the drain layer 18 with a high work function, so as to effectively reduce the preparation cost of the device.

[0080] In the embodiment of the present application, the source electrode layer 17 and the drain electrode layer 18 are formed using the same electrode material. The work function of the electrode material used for the source electrode layer 17 and the drain electrode layer 18 is greater than the work function of the semiconductor layer 14, so that the Schottky barrier between the source electrode layer 17 and the drain electrode layer 18 and the semiconductor layer 14 can be properly generated. The electrode material used for the source electrode layer 17 and the drain electrode layer 18 is any one of Cu, Mo, Co, Ti, Ni, W, Cr, Ag, or ITO.

[0081] In the embodiment of the present application, the thickness of the gate layer 12 is in the range of 10-1000 nm, and the material of the gate layer 12 is any one of Al, Cu, Mo, Ti, and ITO.

[0082] In an embodiment of the present application, the material of the semiconductor layer 14 is any one of InGaZnO, InZnO, InZnSnO, Ln-IZO, InGaO, ZnO, Ga2O3, SnO2 and In2O3, and the thickness of the semiconductor layer 14 is in the range of 5-200 nm.

[0083] In the embodiment of the present application, the substrate 11 can be a rigid substrate such as glass or silicon, or a flexible polymer substrate such as polyimide or polyethylene naphthalate. It is understood that the actual type of the substrate 11 includes but is not limited to the aforementioned examples, and any material that can serve as a substrate for a metal oxide thin film transistor device falls within the scope of protection of the present application.

[0084] In the embodiment of the present application, the material of the gate dielectric layer 13 is a stack of any one or more materials selected from SiO 2 , silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide. The thickness of the gate dielectric layer 13 is in the range of 5-500 nm.

[0085] In the embodiment of the present application, the material of the diffusion barrier layer 15 is any one of SiO 2 , Al 2 O 3 , HfO 2 , and ZrO 2 , and the thickness of the diffusion barrier layer 15 is in the range of 1-5 nm.

[0086] In the embodiment of the present application, the material of the work function regulation layer 16 is a p-type oxide semiconductor material, and the thickness of the work function regulation layer 16 is in the range of 1-100 nm. In one implementation of this embodiment, the material of the work function regulation layer 16 is any one of copper oxide, molybdenum oxide, cobalt oxide, titanium oxide, nickel oxide, tungsten oxide, chromium oxide, silver oxide, tellurium oxide, and tin oxide.

[0087] It is understandable that in Figure 1 A passivation layer is deposited on the outer surface of the Schottky barrier oxide thin film transistor 10 away from the substrate 11 based on plasma enhanced chemical vapor deposition or atomic layer deposition to cover and encapsulate the Schottky barrier oxide thin film transistor 10 through the passivation layer, and then a first via hole and a second via hole are opened on the passivation layer, so that the first via hole partially exposes the source layer 17, and the second via hole partially exposes the drain layer 18, so that the source wiring layer is deployed to be electrically connected to the source layer 17 through the first via hole, and the drain wiring layer is deployed to be electrically connected to the drain layer 18 through the second via hole, thereby completing the Figure 1 The device packaging effect of the Schottky barrier oxide thin film transistor 10 is shown.

[0088] Among them, for Figure 1 The passivation layer deposited on the Schottky barrier oxide thin film transistor 10 shown is made of at least one of silicon nitride and silicon dioxide materials. When the corresponding passivation layer is formed using silicon nitride and silicon dioxide materials, the passivation layer can be formed by stacking an oxide layer formed using silicon dioxide and a silicon nitride layer formed using silicon nitride, wherein the silicon nitride layer is disposed on a side of the oxide layer away from the Schottky barrier oxide thin film transistor 10.

[0089] Alternatively, see Figure 2 , Figure 2 This is the second schematic diagram of the composition of the Schottky barrier oxide thin film transistor 10 provided in the embodiment of the present application. Figure 1Compared with the Schottky barrier oxide thin film transistor 10 shown, Figure 2 The Schottky barrier oxide thin film transistor 10 shown is relatively Figure 2 The differences of the Schottky barrier oxide thin film transistor 10 shown are mainly as follows: Figure 2 The Schottky barrier oxide thin film transistor 10 shown does not have a drain layer 18 prepared separately. Figure 2 The work function control layer 16 in the embodiment does not allocate a work function control portion for the drain layer 18. Figure 2 The projection areas of the diffusion barrier layer 15 and the work function regulating layer 16 on the substrate 11 overlap with each other. Figure 2 The source layer 17 is aligned with the diffusion barrier layer 15 and the work function regulating layer 16 at the same time. Figure 2 The film portion of the semiconductor layer 14 not covered by the source layer 17 and the diffusion barrier layer 15 is used as a drain region after being conductive.

[0090] Specifically, in the embodiments of the present application, Figure 2 The source layer 17 in the Schottky barrier oxide thin film transistor 10 shown covers the work function control layer 16 and also covers the portion of the outer surface of the semiconductor layer 14 that is not covered by the diffusion barrier layer 15. The work function control layer 16 is directly used to increase the work function of the source layer 17, and the diffusion barrier layer 15 is directly used to prevent the electrode material of the source layer 17 from diffusing into the semiconductor layer 14. At this time, the semiconductor layer 14 includes a semiconductor film layer portion 142 and a conductive film layer portion 141. The conductive film layer portion 141 is the film layer portion of the semiconductor layer 14 that is not covered by the source layer 17 and the diffusion barrier layer 15. The semiconductor film layer portion 142 is the remaining film layer portion of the semiconductor layer 14 except the conductive film layer portion 141. The conductive film layer portion 141 is used as Figure 2 In the drain region of the Schottky barrier oxide thin film transistor 10 shown, a portion of the source layer 17 directly contacts the semiconductor film portion 142 to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer 17 makes Schottky contact with the semiconductor film portion 142 via the work function control layer 16 and the diffusion barrier layer 15 to form a Schottky barrier, wherein the source layer 17, the work function control layer 16, and the diffusion barrier layer 15 are laterally aligned. Figure 2When the Schottky barrier oxide thin film transistor 10 shown is operating in a saturated state, the depletion region 19 corresponding to the source layer 17 in the Schottky barrier oxide thin film transistor 10 is a local semiconductor region in the semiconductor film layer portion 142 that is overlapped and covered by the projections of the source layer 17, the work function control layer 16, and the diffusion barrier layer 15. The depletion region 19 will extend from the side where the source layer 17 achieves ohmic (quasi-ohmic) contact to the side where the conductive film layer portion 141 is located, and until it touches the interlayer interface between the semiconductor layer 14 and the gate dielectric layer 13 on the side of the conductive film layer portion 141 (refer to Figure 2 The expansion distribution of the depletion region 19 in the embodiment of the present invention is used to achieve the pinch-off effect of the channel.

[0091] In this embodiment, for Figure 2 For the conductive film portion 141 shown in FIG. 1 , the film portion of the semiconductor layer 14 not covered by the source layer 17 and the diffusion barrier layer 15 can be bombarded with argon plasma to convert the bombarded film portion with semiconductor properties into the conductive film portion 141; or Figure 2 On the outer surface of the Schottky barrier oxide thin film transistor 10 shown, away from the substrate 11, at least silicon nitride material among silicon nitride materials and silicon dioxide materials is deposited to form a passivation layer, and the deposited passivation layer is annealed, so that the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer (i.e., the film layer portion not covered by the source layer 17 and the diffusion barrier layer 15) is conductive under the action of hydrogen diffusion doping of the passivation layer, so as to convert the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion 141.

[0092] Therefore, the application provides Figure 2The Schottky barrier oxide thin film transistor 10 shown can, on the basis of ensuring the device electrical characteristics of high saturation output current by utilizing the ohmic (quasi-ohmic) contact and Schottky contact formed at the source layer 17, prevent the electrode material of the source layer 17 from diffusing into the semiconductor layer 14 through a diffusion barrier layer 15 having carrier tunneling characteristics (i.e., satisfying the carrier tunneling effect), so as to avoid the carrier traps generated by the diffusion of the electrode material of the source layer 17 into the semiconductor layer 14, and greatly improve the work function difference of the source layer 17 relative to the semiconductor layer 14 through the work function control layer 16, thereby greatly improving the Schottky barrier oxide thin film transistor 10. The base barrier height (for example, the barrier height of the Schottky barrier in the thermal equilibrium state is greater than or equal to 0.6 eV) greatly reduces the carrier injection of the source layer 17 at the Schottky contact portion, so as to effectively reduce the capture of carriers by interface defects, and avoid the depletion region 19 corresponding to the source layer 17 in the semiconductor layer 14 to generate hot carrier effects and carrier traps under a strong longitudinal electric field, thereby greatly improving the hysteresis phenomenon of the device electrical characteristics, improving the stability and reliability of the device, and at the same time, there is no need to use expensive precious metals to prepare the source layer 17 and the drain layer 18 with a high work function, so as to effectively reduce the preparation cost of the device.

[0093] It is understandable that when Figure 2 When the conductive film portion 141 in the embodiment is subjected to argon plasma bombardment for conductive treatment, Figure 2 A passivation layer is deposited on the outer surface of the Schottky barrier oxide thin film transistor 10 away from the substrate 11 to cover and encapsulate the Schottky barrier oxide thin film transistor 10 through the passivation layer, and then a first via hole and a second via hole are opened on the passivation layer, so that the first via hole partially exposes the source layer 17, and the second via hole partially exposes the conductive film layer portion 141, so that the source wiring layer is arranged to be electrically connected to the source layer 17 through the first via hole, and the drain wiring layer is arranged to be electrically connected to the conductive film layer portion 141 through the second via hole, thereby completing the Figure 2 The device packaging effect of the Schottky barrier oxide thin film transistor 10 is shown. The passivation layer is formed by plasma-enhanced chemical vapor deposition or atomic layer deposition, and the material used for the passivation layer includes at least silicon nitride and silicon dioxide. When the corresponding passivation layer is formed using silicon nitride and silicon dioxide materials, the passivation layer can be formed by stacking an oxide layer formed using silicon dioxide and a silicon nitride layer formed using silicon nitride, wherein the silicon nitride layer is disposed on a side of the oxide layer away from the Schottky barrier oxide thin film transistor 10.

[0094] It is also understandable that when Figure 2When the conductive film portion 141 in the conductive film is made conductive by hydrogen diffusion doping of the passivation layer, Figure 2 The passivation layer deposited on the Schottky barrier oxide thin film transistor 10 is opened to expose the source layer 17 through a first via hole and the conductive film portion 141 through a second via hole, so that the source wiring layer is electrically connected to the source layer 17 through the first via hole and the drain wiring layer is electrically connected to the conductive film portion 141 through the second via hole, thereby completing the Figure 2 The device packaging effect of the Schottky barrier oxide thin film transistor 10 is shown. The passivation layer is formed by plasma-enhanced chemical vapor deposition or atomic layer deposition, and the material used for the passivation layer includes at least silicon nitride and silicon dioxide. When the corresponding passivation layer is formed using silicon nitride and silicon dioxide, the passivation layer can be formed by stacking an oxide layer formed using silicon dioxide and a silicon nitride layer formed using silicon nitride, wherein the silicon nitride layer is disposed on a side of the oxide layer away from the Schottky barrier oxide thin film transistor 10.

[0095] In this application, to ensure Figure 1 The Schottky barrier oxide thin film transistor 10 shown can be prepared and formed quickly and orderly to reduce the source preparation cost and effectively avoid the generation of carrier traps on the basis of ensuring the device electrical characteristics of high saturation output current, thereby greatly improving the hysteresis phenomenon of the device electrical characteristics, enhancing the stability and reliability of the device, and reducing the preparation cost of the device. The embodiment of the present application achieves the above functions by providing a preparation method of a Schottky barrier oxide thin film transistor.

[0096] Please refer to Figure 3 , Figure 3 This is one of the flow diagrams of the method for preparing a Schottky barrier oxide thin film transistor provided in the embodiment of the present application. In the embodiment of the present application, Figure 3 The preparation method shown may include steps S210 to S230 and step S240 to prepare Figure 1 The Schottky barrier oxide thin film transistor 10 is shown.

[0097] Step S210: providing a substrate.

[0098] In step S220 , a gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate to obtain a first semiconductor device, wherein the gate layer and the semiconductor layer are both patterned.

[0099] In this embodiment, the gate dielectric layer 13 in the first semiconductor device covers the gate layer 12 .

[0100] Optionally, please refer to Figure 4 and Figure 5 ,in Figure 4 yes Figure 3 Schematic diagram of the flow of sub-steps included in step S220, Figure 5 Schematic diagram of the fabrication of the first semiconductor device provided in the embodiment of the present application. In the embodiment of the present application, step S220 may include sub-steps S221 to S223 to fabricate the first semiconductor device in which both the gate layer 12 and the semiconductor layer 14 are patterned.

[0101] In sub-step S221 , a gate layer is formed by sputtering deposition on one side surface of the substrate, and the deposited gate layer is patterned by photolithography.

[0102] In this embodiment, Figure 5 (a) is a schematic diagram of a device in which a patterned gate layer 12 is formed on one side of the substrate 11. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited gate layer 12 away from the substrate 11 and patterned. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the gate layer 12 not covered by the photoresist layer is etched to achieve the patterning effect of the gate layer 12. Acetone can be used to remove the patterned photoresist layer.

[0103] In sub-step S222 , a gate dielectric layer is grown on the side of the substrate where the gate layer is formed based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the gate dielectric layer covers the gate layer and the side area of ​​the substrate not blocked by the gate layer.

[0104] In this embodiment, Figure 5 (b) is a schematic diagram of a device in which the gate dielectric layer 13 is grown on the side of the substrate 11 on which the gate layer 12 is formed.

[0105] In sub-step S223 , a semiconductor layer is deposited on the outer surface of the gate dielectric layer away from the substrate by magnetron sputtering or atomic layer deposition, and the deposited semiconductor layer is patterned by photolithography to obtain a first semiconductor device.

[0106] In this embodiment, Figure 5 (c) is a schematic diagram of a device in which a patterned semiconductor layer 14 is prepared on the outer surface of the gate dielectric layer 13 away from the substrate 11. Figure 5The device structure shown in (c) is the first semiconductor device. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited semiconductor layer 14 away from the gate dielectric layer 13, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the semiconductor layer 14 not covered by the photoresist layer can be etched to achieve the patterning effect of the semiconductor layer 14. Acetone can be used to remove the patterned photoresist layer.

[0107] In step S230 , a diffusion barrier layer, a work function regulating layer, and an electrode film layer are prepared on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device.

[0108] In this embodiment, the diffusion barrier layer 15 in the second semiconductor device satisfies the carrier tunneling effect, and the work function regulation layer 16 in the second semiconductor device is arranged between the diffusion barrier layer 15 and the electrode film layer. The projection areas of the diffusion barrier layer 15 and the work function regulation layer 16 on the substrate 11 overlap with each other, and the projection area corresponding to the diffusion barrier layer 15 is within the projection area of ​​the semiconductor layer 14 on the substrate 11. The area of ​​the projection area corresponding to the diffusion barrier layer 15 is smaller than the area of ​​the projection area corresponding to the semiconductor layer 14; while the electrode film layer covers the work function regulation layer 16 and the diffusion barrier layer 15, it also covers the outer surface of the semiconductor layer 14 not covered by the diffusion barrier layer 15; at this time, the work function regulation layer 16 can be directly used to improve the work function of the electrode film layer, and the diffusion barrier layer 15 is used to prevent the electrode material of the electrode film layer from diffusing to the semiconductor layer 14.

[0109] Optionally, please refer to Figure 6 and Figure 7 ,in Figure 6 yes Figure 3 One of the flowcharts of the sub-steps included in step S230, Figure 7 This is one of the schematic diagrams for manufacturing the second semiconductor device provided in the embodiment of the present application. In the embodiment of the present application, the step S230 may include sub-steps S231 to S233 to prepare the second semiconductor device.

[0110] In sub-step S231 , a diffusion barrier layer and a work function control layer are sequentially deposited on the outer surface of the first semiconductor device away from the substrate based on magnetron sputtering or atomic layer deposition, wherein the diffusion barrier layer satisfies the carrier tunneling effect.

[0111] In this embodiment, Figure 7(a) is a schematic diagram of a device in which a diffusion barrier layer 15 and a work function modulation layer 16 are stacked and distributed as complete film layers on the first semiconductor device. The diffusion barrier layer 15 is disposed between the first semiconductor device and the work function modulation layer 16.

[0112] In sub-step S232, the deposited work function control layer and the diffusion barrier layer are sequentially photolithographically patterned so that the projection areas corresponding to the patterned diffusion barrier layer and the work function control layer overlap with each other, and the projection area corresponding to the patterned diffusion barrier layer is within the projection area corresponding to the semiconductor layer.

[0113] In this embodiment, Figure 7 (b) is a schematic diagram of a device in which a patterned diffusion barrier layer 15 and a patterned work function modulation layer 16 are formed on the first semiconductor device. The projected areas of the patterned diffusion barrier layer 15 and the patterned work function modulation layer 16 overlap, and the projected area of ​​the patterned diffusion barrier layer 15 is smaller than the projected area of ​​the semiconductor layer 14. In one implementation of this embodiment, a photoresist layer may be spin-coated on the outer surface of the newly deposited work function regulation layer 16 away from the first semiconductor device, and the photoresist layer may be patterned so that the projection area of ​​the patterned photoresist layer on the substrate 11 is smaller than the projection area corresponding to the semiconductor layer 14. Then, under the shielding effect of the patterned photoresist layer, the local areas of the work function regulation layer 16 not covered by the photoresist layer are etched. Subsequently, under the shielding effect of the patterned work function regulation layer 16 or the patterned photoresist layer on the work function regulation layer 16, all local areas of the diffusion barrier layer 15 not covered by the patterned photoresist layer or the patterned work function regulation layer 16 are etched so that the projection areas corresponding to the patterned diffusion barrier layer 15 and the patterned work function regulation layer 16 overlap with each other. Acetone may be used to remove the patterned photoresist layer.

[0114] Sub-step S233 , forming an electrode film layer by sputtering deposition on a side of the work function regulating layer away from the diffusion barrier layer to obtain a second semiconductor device.

[0115] In this embodiment, Figure 7 (c) is a schematic diagram of a device in which an electrode film layer covering the work function regulating layer 16 and the diffusion barrier layer 15 and the semiconductor layer 14 is prepared on the first semiconductor device. Figure 7 The device structure shown in (c) is the second semiconductor device.

[0116] Therefore, the present application can directly prepare and form the second semiconductor device by deposition by executing the above sub-steps S231 to S232.

[0117] Optionally, please refer to Figure 8 and Figure 9 ,in Figure 8 yes Figure 3 The second flowchart of the sub-steps included in step S230 is as follows: Figure 9 This is the second schematic diagram of the manufacturing of the second semiconductor device provided in the embodiment of the present application. In the embodiment of the present application, the step S230 may include sub-steps S235 to S237 to prepare the second semiconductor device.

[0118] In sub-step S235, a diffusion barrier layer satisfying the carrier tunneling effect is deposited on the outer surface of the first semiconductor device away from the substrate based on a magnetron sputtering method or an atomic layer deposition method, and the diffusion barrier layer is photolithographically patterned so that the projection area corresponding to the patterned diffusion barrier layer is within the projection area corresponding to the semiconductor layer.

[0119] In this embodiment, Figure 9 (a) is a schematic diagram of a device in which a patterned diffusion barrier layer 15 is formed on the first semiconductor device. The projected area of ​​the patterned diffusion barrier layer 15 is smaller than the projected area of ​​the semiconductor layer 14. In one implementation of this embodiment, a photoresist layer can be spin-coated on the outer surface of the newly deposited diffusion barrier layer 15, away from the first semiconductor device, and patterned. Then, under the shielding effect of the patterned photoresist layer, the localized areas of the diffusion barrier layer 15 not covered by the photoresist layer are etched to achieve the patterning effect of the diffusion barrier layer 15. Acetone can be used to remove the patterned photoresist layer.

[0120] Sub-step S236 , forming an electrode film layer by sputtering deposition on a side of the diffusion barrier layer away from the semiconductor layer.

[0121] In this embodiment, Figure 9 (b) is a schematic diagram of a device in which an electrode film layer is formed on the first semiconductor device, the electrode film layer being coated with the diffusion barrier layer 15 and covering the semiconductor layer 14. The electrode film layer is coated with the patterned diffusion barrier layer 15 and covers the outer surface of the semiconductor layer 14 not covered by the diffusion barrier layer 15.

[0122] Sub-step S237, annealing the electrode film layer and the diffusion barrier layer in a vacuum atmosphere or an inert gas atmosphere, so that the local area of ​​the electrode film layer that is in direct contact with the diffusion barrier layer undergoes an oxidation reaction to form a work function regulation layer that overlaps with the projection area of ​​the diffusion barrier layer, thereby obtaining a second semiconductor device.

[0123] In this embodiment, Figure 9 (c) is a schematic diagram of a device in which a work function control layer 16 is formed between the electrode film layer and the diffusion barrier layer 15 by oxidation using a chemical reaction method. Figure 9 The device structure shown in (c) is the second semiconductor device. The annealing temperature required during the execution of sub-step S237 must be no less than 150°C.

[0124] Therefore, the present application can form the second semiconductor device by performing the above sub-steps S235 to S237 through the cooperation between deposition and chemical reaction methods.

[0125] In step S240, photolithography patterning is performed on the side of the second semiconductor device away from the substrate to pattern the electrode film layer into a source layer and a drain layer spaced apart from each other, and the work function control layer is patterned into two work function control parts that are laterally aligned with the source layer and the drain layer, respectively.

[0126] In this embodiment, the source layer 17 prepared by the step S240 will cover the portion of the outer surface of the semiconductor layer 14 that is not covered by the diffusion barrier layer 15, and the drain layer 18 prepared by the step S240 will cover the remaining outer surface of the semiconductor layer 14 that is not covered by the diffusion barrier layer 15. At this time, a portion of the source layer 17 is in direct contact with the semiconductor layer 14 to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer 17 is spaced apart at a corresponding work function regulation portion and the diffusion barrier layer 15 to form a Schottky barrier with the semiconductor layer 14. At the same time, a portion of the drain layer 18 is in direct contact with the semiconductor layer 14 to form an ohmic contact or a quasi-ohmic contact, and a portion of the drain layer 18 is spaced apart at a corresponding work function regulation portion and the diffusion barrier layer 15 to form a Schottky barrier with the semiconductor layer 14.

[0127] In one implementation of this embodiment, a photoresist layer can be spin-coated on the side of the second semiconductor device away from the substrate 11, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the electrode film layer not covered by the photoresist layer is etched to pattern the electrode film layer into a source layer 17 and a drain layer 18 spaced apart from each other. Then, under the shielding effect of the patterned electrode film layer or the patterned photoresist layer on the electrode film layer, all local areas of the work function regulation layer 16 not covered by the patterned photoresist layer or the patterned electrode film layer are etched to pattern the work function regulation layer 16 into two work function regulation parts that are laterally aligned with the source layer 17 and the drain layer 18, respectively. Acetone can be used to remove the patterned photoresist layer.

[0128] Therefore, the present application can prepare the corresponding Figure 1 The Schottky barrier oxide thin film transistor 10 is shown.

[0129] In addition, it can be understood that the above steps S220, S230, and S240 can be performed in a flip-chip manner based on step S210 (for example, a source layer 17 and a drain layer 18 belonging to the same electrode film layer are first prepared on the substrate 11, and then the work function control layer 16 and the diffusion barrier layer 15 are prepared in sequence, and then the semiconductor layer 14, the gate dielectric layer 13, and the gate layer 12 are prepared in sequence), so that the corresponding Schottky barrier metal oxide thin film transistor device is Figure 1 The Schottky barrier oxide thin film transistor 10 shown is a flip-chip device structure, to which this application does not impose any limitation.

[0130] In this application, to ensure Figure 2 The Schottky barrier oxide thin film transistor 10 shown can be prepared and formed quickly and orderly to reduce the source preparation cost and effectively avoid the generation of carrier traps on the basis of ensuring the device electrical characteristics of high saturation output current, thereby greatly improving the hysteresis phenomenon of the device electrical characteristics, enhancing the stability and reliability of the device, and reducing the preparation cost of the device. The embodiment of the present application achieves the above functions by providing a preparation method of a Schottky barrier oxide thin film transistor.

[0131] Please refer to Figure 10 , Figure 10 This is the second flow chart of the method for preparing a Schottky barrier oxide thin film transistor provided in the embodiment of the present application. In the embodiment of the present application, Figure 10 The preparation method shown is Figure 3 The preparation method shown has the same steps (i.e., steps S210 to S230). Figure 10 The preparation method shown is Figure 3 The differences between the preparation methods shown lie mainly in: Figure 10 The preparation method shown adopts step S250 to replace Figure 1 Step 240 in the preparation method shown corresponds to the preparation of Figure 2 The Schottky barrier oxide thin film transistor 10 is shown.

[0132] In step S250, photolithography patterning is performed on the side of the second semiconductor device away from the substrate to pattern the electrode film layer into a source layer that is laterally aligned with the diffusion barrier layer and the work function regulation layer, and then the film layer portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer is conductorized to form a conductorized film layer portion for serving as a drain region.

[0133] In this embodiment, when a second semiconductor device prepared based on the above steps S210 to S230 is obtained, a photoresist layer can be spin-coated on a side of the second semiconductor device away from the substrate 11, and the photoresist layer can be patterned. Then, under the shielding effect of the patterned photoresist layer, the local area of ​​the electrode film layer not covered by the photoresist layer is etched to etch the electrode film layer into a source layer 17. Then, under the shielding effect of the patterned source layer 17 or the patterned photoresist layer on the source layer 17, all local areas of the work function regulation layer 16 and the diffusion barrier layer 15 not covered by the patterned photoresist layer or the source layer 17 are etched in sequence, so that the source layer 17, the diffusion barrier layer 15 and the work function regulation layer 16 are etched into a state of side alignment. At this time, the prepared source layer 17 will cover the outer surface of the semiconductor layer 14 that is not covered by the diffusion barrier layer 15, and acetone can be used to remove the patterned photoresist layer. Then, the film portion of the semiconductor layer 14 not covered by the source layer 17 and the diffusion barrier layer 15 can be conductively treated to divide the semiconductor layer 14 into a semiconductor film portion 142 and a conductive film portion 141. Figure 2 The Schottky barrier oxide thin film transistor 10 is shown.

[0134] Among them, the conductive film layer portion 141 is the film layer portion of the semiconductor layer 14 that is not covered by the source layer 17 and the diffusion barrier layer 15, and the semiconductor film layer portion 142 is the remaining film layer portion of the semiconductor layer 14 except the conductive film layer portion 141. The conductive film layer portion 141 is used as the drain region of the corresponding Schottky barrier oxide thin film transistor 10, and a partial area of ​​the source layer 17 is in direct contact with the semiconductor film layer portion 142 to form an ohmic contact or a quasi-ohmic contact. A partial area of ​​the source layer 17 is separated from the work function control layer 16 and the diffusion barrier layer 15 and forms a Schottky barrier with the semiconductor film layer portion 142.

[0135] In one implementation of this embodiment, the step of “conducting the film portion of the semiconductor layer 14 not covered by the source layer 17 and the diffusion barrier layer 15 ” in step 250 may include:

[0136] Argon plasma is used to bombard the film portion of the semiconductor layer 14 that is not covered by the source layer 17 and the diffusion barrier layer 15 , so as to convert the bombarded film portion with semiconductor characteristics into the conductive film portion 141 .

[0137] In another implementation of this embodiment, the step of “conducting the film portion of the semiconductor layer 14 not covered by the source layer 17 and the diffusion barrier layer 15 ” in step 250 may include:

[0138] On the outer surface of the source layer 17 of the second semiconductor device, at least silicon nitride material and silicon dioxide material are used to deposit a passivation layer, and the passivation layer is annealed, so that the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer is conductive under the action of hydrogen diffusion doping of the passivation layer, so as to convert the film layer portion of the semiconductor layer 14 that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion 141.

[0139] When the conductive film portion 141 is formed by utilizing the hydrogen diffusion doping effect of the passivation layer, the deposited passivation layer can be opened so that the first via hole partially exposes the source layer 17 and the second via hole partially exposes the conductive film portion 141, so that the source wiring layer is arranged to be electrically connected to the source layer 17 through the first via hole, and the drain wiring layer is arranged to be electrically connected to the conductive film portion 141 through the second via hole, thereby completing the Figure 2 The device packaging effect of the Schottky barrier oxide thin film transistor 10 is shown.

[0140] Therefore, the present application can prepare the corresponding Figure 2 The Schottky barrier oxide thin film transistor 10 is shown.

[0141] The above are merely various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for preparing a Schottky barrier oxide thin film transistor, characterized in that: The preparation method comprises: providing a substrate; A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate to obtain a first semiconductor device, wherein the gate layer and the semiconductor layer are both patterned; A diffusion barrier layer, a work function regulation layer, and an electrode film layer are prepared on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device, wherein the diffusion barrier layer satisfies the carrier tunneling effect, the work function regulation layer is arranged between the diffusion barrier layer and the electrode film layer, the projection areas of the diffusion barrier layer and the work function regulation layer on the substrate overlap with each other, and the projection area corresponding to the diffusion barrier layer is within the projection area of ​​the semiconductor layer on the substrate, the electrode film layer covers the outer surface of the semiconductor layer not covered by the diffusion barrier layer, wherein the work function regulation layer is used to improve the work function of the electrode film layer, and the diffusion barrier layer is used to prevent the electrode material of the electrode film layer from diffusing into the semiconductor layer; Photolithographic patterning is performed on the side of the second semiconductor device away from the substrate to pattern the electrode film layer into a source layer and a drain layer spaced apart from each other, and the work function control layer is patterned into two work function control portions that are aligned with the source layer and the drain layer, respectively, wherein a portion of the source layer is in direct contact with the semiconductor layer to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer is spaced apart from the corresponding work function control portion and the diffusion barrier layer to form a Schottky barrier with the semiconductor layer; or photolithographic patterning is performed on the side of the second semiconductor device away from the substrate to pattern the electrode film layer into a source layer and a drain layer spaced apart from each other, and the work function control portion is aligned with the source layer and the drain layer, respectively. The layer is patterned into a source layer that is laterally aligned with the diffusion barrier layer and the work function regulation layer, and then the film layer portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer is conductorized to form a conductorized film layer portion for serving as a drain region, wherein a portion of the source layer is in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer is separated from the work function regulation layer and the diffusion barrier layer and the semiconductor film layer portion to form a Schottky barrier, wherein the semiconductor film layer portion is the remaining film layer portion of the semiconductor layer except the conductorized film layer portion.

2. The preparation method according to claim 1, characterized in that The step of sequentially stacking a gate layer, a gate dielectric layer, and a semiconductor layer on one side of the substrate to obtain a first semiconductor device comprises: sputtering and depositing a gate layer on one side surface of the substrate, and performing photolithographic patterning on the deposited gate layer; On the side of the substrate where the gate layer is formed, growing the gate dielectric layer based on plasma enhanced chemical vapor deposition or atomic layer deposition, so that the gate dielectric layer covers the gate layer and the side area of ​​the substrate not blocked by the gate layer; The semiconductor layer is deposited on the outer surface of the gate dielectric layer away from the substrate based on magnetron sputtering or atomic layer deposition, and the deposited semiconductor layer is patterned by photolithography to obtain the first semiconductor device.

3. The preparation method according to claim 1, characterized in that The step of preparing a diffusion barrier layer, a work function regulating layer and an electrode film layer on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device comprises: On the outer surface of the first semiconductor device away from the substrate, sequentially depositing the diffusion barrier layer and the work function control layer based on magnetron sputtering or atomic layer deposition, wherein the diffusion barrier layer satisfies the carrier tunneling effect; Sequentially performing photolithographic patterning on the deposited work function regulating layer and the diffusion barrier layer, so that the projection areas corresponding to the patterned diffusion barrier layer and the work function regulating layer overlap with each other, and the projection area corresponding to the patterned diffusion barrier layer is within the projection area corresponding to the semiconductor layer; An electrode film layer is formed by sputtering deposition on a side of the work function regulating layer away from the diffusion barrier layer to obtain the second semiconductor device.

4. The preparation method according to claim 1, characterized in that The step of preparing a diffusion barrier layer, a work function regulating layer and an electrode film layer on a side of the first semiconductor device away from the substrate to obtain a second semiconductor device comprises: Depositing the diffusion barrier layer satisfying the carrier tunneling effect on the outer surface of the first semiconductor device away from the substrate by magnetron sputtering or atomic layer deposition, and photolithographically patterning the diffusion barrier layer so that a projection area corresponding to the patterned diffusion barrier layer is within a projection area corresponding to the semiconductor layer; forming an electrode film layer by sputtering deposition on a side of the diffusion barrier layer away from the semiconductor layer; The electrode film layer and the diffusion barrier layer are annealed in a vacuum atmosphere or an inert gas atmosphere to cause an oxidation reaction in a local area of ​​the electrode film layer that is in direct contact with the diffusion barrier layer to form the work function regulation layer that overlaps with the projection area of ​​the diffusion barrier layer, thereby obtaining the second semiconductor device.

5. The preparation method according to claim 1, characterized in that The step of conducting the film portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer to form a conductive film portion for serving as a drain region includes: Argon plasma is used to bombard the film layer portion of the semiconductor layer that is not covered by the source layer and the diffusion barrier layer, so as to convert the bombarded film layer portion with semiconductor characteristics into the conductive film layer portion.

6. The preparation method according to claim 1, characterized in that The step of conducting the film portion of the semiconductor layer not covered by the source layer and the diffusion barrier layer to form a conductive film portion for serving as a drain region includes: On the outer surface of the source layer of the second semiconductor device, at least silicon nitride material and silicon dioxide material are used to deposit a passivation layer, and the passivation layer is annealed to make the film layer portion of the semiconductor layer that is in direct contact with the passivation layer conductive under the action of hydrogen diffusion doping of the passivation layer, so as to convert the film layer portion of the semiconductor layer that is in direct contact with the passivation layer and has semiconductor properties into the conductive film layer portion.

7. The preparation method according to any one of claims 1 to 6, characterized in that The material of the gate layer is any one of Al, Cu, Mo, Ti, and ITO; The gate dielectric layer is made of a stack of any one or more materials selected from the group consisting of SiO2, silicon nitride, aluminum oxide, hafnium oxide, and zirconium oxide. The material of the semiconductor layer is any one of InGaZnO, InZnO, InZnSnO, Ln-IZO, InGaO, ZnO, Ga2O3, SnO2 and In2O3; The material of the diffusion barrier layer is any one of SiO2, Al2O3, HfO2, and ZrO2; The material of the electrode film layer is any one of Cu, Mo, Co, Ti, Ni, W, Cr, Ag or ITO, wherein the work function of the electrode film layer is greater than the work function of the semiconductor layer; The material of the work function regulating layer is any one of copper oxide, molybdenum oxide, cobalt oxide, titanium oxide, nickel oxide, tungsten oxide, chromium oxide, silver oxide, tellurium oxide, and tin oxide.

8. The preparation method according to claim 7, characterized in that The thickness of the gate layer is in the range of 10-1000 nm; The thickness of the gate dielectric layer is in the range of 5-500 nm; The thickness of the semiconductor layer is in the range of 5-200 nm; The thickness of the diffusion barrier layer is in the range of 1-5 nm; The thickness of the work function regulation layer is in the range of 1-100 nm.

9. A Schottky barrier oxide thin film transistor, characterized in that: The thin film transistor includes: substrate; A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer; A diffusion barrier layer, a work function regulation layer, and an electrode film layer are sequentially stacked on the semiconductor layer, wherein the diffusion barrier layer satisfies the carrier tunneling effect, the work function regulation layer is arranged between the diffusion barrier layer and the electrode film layer, the projection area of ​​the diffusion barrier layer on the substrate is within the projection area of ​​the semiconductor layer on the substrate, the work function regulation layer is used to improve the work function of the electrode film layer, and the diffusion barrier layer is used to prevent the electrode material of the electrode film layer from diffusing into the semiconductor layer; The work function regulating layer comprises two work function regulating sites spaced apart from each other, and the projection areas of the two work function regulating sites on the substrate are both within the projection area corresponding to the diffusion barrier layer; The electrode film layer includes a source layer and a drain layer spaced apart from each other, the source layer covers a portion of the outer surface of the semiconductor layer not covered by the diffusion barrier layer, and the drain layer covers the remaining outer surface of the semiconductor layer not covered by the diffusion barrier layer, the source layer is aligned with the side of one work function regulation portion, and the drain layer is aligned with the side of another work function regulation portion, wherein a portion of the source layer is in direct contact with the semiconductor layer to form an ohmic contact or a quasi-ohmic contact, and a portion of the source layer is spaced apart from the corresponding work function regulation portion and the diffusion barrier layer to form a Schottky barrier with the semiconductor layer.

10. A Schottky barrier oxide thin film transistor, characterized in that: The thin film transistor includes: substrate; A gate layer, a gate dielectric layer, and a semiconductor layer are sequentially stacked on one side of the substrate, wherein the gate dielectric layer covers the gate layer; A diffusion barrier layer, a work function regulation layer, and a source layer are sequentially stacked on the semiconductor layer, wherein the diffusion barrier layer satisfies the carrier tunneling effect, the work function regulation layer is arranged between the diffusion barrier layer and the source layer, the projection area of ​​the diffusion barrier layer on the substrate is within the projection area of ​​the semiconductor layer on the substrate, the projection areas of the diffusion barrier layer and the work function regulation layer on the substrate overlap with each other, the source layer covers the portion of the outer surface of the semiconductor layer not covered by the diffusion barrier layer, and the source layer is laterally aligned with the diffusion barrier layer and the work function regulation layer, wherein the work function regulation layer is used to increase the work function of the source layer, and the diffusion barrier layer is used to prevent the electrode material of the source layer from diffusing into the semiconductor layer; The semiconductor layer includes a semiconductor film layer portion and a conductive film layer portion, wherein the conductive film layer portion is a film layer portion of the semiconductor layer that is not covered by the source layer and the diffusion barrier layer, and the semiconductor film layer portion is a remaining film layer portion of the semiconductor layer except the conductive film layer portion, wherein the conductive film layer portion is used as a drain region of the corresponding thin film transistor, a partial area of ​​the source layer is in direct contact with the semiconductor film layer portion to form an ohmic contact or a quasi-ohmic contact, and a partial area of ​​the source layer is separated by the work function control layer and the diffusion barrier layer and forms a Schottky barrier with the semiconductor film layer portion.

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