Semiconductor standard cell structure, semiconductor structure and memory

Abstract

This disclosure provides a semiconductor standard cell structure, a semiconductor structure, and a memory. The semiconductor standard cell structure includes: a plurality of transistors located in a device layer; a first wiring located in a first metal layer; the first wiring being connected to the plurality of transistors through a first contact via; a second wiring located in a second metal layer, the second wiring being connected to the first wiring through a second contact via; and a power line located in a third metal layer and extending along a first direction; wherein the device layer, the first metal layer, the second metal layer, and the third metal layer are stacked sequentially along a second direction; the projection of the power line along the second direction is located within the projection range of the second wiring along the second direction; the second wiring is connected to the power line through a third contact via.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor standard cell structure, semiconductor structure, and memory. Background Technology

[0002] Semiconductor layout design can be based on a cell-based design approach, which breaks down complex circuits into a series of standard semiconductor cell structures, thus simplifying the design process. A standard semiconductor cell structure comprises a series of basic components, such as metal layers and active regions.

[0003] Currently, the conductivity between metal layers in the standard semiconductor cell structure is still insufficient, which affects the further development of the standard semiconductor cell structure and semiconductor structures. Summary of the Invention

[0004] This disclosure provides a standard semiconductor cell structure, a semiconductor structure, and a memory.

[0005] This disclosure provides a semiconductor standard cell structure, which includes: a plurality of transistors located in a device layer; a first wiring located in a first metal layer; the first wiring being connected to the plurality of transistors through a first contact via; a second wiring located in a second metal layer, the second wiring being connected to the first wiring through a second contact via; and a power line located in a third metal layer and extending along a first direction.

[0006] The device layer, the first metal layer, the second metal layer, and the third metal layer are stacked sequentially along the second direction; the projection of the power line along the second direction is located within the projection range of the second wiring along the second direction; the second wiring is connected to the power line through a third contact via.

[0007] This disclosure provides a semiconductor structure that includes the standard semiconductor cell structure described above.

[0008] This disclosure provides a memory comprising the semiconductor structure described above.

[0009] This disclosure provides a semiconductor standard cell structure, a semiconductor structure, and a memory. The semiconductor standard cell structure includes: a plurality of transistors located in a device layer; a first wiring located in a first metal layer; the first wiring and the plurality of transistors connected through a first contact via; a second wiring located in a second metal layer, the second wiring being connected to the first wiring through a second contact via; and a power line located in a third metal layer and extending along a first direction; wherein the device layer, the first metal layer, the second metal layer, and the third metal layer are stacked sequentially along a second direction; the projection of the power line along the second direction is located within the projection range of the second wiring along the second direction; the second wiring is connected to the power line through a third contact via. By introducing a second wiring located in the second metal layer between the first wiring in the first metal layer and the power line in the third metal layer, and ensuring that the projection of the power line along the second direction is within the projection range of the second wiring along the second direction, the number of third contact vias that can be provided between the second wiring and the power line can be increased. This enhances the overcurrent capability between the first and second metal layers in the semiconductor standard cell structure, which is beneficial for the further development of semiconductor standard cell structures and semiconductor structures. Attached Figure Description

[0010] Figure 1A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure;

[0011] Figure 1B A schematic diagram of a layered structure of a semiconductor standard cell structure provided in this embodiment of the present disclosure;

[0012] Figure 1C A schematic cross-sectional view of a semiconductor standard cell structure along the AA' direction, provided for an embodiment of this disclosure;

[0013] Figure 2A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure;

[0014] Figure 2B A schematic diagram of a layered structure of a semiconductor standard cell structure provided in this embodiment of the present disclosure;

[0015] Figure 3A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure;

[0016] Figure 3B A schematic diagram of a layered structure of a semiconductor standard cell structure provided in this embodiment of the present disclosure;

[0017] Figure 3CThis is a schematic diagram of the layered structure of a semiconductor standard cell structure provided in an embodiment of the present disclosure;

[0018] Figure 4A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure;

[0019] Figure 4B A schematic diagram of a layered structure of a semiconductor standard cell structure provided in this embodiment of the present disclosure;

[0020] Figure 5 for Figure 3A The equivalent circuit diagram of the corresponding semiconductor standard cell structure;

[0021] Figure 6 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0022] Figure 7 A schematic diagram of a memory provided for an embodiment of this disclosure;

[0023] Figure 8 This is a schematic diagram of a partial structure of a DRAM chip.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10: Semiconductor standard cell structure; 11: Device layer; 12: First metal layer; 13: Second metal layer; 14: Third metal layer; 15: First sub-layer; 16: Second sub-layer; 21: Transistor; 22: First wiring; 23: First contact via; 24: Second wiring; 25: Second contact via; 26: Power line; 27: Third contact via; 211: Active region; 212: Gate; 28: First connection portion; 29: Second connection portion; 311: First conductivity type transistor; 312: Second conductivity type transistor; 321: First electrode line; 3 22: Second electrode line; 331: First power line; 332: Second power line; 341: First metal connection structure; 342: Second metal connection structure; 351: First sub-connection portion; 352: Second sub-connection portion; 353: Third sub-connection portion; 354: Fourth sub-connection portion; 361: First active region; 362: Second active region; 363: First gate structure; 364: Second gate structure; 37: Metal interconnect structure; 371: First target metal line; 372: Second target metal line; 381: First well contact; 382: Second well contact. Detailed Implementation

[0026] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0028] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0029] It should be noted that the terms "first, second, third, and fourth" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third, and fourth" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0030] In related technologies, the conductivity between metal layers in the semiconductor standard cell structure is still insufficient, which affects the further development of the semiconductor standard cell structure and semiconductor structure.

[0031] In the process of implementing the embodiments of this disclosure, the inventors discovered that the reason for insufficient conductivity between metal layers in the semiconductor standard cell structure is that the extension direction of the first wiring located in the first metal layer intersects with the extension direction of the power line located in the third metal layer. The overlapping area between the projection of the first wiring along the longitudinal direction and the projection of the power line along the longitudinal direction is limited. This affects the setting of the contact via between the first wiring and the power line, resulting in insufficient conductivity between the first wiring and the power line, which affects the further development of the semiconductor standard cell structure and the semiconductor structure.

[0032] Based on this, the present disclosure provides a semiconductor standard cell structure. By introducing a second wiring in a second metal layer between a first wiring in a first metal layer and a power line in a third metal layer, and with the projection of the power line along a second direction within the projection range of the second wiring along the second direction, the number of contact vias between the second wiring and the power line can be increased, thereby enhancing the overcurrent capability between the first wiring in the first metal layer and the power line in the third metal layer in the semiconductor standard cell structure. This is beneficial to the further development of semiconductor standard cell structures and semiconductor structures.

[0033] Figure 1A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure. Figure 1B A schematic diagram of a layered structure of a semiconductor standard cell structure provided in this disclosure embodiment. Figure 1C This is a schematic cross-sectional view of a semiconductor standard cell structure along the AA' direction, provided in an embodiment of this disclosure. Figure 1A , Figure 1B and Figure 1C As shown, the semiconductor standard cell structure 10 includes:

[0034] A plurality of transistors 21 located in device layer 11; a first wiring 22 located in first metal layer 12; the first wiring 22 is connected to the plurality of transistors 21 through a first contact via 23; a second wiring 24 located in second metal layer 13, the second wiring 24 being connected to the first wiring 22 through a second contact via 25; and a power line 26 located in third metal layer 14 and extending in a first direction.

[0035] The device layer 11, the first metal layer 12, the second metal layer 13, and the third metal layer 14 are stacked sequentially along the second direction; the projection of the power line 26 along the second direction is located within the projection range of the second wiring 24 along the second direction; the second wiring 24 is connected to the power line 26 through the third contact via 27.

[0036] In some embodiments, the semiconductor standard cell structure 10 provided in this disclosure can be understood as a layout template. In this case, the semiconductor standard cell structure 10 is applied to a semiconductor standard cell structure library in integrated circuit design. The semiconductor standard cell structure library is the foundation of integrated circuit design. Integrated circuit design based on the semiconductor standard cell structure library can perform logic synthesis and layout placement and routing, improving circuit design efficiency. The semiconductor standard cell structure library includes several pre-designed semiconductor standard cell (Standard Cell) structures. Integrated circuit designers or circuit design synthesis tools call the semiconductor standard cell structure layout template in the semiconductor standard cell structure library to complete the layout design of the integrated circuit according to design requirements. In other embodiments, the semiconductor standard cell structure 10 provided in this disclosure can be understood as a physical structure prepared through various chemical processes (such as deposition, etching, annealing, etc.), i.e., the physical constituent unit in the chip.

[0037] Here, the semiconductor standard cell structure includes at least a four-layer stacked structure of a device layer, a first metal layer, a second metal layer, and a third metal layer, and the device layer, the first metal layer, the second metal layer, and the third metal layer are stacked sequentially along the second direction. It can be understood that adjacent two layers among the device layer, the first metal layer, the second metal layer, and the third metal layer can be directly adjacent, or they can be indirectly adjacent by setting other metal layers.

[0038] Each transistor located in the device layer can include an active region and a gate. For example... Figure 1C As shown, each transistor 21 may include an active region 211 and a gate 212. It is understood that the active region includes a source region, a channel, and a drain region, and the gate is connected to the channel in the active region, that is, the gate covers the channel in the active region along the second direction.

[0039] The first wiring located in the first metal layer includes at least one of a source or a drain. In some embodiments, one of the source or drain in the first wiring extends in a third direction. The first wiring is connected to a transistor, that is, the first wiring is connected to one of the source or drain regions in the active region. In some embodiments, the first wiring includes a source, and the source in the first wiring is connected to the source region in the active region. The extension direction of the source is the same as the extension direction of the source region. This increases the number of first contact vias that can be provided between the first wiring and the source region, improving the conductivity between the first wiring and the active region. It should be noted that the first wiring can be a metallic conductive material; the first contact via is an electrical connection structure filled with conductive material, which can be polysilicon or a metallic conductive material.

[0040] The second wiring located on the second metal layer is connected to the first wiring located on the first metal layer through a second contact via. The second wiring is also connected to the power line located on the third metal layer through a third contact via. It can be understood that the second wiring is a dual-metal technology, which adds a metal layer between adjacent first and third metal layers. The first and third metal layers can be any adjacent metal layers, in which case the second metal layer is located between the adjacent first and third metal layers.

[0041] In some embodiments, the first metal layer may be referred to as M0, the second metal layer as M0U, and the third metal layer as M1; in some embodiments, the first metal layer may be referred to as M1, the second metal layer as M1U, and the third metal layer as M2; in some embodiments, the first metal layer may be referred to as M2, the second metal layer as M2U, and the third metal layer as M3; ... The embodiments disclosed herein will be described in the following description as an embodiment with the first metal layer M0, the second metal layer M0U, and the third metal layer M1, and other cases can be understood adaptively.

[0042] It should also be noted that, similar to the first contact via, the second and third contact vias are also electrical connection structures filled with conductive material, which can be polycrystalline silicon or metallic conductive material.

[0043] A power line located on the third metal layer and extending along the first direction is electrically connected to the first wiring through a third contact via, a second wiring, and a second contact via, allowing a voltage signal to be applied to the first wiring. The projection of the power line along the second direction lies within the projection range of the second wiring along the second direction; it is understood that the area of ​​the power line is not greater than the area of ​​the second wiring. It should be noted that the projection of the power line along the second direction falling within the projection range of the second wiring along the second direction also includes cases where the projections of the power line and the second wiring along the second direction overlap. Furthermore, it is understood that the second wiring at least includes a connecting portion extending along the first direction, i.e., the projection of the power line along the second direction lies within the projection range of the connecting portion extending along the first direction along the second direction. This increases the number of third contact vias between the power line and the second wiring, reduces the resistance between the power line and the second wiring, and improves the current-carrying capacity between the power line and the first wiring.

[0044] It is understandable that the extension direction of the power line intersects with the extension direction of the first wiring. In related technologies, contact vias are directly provided between the power line and the first wiring. However, the overlap area between the projection of the first wiring along the second direction (corresponding to the aforementioned longitudinal direction) and the projection of the power line along the second direction is limited. This affects the setting of contact vias between the first wiring and the power line, resulting in insufficient conductivity between the first wiring and the power line. This embodiment of the present disclosure introduces a second wiring located in the second metal layer between the first wiring located in the first metal layer and the power line located in the third metal layer. The projection of the power line along the second direction is located within the projection range of the second wiring along the second direction. This increases the number of contact vias between the second wiring and the power line, enhancing the overcurrent capability between the first wiring in the first metal layer and the power line in the third metal layer in the semiconductor standard cell structure. This is beneficial for the further development of semiconductor standard cell structures and semiconductor structures.

[0045] It should be noted that the quantity and specific location of the first wiring, second wiring, and power lines can be flexibly determined according to design requirements. Figure 1A This is just one example.

[0046] It should also be noted that the specific structure formed by the semiconductor standard cell structure 10 can be flexibly determined according to design requirements. For example, the semiconductor standard cell structure 10 may include inverters, OR gates, NOR gates, AND gates, NAND gates, XNOR gates, XOR gates, or antifuse cells.

[0047] In some embodiments, Figure 2A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure. Figure 2B This is a schematic diagram of a layered structure of a semiconductor standard cell structure provided in an embodiment of the present disclosure, such as... Figure 2A and Figure 2B As shown, the second wiring 24 includes a first connection portion 28 extending along a first direction, and the projections of the first connection portion 28 and the power line 26 along the second direction overlap.

[0048] Here, the first connecting portion extends along a first direction, and the power line extends along the first direction, meaning the first connecting portion and the power line extend in the same direction, i.e., the first connecting portion and the power line run parallel to each other along the first direction. The projections of the first connecting portion and the power line along the second direction overlap, meaning the projection of the first connecting portion along the second direction overlaps with the projection of the power line along the second direction, i.e., in the view along the second direction, the first connecting portion and the power line have the same shape. In some other embodiments, the projection of the power line along the second direction is located within the projection range of the first connecting portion along the second direction.

[0049] In this embodiment, the first connecting portion and the power line are routed in parallel, and the first connecting portion and the power line have the same shape. This allows for the provision of more third contact vias between the first connecting portion and the power line, reducing the resistance between the second wiring and the power line, increasing the conductivity between the second wiring and the power line, and thereby enhancing the current carrying capacity between the first wiring and the power line.

[0050] In some embodiments, a plurality of the third contact vias are arranged in an array. Here, each third contact via extends along the second direction and is arranged in an array in a plane perpendicular to the second direction. In some embodiments, the third contact vias completely fill the area between the power line and the second wiring, that is, the third contact vias are arranged in an array according to the minimum size specified in the design rules, filling the area between the power line and the second wiring. It is understood that filling the area with third contact vias can reduce the resistance of the contact vias and further increase the current carrying capacity between the second wiring and the power line.

[0051] In some embodiments, such as Figure 2A and Figure 2B As shown, the second wiring 24 includes a second connecting portion 29 extending in a third direction, and the second connecting portion 29 is connected to the first wiring 22 through the second contact through hole 25.

[0052] Here, the second wiring also includes a second connecting portion, which extends along a third direction. It is understood that the second connecting portion can extend along the positive direction of the third direction, or along the negative direction of the third direction, or simultaneously along both directions. In implementation, those skilled in the art can choose a suitable extension direction for the second connecting portion to maximize the overlap area between the projection of the second connecting portion along the second direction and the projection of the first wiring along the second direction. In some embodiments, the second connecting portion is disposed on both sides of the first connecting portion. It is understood that the second connecting portion being disposed on both sides of the first connecting portion corresponds to the second connecting portion extending simultaneously along both the positive and negative directions of the third direction.

[0053] The second connection extends along a third direction, and the first wiring (either the source or the drain) also extends along a third direction, meaning the second wiring and the first wiring (either the source or the drain) run parallel along the third direction. In some embodiments, in the first direction, the size of the second connection is not smaller than the size of the first wiring. That is, in the first direction, the projection of the first wiring along the third direction is within the projection range of the second connection along the third direction, so that more second contact vias can be provided between the first wiring and the second connection.

[0054] In this embodiment of the disclosure, the second wiring runs parallel to one of the source or drain terminals in the first wiring via a second connection portion extending in a third direction. This allows for the provision of more second contact vias between the second wiring and one of the source or drain terminals in the first wiring, reducing the resistance between the second wiring and the first wiring, increasing the conductivity between the second wiring and the first wiring, and thereby enhancing the current carrying capacity between the first wiring and the power line.

[0055] In some embodiments, a plurality of second contact vias between the second connection portion and the first wiring are arranged in an array. Here, each second contact via extends along a second direction and is arranged in an array in a plane perpendicular to the second direction. In some embodiments, the second contact vias completely fill the area between the source or drain of the first wiring and the second wiring. That is, the second contact vias can be arranged in an array according to the minimum size under the design rules, filling the area between the source or drain of the first wiring and the second wiring. The filled second contact vias can reduce the resistance of the contact vias, further increase the conductivity between the first wiring and the second wiring, and thus enhance the overcurrent capability between the first wiring and the power line.

[0056] In some embodiments, Figure 3A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure. Figure 3B This is a schematic diagram of a layered structure of a semiconductor standard cell structure provided in an embodiment of the present disclosure, such as... Figure 3A and Figure 3B As shown, the transistor 21 includes a first conductivity type transistor 311 and a second conductivity type transistor 312 spaced apart along a third direction; the first wiring 22 includes a first electrode line 321 and a second electrode line 322 spaced apart along the third direction; the power line 26 includes a first power line 331 and a second power line 332 spaced apart along the third direction; and the second wiring 24 includes a first metal connection structure 341 and a second metal connection structure 342 spaced apart along the third direction.

[0057] Here, the transistor includes a first conductivity type transistor and a second conductivity type transistor spaced apart along a third direction. The conductivity type transistor is determined based on the conductivity type of the source and drain regions of the active region in the transistor. For example, if the source and drain regions of the active region are P-type (mainly hole conduction) conductivity type, the formed field-effect transistor is a P-type field-effect transistor; if the source and drain regions of the active region are N-type (mainly electron conduction) conductivity type, the formed field-effect transistor is an N-type field-effect transistor. In some embodiments, the first conductivity type transistor is a P-type field-effect transistor, and the second conductivity type transistor is an N-type field-effect transistor. It should also be noted that the first conductivity type transistor and the second conductivity type transistor are spaced apart along a third direction, which can be a direction intersecting the first direction and parallel to the device layer. Furthermore, an insulating material is provided in the spacer region between the first conductivity type transistor and the second conductivity type transistor to prevent short circuits between the transistors.

[0058] The first wiring includes a first electrode line and a second electrode line spaced apart along a third direction. It is understood that the first electrode line is electrically connected to a first conductivity type transistor, and the second electrode line is electrically connected to a second conductivity type transistor. In some embodiments, the first electrode line is electrically connected to the first conductivity type transistor through a first contact via; the second electrode line is electrically connected to the second conductivity type transistor through a first contact via.

[0059] The second wiring includes a first metal connection structure and a second metal connection structure spaced apart along a third direction. It is understood that the first metal connection structure is electrically connected to the first electrode line, and the second metal connection structure is electrically connected to the second electrode line. In some embodiments, the first metal connection structure is electrically connected to the first electrode line through a second contact via, and the second metal connection structure is electrically connected to the second electrode line through a second contact via.

[0060] The power supply includes a first power supply line and a second power supply line spaced apart along a third direction. It is understood that both the first and second power supply lines extend along a first direction. The first power supply line is electrically connected to a first metal connection structure, and the second power supply line is electrically connected to a second metal connection structure. In some embodiments, the first power supply line is electrically connected to the first metal connection structure through a third contact through-hole, and the second power supply line is electrically connected to the second metal connection structure through a third contact through-hole. It should also be noted that the projection of the first power supply line along a second direction lies within the projection range of the first metal connection structure along the second direction, and the projection of the second power supply line along the second direction lies within the projection range of the second metal connection structure along the second direction.

[0061] In this embodiment, a semiconductor standard cell structure is formed by arranging transistors of different conductivity types at intervals. Since the projection of the first power line along the second direction falls within the projection range of the first metal connection structure along the second direction, the number of contact vias can be increased between the first power line and the first metal connection structure, thereby increasing the overcurrent capability between them in the semiconductor standard cell structure. Similarly, since the projection of the second power line along the second direction falls within the projection range of the second metal connection structure along the second direction, the number of contact vias can be increased between the second power line and the second metal connection structure, further increasing the overcurrent capability between them and improving the performance of the semiconductor standard cell structure.

[0062] In some embodiments, such as Figure 3A and Figure 3B As shown, the first metal connection structure 341 includes a first sub-connection portion 351 extending along the first direction and a second sub-connection portion 352 extending along the third direction, wherein the projection of the first power line 331 along the second direction is located within the projection range of the first sub-connection portion 351 along the second direction; and / or,

[0063] The second metal connection structure 342 includes a third sub-connection portion 353 extending along the first direction and a fourth sub-connection portion 354 extending along the third direction, wherein the projection of the second power line 332 along the second direction is located within the projection range of the third sub-connection portion 353 along the second direction.

[0064] Here, the first sub-connector extends along the first direction, and the first power line extends along the first direction, meaning the first sub-connector and the first power line run parallel to each other along the first direction. In some embodiments, the first sub-connector is electrically connected to the first power line through a third contact via. Furthermore, because the projection of the first power line along the second direction falls within the projection range of the first sub-connector along the second direction, more third contact vias can be provided between the first power line and the first sub-connector.

[0065] The second sub-connector extends along a third direction. It is understood that the second sub-connector is disposed on one or both sides of the first sub-connector. A suitable extension direction for the second sub-connector is selected to maximize the overlap area between the projection of the second sub-connector along the second direction and the projection of the first electrode line along the second direction. In some embodiments, the projection of the first electrode line along the third direction is within the projection range of the first metal connection structure along the third direction, thus allowing for more second contact vias to be provided between the first electrode line and the first metal connection structure.

[0066] The third sub-connector extends along the first direction, and the second power line also extends along the first direction, meaning the third sub-connector and the second power line run parallel to each other along the first direction. In some embodiments, the third sub-connector is electrically connected to the second power line through a third contact via. Furthermore, because the projection of the second power line along the second direction falls within the projection range of the third sub-connector along the second direction, more third contact vias can be provided between the second power line and the third sub-connector.

[0067] The fourth sub-connector extends along a third direction. It is understood that the fourth sub-connector is disposed on one or both sides of the third sub-connector. A suitable extension direction for the fourth sub-connector is selected to maximize the overlap area between the projection of the fourth sub-connector along the second direction and the projection of the second electrode line along the second direction. In some embodiments, the projection of the second electrode line along the third direction is within the projection range of the second metal connection structure along the third direction, thus allowing for more second contact vias to be provided between the second electrode line and the second metal connection structure.

[0068] In some embodiments, Figure 3C This is a schematic diagram of the layered structure of a semiconductor standard cell structure provided in an embodiment of the present disclosure, as shown below. Figure 3A , Figure 3B and 3C As shown, the device layer 11 includes a first sublayer 15 and a second sublayer 16 stacked sequentially along the first direction;

[0069] The first conductivity type transistor 311 includes a first active region 361 and a first gate structure 363; wherein, the first gate structure 363 extends along a third direction;

[0070] The second conductivity type transistor 312 includes a second active region 362 and a second gate structure 364; wherein, the second gate structure 364 extends along the third direction, and the first active region 361 and the second active region 362 are spaced apart along the third direction;

[0071] The first sub-layer 15, the second sub-layer 16, and the first metal layer 12 are stacked along the second direction. The second active region 362 and the first active region 361 are located in the first sub-layer 15, and the second gate structure 364 and the first gate structure 363 are located in the second sub-layer.

[0072] Here, the device layer includes a first sub-layer and a second sub-layer stacked along a first direction. In a standard semiconductor cell structure, the first sub-layer, the second sub-layer, the first metal layer, the second metal layer, and the third metal layer are stacked along a second direction. It can be understood that adjacent layers among the first sub-layer, the second sub-layer, and the first metal layer can be directly adjacent, or they can be indirectly adjacent by providing other metal layers.

[0073] The first sublayer includes a first active region and a second active region spaced apart along a third direction, and the second sublayer includes a first gate structure and a second gate structure spaced apart along a third direction. In some embodiments, the first gate structure includes a first gate and a first gate dielectric, the first gate dielectric covering the channel in the first active region and the first gate covering the first gate dielectric; the second gate includes a second gate and a second gate dielectric, the second gate dielectric covering the second active region and the second gate covering the second gate dielectric. Thus, the first active region and the first gate structure constitute a first conductivity type transistor, and the second active region and the second gate structure constitute a second conductivity type transistor.

[0074] It should be noted that Figure 3A , Figure 3B and Figure 3C The diagram illustrates multiple first gate structures 363 and multiple second gate structures 364. It should be understood that the specific number of first gate structures 363 and second gate structures 364 needs to be determined based on the device formed by the semiconductor standard cell structure 10. In some embodiments, when the semiconductor standard cell structure 10 is used to form an inverter, only one first gate structure 363 and one second gate structure 364 are needed. The first active region 361 and the first gate structure 363 are used to form a first conductivity type transistor, and the second active region 362 and the second gate structure 364 are used to form a second conductivity type transistor. Furthermore, the connection relationship between the first active region and the second active region varies depending on the device formed by the semiconductor standard cell structure 10 and needs to be determined based on the actual circuit logic.

[0075] In some embodiments, the first active region and the first gate structure form a P-type field-effect transistor, and the second active region and the second gate structure form an N-type field-effect transistor.

[0076] Here, the source and drain regions in the first active region are P-type semiconductors, meaning they are hole-conducting semiconductors. The P-type semiconductor can be formed by doping the substrate with a trivalent element (e.g., boron). Since the source and drain regions in the first active region are P-type semiconductors, the first active region and the first gate structure form a P-type field-effect transistor.

[0077] The source and drain regions in the second active region are N-type semiconductors, meaning they are electronically conductive semiconductors. An N-type semiconductor can be formed by doping the substrate with a pentavalent element (e.g., phosphorus). Since the source and drain regions in the second active region are N-type semiconductors, the second active region and the second gate structure form an N-type field-effect transistor.

[0078] In some embodiments, such as Figure 3A , Figure 3B and Figure 3C As shown, the first wiring 22 further includes a metal interconnect structure 37, which is used to electrically connect one pole of the transistor 21 that is not connected to an electrode line (for example, one pole of the first conductivity type transistor 311 that is not connected to the first electrode line 321, or one pole of the second conductivity type transistor 312 that is not connected to the second electrode line 322). The projection of the metal interconnect structure 37 along the second direction is located between the projection of the first active region 361 along the second direction and the projection of the second active region 362 along the second direction.

[0079] Here, the metal interconnect structure is used to electrically connect the gate structure of the transistor, i.e., to input a voltage signal to the transistor; the metal interconnect structure is also used to electrically connect one pole of the transistor that is not connected to the electrode line. It can be understood that the metal interconnect structure is used to connect one pole of the first conductivity type transistor that is not connected to the first electrode line and one pole of the second conductivity type transistor that is not connected to the second electrode line. In some embodiments, the source region of the first conductivity type transistor is connected to the first electrode line (source electrode), the source region of the second conductivity type transistor is connected to the second electrode line (source electrode), and the drain region of the first conductivity type transistor is connected to the metal interconnect structure, and the drain region of the second conductivity type transistor is connected to the metal interconnect structure.

[0080] In some embodiments, such as Figure 3A , Figure 3B and Figure 3C As shown, the semiconductor standard cell structure further includes at least one input terminal (not shown in the figure) and at least one output terminal (not shown in the figure);

[0081] The metal interconnect structure includes a first target metal line 371 electrically connected to at least one of the input terminals and a second target metal line 372 electrically connected to at least one of the output terminals.

[0082] Here, the semiconductor standard cell structure also includes an input terminal and an output terminal, which can be located on a third metal layer or other metal layers. In some embodiments, the input terminal and / or the output terminal is located on a fourth metal layer, and the first metal layer, second metal layer, third metal layer, and fourth metal layer are stacked sequentially along a second direction.

[0083] The metal interconnect structure includes a first target metal line and a second target metal line. The first target metal line is electrically connected to at least one input terminal. It is understood that each input terminal applies an input voltage signal to the gate of a transistor via the electrically connected first target metal line. The second target metal line is connected to at least one output terminal. It is understood that each output terminal outputs an electrical signal from one of the transistors without connected electrode lines via the electrically connected second target metal line. In some embodiments, the electrode line representing the source is electrically connected to the source region of the transistor, the first target metal line is electrically connected to the gate of the transistor, and the second target metal line is the electrode line representing the drain and is electrically connected to the drain region of the transistor. Thus, the power supply line applies a voltage V to the electrode line representing the source. dd (Transistor operating voltage) The first target metal line applies an input voltage to the gate, and the second target metal line outputs an electrical signal through the electrode line characterizing the drain, thereby achieving control of the transistor. It should also be noted that in some embodiments, the first target metal line is connected to the gate of the transistor through a first contact via.

[0084] In some embodiments, Figure 4A This is a top view schematic diagram of a semiconductor standard cell structure provided in an embodiment of the present disclosure. Figure 4B This is a schematic diagram of a layered structure of a semiconductor standard cell structure provided in an embodiment of the present disclosure, such as... Figure 4A and Figure 4B The standard unit further includes an N-type first well contact 381 and a P-type second well contact 382. The first well contact 381 is located on the side of the first active region 361 away from the second active region 362, and the second well contact 382 is located on the side of the second active region 362 away from the first active region 31. The first well contact 381 and the second well contact 382 are located in the first sublayer 16.

[0085] Here, the first well contact is an N-type semiconductor and is located on the side of the first active region away from the second active region, which can prevent holes in the source and drain regions of the P-type field-effect transistor from flowing into the substrate. The second well contact is a P-type semiconductor and is located on the side of the second active region away from the first active region, which can prevent electrons in the source and drain regions of the N-type field-effect transistor from flowing into the substrate.

[0086] Figure 5 for Figure 3A The equivalent circuit diagram of the corresponding standard semiconductor cell structure, such as Figure 5 , Figure 3A , Figure 3B and Figure 3CAs shown, A is an input terminal, connected to the first target metal line 371, and electrically connected to the first gate structure PG1 in the first conductivity type transistor (e.g., MP0) through the first target metal line 371; B is another input terminal, connected to another first target metal line 371, and electrically connected to the second gate structure PG2 in the second conductivity type transistor (e.g., MN0) through the other first target metal line 371; power supply line M11 (corresponding to the aforementioned first power supply line) is electrically connected to the source S1 (corresponding to the aforementioned first electrode line) in the first conductivity type transistor, providing V to S1. dd Voltage; Z is the output terminal, connected to the second target metal line 372, and electrically connected to the drain D1 of the transistor through the second target metal line 372. Thus, an electrical signal is input from input terminal A and / or input terminal B to control the transistor, and an electrical signal is output from output terminal Z.

[0087] In another embodiment of this disclosure, see Figure 6 This illustrates a schematic diagram of a semiconductor structure 40 provided in an embodiment of the present disclosure. For example... Figure 6 As shown, the semiconductor structure 40 includes the aforementioned semiconductor standard cell structure 10.

[0088] It should be noted that, when the semiconductor standard cell structure 10 is used as a layout template, the semiconductor structure 40 can be understood as follows: based on the circuit function, the designer uses the semiconductor standard cell structure 10 as a basis to combine and connect components to obtain the circuit layout.

[0089] Therefore, the semiconductor structure 40 includes at least: a plurality of transistors located in a device layer; a first wiring located in a first metal layer; the first wiring being connected to the plurality of transistors via a first contact via; a second wiring located in a second metal layer, the second wiring being connected to the first wiring via a second contact via; and a power line located in a third metal layer and extending along a first direction; wherein the device layer, the first metal layer, the second metal layer, and the third metal layer are stacked sequentially along a second direction; the projection of the power line along the second direction is located within the projection range of the second wiring along the second direction; and the second wiring is connected to the power line via a third contact via.

[0090] It should be understood that the contents of the above semiconductor standard cell structure 10 are all options provided to designers. Designers need to make adjustments according to the actual situation and only retain the necessary structures.

[0091] This disclosure provides a semiconductor structure in which a second wiring located on a second metal layer is introduced between a first wiring located on a first metal layer and a power line located on a third metal layer, and the projection of the power line along a second direction is located within the projection range of the second wiring along the second direction. This increases the number of contact vias between the second wiring and the power line, enhances the overcurrent capability between the first and second metal layers in the standard semiconductor cell structure, and is beneficial to the further development of semiconductor structures.

[0092] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 7 This illustrates a schematic diagram of the structure of a memory 50 provided in an embodiment of this disclosure. For example... Figure 7 As shown, the memory 50 includes at least the aforementioned semiconductor structure 40.

[0093] It should be noted that the memory 50 can be a Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate DRAM (DDR), Low Power DDR, etc. For the memory 50, by introducing a second wiring located on the second metal layer between the first wiring on the first metal layer and the power line on the third metal layer, and ensuring that the projection of the power line along the second direction falls within the projection range of the second wiring along the second direction, the number of contact vias between the second wiring and the power line can be increased. This enhances the overcurrent capability between the first and second metal layers in the standard semiconductor cell structure, which is beneficial for the further development of memory.

[0094] In a scenario where the device formed by the semiconductor standard cell structure 10 is applied to DRAM, since conventional DRAM adopts a 1T1C memory structure, the chip sequentially includes a transistor layer, MO, a capacitor dielectric layer, M1, etc., along a third direction. In one embodiment, the aforementioned device layer refers to the transistor layer, the first metal layer is MO, and the third metal layer is M1. In particular, the layer MOU where the second wiring is located shares the same space along the third direction with the capacitor dielectric layer. That is, for locations where a capacitor needs to be formed, a capacitor dielectric layer is formed between the first metal layer and the third metal layer; for locations where a capacitor does not need to be formed, a second metal layer MOU is formed between the first metal layer and the third metal layer.

[0095] Please see Figure 8 This illustrates a partial structural diagram of a DRAM chip. (For example...) Figure 8As shown, the DRAM chip includes at least: an active region, a gate structure PG, a contact via PC1 / 2 (corresponding to the first contact via), M0 (corresponding to the first wiring), a contact via PCU (corresponding to the second contact via), M0U (corresponding to the second wiring), a contact via CT (corresponding to the third contact via), and M1 (corresponding to the power line), and the active region, gate structure PG, contact via PC1 / 2, M0, contact via PCU, M0U, contact via CT, and M1 are arranged along a second direction.

[0096] At this time, the following structures may exist at different locations in the chip: (1) The active region is connected to M0 through contact via PC1 / 2, M0 is connected to M0U through contact via PCU, and M0U is connected to M1 through contact via CT; (2) The active region is covered by a gate structure PG, the gate structure PG is connected to M0 through contact via PC1 / 2, M0 is connected to M0U through contact via PCU, and M0U is connected to M1 through contact via CT; (3) The active region is connected to M0 through contact via PC1 / 2, and there is a capacitor dielectric layer between M0 and M1; (4) The active region is covered by a gate structure PG, the gate structure PG is connected to M0 through contact via PC1 / 2, and there is a capacitor dielectric layer between M0 and M1. The above situations are only examples and not exhaustive.

[0097] As can be seen from the above, in some embodiments, the semiconductor standard cell structure 10 is applied to a semiconductor structure, and the semiconductor structure includes a capacitor dielectric layer; the highest point of the first contact via along a third direction is lower than the lowest point of the capacitor dielectric layer along a third direction; the lowest point of the second contact via along a third direction is higher than the lowest point of the capacitor dielectric layer along a third direction, and the highest point of the second contact via along a third direction is lower than the highest point of the capacitor dielectric layer along a third direction; the lowest point of the third contact via along a third direction is higher than the highest point of the capacitor dielectric layer along a third direction. Thus, in the second direction, the height of the second contact via falls within the height range of the capacitor dielectric layer, meaning the second contact via is formed in the originally unused space, improving the structural density and space utilization of the memory. Furthermore, since DRAM chips require many M0 layer traces, one M0 layer would result in an excessively large layout area, failing to meet usage requirements. The Dual Metal provided in this disclosure can solve this problem.

[0098] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0099] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A standard semiconductor cell structure, characterized in that, include: Multiple transistors located in the device layer; The first wiring located in the first metal layer; The first wiring is connected to the plurality of transistors through a first contact via; A second wiring located in the second metal layer, the second wiring being connected to the first wiring through a second contact via; as well as, A power line located in the third metal layer and extending along the first direction; The device layer, the first metal layer, the second metal layer, and the third metal layer are stacked sequentially along a second direction; the projection of the power line along the second direction is located within the projection range of the second wiring along the second direction; the second wiring is connected to the power line through a third contact via. The second wiring includes a first connection portion extending along a first direction, and the projection of the first connection portion and the power line along the second direction overlaps. The second wiring includes a second connecting portion extending in a third direction, and the second connecting portion is connected to the first wiring through the second contact through hole; The second connecting part is disposed on both sides of the first connecting part.

2. The semiconductor standard cell structure according to claim 1, characterized in that, The plurality of the third contact vias are arranged in an array; and / or The second contact holes between the second connection portion and the first wiring are arranged in an array.

3. The semiconductor standard cell structure according to claim 1 or 2, characterized in that, The transistor includes a first conductivity type transistor and a second conductivity type transistor spaced apart along a third direction. The first wiring includes a first electrode line and a second electrode line spaced apart along the third direction. The power line includes a first power line and a second power line spaced apart along the third direction. The second wiring includes a first metal connection structure and a second metal connection structure spaced apart along the third direction.

4. The semiconductor standard cell structure according to claim 3, characterized in that, The first metal connection structure includes a first sub-connection portion extending along the first direction and a second sub-connection portion extending along the third direction, wherein the projection of the first power line along the second direction is located within the projection range of the first sub-connection portion along the second direction; and / or, The second metal connection structure includes a third sub-connection portion extending along the first direction and a fourth sub-connection portion extending along the third direction, wherein the projection of the second power line along the second direction is located within the projection range of the third sub-connection portion along the second direction.

5. The semiconductor standard cell structure according to claim 3, characterized in that, The device layer includes a first sub-layer and a second sub-layer stacked sequentially along the first direction; The first conductivity type transistor includes a first active region and a first gate structure; wherein the first gate structure extends along a third direction; The second conductivity type transistor includes a second active region and a second gate structure; wherein the second gate structure extends along the third direction, and the first active region and the second active region are spaced apart along the third direction; The first sub-layer, the second sub-layer, and the first metal layer are stacked along the second direction, the second active region and the first active region are located in the first sub-layer, and the second gate structure and the first gate structure are located in the second sub-layer.

6. The semiconductor standard cell structure according to claim 5, characterized in that, The first wiring further includes a metal interconnect structure for electrically connecting one pole of the transistor that is not connected to the electrode line, and the projection of the metal interconnect structure along the second direction is located between the projection of the first active region along the second direction and the projection of the second active region along the second direction.

7. The semiconductor standard cell structure according to claim 6, characterized in that, The semiconductor standard cell structure also includes at least one input terminal and at least one output terminal; The metal interconnect structure includes a first target metal line electrically connected to at least one of the input terminals and a second target metal line electrically connected to at least one of the output terminals.

8. The semiconductor standard cell structure according to claim 5, characterized in that, The first active region and the first gate structure form a P-type field-effect transistor, and the second active region and the second gate structure form an N-type field-effect transistor.

9. The semiconductor standard cell structure according to claim 8, characterized in that, The standard cell further includes an N-type first well contact and a P-type second well contact. The first well contact is located on the side of the first active region away from the second active region, and the second well contact is located on the side of the second active region away from the first active region. The first well contact and the second well contact are located in the first sublayer.

10. The semiconductor standard cell structure according to claim 9, characterized in that, The standard unit includes at least one of the following devices: inverter, OR gate, NOR gate, AND gate, NAND gate, XNOR gate, XOR gate, and antifuse unit.

11. A semiconductor structure, characterized in that, The semiconductor structure includes the standard cell as described in any one of claims 1-10.

12. A memory, characterized in that, The memory includes the semiconductor structure as described in claim 11.

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