A BURST control circuit based on forced continuous mode DC-DC

Abstract

The present invention discloses a BURST control circuit based on a forced continuous mode DC-DC, comprising a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN. The present invention adds a BURST mode under the premise of FCCM. When the load is light, the DC-DC can skip cycles to effectively reduce the number of switches. The skip cycle frequency is proportional to the load current, and the reverse current in each switching cycle can be avoided, thereby greatly improving the light load efficiency.

Description

Technical Field

[0001] The invention relates to a BURST control circuit, in particular to a BURST control circuit based on a forced continuous mode DC-DC, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] As electronic products are used more and more widely and their usage scenarios become more complex, the requirements for switching power supply chips are increasing; especially mobile phone chips, which need to achieve multiple functional indicators in the smallest possible size. For AMOLED screen driver chips, in order to avoid the "water ripples" on the screen, the output voltage ripple should be as small as possible, and the switching frequency cannot overlap with the screen refresh frequency. Therefore, the DC-DC modulation mode is limited to fixed-frequency PWM control. And due to the wide input range, the positive voltage output Boost has a 100% duty cycle, and the zero-crossing detection module (Zero Current Detection, ZCD) cannot be used. When the load is light, it can only be forced continuous conduction mode (FCCM). Figure 1 The figure shows the valley current PWM control loop of a typical FCCM. Currently, mainstream mobile phone chip suppliers all use this architecture. Therefore, there is a switching action in each clock cycle of the positive voltage output Boost, and reverse current occurs, such as Figure 7 As shown. In order to meet the requirements of high-brightness display, the chip needs to output high-power current, and the size of the DC-DC power tube cannot be too small. Therefore, limited by the parasitic capacitance of the power tube such as Cgs and Cgd, the switching loss in each switching cycle is large. In summary, the chip using FCCM control can never achieve high efficiency under extremely light loads, which in turn makes it impossible for AMOLED to achieve functions such as ultra-low power consumption off-screen display time.

[0003] Reference 1 [V. Kadlimatti, P. Thota and S. Bhat, "A Novel Methodology of PWM / PFM Mode Transition for Inverting Buck-Boost and Boost Converter for AMOLED Display Applications," 2020 33rd International Conference on VLSIDesign and 2020 19th International Conference on Embedded Systems (VLSID), Bangalore, India, 2020, pp. 165-170, doi: 10.1109 / VLSID49098.2020.00046] uses PWM-DCM / PFM mode switching to improve efficiency, but sacrifices the application of a wide input range, and the PFM switching period is inversely proportional to the load, there is a risk of overlapping with the screen refresh frequency, and the output ripple becomes larger.

[0004] Reference 2 [S. -W. Hong, S. -H. Park, T. -H. Kong and G. -H. Cho, "Inverting Buck-Boost DC-DC Converter for Mobile AMOLED Display Using Real-Time Self-Tuned Minimum Power-Loss Tracking (MPLT) Scheme With Lossless Soft-Switching for Discontinuous Conduction Mode," in IEEE Journal of Solid-StateCircuits, vol. 50, no. 10, pp. 2380-2393, Oct. 2015, doi: 10.1109 / JSSC.2015.2450713] optimized the power consumption of the DC-DC drive circuit to improve the full-load efficiency, but the effect was limited and it could not fundamentally solve the switching loss problem under extremely light loads.

[0005] In summary, due to the many application requirements of AMOLED screen driver chips, its positive voltage output Boost does not have a zero-crossing detection mode (ZCD), and the chip cannot enter the DCM mode. When the chip is working under light load, the Boost inductor current has a reverse flow phenomenon, and there will be a switching action in each clock cycle. This will greatly reduce the light load efficiency of the AMOLED screen driver chip. And due to the ripple limit of the mobile phone chip, the chip cannot use the common COT PFM modulation. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a BURST control circuit based on forced continuous mode DC-DC, which improves light load efficiency and avoids the problem of too large current unit deviation in BURST mode due to slope compensation current under different duty cycles.

[0007] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0008] A BURST control circuit based on a forced continuous mode DC-DC comprises a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN, wherein the inverting input of the error amplifier EA is connected to the output signal FB of the voltage-dividing feedback circuit of the DC-DC converter, the non-inverting input of the error amplifier EA is connected to the reference voltage signal VREF, the output of the error amplifier EA is connected to the non-inverting input of the PWM comparator CMP1 and the inverting input of the BURST comparator CMP2, the input of the current sampling circuit CURRENT SENSE is connected to the source of a power tube M2 in the DC-DC converter, the output of the current sampling circuit CURRENT SENSE outputs a voltage signal CS, the voltage signal CS is added with a slope compensation voltage SLOPE and connected to the inverting input of the PWM comparator CMP1, the output of the PWM comparator CMP1 is connected to the modulator PWM The output end of the BURST comparator CMP2 is connected to the third input end of the modulator PWM MODULE, and the second input end of the modulator PWM MODULE is connected to the clock signal CLK.

[0009] Further, the DC-DC converter includes a power supply V0, an inductor L, a power tube M11, a power tube M12, a capacitor C and a voltage divider feedback circuit, the positive electrode of the power supply V0 is connected to one end of the inductor L, the other end of the inductor L and the drain of the power tube M11 and the drain of the power tube M12 are connected to the switch node SW, the gate of the power tube M11 and the gate of the power tube M12 are connected to the output end of the modulator PWMMODULE, the source of the power tube M12 is connected to the input end of the current sampling circuit CURRENT SENSE, one end of the capacitor C and one end of the voltage divider feedback circuit, and the negative electrode of the power supply V0, the source of the power tube M11, the other end of the capacitor C and the other end of the voltage divider feedback circuit are grounded.

[0010] Furthermore, the voltage divider feedback circuit includes a resistor R11 and a resistor R12, one end of the resistor R11 is connected to the source of the power tube M12, the input end of the current sampling circuit CURRENT SENSE and one end of the capacitor C at the output node OUT, the other end of the resistor R11 is connected to one end of the resistor R12 and generates an output signal FB, and the other end of the resistor R12 is grounded.

[0011] Furthermore, the output terminal of the error amplifier EA generates an output signal EAO, the output terminal of the BURST_VREF generator BURST_VREF_GEN generates an output voltage BURST_VREF, and the output terminal of the BURST comparator CMP2 generates an output voltage IN_BURST.

[0012] Furthermore, the BURST_VREF generator includes a sample-and-hold module SENSE_HOLD, a matching resistor R2 and a bias current source I B2 , the input slope compensation current I of the sampling and holding module SENSE_HOLD input terminal SLOPE The sampling and holding module SENSE_HOLD samples and holds the maximum current value I of the slope compensation of the previous cycle SLOPE_MAX The output end of the sampling and holding module SENSE_HOLD is connected to one end of the matching resistor R2 and the bias current source I B2 The output end of is connected and serves as the output end of the BURST_VREF generator, and the other end of the matching resistor R2 is grounded.

[0013] Furthermore, the input end of the sampling and holding module SENSE_HOLD is connected to one end of the resistor R1, the output end of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE, and the bias current source I B1 The output terminal is connected.

[0014] Furthermore, the resistance values ​​of the matching resistor R2 and the resistor R1 are equal, and the bias current source I B2and bias current source I B1 The currents are equal.

[0015] Furthermore, the sampling and holding module SENSE_HOLD includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a resistor R3, a resistor R4, an operational amplifier OP1, an operational amplifier OP2, an operational amplifier OP3, a switch S1, a switch S2, a holding capacitor C HOLD1 and C HOLD2 , the drain of transistor M1 is connected to the gate of transistor M1, the gate of transistor M2 and the gate of transistor M3 and inputs the source SLOPE CURRENT SOURCE of the slope compensation current, the drain of transistor M2 is connected to the drain of transistor M4, the gate of transistor M4 and the gate of transistor M5, the drain of transistor M3 outputs the slope compensation current SLOPE CURRENT, the source of transistor M4 is connected to the source of transistor M5, the source of transistor M6 and the source of transistor M7, the drain of transistor M5 is connected to one end of resistor R3 and the non-inverting input end of operational amplifier OP1, the output end of operational amplifier OP1 is connected to the inverting input end of operational amplifier OP1 and one end of switch S1, the other end of switch S1 is connected to the non-inverting input end of operational amplifier OP2 and holding capacitor C HOLD1 The output end of the operational amplifier OP2 is connected to the inverting input end of the operational amplifier OP2 and one end of the switch S2, and the other end of the switch S2 is connected to the same-direction input end of the operational amplifier OP3 and the holding capacitor C HOLD2 The output end of the operational amplifier OP3 is connected to the inverting input end of the operational amplifier OP3, one end of the resistor R4, the drain of the transistor M6, the gate of the transistor M6 and the gate of the transistor M7, the drain of the transistor M7 outputs the maximum value SLOPE CURRENT MAX of the slope compensation current, the source of the transistor M1, the source of the transistor M2, the source of the transistor M3, the other end of the resistor R3, the holding capacitor C HOLD1 The other end of the capacitor C HOLD2 The other end of the resistor R4 and the other end of the resistor R4 are grounded.

[0016] Further, the modulator PWM MODULE includes a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4, a first input end of the NOR gate NOR1 is connected to the output end of the comparator CMP1, a second input end of the NOR gate NOR1 is connected to the output end of the NOR gate NOR2, an output end of the NOR gate NOR1 is connected to a first input end of the NOR gate NOR2 and a first input end of the NOR gate NOR3, a second input end of the NOR gate NOR2 is connected to a clock signal CLK, a second input end of the NOR gate NOR3 and a second input end of the NOR gate NOR4 are connected to an output voltage IN_BURST, an output end of the NOR gate NOR3 is connected to a first input end of the NOR gate NOR4 and generates a signal M2_ON, and an output end of the NOR gate NOR4 generates a signal M1_ON.

[0017] Compared with the prior art, the present invention has the following advantages and effects: the present invention adds the BURST mode under the premise of FCCM, and the DC-DC can skip cycles when the load is light, effectively reducing the number of switches, the skip frequency is proportional to the load current, and the reverse current in each switching cycle can be avoided, thereby greatly improving the light load efficiency. In addition, the present invention also introduces adaptive elimination of the influence of slope compensation, which can avoid the problem that the current gear deviation of entering the BURST mode is too large or even the BURST mode cannot be entered due to the slope compensation current under different duty cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a BURST control circuit based on a forced continuous mode DC-DC of the present invention.

[0019] Figure 2 is a circuit diagram of a BURST_VREF generator of the present invention.

[0020] Figure 3 It is a schematic diagram of the BURST control waveform of the BURST control circuit based on the forced continuous mode DC-DC of the present invention.

[0021] Figure 4 It is a circuit diagram of the sample and hold module SENSE_HOLD of the present invention.

[0022] Figure 5 It is a circuit diagram of the modulator PWM MODULE of the present invention.

[0023] Figure 6 It is a waveform diagram of the sampling and holding module SENSE_HOLD of the present invention.

[0024] Figure 7 It is a schematic diagram of a valley current PWM control loop of a forced continuous mode in the prior art.

[0025] Figure 8 It is a schematic diagram of the valley current PWM control waveform of the forced continuous mode in the prior art. DETAILED DESCRIPTION

[0026] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0027] like Figure 1 As shown, a BURST control circuit based on a forced continuous mode DC-DC of the present invention comprises a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN, wherein the inverting input terminal of the error amplifier EA is connected to the output signal FB of the voltage-dividing feedback circuit of the DC-DC converter, the non-inverting input terminal of the error amplifier EA is connected to the reference voltage signal VREF, the output terminal of the error amplifier EA is connected to the non-inverting input terminal of the PWM comparator CMP1 and the inverting input terminal of the BURST comparator CMP2, the input terminal of the current sampling circuit CURRENT SENSE is connected to the source of the power tube M2 in the DC-DC converter, the output terminal of the current sampling circuit CURRENT SENSE outputs a voltage signal CS, the voltage signal CS is added with a slope compensation voltage SLOPE and connected to the inverting input terminal of the PWM comparator CMP1, the output terminal of the PWM comparator CMP1 is connected to the modulator PWM The output end of the BURST comparator CMP2 is connected to the third input end of the modulator PWM MODULE, and the second input end of the modulator PWM MODULE is connected to the clock signal CLK.

[0028] The DC-DC converter includes a power supply V0, an inductor L, a power tube M11, a power tube M12, a capacitor C and a voltage-dividing feedback circuit, wherein the positive electrode of the power supply V0 is connected to one end of the inductor L, the other end of the inductor L is connected to the drain of the power tube M11 and the drain of the power tube M12 at the switch node SW, the gate of the power tube M11 and the gate of the power tube M12 are connected to the output end of the modulator PWM MODULE, the source of the power tube M12 is connected to the input end of the current sampling circuit CURRENT SENSE, one end of the capacitor C and one end of the voltage-dividing feedback circuit, and the negative electrode of the power supply V0, the source of the power tube M11, the other end of the capacitor C and the other end of the voltage-dividing feedback circuit are grounded. This embodiment provides a circuit structure of a DC-DC converter with a Boost structure, and the technical solution of the present invention is also applicable to other DC-DC switching power supply structures.

[0029] The control signal output from the output end of the modulator PWM MODULE controls the gates of the power tubes M11 and M12 at the same time, so that the power tubes M11 and M12 are switched on alternately or both are turned off. When the voltage of the output voltage IN_BURST is at a low level, the output of the modulator PWM MODULE is controlled by the output signal of the PWM comparator CMP1, and the output periodic PWM signal controls the gate drive of the power tubes M11 and M12; when the voltage of the output voltage IN_BURST is at a high level, the output of the modulator PWM MODULE is shielded by the output voltage IN_BURST, and the output signal controls the power tubes M11 and M12 to be turned off.

[0030] The voltage divider feedback circuit includes a resistor R11 and a resistor R12. One end of the resistor R11 is connected to the source of the power tube M12, the input end of the current sampling circuit CURRENT SENSE and one end of the capacitor C at the output node OUT. The other end of the resistor R11 is connected to one end of the resistor R12 to generate an output signal FB. The other end of the resistor R12 is grounded.

[0031] The output terminal of the error amplifier EA generates an output signal EAO.

[0032] The output terminal of the BURST_VREF generator BURST_VREF_GEN generates an output voltage BURST_VREF.

[0033] The output terminal of the BURST comparator CMP2 generates an output voltage IN_BURST. When the voltage of the output signal EAO is lower than the output voltage BURST_VREF, the voltage of the output voltage IN_BURST is output as a high level.

[0034] The BURST_VREF generator includes the sample-and-hold module SENSE_HOLD, matching resistor R2 and bias current source I B2, the input slope compensation current I of the sampling and holding module SENSE_HOLD input terminal SLOPE The sampling and holding module SENSE_HOLD samples and holds the maximum current value I of the slope compensation of the previous cycle SLOPE_MAX The output end of the sampling and holding module SENSE_HOLD is connected to one end of the matching resistor R2 and the bias current source I B2 The output end of is connected as the output end of the BURST_VREF generator, and the other end of the matching resistor R2 is grounded. SLOPE_MAX Flowing out from the positive end of the matching resistor R2, the bias current I B2 Flows into the positive terminal of the matching resistor R2, and the corresponding output voltage BURST_VREF is R2*(I B2 -I SLOPE_MAX ).

[0035] The input end of the sampling and holding module SENSE_HOLD and one end of the resistor R1, the output end of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE, and the bias current source I B1 CURRENT MIRROR is the main circuit of the current sampling circuit CURRENT SENSE, which can proportionally measure the current of the radial power tube M2. The current I flowing out of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE is CS Superimposed Bias Store Building I B1 Subtract the slope compensation current I SLOPE It is the total current flowing through the sampling resistor R1. The output voltage CS with Slope on the sampling resistor R1 is R1*(I CS +I B1 -I SLOPE ).

[0036] The resistance of matching resistor R2 is equal to that of resistor R1, and the bias current source I B2 and bias current source I B1 The currents are equal.

[0037] The BURST_VREF voltage always follows the slope compensation of the previous cycle. The average value of the EAO voltage is approximately equal to the lowest point of the CS withSlope voltage.

[0038] EAO≈(CS with Slope) min = R1*(I CS +I B1 -I SLOPE_MAX )

[0039] The BURST_VREF_GEN matching resistor R2 can be designed to be equal to R1, and the bias current I B2 Equal to I B1 , the BURST_VREF value will be

[0040] BURST_VREF = R1*(I B1 -I SLOPE_MAX )

[0041] This means that when EAO approaches BURST_VREF, I CS is approximately 0, that is, the inductor current is 0mA at this time, thus preventing the DC-DC from entering the reverse current state. SLOPE_MAX The values ​​are different, and the above design can effectively eliminate the impact of slope compensation.

[0042] The sampling and holding module SENSE_HOLD includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a resistor R3, a resistor R4, an operational amplifier OP1, an operational amplifier OP2, an operational amplifier OP3, a switch S1, a switch S2, and a holding capacitor C HOLD1 and C HOLD2 , the drain of transistor M1 is connected to the gate of transistor M1, the gate of transistor M2 and the gate of transistor M3 and inputs the source of slope compensation current SLOPE CURRENT SOURCE, the drain of transistor M2 is connected to the drain of transistor M4, the gate of transistor M4 and the gate of transistor M5, the drain of transistor M3 outputs the slope compensation current SLOPE CURRENT, the source of transistor M4 is connected to the source of transistor M5, the source of transistor M6 and the source of transistor M7, the drain of transistor M5 is connected to one end of resistor R3 and the same-direction input end of operational amplifier OP1, the output end of operational amplifier OP1 is connected to the inverting input end of operational amplifier OP1 and one end of switch S1, the other end of switch S1 is connected to the same-direction input end of operational amplifier OP2 and holding capacitor C HOLD1 The output end of the operational amplifier OP2 is connected to the inverting input end of the operational amplifier OP2 and one end of the switch S2, and the other end of the switch S2 is connected to the same-direction input end of the operational amplifier OP3 and the holding capacitor C HOLD2 The output end of the operational amplifier OP3 is connected to the inverting input end of the operational amplifier OP3, one end of the resistor R4, the drain of the transistor M6, the gate of the transistor M6 and the gate of the transistor M7, the drain of the transistor M7 outputs the maximum value SLOPE CURRENT MAX of the slope compensation current, the source of the transistor M1, the source of the transistor M2, the source of the transistor M3, the other end of the resistor R3, the holding capacitor CHOLD1 The other end of the capacitor C HOLD2 The other end of the resistor R4 and the other end of the resistor R4 are grounded.

[0043] Transistor M1, transistor M2 and transistor M3 form a 1:1:1 current mirror, transistor M4 and transistor M5 form a 1:1 current mirror, and the voltage of node V1 is proportional to the slope compensation current:

[0044] V1=I SLOPE *R3.

[0045] The unity gain negative feedback amplifier formed by operational amplifier OP1 outputs a voltage equal to node V1. In the ramp current rising stage, switch S1 is closed, and operational amplifier OP1 supplies a voltage to holding capacitor C HOLD1 The charging makes the node V2 approximately equal to the voltage of the node V1; before the ramp current drops, the switch S1 is disconnected to keep the capacitor C HOLD1 Maintain the current maximum voltage:

[0046] V2_MAX=V1_MAX=I SLOPE _MAX*R3.

[0047] The unit gain negative feedback amplifier formed by the operational amplifier OP2 outputs a voltage equal to the node V2. When the node V2 maintains the current maximum voltage, the switch S2 is closed, and the operational amplifier OP2 supplies the holding capacitor C HOLD2 The charging makes the voltage of node V3 approximately equal to that of node V2. At the moment before node V2 enters the charging state, switch S2 is disconnected to keep capacitor C HOLD2 Maintain the current voltage, so node V3 maintains each cycle:

[0048] V3= V2_MAX=I SLOPE _MAX*R3.

[0049] The unity gain negative feedback amplifier formed by operational amplifier OP3 outputs a voltage equal to node V3, so the voltage on resistor R4 is V3. Transistors M6 and M7 form a 1:1 current mirror, and the output current is I SLOPE _MAX*R3 / R4; if R3 and R4 have the same value, the output current is I SLOPE _MAX. The above process is as follows Figure 6 shown.

[0050] like Figure 5As shown, the modulator PWM MODULE includes a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4, the first input end of the NOR gate NOR1 is connected to the output end of the comparator CMP1, the second input end of the NOR gate NOR1 is connected to the output end of the NOR gate NOR2, the output end of the NOR gate NOR1 is connected to the first input end of the NOR gate NOR2 and the first input end of the NOR gate NOR3, the second input end of the NOR gate NOR2 is connected to the clock signal CLK, the second input end of the NOR gate NOR3 and the second input end of the NOR gate NOR4 are connected to the output voltage IN_BURST, the output end of the NOR gate NOR3 is connected to the first input end of the NOR gate NOR4 and generates a signal M2_ON, and the output end of the NOR gate NOR4 generates a signal M1_ON. When the output voltage IN_BURST is 1, the signal M1_ON and the signal M2_ON are both 0, that is, the output signal controls the power tubes M11 and M12 to be turned off.

[0051] The present invention solves the problem of low light load efficiency caused by the positive voltage output Boost of the AMOLED driver chip working in a forced continuous mode, the reverse flow phenomenon under light load and the switching action in each clock cycle. Figure 8 The waveform diagram corresponding to the traditional solution is shown. Each switching cycle will cause switching loss, and the reverse flow of the inductor current will also cause additional loss.

[0052] The present invention adds the BURST mode under the premise of forced continuous mode. When the load is light, the DC-DC can skip cycles to effectively reduce the number of switches. The skip frequency is proportional to the load current and can avoid the situation where the reverse current occurs in each switching cycle, thereby greatly improving the light load efficiency. In addition, the present invention also introduces adaptive elimination of the influence of slope compensation, which can avoid the problem that the current gear deviation of entering the BURST mode is too large or even the BURST mode cannot be entered due to the slope compensation current under different duty cycles. Figure 3 The waveform diagram corresponding to the scheme of the present invention is shown. As the load decreases, the frequency of the jump cycle will be lower; when the load is small enough and the jump cycle is much larger than the clock cycle, the switching loss will be at least one order of magnitude smaller than the traditional scheme, which will greatly improve the light load efficiency. In addition, the BURST_VREF signal of the scheme of the present invention follows the dynamic adjustment of the ramp current to eliminate the deviation caused by the ramp compensation, and can ensure that the load current entering the BURST mode does not change significantly under different duty cycles.

[0053] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A BURST control circuit based on forced continuous mode DC-DC, characterized in that: The invention comprises a DC-DC converter, an error amplifier EA, a current sampling circuit CURRENT SENSE, a PWM comparator CMP1, a modulator PWM MODULE, a BURST comparator CMP2 and a BURST_VREF generator BURST_VREF_GEN, wherein the inverting input of the error amplifier EA is connected to the output signal FB of the voltage-dividing feedback circuit of the DC-DC converter, the non-inverting input of the error amplifier EA is connected to the reference voltage signal VREF, the output of the error amplifier EA is connected to the non-inverting input of the PWM comparator CMP1 and the inverting input of the BURST comparator CMP2, the input of the current sampling circuit CURRENT SENSE is connected to the source of the power tube M2 in the DC-DC converter, the output of the current sampling circuit CURRENT SENSE outputs a voltage signal CS, the voltage signal CS is added with a slope compensation voltage SLOPE and connected to the inverting input of the PWM comparator CMP1, the output of the PWM comparator CMP1 is connected to the modulator PWM MODULE, the output end of the BURST_VREF generator BURST_VREF_GEN is connected to the non-inverting input end of the BURST comparator CMP2, the output end of the BURST comparator CMP2 is connected to the third input end of the modulator PWM MODULE, and the second input end of the modulator PWM MODULE is connected to the clock signal CLK; The BURST_VREF generator includes a sample-and-hold module SENSE_HOLD, a matching resistor R2, and a bias current source I B2 , the input slope compensation current I of the sampling and holding module SENSE_HOLD input terminal SLOPE The sampling and holding module SENSE_HOLD samples and holds the maximum current value I of the slope compensation of the previous cycle SLOPE_MAX The output end of the sampling and holding module SENSE_HOLD is connected to one end of the matching resistor R2 and the bias current source I B2 The output end of is connected and used as the output end of the BURST_VREF generator, and the other end of the matching resistor R2 is grounded; The input end of the sampling and holding module SENSE_HOLD and one end of the resistor R1, the output end of the main circuit CURRENT MIRROR of the current sampling circuit CURRENT SENSE, the bias current source I B1 The output terminal connection of The resistance of the matching resistor R2 is equal to that of the resistor R1, and the bias current source I B2 and bias current source I B1 The currents are equal; The sampling and holding module SENSE_HOLD includes a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a resistor R3, a resistor R4, an operational amplifier OP1, an operational amplifier OP2, an operational amplifier OP3, a switch S1, a switch S2, a holding capacitor C HOLD1 and C HOLD2 , the drain of transistor M1 is connected to the gate of transistor M1, the gate of transistor M2 and the gate of transistor M3 and inputs the source of slope compensation current SLOPE CURRENT SOURCE, the drain of transistor M2 is connected to the drain of transistor M4, the gate of transistor M4 and the gate of transistor M5, the drain of transistor M3 outputs the slope compensation current SLOPE CURRENT, the source of transistor M4 is connected to the source of transistor M5, the source of transistor M6 and the source of transistor M7, the drain of transistor M5 is connected to one end of resistor R3 and the same-direction input end of operational amplifier OP1, the output end of operational amplifier OP1 is connected to the inverting input end of operational amplifier OP1 and one end of switch S1, the other end of switch S1 is connected to the same-direction input end of operational amplifier OP2 and holding capacitor C HOLD1 The output end of the operational amplifier OP2 is connected to the inverting input end of the operational amplifier OP2 and one end of the switch S2, and the other end of the switch S2 is connected to the same-direction input end of the operational amplifier OP3 and the holding capacitor C HOLD2 The output end of the operational amplifier OP3 is connected to the inverting input end of the operational amplifier OP3, one end of the resistor R4, the drain of the transistor M6, the gate of the transistor M6 and the gate of the transistor M7, the drain of the transistor M7 outputs the maximum value SLOPE CURRENT MAX of the slope compensation current, the source of the transistor M1, the source of the transistor M2, the source of the transistor M3, the other end of the resistor R3, the holding capacitor C HOLD1 The other end of the capacitor C HOLD2 The other end of the resistor R4 and the other end of the resistor R4 are grounded.

2. A BURST control circuit based on forced continuous mode DC-DC according to claim 1, characterized in that: The DC-DC converter includes a power supply V0, an inductor L, a power tube M11, a power tube M12, a capacitor C and a voltage-dividing feedback circuit. The positive electrode of the power supply V0 is connected to one end of the inductor L, the other end of the inductor L and the drain of the power tube M11 and the drain of the power tube M12 are connected to the switch node SW, the gate of the power tube M11 and the gate of the power tube M12 are connected to the output end of the modulator PWM MODULE, the source of the power tube M12 is connected to the input end of the current sampling circuit CURRENT SENSE, one end of the capacitor C and one end of the voltage-dividing feedback circuit, and the negative electrode of the power supply V0, the source of the power tube M11, the other end of the capacitor C and the other end of the voltage-dividing feedback circuit are grounded.

3. A BURST control circuit based on forced continuous mode DC-DC according to claim 2, characterized in that: The voltage divider feedback circuit includes a resistor R11 and a resistor R12, one end of the resistor R11 is connected to the source of the power tube M12, the input end of the current sampling circuit CURRENT SENSE and one end of the capacitor C at the output node OUT, the other end of the resistor R11 is connected to one end of the resistor R12 to generate an output signal FB, and the other end of the resistor R12 is grounded.

4. The BURST control circuit based on forced continuous mode DC-DC according to claim 1, characterized in that: The output terminal of the error amplifier EA generates an output signal EAO, the output terminal of the BURST_VREF generator BURST_VREF_GEN generates an output voltage BURST_VREF, and the output terminal of the BURST comparator CMP2 generates an output voltage IN_BURST.

5. The BURST control circuit based on forced continuous mode DC-DC according to claim 1, characterized in that: The modulator PWM MODULE comprises a NOR gate NOR1, a NOR gate NOR2, a NOR gate NOR3 and a NOR gate NOR4, a first input end of the NOR gate NOR1 is connected to the output end of the comparator CMP1, a second input end of the NOR gate NOR1 is connected to the output end of the NOR gate NOR2, an output end of the NOR gate NOR1 is connected to a first input end of the NOR gate NOR2 and a first input end of the NOR gate NOR3, a second input end of the NOR gate NOR2 is connected to a clock signal CLK, a second input end of the NOR gate NOR3 and a second input end of the NOR gate NOR4 are connected to an output voltage IN_BURST, an output end of the NOR gate NOR3 is connected to a first input end of the NOR gate NOR4 and generates a signal M2_ON, and an output end of the NOR gate NOR4 generates a signal M1_ON.

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