Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a semiconductor layer, a first isolation groove extending along a first direction and a second isolation groove extending along a second direction; the first isolation groove separates a plurality of semiconductor strips arranged at intervals along the second direction in the semiconductor layer; the second isolation groove separates a plurality of semiconductor columns arranged at intervals along the first direction in the semiconductor strips; a plurality of bit lines extending along the first direction and arranged at intervals along the second direction; the bit lines are located at the bottom surfaces of the corresponding semiconductor strips; a plurality of word lines extending along the second direction and arranged at intervals along the first direction; the word lines are located in the corresponding second isolation grooves; the plurality of word lines and the plurality of semiconductor columns are alternately arranged in the first direction, and two word lines located on the opposite sidewalls of the same semiconductor column are arranged in a staggered mode in the extension direction of the semiconductor column, and jointly form a control word line of the corresponding semiconductor column. The semiconductor structure can reduce the device volume and the difficulty of the preparation process.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of Dynamic Random Access Memory (DRAM) technology, the size of storage cells is getting smaller and smaller, and its array architecture is becoming smaller and smaller. 2 Go to 6F 2 Then go to 4F 2 (F: minimum pattern size obtainable under given process conditions).

[0003] However, in 4F 2 In the designed structure, how to reduce the area of ​​transistors in a single array region as much as possible and pursue higher chip area utilization is still an urgent problem that needs to be solved. Summary of the Invention

[0004] Based on this, the present application provides a semiconductor structure and a method for preparing the same, which can reduce the size of the device and reduce the difficulty of the preparation process.

[0005] In one aspect, the present application provides a semiconductor structure according to some embodiments, characterized by comprising:

[0006] A semiconductor layer having a first isolation trench extending along a first direction and a second isolation trench extending along a second direction; the first isolation trench having a depth greater than a depth of the second isolation trench; the second direction intersecting the first direction; the first isolation trench isolating a plurality of semiconductor strips arranged at intervals along the second direction in the semiconductor layer; and the second isolation trench isolating a plurality of semiconductor pillars arranged at intervals along the first direction in the semiconductor strips;

[0007] a plurality of bit lines extending along the first direction and spaced apart along the second direction; the bit lines being located on the bottom surface of the corresponding semiconductor strips;

[0008] and a plurality of word lines extending along the second direction and arranged at intervals along the first direction; the word lines being located in corresponding second isolation trenches;

[0009] The word lines and the semiconductor pillars are alternately arranged in the first direction, and the two word lines located on the opposite side walls of the same semiconductor pillar are staggered in the extension direction of the semiconductor pillar and together constitute a control word line corresponding to the semiconductor pillar.

[0010] In some embodiments, an orthographic projection of the bit line on the semiconductor layer overlaps or substantially overlaps with the semiconductor strip.

[0011] In some embodiments, among the two word lines corresponding to the same semiconductor column, the word line close to the bottom of the second isolation trench is the first word line, and the word line away from the bottom of the second isolation trench is the second word line; wherein, the top surface of the first word line is flush with the bottom surface of the second word line or lower than the bottom surface of the second word line.

[0012] In some embodiments, the width of the first word line increases in a direction away from the bottom of the second isolation trench; wherein the width of the first word line is a dimension of the first word line in the first direction.

[0013] In some embodiments, a shape of an end portion of the first word line close to a bottom portion of the second isolation trench is similar to a shape of a bottom portion of the second isolation trench.

[0014] In some embodiments, the semiconductor structure further includes: an air gap structure located within the second isolation trench;

[0015] Wherein, the air gap structure comprises:

[0016] a first air gap located above the first word line;

[0017] and / or, a second air gap is located below the second word line.

[0018] In some embodiments, the semiconductor structure further comprises:

[0019] a first isolation structure located in the first isolation trench and filling the spaces between adjacent semiconductor strips;

[0020] A second isolation structure is located in the second isolation trench, filling the space between the adjacent semiconductor pillars in the first direction and covering the word line; the second isolation structure also closes the air gap structure.

[0021] In some embodiments, a bottom surface of the first air gap is flush with or lower than a bottom surface of the second word line, and a top surface of the first air gap is flush with or higher than a top surface of the second word line;

[0022] A top surface of the second air gap is flush with or higher than a top surface of the first word line, and a bottom surface of the second air gap is flush with a bottom surface of the first word line.

[0023] In some embodiments, the semiconductor structure further comprises:

[0024] a bit line contact structure located between the bit line and the semiconductor strip;

[0025] The semiconductor strip is connected to the bit line via the bit line contact structure.

[0026] In some embodiments, the semiconductor structure further comprises:

[0027] The gate dielectric layer covers the sidewall of the semiconductor pillar in the first direction and is located between the semiconductor pillar and the word line.

[0028] On the other hand, according to some embodiments, the present application provides a method for preparing a semiconductor structure, comprising:

[0029] Providing a semiconductor layer; forming a first isolation trench extending along a first direction and a second isolation trench extending along a second direction in the semiconductor layer; the depth of the first isolation trench is greater than the depth of the second isolation trench; the second direction intersects the first direction; the first isolation trench isolates a plurality of semiconductor strips arranged at intervals along the second direction in the semiconductor layer; the second isolation trench isolates a plurality of semiconductor pillars arranged at intervals along the first direction in the semiconductor strips;

[0030] forming bit lines extending along the first direction on bottom surfaces of the plurality of semiconductor strips;

[0031] Word lines extending along the second direction are respectively formed in the plurality of second isolation trenches; wherein the plurality of word lines and the plurality of semiconductor pillars are alternately arranged in the first direction, and the two word lines located on the opposite side walls of the same semiconductor pillar are staggered in the extension direction of the semiconductor pillar and together constitute a control word line corresponding to the semiconductor pillar.

[0032] In some embodiments, among the two word lines corresponding to the same semiconductor pillar, the word line close to the bottom of the second isolation trench is a first word line, and the word line far from the bottom of the second isolation trench is a second word line;

[0033] The word lines extending along the second direction are formed in the plurality of second isolation trenches respectively, comprising:

[0034] forming the first word lines at the bottoms of a portion of the second isolation trenches;

[0035] forming the second word lines in the middle and upper portions of another portion of the second isolation trenches;

[0036] The top surface of the first word line is flush with or lower than the bottom surface of the second word line.

[0037] In some embodiments, before forming the second isolation trench in the semiconductor layer, the method for preparing the semiconductor structure further includes: forming a first isolation structure in the first isolation trench; the first isolation structure filling the space between adjacent semiconductor strips;

[0038] After forming the word line in the second isolation trench, the method for preparing the semiconductor structure further includes: forming a second isolation structure in the second isolation trench; the second isolation structure fills the space between adjacent semiconductor pillars in the first direction and covers the word line.

[0039] In some embodiments, forming the second isolation structure in the second isolation trench includes:

[0040] forming a first air gap above the first word line;

[0041] forming a second air gap below the second word line;

[0042] The first air gap and the second air gap together constitute an air gap structure; the second isolation structure further closes the air gap structure.

[0043] In some embodiments, before forming bit lines extending along the first direction on the bottom surfaces of the plurality of semiconductor strips, the method for preparing the semiconductor structure further includes:

[0044] forming bit line contact structures extending along the first direction on bottom surfaces of the plurality of semiconductor strips;

[0045] Wherein, the bit line is formed on the bottom surface of the bit line contact structure.

[0046] In some embodiments, before forming word lines extending along the second direction in each of the plurality of second isolation trenches, the method for preparing the semiconductor structure further includes:

[0047] forming a gate dielectric layer covering the sidewalls of the semiconductor pillar in the first direction;

[0048] The word line is formed on a side wall of the gate dielectric layer facing away from the semiconductor column.

[0049] The semiconductor structure and the method for manufacturing the same provided by this application have at least the following beneficial effects:

[0050] The semiconductor structure and preparation method provided by the present application form two word lines arranged in an offset manner on the opposite side walls of a semiconductor column, and these two word lines together constitute the control word line of the corresponding semiconductor column. This can reduce the space between adjacent semiconductor columns, thereby reducing the size of the device. In addition, the end of the semiconductor column connected to the bit line is short-circuited together, which can not only further reduce the size of the device, but also reduce the contact resistance between the bit line and the semiconductor column. In addition, compared with the trench in the traditional semiconductor structure, the second isolation trench in the semiconductor structure and preparation method provided by the present application is shallower, which can also reduce the difficulty of the preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 Figure (a) is a schematic diagram of a three-dimensional structure of a semiconductor structure provided by some embodiments of the present application; Figure 1 Figure (b) is Figure 1 Schematic diagram of the cross-sectional structure of the structure shown in (a); Figure 1 Figure (c) is a schematic diagram of a three-dimensional structure of a semiconductor structure provided in some other embodiments of the present application;

[0053] Figure 2 Figure (a) is a schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present application when the first and second word lines on the left side are opened; Figure 2 Figure (b) is Figure 2 Voltage-current diagram of the structure shown in (a);

[0054] Figure 3 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments of the present application;

[0055] Figure 4 A schematic flow chart of step S300 in the method for preparing a semiconductor structure provided in some embodiments of the present application;

[0056] Figure 5 A schematic diagram of a process for forming a second isolation structure in a second isolation trench in a method for manufacturing a semiconductor structure provided in some embodiments of the present application;

[0057] Figure 6 FIG. (a) is a schematic diagram of a three-dimensional structure of a structure obtained after forming a first isolation trench in a method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 6 Figure (b) is Figure 6 Schematic diagram of the top view of the structure shown in (a); Figure 6 Figure (c) is a schematic diagram of the three-dimensional structure of the structure obtained after forming the first isolation structure in the method for preparing the semiconductor structure provided by some embodiments of the present application;

[0058] Figure 7 Figure (a) is a schematic diagram of the three-dimensional structure of the structure obtained after forming the second isolation trench in the method for preparing the semiconductor structure provided by some embodiments of the present application; Figure 7 Figure (b) is Figure 7 Schematic diagram of the top view of the structure shown in (a); Figure 7 Figure (c) is a schematic diagram of the three-dimensional structure of the structure obtained after forming the gate dielectric layer in the preparation method provided in some embodiments of the present application;

[0059] Figure 8 Figure (a) is a schematic diagram of the three-dimensional structure of the structure obtained in step S300 in the method for preparing a semiconductor structure provided in some embodiments of the present application; Figure 8 Figure (b) is Figure 8 Schematic diagram of the top view of the structure shown in (a); Figure 8 Figure (c) is a schematic diagram of the three-dimensional structure of the structure obtained after forming the second isolation structure in the method for preparing the semiconductor structure provided by some embodiments of the present application;

[0060] Figure 9 This is a schematic cross-sectional structural diagram of a structure obtained after forming a bit line contact structure in a method for preparing a semiconductor structure provided in some embodiments of the present application.

[0061] Description of reference numerals:

[0062] T1, first isolation trench; T2, second isolation trench;

[0063] 1. Semiconductor layer; 10. Semiconductor strip; 100. Semiconductor pillar; 2. Bit line; 3. Word line; 31. First word line; 31A. First word line on the left; 31B. First word line on the right; 32. Second word line; 4. Air gap structure; 41. First air gap; 42. Second air gap; 5. First isolation structure; 6. Second isolation structure; 7. Bit line contact structure; 8. Gate dielectric layer; NC, storage node of the left device; NC0, storage node of the right device. DETAILED DESCRIPTION

[0064] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0066] It should be understood that when an element or layer is referred to as being "on" or "adjacent to" it can be directly on or adjacent to another element or layer, or there can be intervening elements or layers. It should be understood that although the terms first, second, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings of the present application; for example, a first isolation trench may be referred to as a second isolation trench, and similarly, a second isolation trench may be referred to as a first isolation trench; the first isolation trench and the second isolation trench are different isolation trenches.

[0067] Spatially relative terms such as "below...", "above...", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "below..." will be oriented as "above" the other elements or features. Therefore, the exemplary term "below..." may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0068] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. As such, variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes as a result, for example, of manufacturing techniques. The regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present invention.

[0070] In view of the shortcomings of the prior art, the present application provides a semiconductor structure and a method for manufacturing the same, which can reduce the size of the device and reduce the difficulty of the manufacturing process. The details will be described in the subsequent embodiments.

[0071] In one aspect, the present application provides a semiconductor structure according to some embodiments.

[0072] See also Figure 1 Figure (a) in Figure 1 Figure (b) and Figure 1 In Figure (c), in some embodiments, the semiconductor structure may include a semiconductor layer 1, a plurality of bit lines 2 extending along a first direction (e.g., the X direction) and arranged at intervals along a second direction (e.g., the Y direction), and a plurality of word lines 3 extending along the second direction (e.g., the Y direction) and arranged at intervals along the first direction (e.g., the X direction).

[0073] It should be noted that, in the embodiment of the present application, the second direction intersects with the first direction.

[0074] The semiconductor layer 1 has a first isolation trench T1 extending along a first direction (e.g., the X direction) and a second isolation trench T2 extending along a second direction (e.g., the Y direction). The first isolation trench T1 can isolate a plurality of semiconductor strips 10 spaced apart along the second direction (e.g., the Y direction) in the semiconductor layer 1, and the second isolation trench T2 can isolate a plurality of semiconductor pillars 100 spaced apart along the first direction (e.g., the X direction) in the semiconductor strips 10. Specifically, the depth of the first isolation trench T1 should be greater than the depth of the second isolation trench T2.

[0075] The bit lines 2 are located on the bottom surfaces of the corresponding semiconductor strips 10. The word lines 3 are located in the corresponding second isolation trenches T2. The word lines 3 and the semiconductor pillars 100 are arranged alternately in a first direction (e.g., the X direction). Two word lines 3 located on opposite sides of the same semiconductor pillar 100 are staggered in the extension direction of the semiconductor pillar 100 and together constitute the control word line 3 of the corresponding semiconductor pillar 100.

[0076] In the semiconductor structure provided by the above embodiment, the two word lines 3 on the opposite side walls of the semiconductor pillar 100 are staggered, and the two word lines 3 together constitute the control word line 3 of the corresponding semiconductor pillar 100. This can reduce the space between adjacent semiconductor pillars 100, thereby reducing the device size.

[0077] Furthermore, the semiconductor structure described above short-circuits one end of the semiconductor pillar 100 connected to the bit line 2 , which not only further reduces the device size but also reduces the contact resistance between the bit line 2 and the semiconductor pillar 100 .

[0078] In addition, compared with the trenches in the traditional semiconductor structure, the second isolation trench T2 in the semiconductor structure is shallower, which can also reduce the difficulty of the manufacturing process.

[0079] The present application does not specifically limit the material of the semiconductor layer 1. As an example, the material of the semiconductor layer 1 may include, but is not limited to, silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc.; alternatively, the material of the semiconductor layer 1 may also include silicon-on-insulator (SOI) or silicon germanium-on-insulator, etc.

[0080] The present application does not impose any specific limitation on the material of the bit line 2. As an example, the material of the bit line 2 may include, but is not limited to, doped polysilicon, titanium (Ti), titanium nitride (TiN), or tungsten (W).

[0081] The present application does not specifically limit the material of the word line 3. As an example, the material of the word line 3 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, metal alloy, or any combination thereof.

[0082] The present application does not specifically limit the positional relationship between the bit line 2 and the semiconductor strip 10. In some embodiments, Figure 1 As shown in FIG. 8( b ), the orthographic projection of the bit line 2 on the semiconductor layer 1 may overlap with the semiconductor strip 10 ; or, the orthographic projection of the bit line 2 on the semiconductor layer 1 may approximately overlap with the semiconductor strip 10 .

[0083] Please continue reading Figure 1 Figure (a) in Figure 1 Figure (b) and Figure 1 In Figure (c), in some embodiments, among the two word lines 3 corresponding to the same semiconductor pillar 100, the word line 3 close to the bottom of the second isolation trench T2 is used as the first word line 31; correspondingly, the word line 3 far from the bottom of the second isolation trench T2 is used as the second word line 32.

[0084] The top surface of the first word line 31 may be flush with the bottom surface of the second word line 32 ; or the top surface of the first word line 31 may be lower than the bottom surface of the second word line 32 .

[0085] The present application does not specifically limit the width of the first word line 31. In some embodiments, the width of the first word line 31 may gradually increase in a direction away from the bottom of the second isolation trench T2.

[0086] It should be noted that, in the present application, the width of the first word line 31 refers to the size of the first word line 31 in the first direction (eg, the X direction).

[0087] The present application does not specifically limit the shape of the first word line 31. In some embodiments, the shape of the end of the first word line 31 close to the bottom of the second isolation trench T2 may be similar to the shape of the bottom of the second isolation trench T2.

[0088] Please continue reading Figure 1 As shown in FIG. 5( c ), in some embodiments, the semiconductor structure may further include an air gap structure 4 .

[0089] The air gap structure 4 is located in the second isolation trench T2 and may include a first air gap 41 and / or a second air gap 42 . The first air gap 41 is located above the first word line 31 , and the second air gap 42 is located below the second word line 32 .

[0090] In the semiconductor structure provided by the above embodiment, the air gap structure 4 in the second isolation trench T2 can reduce the floating body effect between adjacent semiconductor pillars 100 , thereby further reducing the static leakage of the device during use.

[0091] Furthermore, since the dielectric constant of air is 1.001, which is close to the dielectric constant of a vacuum, the semiconductor structure provided in the above embodiment forms an air gap structure 4 in the second isolation trench T2, and can also make the area above the first word line 31 and the area below the second word line 32 reflect the effect of a low dielectric constant material to reduce the overall dielectric constant. This can reduce the size of the parasitic capacitance and avoid the capacitive coupling effect between the word line 3 and the adjacent word line 3, thereby reducing the impact of the parasitic capacitance on the device performance parameters.

[0092] The present application does not specifically limit the shape of the air gap structure 4. As an example, the shape of the air gap structure 4 may include a long strip shape (air line), a short tube shape (air pipe), an elliptical shape (air gap) or other suitable shapes.

[0093] The present application does not impose any specific limitation on the position of the first air gap 41, as long as the first air gap 41 is located above the first word line 31. In some embodiments, the orthographic projection of the first air gap 41 on the semiconductor pillar 100 may overlap or substantially overlap with the orthographic projection of the second word line 32 on the semiconductor pillar 100.

[0094] The present application does not impose any specific restrictions on the position of the second air gap 42, as long as the second air gap 42 is located below the second word line 32. In some embodiments, the orthographic projection of the second air gap 42 on the semiconductor pillar 100 can overlap or substantially overlap with the orthographic projection of the first word line 31 on the semiconductor pillar 100.

[0095] Please continue reading Figure 1In FIG. 5( c ), in some embodiments, the semiconductor structure may further include a first isolation structure 5 and a second isolation structure 6 .

[0096] The first isolation structure 5 is located within the first isolation trench T1 and can be used to fill the space between adjacent semiconductor strips 10. The second isolation structure 6 is located within the second isolation trench T2 and can be used to fill the space between adjacent semiconductor pillars 100 in a first direction (e.g., the X direction) and cover the word line 3. In addition, the second isolation structure 6 can also be used to enclose the air gap structure 4.

[0097] The present application does not specifically limit the materials of the first isolation structure 5 and the second isolation structure 6. As an example, the material of the first isolation structure 5 can be the same as that of the second isolation structure 6; in this case, the first isolation structure 5 and the second isolation structure 6 can actually be an integrally formed structure.

[0098] In some embodiments, the material of the first isolation structure 5 and the material of the second isolation structure 6 may include but is not limited to silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), or a combination thereof.

[0099] The present application does not specifically limit the positional relationship between the first air gap 41 and the second word line 32. In some embodiments, the bottom surface of the first air gap 41 can be flush with the bottom surface of the second word line 32; or, the bottom surface of the first air gap 41 can be lower than the bottom surface of the second word line 32.

[0100] In some embodiments, a top surface of the first air gap 41 may be flush with a top surface of the second word line 32 ; or, a top surface of the first air gap 41 may be higher than a top surface of the second word line 32 .

[0101] The present application does not specifically limit the positional relationship between the second air gap 42 and the first word line 31. In some embodiments, the top surface of the second air gap 42 can be flush with the top surface of the first word line 31; or, the top surface of the second air gap 42 can be higher than the top surface of the first word line 31.

[0102] In some embodiments, a bottom surface of the second air gap 42 may be flush with a bottom surface of the first word line 31 .

[0103] Please continue reading Figure 1 In FIG. 5( b ), in some embodiments, the semiconductor structure may further include a bit line contact structure 7 . The bit line contact structure 7 may be located between the bit line 2 and the semiconductor strip 10 , and the semiconductor strip 10 may be connected to the bit line 2 via the bit line contact structure 7 .

[0104] Please continue reading Figure 1As shown in FIG. 5( c ), in some embodiments, the semiconductor structure may further include a gate dielectric layer 8. The gate dielectric layer 8 may cover the sidewalls of the semiconductor pillar 100 in a first direction (eg, the X direction) and be located between the semiconductor pillar 100 and the word line 3.

[0105] The present application does not specifically limit the material of the gate dielectric layer 8. As an example, the material of the gate dielectric layer 8 may include, but is not limited to, one or more of a high-K dielectric material, silicon oxide, silicon nitride, or silicon oxynitride. A high-K dielectric material refers to a material having a relative dielectric constant greater than that of silicon oxide, such as hafnium oxide (HfO2) or aluminum oxide (Al2O3).

[0106] It should be noted that, in some embodiments, the material of the gate dielectric layer 8 may be the same as the material of the first isolation structure 5 and / or the material of the second isolation structure 6. When the material of the gate dielectric layer 8 is the same as the material of the first isolation structure 5 and the second isolation structure 6, the gate dielectric layer 8, the material of the first isolation structure 5, and the second isolation structure 6 can actually be presented as an integrally formed structure.

[0107] This application also does not specifically limit the structure of the gate dielectric layer 8. As an example, the gate dielectric layer 8 can be a single-layer structure or a stacked-layer structure; and the number of gate dielectric layers 8 can be adaptively set according to different actual preparation processes and different requirements for the thickness of the gate dielectric layer 8.

[0108] Regarding the feasibility of the performance of the semiconductor structure provided in the present application, the feasibility of the semiconductor structure provided in the present application can be verified by simulation using semiconductor process simulation and device simulation tools (Technology Computer Aided Design, abbreviated as TCAD).

[0109] like Figure 2 Figure (a) and Figure 2 As shown in Figure (b), when the first word line 31A and the second word line 32 on the left are turned on (Sweep), the device on the left is turned on; at this time, the first word line 31B on the right remains in the off state, and the leakage current of the device on the right can be kept below 0.1FA. Figure 2 FIG. 2( b) shows the current IDS flowing through the storage nodes NC and NC0 corresponding to the two devices, where Vg refers to the voltage applied to the storage node and IDS refers to the current flowing through the storage node.

[0110] In some embodiments, the semiconductor structure may further include a plurality of capacitor units. As an example, the plurality of capacitor units may be disposed above the semiconductor pillars 100 , respectively.

[0111] In some embodiments, capacitor contact structures may be aligned and arranged on the semiconductor pillars 100 , which is beneficial for improving the contact between the capacitor unit and the corresponding semiconductor pillar 100 .

[0112] On the other hand, the present application also provides a method for preparing a semiconductor structure according to some embodiments.

[0113] See also Figure 3 In some embodiments, the method for preparing the semiconductor structure may include the following steps:

[0114] S100: Provide a semiconductor layer; form a first isolation trench extending along a first direction and a second isolation trench extending along a second direction in the semiconductor layer; the depth of the first isolation trench is greater than the depth of the second isolation trench; the second direction intersects the first direction; the first isolation trench isolates a plurality of semiconductor strips arranged at intervals along the second direction in the semiconductor layer; the second isolation trench isolates a plurality of semiconductor columns arranged at intervals along the first direction in the semiconductor strips.

[0115] S200 : forming bit lines extending along a first direction on bottom surfaces of the plurality of semiconductor strips.

[0116] S300: forming word lines extending along the second direction in the plurality of second isolation trenches; wherein the plurality of word lines and the plurality of semiconductor pillars are alternately arranged in the first direction, and two word lines located on opposite side walls of the same semiconductor pillar are staggered in the extension direction of the semiconductor pillar and together constitute a control word line of the corresponding semiconductor pillar.

[0117] In the method for fabricating the semiconductor structure provided in the above embodiment, two staggered word lines can be formed on opposite sidewalls of a semiconductor pillar, and these two word lines together constitute a control word line for the corresponding semiconductor pillar. This can reduce the space between adjacent semiconductor pillars, thereby reducing the size of the device.

[0118] Furthermore, the above-mentioned preparation method short-circuits one end of the semiconductor pillar connected to the bit line, which can not only further reduce the device size, but also reduce the contact resistance between the bit line and the semiconductor pillar.

[0119] In addition, compared with the trenches in the traditional semiconductor structure, the second isolation trench formed in the above preparation method is shallower, which can also reduce the difficulty of the preparation process.

[0120] See also Figure 4 In some embodiments, step S300 of forming word lines extending along the second direction in the plurality of second isolation trenches may specifically include the following steps:

[0121] S310 : forming first word lines at the bottoms of a portion of the second isolation trenches.

[0122] S320 : forming second word lines in the middle and upper portions of another portion of the second isolation trenches.

[0123] The top surface of the first word line is flush with or lower than the bottom surface of the second word line.

[0124] In some embodiments, before forming the second isolation trench in the semiconductor layer, the method for preparing the semiconductor structure may further include the following step: forming a first isolation structure in the first isolation trench, wherein the first isolation structure fills the space between adjacent semiconductor strips.

[0125] After forming the word line in the second isolation trench, the method for preparing the semiconductor structure may further include the following steps: forming a second isolation structure in the second isolation trench, the second isolation structure filling the space between adjacent semiconductor pillars in the first direction and covering the word line.

[0126] See also Figure 5 In some embodiments, forming a second isolation structure in the second isolation trench may include the following steps:

[0127] S410 : forming a first air gap above the first word line.

[0128] S420: forming a second air gap below the second word line.

[0129] The first air gap and the second air gap together constitute an air gap structure, and the second isolation structure further closes the air gap structure.

[0130] In some embodiments, before forming bit lines extending along the first direction on the bottom surfaces of the plurality of semiconductor strips, the method for fabricating the semiconductor structure may further include the following steps:

[0131] Bit line contact structures extending along a first direction are formed on the bottom surfaces of the plurality of semiconductor strips, and bit lines can be formed on the bottom surfaces of the bit line contact structures.

[0132] In some embodiments, before forming word lines extending along the second direction in each of the plurality of second isolation trenches, the method for fabricating the semiconductor structure may further include the following steps:

[0133] A gate dielectric layer is formed to cover the sidewalls of the semiconductor pillar in the first direction. A word line can be formed on the sidewall of the gate dielectric layer facing away from the semiconductor pillar.

[0134] It should be understood that although Figures 3 to 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 3 to 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0135] In order to more clearly illustrate the preparation methods in some of the above embodiments, Figures 6 to 9 Understanding some embodiments of the present application. It should be noted that, in the embodiments of the present application, the second direction intersects with the first direction.

[0136] In step S100, a semiconductor layer 1 is provided. Figure 6 Figure (a) and Figure 6 As shown in FIG. 1( b ), a first isolation trench T1 extending along a first direction (e.g., the X direction) is formed in the semiconductor layer 1. The first isolation trench T1 can isolate a plurality of semiconductor strips 10 spaced apart along a second direction (e.g., the Y direction) in the semiconductor layer 1. Figure 7 Figure (a) and Figure 7 As shown in FIG. 1 , a second isolation trench T2 extending along a second direction (e.g., the Y direction) is formed in the semiconductor layer 1. The second isolation trench T2 can isolate a plurality of semiconductor pillars 100 spaced apart along a first direction (e.g., the X direction) in the semiconductor strip 10.

[0137] The depth of the first isolation trench T1 is greater than the depth of the second isolation trench T2.

[0138] The present application does not specifically limit the method for forming the first isolation trench T1 and the second isolation trench T2. As an example, the first isolation trench T1 and the second isolation trench T2 can be formed in the semiconductor layer 1 using, but not limited to, a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process.

[0139] See also Figure 6 In FIG. 5( c ), in some embodiments, before forming the second isolation trench T2 in the semiconductor layer 1 , the method for preparing the semiconductor structure may further include the following steps:

[0140] A first isolation structure 5 is formed in the first isolation trench T1 . The first isolation structure 5 can be used to fill the spaces between adjacent semiconductor strips 10 .

[0141] The present application does not specifically limit the method for forming the first isolation structure 5. As an example, the first isolation structure 5 can be formed in the first isolation trench T1 by using, but not limited to, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0142] In step S200 , bit lines extending along a first direction (eg, X direction) are formed on the bottom surfaces of the plurality of semiconductor strips 10 .

[0143] The present application does not specifically limit the method for forming the bit lines. As an example, the bit lines can be formed on the bottom surface of the semiconductor strip 10 using, but not limited to, a Heterogeneous Integration Technology On Chip (HITOC) process.

[0144] See also Figure 7 As shown in FIG. 5( c ), in some embodiments, the method for preparing the semiconductor structure may further include the following step: forming a gate dielectric layer 8 covering the sidewalls of the semiconductor pillar 100 in a first direction (eg, the X direction).

[0145] The present application does not specifically limit the method for forming the gate dielectric layer 8. As an example, the gate dielectric layer 8 can be formed on the sidewalls of the semiconductor pillar 100 by, but not limited to, an atomic layer deposition process, a chemical vapor deposition process, or a rapid thermal oxidation (RTO) process.

[0146] See also Figure 8 Figure (a) in Figure 8 Figure (b) and Figure 8 As shown in FIG. 2( c ), in step S300 , word lines 3 extending along a second direction (e.g., the Y direction) are formed in each of the plurality of second isolation trenches T2 . The plurality of word lines 3 and the plurality of semiconductor pillars 100 are alternately arranged in a first direction (e.g., the X direction). Two word lines 3 located on opposite sides of the same semiconductor pillar 100 are staggered in the extending direction of the semiconductor pillar 100 and together constitute a control word line 3 of the corresponding semiconductor pillar 100 .

[0147] It should be noted that, in some embodiments, step S300 may be performed after forming the gate dielectric layer 8 covering the sidewalls of the semiconductor pillar 100 in the first direction (e.g., the X direction). As an example, the word line 3 may be formed on the sidewall of the gate dielectric layer 8 facing away from the semiconductor pillar 100.

[0148] Please continue reading Figure 8 In FIG. 5( c ), in some embodiments, after forming the word line 3 in the second isolation trench T2 in step S300 , the method for manufacturing the semiconductor structure may further include the following steps:

[0149] A second isolation structure 6 is formed in the second isolation trench T2 . The second isolation structure 6 can be used to fill the spaces between adjacent semiconductor pillars 100 in a first direction (eg, the X direction) and can also be used to cover the word lines 3 .

[0150] The present application does not specifically limit the method for forming the second isolation structure 6. As an example, the second isolation structure 6 can be formed in the second isolation trench T2 by, but not limited to, physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0151] The following combination Figure 8 Figure (a) in Figure 8 Figure (b) and Figure 8 In Figure (c), some embodiments of the present application are described in more detail by taking the two word lines 3 corresponding to the same semiconductor column 100, where the word line 3 close to the bottom of the second isolation trench T2 is the first word line 31 and the word line 3 away from the bottom of the second isolation trench T2 is the second word line 32 as an example.

[0152] like Figure 8 Figure (a) in Figure 8 Figure (b) and Figure 8 As shown in FIG. 5( c ), in some embodiments, step S300 forms word lines 3 extending along a second direction (e.g., a Y direction) in each of the plurality of second isolation trenches T2 , which may be specifically performed as follows: steps S310 to S320 :

[0153] In step S310 , first word lines 31 are formed at the bottoms of a portion of the second isolation trenches T2 .

[0154] In step S320 , second word lines 32 are formed in the middle and upper portions of another portion of the second isolation trenches T2 .

[0155] As an example, the top surface of the first word line 31 may be flush with the bottom surface of the second word line 32 ; alternatively, the top surface of the first word line 31 may be lower than the bottom surface of the second word line 32 .

[0156] Please continue reading Figure 8 In FIG. 5( c ), in some embodiments, forming the second isolation structure 6 in the second isolation trench T2 may further include the following steps S410 to S420 :

[0157] In step S410 , a first air gap 41 is formed above the first word line 31 .

[0158] In step S420 , a second air gap 42 is formed below the second word line 32 .

[0159] The first air gap 41 and the second air gap 42 may together constitute an air gap structure 4 , and the second isolation structure 6 may be used to seal the air gap structure 4 .

[0160] In the method for preparing the semiconductor structure provided in the above embodiment, an air gap structure 4 can be formed in the second isolation trench T2 through the second isolation structure 6. The air gap structure 4 can reduce the floating body effect between adjacent semiconductor pillars 100, thereby further reducing the static leakage of the device during use.

[0161] Furthermore, since the dielectric constant of air is 1.001, which is close to the dielectric constant of a vacuum, the above-mentioned preparation method forms an air gap structure 4 in the second isolation trench T2, and can also make the area above the first word line 31 and the area below the second word line 32 reflect the effect of a low dielectric constant material, thereby reducing the overall dielectric constant. This can reduce the size of the parasitic capacitance and avoid the capacitive coupling effect between the word line 3 and the adjacent word line 3, thereby reducing the impact of the parasitic capacitance on the device performance parameters.

[0162] See also Figure 9 In some embodiments, before forming the bit lines 2 extending along the first direction (e.g., the X direction) on the bottom surfaces of the plurality of semiconductor strips 10 in step S200, the method for preparing the semiconductor structure may further include the following steps:

[0163] Bit line contact structures 7 extending along a first direction (eg, the X direction) are respectively formed on bottom surfaces of the plurality of semiconductor strips 10 .

[0164] As an example, Figure 9 As shown, the bit line 2 may be formed on the bottom surface of the bit line contact structure 7 .

[0165] In some embodiments, the method for fabricating the semiconductor structure may further include the following step: forming a capacitor unit above the semiconductor pillar 100 .

[0166] It should be noted that the preparation methods of the semiconductor structures in the embodiments of the present application can be used to prepare corresponding semiconductor structures. Therefore, the technical features between the method embodiments and the structural embodiments can be replaced and supplemented with each other without causing conflicts, so that those skilled in the art can understand the technical content of the present application.

[0167] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0168] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: The semiconductor layer has a first isolation trench extending along a first direction and a second isolation trench extending along a second direction; The depth of the first isolation trench is greater than the depth of the second isolation trench; The second direction intersects the first direction; The first isolation trench isolates a plurality of semiconductor strips arranged at intervals along the second direction in the semiconductor layer; the second isolation trench isolates a plurality of semiconductor columns arranged at intervals along the first direction in the semiconductor strips; a plurality of bit lines extending along the first direction and arranged at intervals along the second direction; The bit line is located at the bottom surface of the corresponding semiconductor strip; and a plurality of word lines extending along the second direction and arranged at intervals along the first direction; The word line is located in the corresponding second isolation trench; The plurality of word lines and the plurality of semiconductor pillars are alternately arranged in the first direction, and two word lines located on opposite side walls of the same semiconductor pillar are staggered in the extension direction of the semiconductor pillar and together constitute a control word line corresponding to the semiconductor pillar; Among the two word lines corresponding to the same semiconductor column, the word line close to the bottom of the second isolation trench is the first word line, and the word line away from the bottom of the second isolation trench is the second word line; wherein the top surface of the first word line is flush with the bottom surface of the second word line or lower than the bottom surface of the second word line.

2. The semiconductor structure according to claim 1, wherein: The width of the first word line increases in a direction away from the bottom of the second isolation trench; wherein the width of the first word line is a dimension of the first word line in the first direction.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: an air gap structure located in the second isolation trench; Wherein, the air gap structure comprises: a first air gap located above the first word line; and / or, a second air gap is located below the second word line.

4. The semiconductor structure according to claim 3, wherein: The semiconductor structure further comprises: a first isolation structure located in the first isolation trench and filling the spaces between adjacent semiconductor strips; A second isolation structure is located in the second isolation trench, filling the space between the adjacent semiconductor pillars in the first direction and covering the word line; the second isolation structure also closes the air gap structure.

5. The semiconductor structure according to claim 3, wherein: The bottom surface of the first air gap is flush with or lower than the bottom surface of the second word line, and the top surface of the first air gap is flush with or higher than the top surface of the second word line; A top surface of the second air gap is flush with or higher than a top surface of the first word line, and a bottom surface of the second air gap is flush with a bottom surface of the first word line. The semiconductor structure according to claim 1 , wherein: The orthographic projection of the bit line on the semiconductor layer overlaps or substantially overlaps with the semiconductor strip; Also includes: a bit line contact structure located between the bit line and the semiconductor strip; The semiconductor strip is connected to the bit line via the bit line contact structure.

7. A method for preparing a semiconductor structure, characterized in that: include: providing a semiconductor layer; forming a first isolation trench extending along a first direction and a second isolation trench extending along a second direction in the semiconductor layer; The depth of the first isolation trench is greater than the depth of the second isolation trench; the second direction intersects the first direction; The first isolation trench isolates a plurality of semiconductor strips arranged at intervals along the second direction in the semiconductor layer; the second isolation trench isolates a plurality of semiconductor columns arranged at intervals along the first direction in the semiconductor strips; forming bit lines extending along the first direction on bottom surfaces of the plurality of semiconductor strips; forming word lines extending along the second direction in each of the plurality of second isolation trenches; wherein the plurality of word lines and the plurality of semiconductor pillars are alternately arranged in the first direction, and two word lines located on opposite side walls of the same semiconductor pillar are staggered in the extending direction of the semiconductor pillar and together constitute a control word line corresponding to the semiconductor pillar; Of the two word lines corresponding to the same semiconductor column, the word line close to the bottom of the second isolation trench is a first word line, and the word line far from the bottom of the second isolation trench is a second word line; The word lines extending along the second direction are formed in the plurality of second isolation trenches respectively, comprising: forming the first word lines at the bottoms of a portion of the second isolation trenches; forming the second word lines in the middle and upper portions of another portion of the second isolation trenches; The top surface of the first word line is flush with or lower than the bottom surface of the second word line.

8. The method for preparing a semiconductor structure according to claim 7, wherein: Before forming the second isolation trench in the semiconductor layer, the method for preparing the semiconductor structure further includes: forming a first isolation structure in the first isolation trench; the first isolation structure filling the space between adjacent semiconductor strips; After forming the word line in the second isolation trench, the method for preparing the semiconductor structure further includes: forming a second isolation structure in the second isolation trench; the second isolation structure fills the space between adjacent semiconductor pillars in the first direction and covers the word line.

9. The method for preparing a semiconductor structure according to claim 8, wherein: The forming of the second isolation structure in the second isolation trench includes: forming a first air gap above the first word line; forming a second air gap below the second word line; The first air gap and the second air gap together constitute an air gap structure; the second isolation structure further closes the air gap structure.

10. The method for preparing a semiconductor structure according to claim 7, wherein: Before forming bit lines extending along the first direction on the bottom surfaces of the plurality of semiconductor strips, the method for preparing the semiconductor structure further includes: forming bit line contact structures extending along the first direction on bottom surfaces of the plurality of semiconductor strips; Wherein, the bit line is formed on the bottom surface of the bit line contact structure.

11. The method for preparing a semiconductor structure according to claim 7, wherein: Before forming word lines extending along the second direction in each of the plurality of second isolation trenches, the method for preparing the semiconductor structure further includes: forming a gate dielectric layer covering the sidewalls of the semiconductor pillar in the first direction; The word line is formed on a side wall of the gate dielectric layer facing away from the semiconductor column.

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