Low power consumption implementation method, device, equipment and storage medium for despreader

Abstract

The present invention provides a low-power implementation method, apparatus, device, and storage medium for a despreader, comprising: during a pre-charge phase, the despreader stores each group of m ADC sampling signals processed by a digital front end into corresponding registers according to the value of a shift counter, until the storage of N groups of processed ADC sampling signals is completed; after the pre-charge phase ends, the shift counter value is reset to 0, and a new clock cycle begins. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into corresponding registers, performs correlation operations with the corresponding shifted and stored spread spectrum code sequences to obtain corresponding despread values, increments the shift counter value by 1, and repeatedly triggers execution until the correlation operations of N groups of registers are completed. By replacing data shifts with spread spectrum code shifts, the present invention can reduce the number of register flipped bits in each clock cycle, thereby reducing dynamic power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of despreaders, specifically to a method, device, equipment and storage medium for implementing low power consumption of a despreader, and more specifically to a method, device, equipment and storage medium for implementing low power consumption of a despreader in an ultra-wideband system. Background Art

[0002] According to the protocol, the despreader receives the IQ sampled data processed by the digital front-end, multiplies it by the corresponding spreading code, and then calculates the cumulative sum to obtain the despread value for the corresponding phase. During the acquisition phase, the maximum spreading code length is 1016, so the despread values ​​for 1016 phase points must be calculated. The phase position of the maximum value among these 1016 despread values ​​is then used as the decision criterion for successful acquisition.

[0003] In order to calculate the despread value of each phase point, the existing solution designs an IQ shift register. The first register receives new data at each sampling clock, and the subsequent registers shift data one by one. The shift register collects the first group of 1016 IQ sampling data, multiplies them with the corresponding 1016 spread spectrum codes, and then accumulates them to obtain the despread value of the first phase point. The pre-charge process of the existing design is as follows: Figure 1 As shown; in the next clock cycle, shift again to obtain new 1016 IQ data, calculate the data of the second phase, and calculate the despread value of other phase points in the same way, as shown in Figure 2 shown.

[0004] The despread input IQ data bit width is nbit. Assuming n=8 for the maximum usage scenario, the number of register flip bits per system clock cycle is: 1016*2(IQ two channels)*8(IQ data bit width). Such a large register flip rate will result in very high dynamic power consumption, increasing usage costs and, in severe cases, may reduce performance and work efficiency.

[0005] When the despreader is working in the Payload demodulation stage, because it receives a multipath signal, it needs to calculate the despread values ​​of 128 phase points. The calculation method used is the same as that in the acquisition stage, but the data volume and spread spectrum code length are much smaller. The existing technology does not distinguish between them and still shifts and stores 1016 groups of data. Only a part of the data is intercepted for related calculations, which also results in a large waste of power consumption. Summary of the Invention

[0006] The main purpose of the present invention is to solve the problem in the prior art that the flip rate of the register causes very high dynamic power consumption and increases the cost of use.

[0007] A first aspect of the present invention provides a method for implementing low power consumption of a despreader, comprising:

[0008] In the pre-charge phase, the despreader stores each group of m ADC sampling signals processed by the digital front end into the corresponding register according to the value of the shift counter until the storage of N groups of processed ADC sampling signals is completed;

[0009] After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the trigger is repeated until the correlation operations of N groups of registers are completed and the corresponding despread value is obtained.

[0010] Optionally, in a first implementation of the first aspect of the present invention, storing each group of m ADC sampling signals processed by the digital front end into corresponding registers until the storage of N groups of processed ADC sampling signals is completed includes:

[0011] The despreader stores the received N groups of ADC sampling signals processed by the digital front end into corresponding registers by using address mapping.

[0012] Optionally, in a second implementation of the first aspect of the present invention, in the precharge phase, the despreader stores each group of m ADC sampling signals processed by the digital front end into a corresponding register according to the value of the shift counter until the storage of N groups of processed ADC sampling signals is completed, including:

[0013] When the digital front end outputs the first set of processed ADC sampling signals, the despreader is enabled to be turned on and receive the first processed ADC sampling signal;

[0014] The despreader receives N groups of ADC sampling signals processed by the digital front end in N consecutive clock cycles and stores them in corresponding registers respectively;

[0015] Among them, when the pre-charge phase begins, the register shift counter starts timing; when the shift counter value is 0, the processed ADC sampling signals received by the despreader in the first clock cycle are stored in the first group of m registers; when the shift counter value is 1, the processed ADC sampling signals received by the despreader in the second clock cycle are stored in the second group of m registers; and so on, until when the counter value is N-1, the processed ADC sampling signals received by the despreader in the Nth clock cycle are stored in the Nth group of m registers.

[0016] Optionally, in a third implementation of the first aspect of the present invention, the method further includes: when the digital front end outputs the first group of processed ADC sampling signals, enabling the despreader, generating an initial value of the spreading code, and storing the initial value in the spreading code register;

[0017] The length of the spreading code is N, and a correlation operation is performed with the corresponding processed ADC sampling signal to obtain a corresponding despread value.

[0018] Optionally, in a fourth implementation of the first aspect of the present invention, after the pre-charge phase ends, the shift counter value is set to 0, and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle to the corresponding register, and performs a correlation operation with the corresponding shift storage spread spectrum code sequence to obtain a corresponding despread value. The shift counter value is incremented by 1, and the triggering is repeated until the correlation operation of N groups of registers is completed to obtain the corresponding despread value, including:

[0019] After the precharge phase is completed, the shift counter value returns to 0 and enters a new clock cycle;

[0020] In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers;

[0021] At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence position 0 to the (N-1) position for storage, shifting the value of the original spread spectrum sequence position 1 to the 0 position for storage, and so on, until the value of the (N-1) position is shifted to the (N-2) position for storage;

[0022] Correlation operations are performed on the updated N groups of registers stored in a one-to-one correspondence with the updated N spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases;

[0023] When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers;

[0024] At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated N groups of registers are matched one by one with the updated N spread spectrum code sequences and correlation operations are performed to obtain m correlation results;

[0025] Repeat the triggering and execution until the relevant operations of N groups of registers are completed and the corresponding despread values ​​are obtained.

[0026] Optionally, in a fifth implementation of the first aspect of the present invention, the method further includes: despreading the Payload demodulated data;

[0027] After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the trigger is repeated until the correlation operations of 18 groups of registers are completed and the corresponding despread value is obtained.

[0028] Optionally, in a sixth implementation of the first aspect of the present invention, after the pre-charge phase ends, the shift counter value is set to 0, and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle to the corresponding register, and performs a correlation operation with the corresponding shift storage spread spectrum code sequence to obtain a corresponding despread value. The shift counter value is incremented by 1, and the triggering is repeated until the correlation operation of 18 groups of registers is completed to obtain the corresponding despread value, including:

[0029] After the precharge phase is completed, the shift counter value returns to 0 and enters a new clock cycle;

[0030] In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers;

[0031] At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence at position 0 to position 17 for storage, shifting the value of the original spread spectrum sequence at position 1 to position 0 for storage, and so on, until the value of position 17 is shifted to position 16 for storage;

[0032] Correlation operations are performed on the updated 18 groups of registers stored in a one-to-one correspondence with the updated 18 spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases;

[0033] When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers;

[0034] At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated 18 groups of registers are matched one by one with the updated 18 spread spectrum code sequences and correlation operations are performed to obtain m correlation results;

[0035] Repeat the triggering and execution until the relevant operations of 18 groups of registers are completed and the corresponding despread values ​​are obtained.

[0036] A second aspect of the present invention provides a low-power implementation system for a despreader, comprising:

[0037] A pre-charge phase module is used to store each group of m ADC sampling signals processed by the digital front end into corresponding registers according to the value of the shift counter in the pre-charge phase until the storage of N groups of processed ADC sampling signals is completed;

[0038] The despread value acquisition module is used to set the shift counter value to 0 after the pre-charge phase ends and enter a new clock cycle. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the triggering execution is repeated until the correlation operations of N groups of registers are completed to obtain the corresponding despread value.

[0039] Optionally, in a first implementation manner of the second aspect of the present invention, storing each group of m ADC sampling signals processed by the digital front end into a corresponding register until the storage of N groups of processed ADC sampling signals is completed includes: the demodulator stores the received N groups of ADC sampling signals processed by the digital front end into the corresponding register using address mapping.

[0040] Optionally, in a second implementation of the second aspect of the present invention, the pre-charge stage module includes: when the digital front end outputs the first group of processed ADC sampling signals, the despreader is enabled to turn on and receive the first processed ADC sampling signal; the despreader receives N groups of ADC sampling signals processed by the digital front end for N consecutive clock cycles and stores them in corresponding registers respectively; wherein, when the pre-charge stage starts, the register shift counter starts timing; when the shift counter value is 0, the processed ADC sampling signals received by the despreader in the first clock cycle are stored in the first group of m registers; when the shift counter value is 1, the processed ADC sampling signals received by the despreader in the second clock cycle are stored in the second group of m registers; and so on, until when the counter value is N-1, the processed ADC sampling signals received by the despreader in the Nth clock cycle are stored in the Nth group of m registers.

[0041] Optionally, in a third implementation of the second aspect of the present invention, the device further includes: a spread spectrum code generation module, which is used to enable the despreader when the digital front end outputs the first group of processed ADC sampling signals, generate an initial value of the spread spectrum code, and store it in a spread spectrum code register; the length of the spread spectrum code is N, and a correlation operation is performed with the corresponding processed ADC sampling signal to obtain a corresponding despread value.

[0042] Optionally, in a fourth implementation of the second aspect of the present invention, the despreading value acquisition module includes: after the pre-charge phase ends, the shift counter value returns to 0 and enters a new clock cycle; in the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers; at the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence position 0 to the (N-1) position for storage, shifting the value of the original spread spectrum sequence position 1 to the 0 position for storage, and so on, until the value of the (N-1) position is shifted to the (N-2) position for storage; the updated N groups of registers are stored. The stored correlation data and the updated N spreading code sequences are matched one-to-one and correlation operations are performed to obtain m correlation results; wherein the m correlation results are the despread values ​​of the corresponding m phases; when the shift counter value is 1, the next clock cycle is entered, and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers; at the same time, the spreading code sequence is shifted again; the correlation data stored in the updated N groups of registers are matched one-to-one with the updated N spreading code sequences and correlation operations are performed to obtain m correlation results; the triggering execution is repeated until the correlation operations of the N groups of registers are completed and the corresponding despread values ​​are obtained.

[0043] Optionally, in a fifth implementation of the second aspect of the present invention, the apparatus further comprises: a Payload demodulated data despreading module, configured to despread the Payload demodulated data;

[0044] After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the trigger is repeated until the correlation operations of 18 groups of registers are completed and the corresponding despread value is obtained.

[0045] Optionally, in a sixth implementation of the second aspect of the present invention, the Payload demodulation data despreading module includes:

[0046] After the precharge phase is completed, the shift counter value returns to 0 and enters a new clock cycle;

[0047] In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers;

[0048] At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence at position 0 to position 17 for storage, shifting the value of the original spread spectrum sequence at position 1 to position 0 for storage, and so on, until the value of position 17 is shifted to position 16 for storage;

[0049] Correlation operations are performed on the updated 18 groups of registers stored in a one-to-one correspondence with the updated 18 spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases;

[0050] When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers;

[0051] At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated 18 groups of registers are matched one by one with the updated 18 spread spectrum code sequences and correlation operations are performed to obtain m correlation results;

[0052] Repeat the triggering and execution until the relevant operations of 18 groups of registers are completed and the corresponding despread values ​​are obtained.

[0053] According to a third aspect of the present invention, a computer-readable storage medium storing a computer program is provided. When the computer program is executed by a processor, the steps of the method for realizing low power consumption of a despreader are implemented.

[0054] A fourth aspect of the present invention provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the above-mentioned method for implementing low power consumption of a despreader.

[0055] Compared with the prior art, the present invention has the following beneficial effects:

[0056] 1. The present invention proposes a low-power implementation method, device, equipment and storage medium of a despreader. The method replaces the original data shift storage by shifting and storing the spread spectrum code sequence. The data is stored in an address mapping manner, without changing the corresponding relationship between the data and the spread spectrum code. At the same time, the data shares a set of spread spectrum codes. Therefore, in each clock cycle, taking the maximum usage scenario as an example, the number of register flips is 128*8*2*8=2 14 =16384, reduced to 128*2=2 8 =256, the number of register flips is reduced by 1 / 64, and it can be foreseen that the dynamic power consumption saved is very considerable;

[0057] 2. The implementation complexity and additional storage requirements caused by the change in the data storage method of the present invention are very small, and no major adjustments to the design timing are required, so the impact on the overall operation of the receiver is not significant;

[0058] 3. The present invention proposes to use spread spectrum code shift instead of data shift, which not only satisfies the one-to-one correspondence between the spread spectrum code and the despread input data and obtains the correct despread value, but also greatly reduces the number of flipped bits of the register in each clock cycle, thereby reducing dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0060] Figure 1 Schematic diagram of data pre-charging in the prior art.

[0061] Figure 2 Schematic diagram of despread value calculation in the prior art.

[0062] Figure 3 A schematic diagram of data pre-charging provided in an embodiment of the present invention.

[0063] Figure 4 A schematic diagram of a preamble despreading operation provided by an embodiment of the present invention.

[0064] Figure 5 A schematic diagram of the Payload data despreading operation provided by an embodiment of the present invention.

[0065] Figure 6 This is a first flow chart of a method for implementing low power consumption of a despreader provided by an embodiment of the present invention.

[0066] Figure 7 This is a second flow chart of the method for implementing low power consumption of a despreader provided by an embodiment of the present invention.

[0067] Figure 8 A schematic structural diagram of a low-power implementation device for a despreader provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0068] Embodiments of the present invention provide a low-power implementation method, apparatus, device, and storage medium for a despreader. In a pre-charge phase, the despreader stores each group of m ADC sampling signals processed by a digital front end into corresponding registers based on the value of a shift counter until the storage of N groups of processed ADC sampling signals is completed. After the pre-charge phase, the shift counter value is reset to 0, and a new clock cycle begins. The despreader updates the m ADC sampling signals processed by the digital front end received within the current clock cycle into corresponding registers, and performs correlation operations with the corresponding shift-stored spread spectrum code sequence to obtain corresponding despread values. The shift counter value is incremented by 1, and the execution is repeatedly triggered until the correlation operations of N groups of registers are completed and the corresponding despread values ​​are obtained. The present invention solves the problem of very high dynamic power consumption caused by the register flip rate.

[0069] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or that are inherent to these processes, methods, products, or apparatus.

[0070] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 6 A first embodiment of a method for implementing low power consumption of a despreader in an embodiment of the present invention includes:

[0071] 101. In the pre-charge phase, the despreader stores each group of m ADC sampling signals processed by the digital front end into corresponding registers according to the value of the shift counter until the storage of N groups of processed ADC sampling signals is completed;

[0072] In this embodiment, when the digital front end outputs the first set of processed ADC sampling signals, the despreader is enabled and receives the first processed ADC sampling signal; at the same time, an initial value of the spreading code is generated and stored in the spreading code register; the spreading code has a length of N, and a correlation operation is performed with the corresponding processed ADC sampling signal to obtain a corresponding despread value.

[0073] Although the working clock of the digital front end is synchronized with the working clock of the despreader, the working clock frequency of the despreader is relatively low. Therefore, in each clock cycle, the despreader will receive m data and store them in the corresponding m storage units. m is the ratio of the working clock frequency of the digital front end to the working clock frequency of the despreader. These m data share a set of 2-bit spreading codes.

[0074] When the digital front end outputs the first set of processed ADC sampling signals, the despreader is enabled to be turned on and receive the first processed ADC sampling signal;

[0075] The despreader receives N groups of ADC sampling signals processed by the digital front end in N consecutive clock cycles and stores them in corresponding registers respectively;

[0076] Among them, when the pre-charge phase begins, the register shift counter starts timing; when the shift counter value is 0, the processed ADC sampling signals received by the despreader in the first clock cycle are stored in the first group of m registers; when the shift counter value is 1, the processed ADC sampling signals received by the despreader in the second clock cycle are stored in the second group of m registers; and so on, until when the counter value is N-1, the processed ADC sampling signals received by the despreader in the Nth clock cycle are stored in the Nth group of m registers.

[0077] In this embodiment, data is stored in an address mapping manner, which does not change the corresponding relationship between data and spread spectrum codes, and all data share a set of spread spectrum codes.

[0078] 102. After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the triggering execution is repeated until the correlation operations of N groups of registers are completed and the corresponding despread value is obtained.

[0079] In this embodiment, after the pre-charge phase ends, the shift counter value returns to 0 and enters a new clock cycle;

[0080] In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers;

[0081] At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence position 0 to the (N-1) position for storage, shifting the value of the original spread spectrum sequence position 1 to the 0 position for storage, and so on, until the value of the (N-1) position is shifted to the (N-2) position for storage;

[0082] Correlation operations are performed on the updated N groups of registers stored in a one-to-one correspondence with the updated N spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases;

[0083] When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers;

[0084] At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated N groups of registers are matched one by one with the updated N spread spectrum code sequences and correlation operations are performed to obtain m correlation results;

[0085] Repeat the triggering and execution until the relevant operations of N groups of registers are completed and the corresponding despread values ​​are obtained.

[0086] This embodiment stores the spreading code sequence by shifting. This implementation method does not change the corresponding relationship between the spreading codes in the despreading input domain, and the same result can be obtained in the correlation operation.

[0087] The present invention also includes despreading the Payload demodulated data;

[0088] After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the trigger is repeated until the correlation operations of 18 groups of registers are completed and the corresponding despread value is obtained.

[0089] More specifically, after the precharge phase ends, the shift counter value returns to 0 and enters a new clock cycle;

[0090] In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers;

[0091] At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence at position 0 to position 17 for storage, shifting the value of the original spread spectrum sequence at position 1 to position 0 for storage, and so on, until the value of position 17 is shifted to position 16 for storage;

[0092] Correlation operations are performed on the updated 18 groups of registers stored in a one-to-one correspondence with the updated 18 spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases;

[0093] When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers;

[0094] At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated 18 groups of registers are matched one by one with the updated 18 spread spectrum code sequences and correlation operations are performed to obtain m correlation results;

[0095] Repeat the triggering and execution until the relevant operations of 18 groups of registers are completed and the corresponding despread values ​​are obtained.

[0096] In this embodiment, the assignment of values ​​to some registers is stopped during the data phase, which greatly reduces the number of register flips and lowers dynamic power consumption without affecting the correctness of the data despreading result.

[0097] See also Figure 7 A second embodiment of the method for implementing low power consumption of a despreader in an embodiment of the present invention includes:

[0098] 201. In the pre-charge phase, the despreader stores each group of m ADC sampling signals processed by the digital front end into corresponding registers according to the value of the shift counter until the storage of N groups of processed ADC sampling signals is completed;

[0099] In this embodiment, the despreader uses different data lengths at different stages. For example, during preamble acquisition, every received sample must be despread, while loop tracking uses only a subset of samples. Consequently, the spreading code sequence used also changes. However, the despreading principle is still based on a correlator, so a single set of despreader units can be reused for different data domains. The UWB despreading stage performs the same calculations on both I and Q channels. The following calculations use one channel as an example.

[0100] The despreader receives the ADC sampled signal after processing by the digital front-end. When the digital front-end outputs the first set of data, the despreader is enabled and begins receiving the first data. Simultaneously, the initial value of the spreading code is generated, with a spreading code length of N. Since the digital front-end and despreader operating clocks are synchronized, the despreader clock frequency is relatively low. Therefore, during each clock cycle, the despreader receives m data points and stores them in the corresponding m storage cells, where m is the ratio of the digital front-end clock frequency to the despreader clock frequency. These m data points share a common 2-bit spreading code.

[0101] After the despreader is enabled, the register shift counter starts counting during the pre-charge period. The despreader needs to continuously receive N groups of m data and pre-charge them into the storage area inside the module. After the pre-charge is completed, the despreader starts to perform correlation and other operations. Figure 3 The figure shows a storage example during the pre-charge phase, considering the maximum usage scenario of N, tentatively set to 128. Each time the despreader receives m data, it stores the m data in the corresponding register location based on the current shift counter value. For example, if the counter value is 0, the first group of m registers stores the despreader received data; if the counter value is 1, the first group of m registers remains unchanged, while the second group of m registers stores the despreader received data; and so on; if the counter value is N, only the (N-1)th group of m registers stores the despreader received data, and the register values ​​of the other groups are not updated. The N groups of m data have been stored in the corresponding registers, and the pre-charge phase ends.

[0102] In this embodiment, during the pre-charge phase, the spreading code to be correlated with the despread input data does not change. The shift counter increments by 1 after each clock cycle, and the pre-charge phase ends when the value reaches N-1. During this period, only m*8-bit registers are flipped during each clock cycle. Compared to the shift-and-store approach, the pre-charge phase alone reduces the number of register flips by (N-1)*m*8-bit.

[0103] 202. After the pre-charge phase is completed, the preamble processing phase is entered;

[0104] In this embodiment, the shift counter returns to 0 and the despreader officially starts to perform the correlation operation. At this time, the N*m registers have been fully stored with 8 bits of despread data. Figure 4 As shown in Figure 1, the despreader stores the m most recently received data at position 0 of the N sequences, while the values ​​at the other positions remain unchanged. Simultaneously, the spreading code sequence begins shifting: the value at position 1 of the original spreading code is shifted to position 0 for storage, the value at position 0 is shifted to position (N-1), the value at position (N-1) is shifted to position (N-2), and so on. The updated N sequences and N spreading codes are correlated one-to-one, and the m correlation results are used as the despreader output. This way, the despread values ​​of the m phases of the preamble are obtained in each clock cycle.

[0105] In the next clock cycle, the shift counter increments to 1, and the m most recently received data bits are stored in the first position of the N sequences. The values ​​of the other positions in the sequences remain unchanged. The shift process of the spreading code and the related operation process are the same as above. After this, the despreader continues to receive new despread data input until the preamble processing is completed. Therefore, in the preamble processing stage, each clock cycle has:

[0106] N*2(spread spectrum code data width)+m*8(IQ data bit width)

[0107] Compared with the shift storage method, the number of register flips reduced per clock cycle is:

[0108] N*(m*8–2)-m*8 (IQ data bit width)

[0109] 203. After the preamble processing stage is completed, the Payload demodulated data needs to be despread.

[0110] In this embodiment, because the preamble and Payload use different modulation schemes and different spreading code lengths, the despreading lengths are also different. This is reflected in the storage of the despreading input, where the length of N is reduced. For example, the maximum despreading sequence N required for receiving the preamble is 128, while in the Payload data despreading stage, the maximum value of N is 18. The despreading input storage method is as follows: Figure 5 As shown, P_ represents the spreading code used by Payload and the despread input storage.

[0111] After precharging N m-sequences, the shift counter reaches 17. In the next cycle, it starts to increase by 1 from 0. The m data recently received by the despreader are stored in the 0th position of the N sequences. At the same time, the spreading code sequence starts to shift. The shift process is the same as when N=128. The difference is that only 18 spreading codes are flipped each time. Compared with other design methods that shift all registers, the number of register flips reduced per clock cycle is:

[0112] (N-18)*(m*8–2)-m*8 (IQ data bit width)

[0113] Therefore, during the PayPal despreading process, the power consumption is also reduced considerably.

[0114] In this embodiment, the present invention proposes shifting the spreading code sequence instead of shifting and storing data. During the payload demodulation phase, only a portion of the spreading sequence is shifted. This implementation does not change the correspondence between the despreading input and the spreading code, and the same results are achieved in correlation operations. Furthermore, during the data phase, assignment to some registers is stopped. This significantly reduces the number of register flips and dynamic power consumption without compromising the accuracy of the data despreading results. The despreader output is used to search, capture, and track the preamble, as well as to demodulate and decode the payload data, thereby completing the reception process for each message.

[0115] The above describes the low power consumption method for implementing the despreader in the embodiment of the present invention. The following describes the low power consumption device for implementing the despreader in the embodiment of the present invention. Figure 8 An embodiment of a low-power implementation device for a despreader according to an embodiment of the present invention includes:

[0116] A second aspect of the present invention provides a low-power implementation system for a despreader, comprising:

[0117] A pre-charge phase module 301 is configured to store, in the pre-charge phase, m groups of ADC sampling signals processed by the digital front end into corresponding registers by the despreader according to the value of the shift counter until the storage of N groups of processed ADC sampling signals is completed;

[0118] The despread value acquisition module 302 is used to set the shift counter value to 0 after the pre-charge phase ends and enter a new clock cycle. The despreader updates the m ADC sampling signals processed by the digital front end in the current clock cycle to the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is incremented by 1, and the triggering execution is repeated until the correlation operations of N groups of registers are completed to obtain the corresponding despread value.

[0119] The pre-charge phase module 301 includes: the despreader stores the received N groups of ADC sampling signals processed by the digital front end into corresponding registers by using address mapping.

[0120] More specifically, the pre-charge phase module 301 includes:

[0121] The pre-charge unit 3011 is configured to enable the despreader to be turned on and receive the first processed ADC sampling signal when the digital front end outputs the first group of processed ADC sampling signals; the despreader receives N groups of ADC sampling signals processed by the digital front end for N consecutive clock cycles and stores them in corresponding registers respectively; wherein, when the pre-charge phase begins, the register shift counter begins timing; when the shift counter value is 0, the processed ADC sampling signals received by the despreader in the first clock cycle are stored in the first group of m registers; when the shift counter value is 1, the processed ADC sampling signals received by the despreader in the second clock cycle are stored in the second group of m registers; and so on, until when the counter value is N-1, the processed ADC sampling signals received by the despreader in the Nth clock cycle are stored in the Nth group of m registers.

[0122] The spread spectrum code generation unit 3012 is used to enable the despreader when the digital front end outputs the first group of processed ADC sampling signals, generate an initial value of the spread spectrum code, and store it in the spread spectrum code register; the length of the spread spectrum code is N, and a correlation operation is performed with the corresponding processed ADC sampling signal to obtain the corresponding despread value.

[0123] The despread value acquisition module 302 includes: after the pre-charge phase ends, the shift counter value is reset to 0 and a new clock cycle is entered; in the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers; at the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence position 0 to the (N-1) position for storage, shifting the value of the original spread spectrum sequence position 1 to the 0 position for storage, and so on, until the value of the (N-1) position is shifted to the (N-2) position for storage; the relevant data stored in the updated N groups of registers and the updated The N spreading code sequences after the shift are matched one by one and correlation operations are performed to obtain m correlation results; among which, the m correlation results are the despread values ​​of the corresponding m phases; when the shift counter value is 1, the next clock cycle is entered, and the despreader stores the ADC sampling signals of the m data front-end processed by the currently received data into the second group of m registers; at the same time, the spreading code sequence is shifted again; the correlation data stored in the updated N groups of registers are matched one by one with the updated N spreading code sequences and correlation operations are performed to obtain m correlation results; the triggering execution is repeated until the correlation operations of the N groups of registers are completed and the corresponding despread values ​​are obtained.

[0124] The system further comprises a Payload demodulated data despreading module 303 for despreading the Payload demodulated data;

[0125] After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle into the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is increased by 1, and the trigger is repeated until the correlation operations of 18 groups of registers are completed and the corresponding despread value is obtained.

[0126] More specifically, the Payload demodulation data despreading module 303 includes:

[0127] After the precharge phase is completed, the shift counter value returns to 0 and enters a new clock cycle;

[0128] In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers;

[0129] At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence at position 0 to position 17 for storage, shifting the value of the original spread spectrum sequence at position 1 to position 0 for storage, and so on, until the value of position 17 is shifted to position 16 for storage;

[0130] Correlation operations are performed on the updated 18 groups of registers stored in a one-to-one correspondence with the updated 18 spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases;

[0131] When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers;

[0132] At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated 18 groups of registers are matched one by one with the updated 18 spread spectrum code sequences and correlation operations are performed to obtain m correlation results;

[0133] Repeat the triggering and execution until the relevant operations of 18 groups of registers are completed and the corresponding despread values ​​are obtained.

[0134] above Figure 8 The low power consumption implementation device of the despreader in the embodiment of the present invention is described in detail from the perspective of modular functional entities.

[0135] The present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, the steps of the method for realizing low power consumption of a despreader are implemented.

[0136] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions, which, when executed on a computer, cause the computer to execute the steps of the artificial intelligence data acquisition method.

[0137] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0138] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0139] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for realizing low power consumption of a despreader, characterized in that: include: In the precharge phase, the despreader stores each group of m ADC sampled signals processed by the digital front-end into the corresponding register according to the value of the shift counter until the storage of N groups of processed ADC sampled signals is completed; where N is the length of the spreading code; and m is the ratio of the digital front-end operating clock frequency to the despreader operating clock frequency. After the pre-charge phase is completed, the shift counter value is set to 0 and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end in the current clock cycle to the corresponding registers, and performs a correlation operation with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is incremented by 1, and the trigger is repeated until the correlation operation of N groups of registers is completed and the corresponding despread value is obtained. After the pre-charge phase is completed, the shift counter value is set to 0, and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle to the corresponding register, and performs a correlation operation with the corresponding shift storage spread spectrum code sequence to obtain a corresponding despread value. The shift counter value is increased by 1, and the triggering is repeated until the correlation operation of N groups of registers is completed to obtain the corresponding despread value, including: After the precharge phase is completed, the shift counter value returns to 0 and enters a new clock cycle; In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers; At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence position 0 to the (N-1) position for storage, shifting the value of the original spread spectrum sequence position 1 to the 0 position for storage, and so on, until the value of the (N-1) position is shifted to the (N-2) position for storage; Correlation operations are performed on the updated N groups of registers stored in a one-to-one correspondence with the updated N spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases; When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers; At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated N groups of registers are matched one by one with the updated N spread spectrum code sequences and correlation operations are performed to obtain m correlation results; Repeat the triggering and execution until the relevant operations of N groups of registers are completed and the corresponding despread values ​​are obtained.

2. The method for realizing low power consumption of a despreader according to claim 1, wherein: The step of storing each group of m ADC sampling signals processed by the digital front end into corresponding registers until the storage of N groups of processed ADC sampling signals is completed includes: The despreader stores the received N groups of ADC sampling signals processed by the digital front end into corresponding registers by using address mapping.

3. The method for realizing low power consumption of a despreader according to claim 1, wherein: In the pre-charge phase, the despreader stores each group of m ADC sampling signals processed by the digital front end into a corresponding register according to the value of the shift counter until the storage of N groups of processed ADC sampling signals is completed, including: When the digital front end outputs the first set of processed ADC sampling signals, the despreader is enabled to be turned on and receive the first processed ADC sampling signal; The despreader receives N groups of ADC sampling signals processed by the digital front end in N consecutive clock cycles and stores them in corresponding registers respectively; Among them, when the pre-charge phase begins, the register shift counter starts timing; when the shift counter value is 0, the processed ADC sampling signals received by the despreader in the first clock cycle are stored in the first group of m registers; when the shift counter value is 1, the processed ADC sampling signals received by the despreader in the second clock cycle are stored in the second group of m registers; and so on, until when the counter value is N-1, the processed ADC sampling signals received by the despreader in the Nth clock cycle are stored in the Nth group of m registers.

4. The method for realizing low power consumption of a despreader according to claim 1, wherein: The method further includes: when the digital front end outputs the first group of processed ADC sampling signals, enabling the despreader, generating an initial value of the spread spectrum code, and storing the initial value in the spread spectrum code register; The length of the spreading code is N, and a correlation operation is performed with the corresponding processed ADC sampling signal to obtain a corresponding despread value.

5. A low power consumption implementation system for a despreader, characterized in that: include: A pre-charge phase module is used to store each group of m ADC sampling signals processed by the digital front end into corresponding registers according to the value of the shift counter during the pre-charge phase, until the storage of N groups of processed ADC sampling signals is completed; where N is the length of the spreading code; and m is the ratio of the digital front end operating clock frequency to the de-spreader operating clock frequency. The despread value acquisition module is used to set the shift counter value to 0 after the pre-charge phase ends and enter a new clock cycle. The despreader updates the m ADC sampling signals processed by the digital front end in the current clock cycle to the corresponding registers, and performs correlation operations with the corresponding shift storage spread spectrum code sequence to obtain the corresponding despread value. The shift counter value is incremented by 1, and the triggering execution is repeated until the correlation operations of N groups of registers are completed to obtain the corresponding despread value. After the pre-charge phase is completed, the shift counter value is set to 0, and a new clock cycle is entered. The despreader updates the m ADC sampling signals processed by the digital front end received in the current clock cycle to the corresponding register, and performs a correlation operation with the corresponding shift storage spread spectrum code sequence to obtain a corresponding despread value. The shift counter value is increased by 1, and the triggering is repeated until the correlation operation of N groups of registers is completed to obtain the corresponding despread value, including: After the precharge phase is completed, the shift counter value returns to 0 and enters a new clock cycle; In the current clock cycle, the despreader stores the m ADC sampling signals processed by the digital front end currently received into the first group of m registers; At the same time, the spread spectrum code sequence is shifted, including: shifting the value of the original spread spectrum sequence position 0 to the (N-1) position for storage, shifting the value of the original spread spectrum sequence position 1 to the 0 position for storage, and so on, until the value of the (N-1) position is shifted to the (N-2) position for storage; Correlation operations are performed on the updated N groups of registers stored in a one-to-one correspondence with the updated N spreading code sequences to obtain m correlation results, wherein the m correlation results are despread values ​​of the corresponding m phases; When the shift counter value is 1, the next clock cycle begins and the despreader stores the ADC sampling signals of the currently received m data after front-end processing into the second group of m registers; At the same time, the spread spectrum code sequence is shifted again; the relevant data stored in the updated N groups of registers are matched one by one with the updated N spread spectrum code sequences and correlation operations are performed to obtain m correlation results; Repeat the triggering and execution until the relevant operations of N groups of registers are completed and the corresponding despread values ​​are obtained.

6. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method for implementing a low power consumption despreader according to any one of claims 1 to 4 are implemented.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the computer program is executed by a processor, the steps of the method for implementing a low power consumption despreader according to any one of claims 1 to 4 are implemented.

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