Preparation method of low-power-consumption photonic integrated device and corresponding device of low-power-consumption photonic integrated device

Abstract

The invention discloses a low-power-consumption photonic integrated device preparation method and a corresponding device, and relates to the technical field of semiconductor optoelectronic integrated devices.The device comprises a substrate, a cantilever beam type grating layer, two gain layers, two modulator layers, a wrapping layer and an electric contact layer, the two gain layers and the two modulator layers are symmetrically distributed, and the wrapping layer and the electric contact layer form a shallow ridge waveguide structure. The two symmetrically-distributed gain layers and the middle cantilever beam type grating layer jointly form a double-end resonant cavity structure, the structure shares a unified grating and a thermal tuning platform to achieve continuous, synchronous and high-precision control over cavity mode wavelengths, and balanced modulation and phase synchronization of double-end output are achieved in cooperation with the symmetrically-integrated high-speed modulator layers on the two sides. According to the technical scheme, the gain layer, the grating layer and the modulator layer are symmetrically integrated on the same substrate, the alignment error of a multi-cavity structure is reduced, synchronous scanning, low drift and strong anti-interference high-quality laser output can be obtained, meanwhile, efficient thermal tuning is conducted through the cantilever beam type grating layer, and power consumption is remarkably reduced.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor optoelectronic integrated devices, and more specifically, to a method for fabricating a low-power photonic integrated device and a corresponding device. Background Technology

[0002] With the rapid development of optical communication technology, the performance requirements of optical devices in data transmission modules are continuously increasing. On the one hand, optical devices must support higher transmission rates to meet the needs of data center interconnection, high-bandwidth optical links, and advanced modulation formats; on the other hand, the power consumption of optical devices needs to be further reduced to achieve efficient on-chip integration with electrical chips, while meeting the development trend of high-speed, high-density optoelectronic integration. Furthermore, with the continuous enrichment of communication protocols and network standards, different standards are placing increasingly stringent requirements on the center wavelength, tuning range, and stability of the transmitting end light source, requiring lasers to maintain continuous, controllable, and low-drift wavelength tuning characteristics over a wide range.

[0003] To meet the diverse needs of optical modules for different types of light sources, existing tunable lasers typically employ single-end gain structures, multiple independent cavities, or multi-plate grating structures. However, these structures generally suffer from the following problems:

[0004] 1) Since the gain region, phase region, and modulation region are all single-ended, the integration density is low and the utilization rate of gain materials is low; 2) Existing thermal tuning often relies on high current drive, resulting in high power consumption. Furthermore, due to insufficient thermal isolation in the grating region, the wavelength tuning efficiency is low, which cannot meet the requirements of low-power on-chip systems; 3) The modulator and laser cavity are mostly heterogeneous or asymmetric integrated structures, which makes it impossible to achieve synchronous modulation of dual-ended outputs. This makes it difficult to apply to coherent link bidirectional compensation, dual-ended interconnection, or sensitive fiber optic sensing systems with extremely high requirements for synchronization and interference suppression. Summary of the Invention

[0005] The purpose of this invention is to address the significant shortcomings of existing technologies in terms of synchronous dual-end output, consistency control, low-power tuning, and large-scale reproducible manufacturing. This invention provides a method for fabricating low-power photonic integrated devices and corresponding devices. Using this method, a novel integrated tunable device structure with highly symmetrical structure can be fabricated, which can simultaneously achieve dual-end gain, synchronous tuning, and dual-end high-speed modulation, in order to meet the high-performance and low-power requirements of high-speed optical communication systems.

[0006] The technical solution of this invention is: a method for fabricating a low-power photonic integrated device, the method comprising:

[0007] S1: Prepare a substrate and divide it into a first modulator region, a first gain region, a first phase region, a grating region, a second phase region, a second gain region and a first modulator region in a predetermined direction, with adjacent regions closely connected;

[0008] S2: Grow gain layer material on the substrate to form a first gain layer and a second gain layer; selectively remove the material from the first modulator region and the second modulator region and grow modulator material to form a first modulator layer and a second modulator layer.

[0009] S3: Selectively remove the gain layer material in the first phase region, grating region and second phase region and grow grating layer material to form a grating layer. Then, fabricate periodically arranged micro-reflective structures on the grating layer material within the grating region.

[0010] S4: A cladding layer and an electrical contact layer are grown sequentially from bottom to top above the entire functional layer consisting of the first modulator layer, the first gain layer, the grating layer, the second gain layer, and the second modulator layer. The cladding layer and the electrical contact layer are etched as a whole according to a predetermined ridge strip pattern to form a shallow ridge waveguide structure. The shallow ridge waveguide structure is laterally distributed in the center of the entire upper surface of the functional layer.

[0011] S5: Etch the grating layer within the grating area according to the predetermined cantilever strip pattern to form a cantilever beam structure. The cantilever beam structure includes a cantilever arm located directly below the shallow ridge waveguide structure and air slots symmetrically distributed on both sides.

[0012] S6: P-side electrodes are disposed above the electrical contact layers corresponding to the first gain region, the first phase region, the second phase region, and the second gain region, respectively. A heating resistor is disposed above the electrical contact layer corresponding to the grating region. N-side electrodes are fabricated below the substrate.

[0013] Furthermore, S2 specifically includes:

[0014] Gain layer material is grown layer by layer from bottom to top on the substrate. A first gain layer and a second gain layer with identical structures are formed in the first gain region and the second gain region, respectively. The first gain layer, from bottom to top, includes a first lower confinement layer, a first multiple quantum well layer, and a first upper confinement layer. A mask is used to cover the materials of the first gain region, the first phase region, the grating region, the second phase region, and the second gain region. The active layer material of the first modulator region and the second modulator region is etched away using reactive ion etching equipment. The remaining gain layer material is then removed using H2SiO4 solution. Then, a modulator layer material is grown layer by layer from bottom to top in the first modulator region and the second modulator region using metal-organic chemical vapor deposition equipment, forming a first modulator layer and a second modulator layer with identical structures. The first modulator layer, from bottom to top, includes a second lower confinement layer, a second multiple quantum well layer, and a second upper confinement layer. The mask is then removed. The photofluorescence wavelength of the second multiple quantum well layer is shorter than the photofluorescence wavelength of the first multiple quantum well layer by a predetermined wavelength value.

[0015] Furthermore, S3 specifically includes:

[0016] First, a mask is used to cover the first modulator layer, the first gain layer, the second gain layer, and the second modulator layer. Then, reactive ion etching is used to remove the material from the first phase region, the grating region, and the second phase region. Next, the substrate is cleaned with acetone and ethanol, and the remaining gain layer material is removed by etching with H2SiO4 solution. Finally, grating layer material is grown by mating within the entire area formed by the first phase region, the grating region, and the second phase region using metal-organic chemical vapor deposition. The mask is then removed, and periodically arranged micro-reflective structures are etched above the grating layer material within the grating region to form a patterned grating layer. The photofluorescence wavelength of the grating layer is shorter than the photofluorescence wavelength of the first multi-quantum-well layer by a second predetermined wavelength value.

[0017] Furthermore, S4 specifically includes:

[0018] First, a transverse strip mask is fabricated at the center of the electrical contact layer. The entire cladding and electrical contact layer are then etched using SiCl4 gas dry etching to form a shallow ridge structure. Next, the two sides of the shallow ridge structure are modified by wet etching with HCl solution to form an inverted shallow ridge waveguide structure that conforms to the predetermined ridge strip pattern. The etching depth is controlled within the range of the cladding and electrical contact layer.

[0019] Electrical isolation trenches are etched on the electrical contact layers located between two adjacent regions to form electrical isolation between the first modulator layer, the first gain layer, the grating layer within the first phase region, the grating layer within the grating region, the grating layer within the second phase region, the second gain layer, and the second modulator layer, thereby avoiding mutual interference of current in each functional region.

[0020] Furthermore, S5 specifically includes:

[0021] First, two symmetrically distributed air slots are marked on the upper surface of the grating layer within the grating region. The two air slots are located on both sides of the shallow ridge waveguide structure and are arranged parallel to the shallow ridge waveguide structure. Then, a mask with a cantilever strip pattern is fabricated on the top of the entire device. This mask is used to cover all areas except the locations of the air slots. The grating layer material corresponding to the air slots is removed using reactive ion etching equipment and hydrobromic acid etching to form a cantilever beam structure consisting of a central cantilever arm and symmetrical air slots on both sides. The etching depth is controlled within the grating layer. The upper surface of the cantilever arm is wider than the shallow ridge waveguide structure by a predetermined distance, and the air slots are hexagonal slot structures.

[0022] Furthermore, in S6, an N-plane electrode is fabricated beneath the substrate, specifically including:

[0023] First, the substrate is thinned, and then N-sided electrodes are set on the entire surface of the thinned substrate to provide a common current loop for the entire device.

[0024] The technical solution of the present invention also provides a low-power photonic integrated device, which includes: a substrate, a first gain layer, a second gain layer, a grating layer, a first modulator layer, a second modulator layer, a cladding layer, and an electrical contact layer;

[0025] The first modulator layer, the first gain layer, the grating layer, the second gain layer, and the second modulator layer are arranged closely above the substrate in a predetermined direction and are located in the same plane. The cladding layer and the electrical contact layer are arranged from bottom to top above the entire functional layer composed of the first modulator layer, the first gain layer, the grating layer, the second gain layer, and the second modulator layer. The cladding layer and the electrical contact layer together form a shallow ridge waveguide structure, which is laterally arranged in the center of the entire upper surface of the functional layer. It is formed by etching the cladding layer and the electrical contact layer arranged on the entire surface according to a predetermined ridge strip pattern.

[0026] The grating layer has a cantilever beam structure arranged laterally in the middle. The cantilever beam structure consists of a cantilever arm in the center and air slots symmetrically distributed on both sides. The cantilever arm is located directly below the shallow ridge waveguide structure. The air slots are hexagonal slot structures. The cantilever beam structure is formed by etching the grating layer located below the shallow ridge waveguide structure according to a predetermined cantilever strip pattern.

[0027] Furthermore, the first gain layer and the second gain layer are respectively disposed in the first gain region and the second gain region of the substrate. The first gain region and the second gain region have equal areas and are symmetrical about the center of the substrate. The first gain layer includes a first lower confinement layer, a first multiple quantum well layer and a first upper confinement layer from bottom to top. The structure and function of the second gain layer are the same as those of the first gain layer.

[0028] The first modulator layer and the second modulator layer are respectively disposed in the first modulator region and the second modulator region of the substrate by docking growth. The first modulator layer is located on the side of the first gain layer away from the center of the substrate, and the second modulator layer is located on the side of the second gain layer away from the center of the substrate. The first modulator region and the second modulator region are symmetrical about the center of the substrate. The first modulator layer includes, from bottom to top, a second lower confinement layer, a second multiple quantum well layer and a second upper confinement layer. The structure and function of the second modulator layer are the same as those of the first modulator layer. The photofluorescence wavelength of the second multiple quantum well layer is 40-70 nm shorter than that of the first multiple quantum well layer.

[0029] Furthermore, the grating layer is disposed on the substrate in the entire region consisting of the first phase region, the grating region, and the second phase region by a butt joint growth method, and is located between the first gain layer and the second gain layer, with the grating region located between the first phase region and the second phase region.

[0030] The grating layer within the grating region is etched with periodically arranged micro-reflective structures, while the grating layer within the first and second phase regions retains its original flat structure and is not etched. The photofluorescence wavelength of the grating layer is 100-200 nm shorter than that of the first quantum well layer.

[0031] Furthermore, electrical isolation trenches are etched on the electrical contact layer, and the electrical isolation trenches are located between two adjacent regions arranged in a predetermined direction on the substrate;

[0032] P-plane electrodes are respectively disposed above the electrical contact layers corresponding to the first gain region, the first phase region, the second phase region, and the second gain region. A heating resistor is disposed above the electrical contact layer corresponding to the grating region, with the two ends of the heating resistor being positive and negative electrodes. After thinning treatment, N-plane electrodes are disposed on the entire surface below the substrate. A silicon nitride thin film is also disposed above the electrical contact layer, and the silicon nitride thin film is located below each P-plane electrode and the heating resistor.

[0033] The beneficial effects of this invention are:

[0034] The technical solution of this invention utilizes two symmetrically distributed gain layers and a cantilever beam grating layer located in the middle to form a resonant cavity structure for dual-end synchronous amplification and tuning. High-speed modulators are symmetrically integrated on both sides of this dual-end resonant cavity structure. By sharing a unified grating and thermal tuning platform, continuous, synchronous, and high-precision control of the cavity mode wavelength is achieved. Combined with the symmetrically distributed high-speed modulators on both sides, balanced modulation and phase synchronization of the dual-end output are achieved, thereby obtaining high-quality laser output with synchronous scanning, low drift, and strong anti-interference. The technical solution of this invention reduces multi-spectral interference by symmetrically integrating the gain layer, grating layer, and modulator layer on the same substrate. The alignment error introduced by the gate and multi-cavity structure improves the consistency and process repeatability of the device (i.e., the ability to continuously and stably manufacture devices with consistent performance when the same process is repeated multiple times). At the same time, the cantilever beam grating layer enables efficient thermal tuning of the effective refractive index and wavelength within the cavity, significantly reducing power consumption while reducing tuning current. The technical solution in this invention can also fabricate gain layers, phase tuning layers, and modulator layers with identical structures and functions in one go, reducing registration errors between different devices. While achieving dual-end synchronization and precise control, it reduces manufacturing costs and significantly improves mass production efficiency. Attached Figure Description

[0035] The advantages of the above and additional aspects of the present invention will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0036] Figure 1 This is a schematic diagram of a low-power photonic integrated device structure according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram after the growth of the gain layer material according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram after removing the gain layer material of the dual-ended modulator region according to an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the growth of modulator material in the dual-end modulator region according to an embodiment of the present invention.

[0040] Figure 5 This is a schematic diagram of the gain layer material after removing the double-ended phase region and grating region according to an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the growth of grating layer material after docking the double-ended phase region and the grating region according to an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of the entire surface after the cladding and electrical contact layer have been grown according to an embodiment of the present invention;

[0043] Figure 8 This is a side view of an inverted shallow ridge waveguide structure according to an embodiment of the present invention;

[0044] Figure 9 This is a top view of a cantilever beam structure according to an embodiment of the present invention;

[0045] Figure 10 This is a side-section schematic diagram of a cantilever beam structure according to an embodiment of the present invention;

[0046] Figure 11 This is a top view of a low-power photonic integrated device structure according to an embodiment of the present invention.

[0047] Among them, 10-substrate, 11-first gain layer, 111-first lower confinement layer, 112-first multiple quantum well layer, 113-first upper confinement layer, 12-second gain layer, 13-grating layer, 131-micro-reflective structure, 132-cantilever arm, 133-air groove, 14-first modulator layer, 141-second lower confinement layer, 142-second multiple quantum well layer, 143-second upper confinement layer, 15-second modulator layer, 16-cladding layer, 17-electrical contact layer, 171-electrical isolation trench, 18-P-side electrode, 19-heating resistor, 191-positive electrode, 192-negative electrode, 20-N-side electrode, 21-mask. Detailed Implementation

[0048] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0049] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0050] This embodiment takes the InP-based material system as an example. The following is a general introduction to a method for fabricating a low-power photonic integrated device and its corresponding device in this embodiment of the invention.

[0051] like Figure 11 As shown, this embodiment provides a low-power photonic integrated device, which includes: a substrate 10, a first gain layer 11, a second gain layer 12, a grating layer 13, a first modulator layer 14, a second modulator layer 15, a cladding layer 16, and an electrical contact layer 17.

[0052] The first modulator layer 14, the first gain layer 11, the grating layer 13, the second gain layer 12, and the second modulator layer 15 are arranged closely above the substrate 10 in a preset direction and are located in the same plane. The cladding layer 16 and the electrical contact layer 17 are arranged from bottom to top above the functional layer composed of the first modulator layer 14, the first gain layer 11, the grating layer 13, the second gain layer 12, and the second modulator layer 15. The corresponding P-side electrodes are respectively arranged above the electrical contact layers 17 corresponding to the first gain layer 11 and the second gain layer 12. The heating resistor is arranged above the electrical contact layer 17 corresponding to the middle part of the grating layer 13. The P-side electrodes are arranged above the electrical contact layers 17 corresponding to both sides of the grating layer 13. The N-side electrodes are arranged below the substrate 10.

[0053] The upper surface of substrate 10 is sequentially divided along a predetermined direction into a first modulator region (marked 1), a first gain region (marked 2), a first phase region (marked 3), a grating region (marked 4), a second phase region (marked 5), a second gain region (marked 6), and a first modulator region (marked 7), with adjacent regions closely connected. The grating region is located at the center of the upper surface of substrate 10. The first and second phase regions have equal areas and are symmetrically arranged on both sides of the grating region. The first and second gain regions have equal areas and are symmetrically arranged on both sides of the entire region composed of the grating region and the two phase regions. The first and second modulator regions have equal areas and are symmetrically arranged on both sides of the entire region composed of the grating region, the two phase regions, and the two gain regions, with adjacent regions closely connected. In this embodiment, the predetermined direction is represented as follows: Figure 11 The direction shown is from left to right.

[0054] The first gain layer 11 and the second gain layer 12 are respectively disposed in the first gain region and the second gain region of the substrate 10. The first gain region and the second gain region have equal areas and are symmetrical about the center of the substrate 10. The first gain layer 11 and the second gain layer 12 are respectively used to provide a light source and a gain medium for the device to emit light. The two gain layers can generate photon gain by injecting current, enabling the device to emit tunable light signals. Furthermore, applying different DC voltages can also excite multiple lasers of different wavelengths, meeting the device's requirement for multiple wavelengths.

[0055] Specifically, the first gain layer 11 includes, from bottom to top, a first lower confinement layer 111, a first multi-quantum well layer 112, and a first upper confinement layer 113. The first multi-quantum well layer 112 is the carrier recombination and photon generation region. The first gain layer 111 and the first upper confinement layer 113 are used to form the lower and upper potential barriers of the quantum well, respectively, to restrict the movement of carriers in the quantum well, prevent diffusion, and ensure the stability of the optical field and carrier distribution. The structure and function of the second gain layer 12 are the same as those of the first gain layer 11, and will not be described in detail here.

[0056] It should be noted that by symmetrically setting two gain regions at both ends of the grating region and the two-phase region, the light field can form a symmetrical resonant structure along both sides of the device, thus forming two independent yet coherently coupled wavelength-tunable lasers. Relying on the common grating region, these two lasers can achieve double-end face light output, which can not only meet the application requirements of the device under different transmission directions and different link topologies, but also facilitate the flexible configuration of the light source in multi-channel or bidirectional communication scenarios.

[0057] The first modulator layer 14 and the second modulator layer 15 are respectively disposed in the first modulator region and the second modulator region of the substrate 10 by a docking growth method. The first modulator layer 14 is located on the side of the first gain layer 11 away from the center of the substrate 10, and the second modulator layer 15 is located on the side of the second gain layer 12 away from the center of the substrate 10. The first modulator layer 14 and the second modulator layer 15 are symmetrical about the center of the substrate 10. The first modulator layer 14 and the second modulator layer 15 are respectively used to perform electrical absorption modulation on the optical signal.

[0058] Specifically, the first modulator layer 14 includes, from bottom to top, a second lower confinement layer 141, a second multiple quantum well layer 142, and a second upper confinement layer 143. The second multiple quantum well layer 142 is an active absorption layer used to absorb and modulate optical signals under the action of an external electric field. The second lower confinement layer 141 and the second upper confinement layer 143 are used to form the lower and upper potential barriers of the quantum well, respectively, to restrict the movement of charge carriers in the quantum well, prevent diffusion, and ensure the stability of the optical field and charge carrier distribution. The structure and function of the second modulator layer 15 are the same as those of the first modulator layer 14, and will not be described in detail here.

[0059] The photofluorescence wavelength of the second quantum well layer 142 is shorter than that of the first quantum well layer 112 by a predetermined wavelength value, which is in the range of 40-70 nm. The photofluorescence wavelength of the quantum well layer in the second modulator layer 15 is the same as that of the second quantum well layer 142, and the photofluorescence wavelength of the quantum well layer in the second gain layer 12 is the same as that of the first quantum well layer 112.

[0060] The first modulator layer 14 and the second modulator layer 15 are used to realize the electro-absorption modulation of the optical signal. Specifically, applying a reverse voltage (e.g., 0-3V) to the modulator region can cause a wavelength redshift, enhance the absorption capability of the emitted laser, and achieve controllable attenuation of the light intensity. On this basis, an radio frequency signal is superimposed on the reverse bias voltage, causing the electric field at both ends of the modulator to change rapidly with time, resulting in a periodic change in the absorption coefficient. When the applied radio frequency signal is at a high level, the total reverse voltage increases, the absorption is enhanced, and the output light intensity is weakened. When the radio frequency signal is at a low level, the total reverse voltage decreases, the absorption is weakened, and the output light intensity is enhanced. Through this electric field modulation, the high and low levels of the electrical signal can be corresponding to the "0" and "1" states of the optical signal, respectively, thereby realizing high-speed intensity modulation of continuous laser and improving the optical signal transmission rate and modulation accuracy. When the modulator is working, it can support optical signal modulation and transmission rates of more than 100 Gbps (i.e., 100 billion bits per second).

[0061] The grating layer 13 is disposed on the substrate 10 in the entire region consisting of the first phase region, the grating region, and the second phase region by a butt joint growth method. The grating layer 13 is located in the center of the entire substrate 10 and is disposed between the first gain layer 11 and the second gain layer 12. The grating region is located between the first phase region and the second phase region. The grating layer 13 in the grating region is etched above to form periodically arranged micro-reflective structures 131, which are used to construct feedback coupling (i.e., the grating reflects light of a specific wavelength back, so that it couples with the propagating light to form the feedback loop required for laser oscillation) and wavelength selection (i.e., only a specific wavelength of light is reflected most strongly, and other wavelengths are reflected weakly). The grating layer 13 in the first phase region and the second phase region is kept in its original flat structure and is not etched to avoid introducing additional optical feedback in this region (to prevent the phase region from becoming a redundant mirror, only changing the phase of the light without reflection, and avoiding functional mixing), and to ensure the independence of phase modulation of the two phase regions and the continuity of the light field distribution.

[0062] The photofluorescence wavelength of the grating layer 13 is shorter than the photofluorescence wavelength of the first quantum well layer 112 by a second predetermined wavelength value, which is in the range of 100-200 nm.

[0063] The cladding layer 16 and the electrical contact layer 17 together constitute a shallow ridge waveguide structure. This shallow ridge waveguide structure is laterally positioned at the center of the upper surface of the functional layer composed of the first modulator layer 14, the first gain layer 11, the grating layer 13, the second gain layer 12, and the second modulator layer 15. It is formed by integrally etching the cladding layer 16 and the electrical contact layer 17, which are arranged on the entire surface, according to a predetermined ridge strip pattern. The cladding layer 16 is used to provide a refractive index difference in the vertical direction to effectively limit and constrain the optical mode, so that the light field is concentrated in the lower gain layer and the central region of the waveguide, thereby improving the optical coupling efficiency and gain efficiency, and reducing light leakage and propagation loss. The electrical contact layer 17 is used to achieve good ohmic contact.

[0064] It should be noted that the cladding layer 16 and the electrical contact layer 17 are formed after partial etching, as shown in the figure. Figure 7 The ridge structure shown has an etching depth limited to the area where the cladding layer 16 and the electrical contact layer 17 are located, and does not penetrate the underlying active layer (including the first modulator layer 14, the first gain layer 11, the grating layer 13, the second gain layer 12, and the second modulator layer 15). This shallow ridge waveguide structure can improve carrier injection efficiency and optimize electro-optic conversion performance through the refractive index difference in shape and current confinement. At the same time, it can also achieve lateral confinement of light waves and current, reduce optical losses, and improve the stability and reliability of the device.

[0065] like Figure 8 As shown, in this embodiment, the shallow ridge waveguide structure is laterally distributed along the horizontal direction from the first modulator layer 14 to the second modulator layer 15 (that is, the preset direction).

[0066] A cantilever beam structure is laterally arranged in the middle of the grating layer 13. The cantilever beam structure consists of a cantilever arm 132 at the central position and air slots 133 symmetrically distributed on both sides. The cantilever arm 132 is located directly below the shallow ridge waveguide structure, and its upper surface is wider than the shallow ridge waveguide structure by a predetermined distance, which can be set to 5 micrometers. The air slots 133 are hexagonal slot structures. The cantilever beam structure is formed by etching the grating layer 13 located below the shallow ridge waveguide structure according to a predetermined cantilever strip pattern.

[0067] Electrical isolation trenches 171 are also etched on the electrical contact layer 17. The electrical isolation trenches 171 are located between two adjacent regions (first modulator region, first gain region, first phase region, grating region, second phase region, second gain region and first modulator region) arranged in a preset direction on the substrate 10, and are used to electrically isolate each region.

[0068] It should be noted that the first gain layer 11, the grating layer 13 within the grating region, and the second gain layer 12 together constitute the laser resonant cavity structure. The first gain layer 11 and the second gain layer 12 are symmetrical in structure, and both can provide optical gain after the injection of driving current. They generate stimulated emission light field through carrier recombination, providing double-end gain compensation for the resonant cavity. The grating layer 13 within the grating region can provide Bragg reflection through its periodic microstructure (periodically arranged micro-reflective structures 131), realizing feedback and wavelength selection of the optical field in the cavity, ensuring stable oscillation in a specific wavelength mode. The first gain layer 11, the grating layer 13 within the grating region, and the second gain layer 12 work together to construct a symmetrical distributed feedback cavity structure, so that laser signals with selected wavelengths are simultaneously output from both ends of the device, improving coupling flexibility and adaptability to multi-directional links.

[0069] P-surface electrodes 18 are respectively disposed above the electrical contact layers 17 corresponding to the first gain region, the first phase region, the second phase region, and the second gain region. The P-surface electrodes disposed above the first gain region and the second gain region are used to input driving current into the gain layer to drive the laser resonator to oscillate and achieve stable light output. The P-surface electrodes disposed above the first phase region and the second phase region are used to input tuning current into the phase region to change the refractive index of the phase region, thereby achieving fine control of the phase of the optical signal in the cavity and enabling the output wavelength to be continuously and stably tuned.

[0070] A heating resistor 19 is disposed above the electrical contact layer 17 corresponding to the grating region. The middle part of the heating resistor 19 covers the shallow ridge waveguide structure. The two ends of the heating resistor 19 are a positive electrode 191 and a negative electrode 192. The positive electrode 191 and the negative electrode 192 are used to connect to the positive and negative terminals of the external power supply, respectively. The heating resistor 19 is used to provide heating power to the grating layer 13 within the grating region through the shallow ridge waveguide structure below it, so as to change its refractive index and reflection phase, perform thermal tuning, and thus realize fine wavelength tuning of the output optical signal.

[0071] After thinning, N-face electrodes 20 are formed on the entire surface of the substrate 10. The N-face electrodes 20 are used to provide a common current loop for the entire device.

[0072] A silicon nitride thin film is also disposed above the electrical contact layer 17. The silicon nitride thin film is located below each P-side electrode 18 and the heating resistor 19 to achieve electrical insulation, surface passivation and structural protection, while suppressing surface state recombination and metal absorption, thereby improving device stability and tuning efficiency.

[0073] In this embodiment, under the InP-based material system, the substrate 10 is an N-type InP substrate (indium phosphide), the first modulator layer 14 and the second modulator layer 15 are InGaAlAs (indium gallium aluminum arsenide) active materials, the first gain layer 11 and the second gain layer 12 are InGaAlAs active materials, wherein the modulator layer and the gain layer are made of the same material composition but with different proportions, which can achieve different effects, the grating layer 13 is InGaAsP (indium gallium arsenide phosphide) bulk material, the cladding layer 16 is InP cladding material, the electrical contact layer 17 is InGaAs contact layer material, the heating resistor 19 is titanium-platinum material, the P-side electrode can be titanium-gold material, and the N-side electrode can be gold-germanium-nickel alloy material.

[0074] like Figures 1 to 11 As shown, this embodiment provides a method for fabricating a low-power photonic integrated device, including:

[0075] S1: Prepare substrate 10, and divide the substrate 10 into a first modulator region, a first gain region, a first phase region, a grating region, a second phase region, a second gain region and a first modulator region in a predetermined direction, with adjacent regions closely connected.

[0076] S2: A gain layer material is grown on the substrate 10, and a first gain layer 11 and a second gain layer 12 are formed in the first gain region and the second gain region, respectively. The gain layer material in the first modulator region and the second modulator region is selectively removed, and a first modulator layer 14 and a second modulator layer 15 are grown in the first modulator region and the second modulator region, respectively. The photofluorescence wavelength of the modulator layer material is shorter than that of the gain layer material.

[0077] Specifically, gain layer materials are grown layer by layer from bottom to top on the substrate 10. A first gain layer 11 and a second gain layer 12 with identical structures are formed in the first gain region and the second gain region, respectively. The first gain layer 11 includes, from bottom to top, a first lower confinement layer 111, a first multiple quantum well layer 112, and a first upper confinement layer 113. A SiO2 mask 21 is used to cover the gain layer materials in the first gain region, the first phase region, the grating region, the second phase region, and the second gain region. The active layer materials in the first modulator region and the second modulator region are etched away using reactive ion etching equipment, and etching residues are removed using H2SiO4 solution. The gain layer material is then grown by metal-organic chemical vapor deposition (MOCVD) in the first and second modulator regions, respectively, layer by layer from bottom to top, to form a first modulator layer 14 and a second modulator layer 15 with identical structures. The first modulator layer 14 includes a second lower confinement layer 141, a second multiple quantum well layer 142, and a second upper confinement layer 143 from bottom to top. The SiO2 mask 21 is removed. The photofluorescence wavelength of the second multiple quantum well layer 142 is shorter than that of the first multiple quantum well layer 112 by a first predetermined wavelength value, which is in the range of 40-70 nm.

[0078] In this embodiment, the SiO2 mask 21 can be fabricated by etching, including the following steps: growing a SiO2 thin film layer with a thickness of 200 nm on the surface using a plasma chemical vapor deposition device, and fabricating a predetermined pattern on the SiO2 thin film layer using photolithography and wet etching to cover the material layers that do not need to be removed; after completing the selective removal operation of other material layers, removing the SiO2 thin film layer by wet etching or dry etching.

[0079] S3: Selectively remove the gain layer material of the first phase region, grating region and second phase region, and grow grating layer material in the region composed of the first phase region, grating region and second phase region to form grating layer 13. Then, periodically arranged micro-reflective structures 131 are made on the grating layer material within the grating region.

[0080] Specifically, a SiO2 mask 21 is first used to cover the first modulator layer 14, the first gain layer 11, the second gain layer 12, and the second modulator layer 15. Then, a reactive ion etching device is used to etch and remove the gain layer material of the first phase region, the grating region, and the second phase region. The substrate 10 is cleaned with acetone and ethanol, and the residual gain layer material is removed by etching with H2SiO4 solution. Finally, a metal-organic chemical vapor deposition device is used to grow and connect the grating layer material in the region composed of the first phase region, the grating region, and the second phase region. The SiO2 mask 21 is removed, and periodically arranged micro-reflective structures 131 are etched above the grating layer material within the grating region, ultimately forming a patterned grating layer 13. The photofluorescence wavelength of the grating layer 13 is shorter than the photofluorescence wavelength of the first multi-quantum well layer 112 by a second predetermined wavelength value, which is in the range of 100-200 nm.

[0081] In this embodiment, the periodically arranged micro-reflective structures 131 fabricated above the grating layer material can be formed by photolithography and dry etching. A periodic patterned mask is formed by photolithography, and then the microstructure is etched by reactive ion etching or deep silicon etching. Finally, the patterned mask is removed.

[0082] S4: A cladding layer 16 and an electrical contact layer 17 are grown sequentially from bottom to top above the entire functional layer consisting of the first modulator layer 14, the first gain layer 11, the grating layer 13, the second gain layer 12, and the second modulator layer 15. The cladding layer 16 and the electrical contact layer 17 are etched as a whole according to a predetermined ridge strip pattern to form a shallow ridge waveguide structure. The shallow ridge waveguide structure is laterally distributed at the center of the upper surface of the entire functional layer consisting of the first modulator layer 14, the first gain layer 11, the grating layer 13, the second gain layer 12, and the second modulator layer 15.

[0083] Specifically, a transverse strip mask is first fabricated at the center of the electrical contact layer 17. The entire cladding layer 16 and the electrical contact layer 17 are then etched using SiCl4 gas dry etching to form a shallow ridge structure. Next, the two sides of the shallow ridge structure are modified using HCl solution wet etching to finally form an inverted shallow ridge waveguide structure that conforms to the predetermined ridge strip pattern. The etching depth is controlled within the range of the cladding layer 16 and the electrical contact layer 17, without penetrating the cladding layer 16 to the material layer below it.

[0084] Electrical isolation trenches 171 are etched on the electrical contact layer 17 located between two adjacent regions, so that electrical isolation is formed between the first modulator layer 14, the first gain layer 11, the grating layer 13 within the first phase region, the grating layer 13 within the grating region, the grating layer 13 within the second phase region, the second gain layer 12, and the second modulator layer 15, to avoid mutual interference of current in each functional region and ensure independent driving and independent tuning of each region.

[0085] In this embodiment, the etching of the electrical isolation trench 171 can be carried out by photolithography and dry etching. For example, a patterned mask corresponding to the electrical isolation trench 171 can be formed by photolithography first, and then the electrical isolation trench 171 can be etched on the electrical contact layer 17 between adjacent areas by reactive ion etching or deep silicon etching process, and finally the mask can be removed.

[0086] S5: Etch the grating layer 13 within the grating area according to the predetermined cantilever strip pattern to form a cantilever beam structure. The cantilever beam structure includes a cantilever arm 132 located directly below the shallow ridge waveguide structure and air slots 133 symmetrically distributed on both sides.

[0087] Specifically, firstly, two symmetrically distributed air slots 133 are marked on the upper surface of the grating layer 13 within the grating region. The two air slots 133 are located on both sides of the shallow ridge waveguide structure and are arranged parallel to the shallow ridge waveguide structure. Then, a mask with a cantilever strip pattern is fabricated on the entire device using photolithography. This mask covers all positions except for the positions of the air slots 133. The grating layer material corresponding to the positions of the air slots 133 is removed using reactive ion etching equipment and hydrobromic acid etching to form a cantilever beam structure composed of a central cantilever arm 132 and two symmetrical air slots 133 on both sides. The etching depth is controlled within the grating layer 13 and does not penetrate the grating layer 14 to the substrate 10 below it. The upper surface of the cantilever arm 132 is wider than the shallow ridge waveguide structure by a predetermined distance, which can be set to 5 micrometers. The air slots 133 are hexagonal slot structures.

[0088] S6: P-side electrodes 18 are disposed above the electrical contact layers 17 corresponding to the first gain region, the first phase region, the second phase region, and the second gain region, respectively; heating resistors 19 are disposed above the electrical contact layers 17 corresponding to the grating region; and N-side electrodes 20 are fabricated below the substrate 10.

[0089] Specifically, a silicon nitride thin film with a thickness of 250 nm is first grown on the entire device. Then, P-side electrodes 18 are set on the electrical contact layers 17 corresponding to the first gain region, the first phase region, the second phase region, and the second gain region, respectively. A heating resistor 19 is fabricated on the electrical contact layer 17 corresponding to the grating region using titanium-platinum material. The heating resistor 19 includes a positive electrode 191 and a negative electrode 192, which are used to connect to the positive and negative terminals of the external power supply, respectively. The titanium-platinum heating resistor has a strong bonding force with the silicon nitride insulating film, and the combination of the two can improve the heating efficiency after power is applied. Finally, the substrate 10 is thinned below and N-side electrodes 20 are set on the entire surface to provide a common current loop for the entire device.

[0090] In this embodiment, the thinning process below the substrate 10 can be carried out by mechanical grinding and polishing, wet chemical etching, dry etching, etc., to ensure that the substrate thickness is uniform and the surface is flat, which is beneficial to the subsequent deposition and adhesion of the N-side electrode 20, while reducing the device resistance and improving the overall current loop efficiency.

[0091] It should be noted that this application employs two symmetrically distributed gain layers and a cantilever beam grating layer located in the middle to form a laser resonant cavity structure. The cladding and electrical contact layers are fabricated into shallow ridge waveguide structures. The two symmetrically distributed gain layers simultaneously provide optical gain, ensuring symmetrical amplification of the intracavity optical field and power balance at both ends. The shallow ridge waveguide structure enhances optical field confinement and thermal isolation to thermally tune the cantilever beam grating layer, achieving precise and controllable adjustment of the intracavity optical wavelength. The two ends of the grating layer are located in symmetrical phase regions and do not contain micro-reflective structures, allowing for the application of tuning current. Under certain conditions, the output optical signal is independently phase modulated, enabling the laser output wavelength to be scanned continuously and stably. Simultaneously, this application also symmetrically integrates two modulator layers on both sides of the entire laser resonant cavity structure. These modulator layers apply independent modulation to the optical signal within the cavity, achieving precise control of the optical signal amplitude. This allows the entire device to output modulated, dual-end synchronized laser signals. With the combined action of the symmetrically distributed gain layers and modulator layers, symmetrical amplification of the intracavity optical field, synchronous wavelength scanning, and synchronous modulation control can be achieved, resulting in high-precision, low-interference optical signal output.

[0092] The device structure described in this application, comprising two symmetrically distributed gain layers and a modulator layer at both ends, and a shared cantilever beam grating layer at the center, can be applied to scenarios requiring strict wavelength consistency and synchronous tunability, such as coherent link bidirectional compensation, fiber optic sensor array demodulation, on-chip bidirectional interconnection, and frequency-locked systems. Because the two gain regions share a unified grating structure and thermal tuning platform, and the two ends of the grating structure are located in symmetrical phase regions, the intracavity phase can be independently adjusted, enabling continuous fine-tuning and precise synchronous control of the cavity mode wavelength. This ensures that the output light at both ends remains highly synchronized and mode-consistent during scanning, minimizing wavelength drift. Combined with the symmetrically arranged modulator layer, it achieves balanced modulation and phase synchronization in both outputs, significantly improving system stability, anti-interference capability, and measurement accuracy. Furthermore, by symmetrically integrating two gain layers and two modulator layers on the same substrate and sharing a cantilever beam grating layer, not only is the number of gratings reduced, avoiding alignment and registration errors between multiple independent devices, but process consistency is also improved, the manufacturing process is simplified, mass production efficiency is increased, and the manufacturing cost of a single device is reduced.

[0093] In this embodiment, the low-power photonic integrated device fabricated using the method of this application is tested. The specific steps are as follows:

[0094] By applying an 80 mA DC current to the first gain region and the second gain layer 12 through the P-side electrode, stimulated emission is generated, and the device emits light normally, outputting a laser signal. A current of 0-50 mA is applied to the heating resistor 19 (gradually changing from 0 to 50 mA) to locally heat the grating region, achieving mode selection and thermal tuning of the laser wavelength. A current of 0-20 mA is applied to the first and second phase regions through the P-side electrode to assist the grating region in achieving continuous wavelength tuning. Then, a reverse voltage is applied to the modulator region to achieve absorption modulation. At the same time, an RF signal is superimposed on the reverse voltage to achieve "0" and "1" modulation of the optical signal. The output laser signal intensity is adjusted to a preset value for experimental observation. Finally, the center wavelength of the laser output is measured at each current point from 0-50 mA, the tuning range of the wavelength as a function of the current is recorded, and the overall transmission rate of the device is tested.

[0095] The test results show that wavelength tuning of more than 12 nm can be achieved with a phase current in the range of 0-20 mA, while traditional current tuning methods require 0-80 mA to achieve the same wavelength tuning range. Therefore, this invention significantly reduces power consumption. Driven by the reverse voltage in the modulator region and the superimposed high-speed radio frequency signal, this device with integrated high-speed absorption modulator can achieve a data transmission rate of more than 100 Gbps.

[0096] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0097] The units in the device of the present invention can be merged, divided, or reduced according to actual needs.

[0098] In this invention, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention according to the specific circumstances.

[0099] The shapes of the components in the accompanying drawings are schematic and may differ from their actual shapes. The drawings are only used to illustrate the principles of the present invention and are not intended to limit the present invention.

[0100] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. A method for fabricating a low-power photonic integrated device, characterized in that, The method includes: S1: Prepare a substrate (10) and divide it into a first modulator region, a first gain region, a first phase region, a grating region, a second phase region, a second gain region and a first modulator region in a predetermined direction, with adjacent regions closely connected; S2: Grow gain layer material on substrate (10) to form first gain layer (11) and second gain layer (12), selectively remove material from first modulator region and second modulator region and grow modulator material to form first modulator layer (14) and second modulator layer (15). S3: Selectively remove the gain layer material of the first phase region, the grating region and the second phase region and grow the grating layer material to form a grating layer (13). Then, periodically arranged micro-reflection structures (131) are fabricated on the grating layer material within the grating region. S4: A cladding layer (16) and an electrical contact layer (17) are grown sequentially from bottom to top above the entire functional layer consisting of the first modulator layer (14), the first gain layer (11), the grating layer (13), the second gain layer (12), and the second modulator layer (15). The cladding layer (16) and the electrical contact layer (17) are etched as a whole according to a predetermined ridge strip pattern to form a shallow ridge waveguide structure. The shallow ridge waveguide structure is laterally distributed in the center of the entire upper surface of the functional layer. S5: Etch the grating layer (13) within the grating area according to the predetermined cantilever strip pattern to form a cantilever beam structure. The cantilever beam structure includes a cantilever arm (132) located directly below the shallow ridge waveguide structure and air slots (133) symmetrically distributed on both sides. S6: P-side electrodes (18) are disposed above the electrical contact layers (17) corresponding to the first gain region, the first phase region, the second phase region and the second gain region respectively, heating resistors (19) are disposed above the electrical contact layers (17) corresponding to the grating region, and N-side electrodes (20) are fabricated below the substrate (10).

2. The method for fabricating a low-power photonic integrated device as described in claim 1, characterized in that, S2 specifically includes: Gain layer materials are grown layer by layer from bottom to top on the substrate (10). A first gain layer (11) and a second gain layer (12) with the same structure are formed in the first gain region and the second gain region, respectively. The first gain layer (11) includes a first lower confinement layer (111), a first multiple quantum well layer (112), and a first upper confinement layer (113) from bottom to top. The materials of the first gain region, the first phase region, the grating region, the second phase region, and the second gain region are covered with a mask. The active layer materials of the first modulator region and the second modulator region are removed by etching using a reactive ion etching device, and the active layer materials of the first modulator region and the second modulator region are removed by etching with H2SiO4 solution. After removing the residual gain layer material from the etching process, a modulator layer material is grown layer by layer from bottom to top in the first modulator region and the second modulator region using a metal-organic chemical vapor deposition apparatus to form a first modulator layer (14) and a second modulator layer (15) with the same structure. The first modulator layer (14) includes a second lower confinement layer (141), a second multiple quantum well layer (142), and a second upper confinement layer (143) from bottom to top. The mask is then removed. The photofluorescence wavelength of the second multiple quantum well layer (142) is shorter than the photofluorescence wavelength of the first multiple quantum well layer (112) by a first predetermined wavelength value.

3. The method for fabricating a low-power photonic integrated device as described in claim 2, characterized in that, S3 specifically includes: First, a mask is used to cover the first modulator layer (14), the first gain layer (11), the second gain layer (12), and the second modulator layer (15). The material of the first phase region, the grating region, and the second phase region is removed by etching using a reactive ion etching device. Then, the substrate (10) is cleaned with acetone and ethanol, and the residual gain layer material is removed by etching using H2SiO4 solution. Finally, the grating layer material is grown by docking in the entire area formed by the first phase region, the grating region, and the second phase region using a metal-organic chemical vapor deposition device. The mask is removed, and periodically arranged micro-reflective structures (131) are etched above the grating layer material within the grating region to form a patterned grating layer (13). The photofluorescence wavelength of the grating layer (13) is shorter than the photofluorescence wavelength of the first multi-quantum well layer (112) by a second predetermined wavelength value.

4. The method for fabricating a low-power photonic integrated device as described in claim 1, characterized in that, S4 specifically includes: First, a transverse strip mask is fabricated at the center of the electrical contact layer (17). The entire cladding (16) and electrical contact layer (17) are then subjected to SiCl4 gas dry etching to form a shallow ridge structure. Then, the two sides of the shallow ridge structure are modified by HCl solution wet etching to form an inverted shallow ridge waveguide structure that conforms to the predetermined ridge strip pattern. The etching depth is controlled within the range of the cladding (16) and electrical contact layer (17). Electrical isolation trenches (171) are etched on the electrical contact layer (17) located between two adjacent regions, so that electrical isolation is formed between the first modulator layer (14), the first gain layer (11), the grating layer (13) within the first phase region, the grating layer (13) within the grating region, the grating layer (13) within the second phase region, the second gain layer (12), and the second modulator layer (15), so as to avoid mutual interference of current in each functional region.

5. The method for fabricating a low-power photonic integrated device as described in claim 1, characterized in that, S5 specifically includes: First, two symmetrically distributed air slots (133) are divided on the upper surface of the grating layer (13) within the grating area. The two air slots (133) are located on both sides of the shallow ridge waveguide structure and are arranged parallel to the shallow ridge waveguide structure. Then, a mask with a cantilever strip pattern is fabricated on the top of the entire device. The mask is used to cover the other positions except for the positions of the air slots (133). The grating layer material corresponding to the positions of the air slots (133) is removed by reactive ion etching equipment and hydrobromic acid etching to form a cantilever beam structure consisting of a central cantilever arm (132) and two symmetrical air slots (133) on both sides. The etching depth is controlled inside the grating layer (13). The upper surface of the cantilever arm (132) is wider than the shallow ridge waveguide structure by a predetermined distance. The air slots (133) are hexagonal slot structures.

6. The method for fabricating a low-power photonic integrated device as described in claim 1, characterized in that, In step S6, an N-plane electrode (20) is fabricated below the substrate (10), specifically including: First, the substrate (10) is thinned, and then N-face electrodes (20) are set on the entire surface of the thinned substrate (10) to provide a common current loop for the entire device.

7. A low-power photonic integrated device fabricated using the low-power photonic integrated device fabrication method according to any one of claims 1-6, characterized in that, The device includes: a substrate (10), a first gain layer (11), a second gain layer (12), a grating layer (13), a first modulator layer (14), a second modulator layer (15), a cladding layer (16), and an electrical contact layer (17). The first modulator layer (14), the first gain layer (11), the grating layer (13), the second gain layer (12), and the second modulator layer (15) are arranged closely above the substrate (10) in a predetermined direction and are located in the same plane; the cladding layer (16) and the electrical contact layer (17) are arranged from bottom to top above the entire functional layer composed of the first modulator layer (14), the first gain layer (11), the grating layer (13), the second gain layer (12), and the second modulator layer (15); the cladding layer (16) and the electrical contact layer (17) together constitute a shallow ridge waveguide structure, which is laterally arranged in the center of the entire upper surface of the functional layer, and is formed by etching the cladding layer (16) and the electrical contact layer (17) arranged on the entire surface according to a predetermined ridge strip pattern; Among them, a cantilever beam structure is arranged horizontally in the middle of the grating layer (13). The cantilever beam structure consists of a cantilever arm (132) at the central position and air slots (133) symmetrically distributed on both sides. The cantilever arm (132) is located directly below the shallow ridge waveguide structure. The air slots (133) are hexagonal slot structures. The cantilever beam structure is formed by etching the grating layer (13) set below the shallow ridge waveguide structure according to a predetermined cantilever strip pattern.

8. The low-power photonic integrated device as described in claim 7, characterized in that, The first gain layer (11) and the second gain layer (12) are respectively disposed in the first gain region and the second gain region of the substrate (10). The first gain region and the second gain region have equal areas and are symmetrical about the center of the substrate (10). The first gain layer (11) includes a first lower confinement layer (111), a first multiple quantum well layer (112) and a first upper confinement layer (113) from bottom to top. The structure and function of the second gain layer (12) are the same as those of the first gain layer (11). The first modulator layer (14) and the second modulator layer (15) are respectively disposed in the first modulator region and the second modulator region of the substrate (10) by docking growth. The first modulator layer (14) is located on the side of the first gain layer (11) away from the center of the substrate (10), and the second modulator layer (15) is located on the side of the second gain layer (12) away from the center of the substrate (10). The first modulator region and the second modulator region are symmetrical about the center of the substrate (10). The first modulator layer (14) includes a second lower confinement layer (141), a second multiple quantum well layer (142) and a second upper confinement layer (143) from bottom to top. The structure and function of the second modulator layer (15) are the same as those of the first modulator layer (14). The photofluorescence wavelength of the second multiple quantum well layer (142) is 40-70 nm shorter than that of the first multiple quantum well layer (112).

9. The low-power photonic integrated device as described in claim 8, characterized in that, The grating layer (13) is disposed on the substrate (10) in the entire region consisting of the first phase region, the grating region and the second phase region by a butt joint growth method, and is located between the first gain layer (11) and the second gain layer (12), with the grating region located between the first phase region and the second phase region; The grating layer (13) within the grating region is etched with periodically arranged micro-reflective structures (131), while the grating layer (13) within the first and second phase regions retains its original flat structure and is not etched. The photoluminescence wavelength of the grating layer (13) is 100-200 nm shorter than that of the first quantum well layer (112).

10. The low-power photonic integrated device as described in claim 9, characterized in that, An electrical isolation trench (171) is also etched on the electrical contact layer (17). The electrical isolation trench (171) is located between two adjacent regions arranged in a preset direction on the substrate (10). P-side electrodes (18) are respectively disposed above the electrical contact layers (17) corresponding to the first gain region, the first phase region, the second phase region, and the second gain region. A heating resistor (19) is disposed above the electrical contact layer (17) corresponding to the grating region. The two ends of the heating resistor (19) are a positive electrode (191) and a negative electrode (192). After thinning treatment, N-side electrodes (20) are disposed on the entire surface below the substrate (10). A silicon nitride thin film is also disposed above the electrical contact layer (17). The silicon nitride thin film is located below each P-side electrode (18) and the heating resistor (19).

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